CS4398-CZZ

CS4398 120-dB, 192-kHz Multibit DAC with Volume Control Features  Advanced Multibit Delta-Sigma Architecture – – – –  Direct Stream Digital (DSD) 120 dB Dynamic Range -107 dB THD+N Low Clock Jitter Sensitivity Differential Analog Outputs – – –  PCM input – – – – – – – – – 102 dB of Stopband Attenuation Supports Sample Rates up to 192 kHz Accepts up to 24 bit Audio Data Supports All Industry Standard Audio Interface Formats Selectable Digital Filter Response Volume Control with 1/2 dB Step Size and Soft Ramp Flexible Channel Routing and Mixing Selectable De-Emphasis – – – Dedicated DSD Input Pins On-Chip 50 kHz Filter to Meet Scarlet Book SACD Recommendations Matched PCM and DSD Analog Output Levels Non-Decimating Volume Control with 1/2 dB Step Size and Soft Ramp DSD Mute Detection Supports Phase-Modulated Inputs Optional Direct DSD Path to On-Chip Switched Capacitor Filter  Control Output for External Muting – – Independent Left and Right Mute Controls Supports Auto Detection of Mute Output Polarity  Typical Applications  Supports Stand-Alone or I²C/SPI – – – – Configuration Embedded Level Translators – 1.8 V to 5 V Serial Audio Input – 1.8 V to 5 V Control Data Input DVD Players SACD Players A/V Receivers Professional Audio Products DSD Input Interpolation Filter with Volume Control PCM Serial Interface DSD Interface Multibit Modulator DSD Processor -Volume control -50kHz filter Direct DSD http://www.cirrus.com Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. All Rights Reserved. MUX Multibit Modulator MUX PCM Input Level Translator 1.8 V to 5V Interpolation Filter with Volume Control MUX Register/Hardware Configuration 5V MUX 1.8 V to 5 V Hardware or I 2C/SPI Control Data Level Translator 3.3 V to 5 V Switched Capacitor DAC and Filter Left Differential Output Switched Capacitor DAC and Filter Right Differential Output External Mute Control Left and Right Mute Controls Internal Voltage Reference DS568F3 MAY 2021 CS4398 Stand-Alone Mode Features  Direct Stream Digital Mode  Selectable Oversampling Modes  Selectable Auto or Manual Mute Polarity – – – 32 kHz to 54 kHz Sampling Rates 50 kHz to 108 kHz Sampling Rates 100 kHz to 216 kHz Sampling Rates  Selectable Interpolation Filters  Selectable 32, 44.1, and 48 kHz De-Emphasis  Configurable ATAPI Mixing Functions  Selectable Serial Audio Interface Formats – – – – Left-Justified, up to 24 bit I²S, up to 24 bit Right-Justified 16 bit Right-Justified 24 bit  Configurable Volume and Muting Controls Description  Auto Mute Output Polarity Detect  Auto Mute on Static PCM Samples  44.1 kHz 50/15 s De-Emphasis Available  Soft Volume Ramp-up after Reset is Released Control Port Mode Features  Selectable Oversampling Modes – – – 32 kHz to 54 kHz Sampling Rates 50 kHz to 108 kHz Sampling Rates 100 kHz to 216 kHz Sampling Rates The CS4398 also has a proprietary DSD processor that allows for volume control and 50 kHz on-chip filtering without an intermediate decimation stage. It also offers an optional path for direct DSD conversion by directly using the multi-element switched capacitor array.  Selectable Serial Audio Interface Formats – – – – – – The CS4398 is a complete stereo 24 bit/192 kHz digitalto-analog system. This D/A system includes digital deemphasis, half dB step size volume control, ATAPI channel mixing, selectable fast and slow digital interpolation filters followed by an oversampled multi-bit deltasigma modulator that includes mismatch shaping technology that eliminates distortion due to capacitor mismatch. Following this stage is a multi-element switched capacitor stage and low pass filter with differential analog outputs. Left-Justified, up to 24 bit I²S, up to 24 bit Right-Justified 16 bit Right-Justified 18 bit Right-Justified 20 bit Right-Justified 24 bit The CS4398 accepts PCM data at sample rates from 32 kHz to 216 kHz, DSD audio data, has selectable digital filters, consumes little power, and delivers excellent sound quality. ORDERING INFORMATION Product CS4398 CDB4398 2 Description Package 120 dB, 192 kHz Multi28-pin Bit DAC with Volume TSSOP Control CS4398 Evaluation Board Pb-Free Grade Temp Range YES Commercial -10° to +70° C - - - Container Rail Order # CS4398-CZZ Tape & Reel CS4398-CZZR - CDB4398 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 TABLE OF CONTENTS 1. PINOUT DRAWING ................................................................................................................. 6 2. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 8 SPECIFIED OPERATING CONDITIONS ................................................................................. 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 8 ANALOG CHARACTERISTICS................................................................................................ 9 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................ 10 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................ 11 DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE............................... 11 SWITCHING CHARACTERISTICS ........................................................................................ 12 SWITCHING CHARACTERISTICS- DSD .............................................................................. 14 SWITCHING CHARACTERISTICS- CONTROL PORT - I²C FORMAT ................................. 15 SWITCHING CHARACTERISTICS- CONTROL PORT - SPI™ FORMAT............................. 16 DC ELECTRICAL CHARACTERISTICS ............................................................................... 17 DIGITAL INTERFACE SPECIFICATIONS ............................................................................. 18 3. TYPICAL CONNECTION DIAGRAM .................................................................................. 19 4. APPLICATIONS ..................................................................................................................... 20 4.1 Grounding and Power Supply Decoupling ....................................................................... 20 4.2 Analog Output and Filtering ............................................................................................. 20 4.3 The MUTEC Outputs ....................................................................................................... 20 4.4 Oversampling Modes ....................................................................................................... 21 4.5 Master and Serial Clock Ratios ....................................................................................... 21 4.6 Stand-Alone Mode Settings ............................................................................................. 22 4.7 Control Port Mode ........................................................................................................... 23 5. CONTROL PORT INTERFACE ............................................................................................. 25 5.1 Memory Address Pointer (MAP) ...................................................................................... 25 5.2 Enabling the Control Port ................................................................................................ 25 5.3 Format Selection ............................................................................................................. 25 5.4 I²C Format ....................................................................................................................... 25 5.5 SPI Format ...................................................................................................................... 26 7.1 Chip ID - Register 01h ..................................................................................................... 29 7.2 Mode Control 1 - Register 02h ........................................................................................ 29 7.3 Volume Mixing and Inversion Control - Register 03h ...................................................... 30 7.4 Mute Control - Register 04h ............................................................................................ 33 7.5 Channel A Volume Control - Register 05h ....................................................................... 34 7.6 Channel B Volume Control - Register 06h ....................................................................... 34 7.7 Ramp and Filter Control - Register 07h ........................................................................... 35 7.8 Misc. Control - Register 08h ............................................................................................ 37 7.9 Misc. Control - Register 09h ............................................................................................ 38 8. PARAMETER DEFINITIONS .................................................................................................. 39 9. REFERENCES ........................................................................................................................ 39 10. PACKAGE DIMENSIONS .................................................................................................... 40 10.1 28-TSSOP ..................................................................................................................... 40 THERMAL CHARACTERISTICS AND SPECIFICATIONS ................................................... 40 11. APPENDIX ....................................................................................................................... 41 DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 3 CS4398 LIST OF FIGURES Figure 1. Pinout Drawing —TSSOP................................................................................................ 6 Figure 2. Serial Mode Input Timing ............................................................................................... 12 Figure 3. Format 0 - Left-Justified up to 24-bit Data ..................................................................... 13 Figure 4. Format 1 - I²S up to 24-bit Data ..................................................................................... 13 Figure 5. Format 2, Right-Justified 16-Bit Data. Format 3, Right-Justified 24-Bit Data. Format 4, Right-Justified 20-Bit Data. (Available in Control Port Mode only) Format 5, Right-Justified 18-Bit Data. (Available in Control Port Mode only) ................ 13 Figure 6. Direct Stream Digital - Serial Audio Input Timing........................................................... 14 Figure 7. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode.............. 14 Figure 8. Control Port Timing - I²C Format.................................................................................... 15 Figure 9. Control Port Timing - SPI Format (Read/Write) ............................................................. 16 Figure 10. Typical Connection Diagram........................................................................................ 19 Figure 11. Recommended Output Filter........................................................................................ 20 Figure 12. Recommended Mute Circuitry ..................................................................................... 21 Figure 13. DSD Phase Modulation Mode Diagram ....................................................................... 24 Figure 14. Control Port Timing, I²C Format................................................................................... 26 Figure 15. Control Port Timing, SPI Format (Write) ...................................................................... 27 Figure 16. Control Port Timing, SPI Format (Read)...................................................................... 27 Figure 17. De-Emphasis Curve..................................................................................................... 30 Figure 18. ATAPI Block Diagram .................................................................................................. 31 Figure 19. 28L TSSOP (4.4 mm Body) Package Drawing ............................................................ 40 Figure 20. Single-Speed (fast) Stopband Rejection...................................................................... 41 Figure 21. Single-Speed (fast) Transition Band ............................................................................ 41 Figure 22. Single-Speed (fast) Transition Band (detail) ................................................................ 41 Figure 23. Single-Speed (fast) Passband Ripple .......................................................................... 41 Figure 24. Single-Speed (slow) Stopband Rejection .................................................................... 41 Figure 25. Single-Speed (slow) Transition Band........................................................................... 41 Figure 26. Single-Speed (slow) Transition Band (detail)............................................................... 42 Figure 27. Single-Speed (slow) Passband Ripple......................................................................... 42 Figure 28. Double-Speed (fast) Stopband Rejection .................................................................... 42 Figure 29. Double-Speed (fast) Transition Band........................................................................... 42 Figure 30. Double-Speed (fast) Transition Band (detail)............................................................... 42 Figure 31. Double-Speed (fast) Passband Ripple......................................................................... 42 Figure 32. Double-Speed (slow) Stopband Rejection ................................................................... 43 Figure 33. Double-Speed (slow) Transition Band ......................................................................... 43 Figure 34. Double-Speed (slow) Transition Band (detail) ............................................................. 43 Figure 35. Double-Speed (slow) Passband Ripple ....................................................................... 43 Figure 36. Quad-Speed (fast) Stopband Rejection ....................................................................... 43 Figure 37. Quad-Speed (fast) Transition Band ............................................................................. 43 Figure 38. Quad-Speed (fast) Transition Band (detail) ................................................................. 44 Figure 39. Quad-Speed (fast) Passband Ripple ........................................................................... 44 Figure 40. Quad-Speed (slow) Stopband Rejection...................................................................... 44 Figure 41. Quad-Speed (slow) Transition Band............................................................................ 44 Figure 42. Quad-Speed (slow) Transition Band (detail)................................................................ 44 Figure 43. Quad-Speed (slow) Passband Ripple.......................................................................... 44 4 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 LIST OF TABLES Table 1. Clock Ratios .................................................................................................................... 21 Table 2. Common Clock Frequencies........................................................................................... 22 Table 3. Digital Interface Format, Stand-Alone Mode Options...................................................... 22 Table 4. Mode Selection, Stand-Alone Mode Options .................................................................. 22 Table 5. Digital Interface Formats - PCM Mode............................................................................ 29 Table 6. Digital Interface Formats - DSD Mode ............................................................................ 30 Table 7. Example Digital Volume Settings .................................................................................... 34 Table 8. Revision Table ................................................................................................................ 45 DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 5 CS4398 1. PINOUT DRAWING DSD_B 1 28 DSD_A DSD_SCLK 2 27 VLS SDIN 3 26 VQ SCLK 4 25 AMUTEC LRCK 5 24 AOUTA- MCLK 6 23 AOUTA+ VD 7 22 VA DGND 8 21 AGND M3 (AD1/CDIN) 9 20 AOUTB+ M2 (SCL/CCLK) 10 19 AOUTB- M1 (SDA/CDOUT) 11 18 BMUTEC M0 (AD0/CS) 12 17 VREF RST 13 16 REF_GND VLC 14 15 FILT+ Figure 1. Pinout Drawing —TSSOP 6 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 Pin Name TSSOP Pin # Pin Description DSD_A DSD_B 28 1 Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data. DSD_SCLK 2 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital audio interface. SDIN 3 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. SCLK 4 Serial Clock (Input) - Serial clock for the serial audio interface. LRCK 5 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. MCLK 6 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. VD 7 Digital Power (Input) - Positive power for the digital section. DGND 8 Digital Ground (Input) - Ground reference for the digital section. RST 13 Reset (Input) - The device enters system reset when enabled. VLC 14 Control Port Power (Input) - Positive power for Control Port I/O. FILT+ 15 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. REF_GND 16 Reference Ground (Input) - Ground reference for the internal sampling circuits. VREF 17 Voltage Reference (Input) - Positive voltage reference for internal sampling circuits. BMUTEC AMUTEC 18 25 Mute Control (Output) - The Mute Control pin is active during power-up initialization, muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. During reset, these outputs are set to a high impedance. AOUTB+ AOUTB- 20 19 Differential Right Channel Analog Output (Output) - The full-scale differential analog output level is specified in the Analog Characteristics specification table. AGND 21 Analog Ground (Input) - Ground reference for the analog section. VA 22 Analog Power (Input) - Positive power for the analog section. AOUTA+ AOUTA- 23 24 Differential Left Channel Analog Output (Output) - The full-scale differential analog output level is specified in the Analog Characteristics specification table. VQ 26 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VLS 27 Serial Audio Interface Power (Input) - Positive power for serial audio interface I/O. Stand-Alone Mode Definitions M3 M2 M1 M0 9 10 11 12 Mode Selection (Input) - Determines the operational mode of the device. Control Port Mode Definitions AD1/CDIN 9 Address Bit 1 (I²C) / Control Data Input (SPI) (Input) - AD1 is a chip address pin in I²C mode; CDIN is the input data line for the Control Port interface in SPI mode. SCL/CCLK 10 Serial Control Port Clock (Input) - Serial clock for the serial Control Port. SDA/CDOUT 11 Serial Control Data (I²C) / Control Data Output (SPI) (Input/Output) - SDA is a data I/O line in I²C mode. CDOUT is the output data line for the Control Port interface in SPI mode. AD0/CS 12 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS is the chip select signal for SPI format. DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 7 CS4398 2. CHARACTERISTICS AND SPECIFICATIONS (Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics are derived from measurements taken at TA = 25 C, VA = 5.0 V, VD = 3.3 V.) SPECIFIED OPERATING CONDITIONS (AGND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Specified Temperature Range Analog power Voltage reference Digital power Serial audio interface power Control port interface power -CZ & -CZZ Symbol VA VREF VD VLS VLC TA Min 4.75 4.75 3.1 1.7 1.7 -10 Typ 5.0 5.0 3.3 3.3 3.3 - Max 5.25 5.25 5.25 5.25 5.25 70 Units V V V V V °C ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Analog power Voltage reference Digital power Serial audio interface power Control port interface power Input Current any pin except supplies Digital Input Voltage Serial audio interface Control port interface Ambient Operating Temperature (power applied) Storage Temperature Symbol VA VREF VD VLS VLC Iin VIN-LS VIN-LC TA Tstg Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 -65 Max 6.0 6.0 6.0 6.0 6.0 ±10 VLS+ 0.4 VLC+ 0.4 125 150 Units V V V V V mA V V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 8 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 ANALOG CHARACTERISTICS (Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load RL = 1 k, CL = 10 pF.) Parameter Symbol Min Typ Max Unit 114 111 - 120 117 97 94 - dB dB dB dB - -107 -97 -57 -94 -74 -34 -100 - dB dB dB dB dB dB - 120 - dB 111 108 117 114 - dB dB - -104 -94 -54 -98 - dB dB dB - 110 - dB - 0.1 - dB - 100 - ppm/°C 132%•VA 94%•VA 134%•VA 96%•VA 136%•VA 98%•VA Vpp Vpp Dynamic Performance - All PCM modes and DSD Processor mode Dynamic Range (Note 1) 24-bit A-Weighted unweighted 16-bit A-Weighted (Note 2) unweighted Total Harmonic Distortion + Noise 24-bit 16-bit (Note 2) (Note 1) THD+N 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Idle Channel Noise / Signal-to-noise ratio Dynamic Performance - Direct DSD Dynamic Range (Note 3) A-Weighted unweighted (Note 3) THD+N 0 dB -20 dB -60 dB Total Harmonic Distortion + Noise Dynamic Performance for All Modes Interchannel Isolation (1 kHz) DC Accuracy Interchannel Gain Mismatch ICGM Gain Drift Analog Output Characteristics and Specifications Full Scale Differential Output Voltage PCM, DSD processor Direct DSD mode ZOUT - 118 -  Minimum AC-Load Resistance RL - 1 - k Maximum Load Capacitance CL - 100 - pF Output Impedance Notes: 1. One LSB of triangular PDF dither is added to data. 2. Performance limited by 16-bit quantization noise. 3. DSD performance may be limited by the source recording. 0 dB-SACD = 50% modulation index. DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 9 CS4398 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) (See note 9.) Fast Roll-Off Parameter Min Typ Max Combined Digital and On-Chip Analog Filter Response - Single-Speed Mode - 48 kHz (Note 5) Passband (Note 6) to -0.01 dB corner 0 .454 to -3 dB corner 0 .499 Frequency Response 10 Hz to 20 kHz -0.01 +0.01 StopBand 0.547 StopBand Attenuation (Note 7) 102 Group Delay 9.4/Fs De-emphasis Error (Note 8) Fs = 32 kHz ±0.23 (Relative to 1 kHz) Fs = 44.1 kHz ±0.14 Fs = 48 kHz ±0.09 Combined Digital and On-Chip Analog Filter Response - Double-Speed Mode - 96 kHz (Note 5) Passband (Note 6) to -0.01 dB corner 0 .430 to -3 dB corner 0 .499 Frequency Response 10 Hz to 20 kHz -0.01 0.01 StopBand .583 StopBand Attenuation (Note 7) 80 Group Delay 4.6/Fs Combined Digital and On-Chip Analog Filter Response - Quad-Speed Mode - 192 kHz (Note 5) Passband (Note 6) to -0.01 dB corner 0 .105 to -3 dB corner 0 .490 Frequency Response 10 Hz to 20 kHz -0.01 0.01 StopBand .635 StopBand Attenuation (Note 7) 90 Group Delay 4.7/Fs - Unit Fs Fs dB Fs dB s dB dB dB Fs Fs dB Fs dB s Fs Fs dB Fs dB s 4. Slow Roll-off interpolation filter is only available in Control Port mode. 5. Filter response is guaranteed by design. 6. Response is clock-dependent and will scale with Fs. 7. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs. 8. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in StandAlone mode. 9. Amplitude vs. Frequency plots of this data are available in the “Appendix” on page 41. 10 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (Continued) Parameter Single-Speed Mode - 48 kHz (Note 5) Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 8) (Relative to 1 kHz) Double-Speed Mode - 96 kHz (Note 5) Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Quad-Speed Mode - 192 kHz (Note 5) Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Slow Roll-Off (Note 4) Min Typ Max to -0.01 dB corner to -3 dB corner (Note 7) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz to -0.01 dB corner to -3 dB corner (Note 7) to -0.01 dB corner to -3 dB corner (Note 7) Unit 0 0 -0.01 .583 64 - 6.65/Fs - 0.417 0.499 +0.01 ±0.23 ±0.14 ±0.09 Fs Fs dB Fs dB s dB dB dB 0 0 -0.01 .792 70 - 3.9/Fs .296 .499 0.01 - Fs Fs dB Fs dB s 0 0 -0.01 .868 75 - 4.2/Fs .104 .481 0.01 - Fs Fs dB Fs dB s DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE Parameter DSD Processor Mode (Note 5) Passband (Note 6) Frequency Response 10 Hz to 20 kHz Roll-off Direct DSD Mode (Note 5) Passband (Note 6) Frequency Response 10 Hz to 20 kHz DS568F3 Min Typ Max Unit to -3 dB corner 0 -0.05 27 - 50 0.05 - kHz dB dB/Oct to -0.1 dB corner to -3 dB corner 0 0 -0.1 - 26.9 176.4 0 kHz kHz dB Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 11 CS4398 SWITCHING CHARACTERISTICS (Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 20 pF) Parameters Input Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode MCLK Frequency Symbol Min Typ Max Units Fs Fs Fs 30 50 100 - 54 108 216 kHz kHz kHz See Tables 1 & 2 (page 21) for compatible frequencies MCLK Duty Cycle 40% - 60% LRCK Duty Cycle 45% 50 55% SCLK Pulse Width Low tsclkl 20 - - ns SCLK Pulse Width High tsclkh 20 - - ns tsclkw 1 -------------------- 128 Fs - - ns tsclkw 1 ----------------- 64 Fs - - ns tsclkw 2 ----------------MCLK - - ns SCLK rising to LRCK edge delay tslrd 20 - - ns SCLK rising to LRCK edge setup time tslrs 20 - - ns SDATA valid to SCLK rising setup time tsdlrs 22 - - ns SCLK rising to SDATA hold time tsdh 20 - - ns SCLK Period Single-Speed Mode Double-Speed Mode Quad-Speed Mode LRCK t sclkh t slrs t slrd t sclkl SCLK t sdlrs t sdh SDATA Figure 2. Serial Mode Input Timing 12 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 Left Channel LRCK Right Channel SCLK SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 3. Format 0 - Left-Justified up to 24-bit Data Left Channel LRCK Right Channel SCLK SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 4. Format 1 - I²S up to 24-bit Data LRCK R ight Channel Left Channel SCLK SDATA LSB MSB-1 -2 -3 -4 -5 -6 +6 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 -5 -6 +6 +5 +4 +3 +2 +1 LSB 32 clo cks Figure 5. Format 2, Right-Justified 16-Bit Data. Format 3, Right-Justified 24-Bit Data. Format 4, Right-Justified 20-Bit Data. (Available in Control Port Mode only) DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 13 CS4398 SWITCHING CHARACTERISTICS- DSD (Logic 0 = AGND = DGND; Logic 1 = VLS Volts; CL = 20 pF) Parameter MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency Symbol Min 40 80 80 1.024 2.048 20 20 -20 tsclkl tsclkh (64x Oversampled) (128x Oversampled) DSD_A / _B valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_A or DSD_B hold time DSD clock to data transition (Phase Modulation mode) tsdlrs tsdh tdpm t t Typ - Max 60 3.2 6.4 20 Unit % ns ns MHz MHz ns ns ns sclkh sclkl DSD_SCLK t sdlrs t sdh DSD_A,DSD_B Figure 6. Direct Stream Digital - Serial Audio Input Timing t dpm t dpm DSD_SCLK (128Fs) DSD_SCLK (64Fs) DSD_A, DSD_B Figure 7. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode 14 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 SWITCHING CHARACTERISTICS- CONTROL PORT - I²C FORMAT (Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 20 pF) Parameter Symbol Min Max Unit fscl - 100 kHz RST Rising Edge to Start tirs 500 - ns Bus Free-Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low Time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.7 - µs thdd 0 - µs tsud 250 - ns SCL Clock Frequency SDA Hold Time from SCL Falling (Note 10) SDA Setup Time to SCL Rising Rise Time of SCL and SDA trc, trd - 1 µs Fall Time SCL and SDA tfc, tfd - 300 ns Setup Time for Stop Condition tsusp 4.7 - µs Acknowledge Delay from SCL Falling tack 300 1000 ns 10. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. RST t irs Stop R e p e a te d S t a rt S t a rt t t rd Stop fd SDA t buf t t hdst t high t hdst fc t susp SCL t lo w t hdd t sud t ack t sust t rc Figure 8. Control Port Timing - I²C Format DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 15 CS4398 SWITCHING CHARACTERISTICS- CONTROL PORT - SPI™ FORMAT (Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 20 pF) Parameter Symbol Min Max Unit CCLK Clock Frequency fsclk - 6 MHz RST Rising Edge to CS Falling tsrs 500 - ns tspi 500 - ns CS High Time Between Transmissions tcsh 1.0 - µs CS Falling to CCLK Edge tcss 20 - ns CCLK Low Time tscl 66 - ns CCLK High Time tsch 66 - ns CDIN to CCLK Rising Setup Time tdsu 40 - ns CCLK Edge to CS Falling (Note 11) CCLK Rising to DATA Hold Time (Note 12) tdh 15 - ns Rise Time of CCLK and CDIN (Note 13) tr2 - 100 ns Fall Time of CCLK and CDIN (Note 13) tf2 - 100 ns Transition time from CCLK to CDOUT valid (Note 14) tscdov - 40 ns Time from CS rising to CDOUT high-Z (Note 15) tcscdo - 20 ns 11. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 12. Data must be held for sufficient time to bridge the transition time of CCLK. 13. For FSCK < 1 MHz. 14. CDOUT should not be sampled during this time period. 15. This time is by design and not tested. RST t srs CS t spi t css t scl t sch t csh CCLK t r2 t f2 C DIN t dsu t dh H i-Im pedance CDOUT t scdov t scdov t cscdo Figure 9. Control Port Timing - SPI Format (Read/Write) 16 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 DC ELECTRICAL CHARACTERISTICS Parameters Normal Operation (Note 16) Power Supply Current Min Typ Max Units IA Iref ID ID ILC ILS - 25 1.5 25 18 2 80 28 2 38 27 - mA mA mA mA A A - 258 192 340 240 mW mW Ipd - 200 1 1 - A mW mW PSRR - 60 40 0.5•VA 1 0.93•VA 3 VA 0 - dB dB V A V mA V V VA= 5 V (Note 17) Vref= 5 V VD = 5 V VD = 3.3 V Interface current (Note 18) Power Dissipation VA = 5 V, VD = 3.3 V Power-Down Mode (Note 19) Power Supply Current Power Dissipation VA = 5 V, VD = 3.3 V All Modes of Operation Power Supply Rejection Ratio (Note 20) Common Mode Voltage Max Current draw from VQ FILT+ Nominal Voltage Maximum MUTEC Drive Current MUTEC High-Level Output Voltage MUTEC Low-Level Output Voltage Symbol VA = 5 V, VD = 5 V VA = 5 V, VD = 5 V (1 kHz) (60 Hz) VQ IQmax (Note 21) VOH VOL 16. Normal operation is defined as RST pin = High with a 997 Hz, 0 dBFS input sampled at the highest Fs for each speed mode, and open outputs, unless otherwise specified. 17. IA measured with no loading on the AMUTEC and BMUTEC pins. 18. ILC measured with no external loading on pin 11 (SDA). 19. Power-Down mode is defined as RST pin = Low with all clock and data lines held static. 20. Valid with the recommended capacitor values on FILT+ and VQ as shown in the “Typical Connection Diagram” on page 19. 21. This current is sourced/sinked directly from the VA supply. DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 17 CS4398 DIGITAL INTERFACE SPECIFICATIONS Parameters High-Level Output Voltage (IOH = -1.2 mA) Serial I/O Control I/O Serial I/O Control I/O Control I/O VIH VIH VIL VIL VOH Min 70% 70% 80% Low-Level Output Voltage (IOL = 1.2 mA) Control I/O VOL - Input Leakage Current Input Capacitance High-Level Input Voltage Low-Level Input Voltage MUTEC auto detect input high voltage MUTEC auto detect input low voltage 18 Symbol Iin Typ 8 - Max ±10 30% 30% - Units A pF VLS VLC VLS VLC VLC - 20% VLC 30% VA VA 70% Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 3. TYPICAL CONNECTION DIAGRAM +3.3V to +5V 10 µF +5V 0.1 µF 10 µF 0.1 µF VD VA System Clock MCLK PCM Digital Audio Source AMUTEC SCLK LRCK AOUTA+ SDIN +1.8V to 0.1 µF +5V Left Channel Analog Conditioning and Mute AOUTA - VLS AOUTB+ DSD_SCLK DSD Audio Source DSD_A AOUTB - DSD_B Right Channel Analog Conditioning and Mute BMUTEC CS4398 +1.8V to 0.1 µF +5V VLC VQ M0 (AD0/CS) M1 (SDA/CDOUT) Microcontroller or stand alone pull-ups/downs 3.3 µF FILT+ 0.1 µF 100 µF 0.1 µF 33 µF M2 (SCL/CCLK) REF_GND M3 (AD1/CDIN) RST VREF DGND AGND VA Figure 10. Typical Connection Diagram DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 19 CS4398 4. APPLICATIONS 4.1 Grounding and Power Supply Decoupling As with any high resolution converter, the CS4398 requires careful attention to power supply and grounding arrangements to optimize performance. The Typical Connection Diagram shows the recommended power arrangement with VA, VD, VLS and VLC connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible. If desired, all supply pins may be connected to the same supply, but the recommended decoupling capacitors should still be placed on each supply pin. The AGND and DGND pins should be tied together with solid ground plane fill underneath the converter extending out to the GND side of the decoupling caps for VA, VD, VREF, and FILT+. This recommended layout can be seen in the CDB4398 evaluation board and datasheet. 4.2 Analog Output and Filtering The Cirrus Logic application note “Design Notes for a 2-Pole Filter with Differential Input” (AN48) discusses the second-order Butterworth filter and differential to single-ended converter topology that was implemented on the CS4398 evaluation board, CDB4398, as seen in Figure 11. The CS4398 does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response is dependent on the external analog circuitry. Figure 11. Recommended Output Filter 4.3 The MUTEC Outputs The AMUTEC and BMUTEC pins have an auto-polarity detect feature. The MUTEC output pins are high impedance at the time of reset. The external mute circuitry needs to be self-biased into an active state in order to be muted during reset. Upon release of reset, the CS4398 detects the status of the MUTEC pins (high or low) and then selects that state as the polarity to drive when the mutes become active. The externalbias voltage level that the MUTEC pins see at the time of release of reset must meet the “MUTEC auto detect input high/low voltage” specifications as outlined in the Digital Characteristics in Section 2. Figure 12 shows a single example of both an active-high and an active-low mute drive circuit. In these designs, the pull-up and pull-down resistors have been specifically chosen to meet the input high/low threshold when used with the MMUN2111 and MMUN2211 internal bias resistances of 10 k. 20 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. Figure 12. Recommended Mute Circuitry 4.4 Oversampling Modes The CS4398 operates in one of three oversampling modes based on the input sample rate. Single-Speed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed mode supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x. 4.5 Master and Serial Clock Ratios The required MCLK-to-LRCK ratio and suggested SCLK-to-LRCK ratio are outlined in Table 1. MCLK can be at any phase in regards to LRCK and SCLK. SCLK, LRCK and SDATA must meet the phase and timing relationships outlined in Section 2. Some common MCLK frequencies have been outlined in Table 2. MCLK/LRCK SCLK/LRCK LRCK Single-Speed 256, 384, 512, 768*, 1024*, 1152* 32, 48, 64, 96, 128 Fs Double-Speed 128, 192, 256, 384, 512* 32, 48, 64 Fs 64 32 (16 bits only) Fs 96 32, 48 Fs 128, 256* 32, 64 Fs 192 32, 48, 64, 96 Fs Quad-Speed *These modes are only available in Control Port mode by setting the appropriate MCLKDIV bit. Table 1. Clock Ratios DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 21 CS4398 Mode Sample MCLK (MHz) (sampleRate MCLKDIV2 MCLKDIV3 rate range) (kHz) MCLK Ratio 256x 384x 512x 768x 1024x 1152x 32 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 Single-Speed (32 to 50 kHz) 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 MCLK Ratio 128x 192x 256x 384x 512x 64 8.1920 12.2880 16.3840 24.5760 32.7680 Double-Speed (50 to 100 kHz) 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 MCLK Ratio 64x* 96x 128x 192x 256x 176.4 11.2896* 16.9344 22.5792 33.8688 45.1584 Quad-Speed (100 to 200 kHz) 192 12.2880* 18.4320 24.5760 36.8640 49.1520 These modes are only available in Control Port mode by setting the appropriate MCLKDIV bit. * This MCLK ratio limits the audio word length to 16 bits; see Table 1 on page 21 Table 2. Common Clock Frequencies 4.6 Stand-Alone Mode Settings In Stand-Alone mode (also referred to as “Hardware mode”), the device is configured using the M0 through M3 pins. These pins must be connected to either the VLC supply or ground. The Interface format is set by pins M0 and M1. The sample rate range/oversampling mode (Single/Double/Quad-Speed mode) and deemphasis are set by pins M2 and M3. The settings can be found in Tables 3 and 4. M1 0 0 1 1 M0 0 1 0 1 Description Left-Justified, up to 24-bit data I²S, up to 24-bit data Right-Justified, 16-bit Data Right-Justified, 24-bit Data Format 0 1 2 3 Figure 3 4 5 5 Table 3. Digital Interface Format, Stand-Alone Mode Options M3 0 0 1 1 M2 0 1 0 1 Description Single-Speed without De-Emphasis (32 to 50 kHz sample rates) Single-Speed with 44.1 kHz De-Emphasis; see Figure 17 on page 30 Double-Speed (50 to 100 kHz sample rates) Quad-Speed (100 to 200 kHz sample rates) Table 4. Mode Selection, Stand-Alone Mode Options The following features are always enabled in Stand-Alone mode: Auto-mute on zero data, Auto MUTEC polarity detect, ramp volume from mute to 0dB by 1/8th dB steps every LRCK (soft ramp) after reset or clock mode change, and the fast roll-off interpolation filter is used. The following features are not available in Stand-Alone mode: DSD mode, Right-Justified 20- and 18-bit serial audio interfaces, MCLK divide-by-2 and MCLK divide-by-3 (allows 1024 and 1152 clock ratios), slow rolloff interpolation filter, volume control, ATAPI mixing, 48 kHz and 32 kHz de-emphasis, and all other features enabled by registers that are not mentioned above. 22 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 4.6.1 Recommended Power-Up Sequence (Stand-Alone Mode) 1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the Control Port is reset to its default settings. 2. Bring RST high. The device will remain in a low power state and will initiate the Stand-Alone powerup sequence following approximately 218 MCLK cycles. 4.7 Control Port Mode 4.7.1 Recommended Power-Up Sequence (Control Port Mode) 1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the Control Port is reset to its default settings. 2. Bring RST high. Set the CPEN bit (Reg. 8h) prior to the completion of the Stand-Alone power-up sequence (approximately 218 MCLK cycles). Setting this bit halts the Stand-Alone power-up sequence and initializes the Control Port to its default settings. The desired register settings can be loaded while keeping the PDN bit (Reg. 8h) set to 1. 3. Clear the PDN bit to initiate the power-up sequence. If the CPEN bit is not written within the allotted time, the device will start-up in stand-alone mode and begin converting data according to the current state of the M0 to M3 pins. Since these pins are also the control port pins, an undesired mode may be entered. For this reason, if the CPEN bit is not set before the allotted time elapses, the SDIN line must be kept at static 0 (not dithered) until the device is properly configured. This will keep the device from converting data improperly. 4.7.2 Sample Rate Range/Oversampling Mode (Control Port Mode) Sample rate mode selection is determined by the FM bits (Reg. 02h). 4.7.3 Serial Audio Interface Formats (Control Port Mode) The desired serial audio interface format is selected using the DIF2:0 bits (Reg. 02h). 4.7.4 MUTEC Pins (Control Port Mode) The auto-mute polarity feature (mentioned in Section 4.3) is defeatable. The MUTEP1:0 bits in register 04h give the option to override the mute polarity which was auto detected at startup (see the Register Description section for more details). 4.7.5 Interpolation Filter (Control Port Mode) To accommodate the increasingly complex requirements of digital audio systems, the CS4398 incorporates selectable interpolation filters. A fast and a slow roll-off filter are available in each of Single-, Double-, and Quad-Speed modes. These filters have been designed to accommodate a variety of musical tastes and styles. The FILT_SEL bit (Reg. 07h) is used to select which filter is used (see the Register Description section for more details). Filter specifications can be found in Section 2, and filter response plots can be found in Figures 20 to 43 in the “Appendix” on page 41. DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 23 CS4398 4.7.6 Direct Stream Digital (DSD) Mode (Control Port Mode) In Control Port mode, the FM bits (Reg. 02h) are used to configure the device for DSD mode. The DIF bits (Reg 02h) then control the expected DSD rate and MCLK ratio. The DSD_SRC bit (Reg. 02h) selects the input pins for DSD clocks and data. During DSD operation, the PCM-related pins should either be tied low or remain active with clocks. When the DSD related pins are not being used, they should either be tied low or remain active with clocks. The DIR_DSD bit (Reg 07h) selects between two proprietary methods for DSD-to-analog conversion. The first method uses a decimation-free DSD processing technique that allows for features such as matched PCM level output, DSD volume control, and 50 kHz on-chip filter. The second method sends the DSD data directly to the on-chip switched-capacitor filter for conversion (without the above mentioned features). The DSD_PM_EN bit (Reg. 09h) selects Phase Modulation (data plus data inverted) as the style of data input. In this mode, the DSD_PM_mode bit selects whether a 128Fs or 64x clock is used for phase modulated 64x data (see Figure 13). Use of phase modulation mode may not directly affect the performance of the CS4398, but may lower the sensitivity to board-level routing of the DSD data signals. The CS4398 can detect errors in the DSD data that do not comply to the SACD specification. The STATIC_DSD and INVALID_DSD bits (Reg. 09h) allow the CS4398 to alter the incoming invalid DSD data. Depending on the error, the data may either be attenuated or replaced with a muted DSD signal (the MUTEC pins would set according to the DAMUTE bit (Reg. 04h)). More information for any of these register bits can be found in the Register Description section. The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation index) at full rated performance. Signals of +3 dB-SACD may be applied for brief periods of time; however, performance at these levels is not guaranteed. If sustained +3 dB-SACD levels are required, the digital volume control should be set to -3.0 dB. This same volume control register affects PCM output levels. There is no need to change the volume control setting between PCM and DSD in order to have the 0 dB output levels match (both 0 dBFS and 0 dB-SACD will output at -3 dB in this case). D S D P hase M odulation M ode D S D N orm al M ode BC KA D S D _S C LK (128Fs) D S D _S C LK BCKD D S D _S C LK (64Fs) BCKA (64Fs) D0 D S D _A , D S D _B D0 D1 D1 D1 D2 D S D _A , D S D _B D2 Figure 13. DSD Phase Modulation Mode Diagram 24 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 5. CONTROL PORT INTERFACE The Control Port is used to load all the internal settings. The operation of the Control Port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the Control Port pins should remain static if no operation is required. 5.1 Memory Address Pointer (MAP) 5.1.1 Memory Address Pointer (MAP) Register Detail 7 INCR 0 6 Reserved 0 5.1.2 5 Reserved 0 4 Reserved 0 3 MAP3 0 2 MAP2 0 1 MAP1 0 0 MAP0 0 INCR (Auto Map Increment Enable) Default = ‘0’ 0 - Disabled, the MAP will stay constant for successive writes 1 - Enabled, the MAP will auto increment after each byte is written, allowing block reads or writes of successive registers 5.1.3 MAP3-0 (Memory Address Pointer) Default = ‘0000’ 5.2 Enabling the Control Port On the CS4398, the Control Port pins are shared with Stand-Alone configuration pins. To enable the Control Port, the user must set the CPEN bit. This is done by performing an I²C or SPI write. Once the Control Port is enabled, these pins are dedicated to Control Port functionality. To prevent audible artifacts, the CPEN bit (see Section 7) should be set prior to the completion of the StandAlone power-up sequence, approximately 218 MCLK cycles. Setting this bit halts the stand-alone power-up sequence and initializes the Control Port to its default settings. Note, the CPEN bit can be set any time after RST goes high; however, setting this bit after the stand-alone power-up sequence has completed can cause audible artifacts. 5.3 Format Selection The Control Port has two formats: SPI and I²C, with the CS4398 operating as a slave device. If I²C operation is desired, AD0/CS should be tied to VLC or GND. If the CS4398 ever detects a high-to-low transition on AD0/CS after power-up, SPI format will automatically be selected. 5.4 I²C Format In I²C Format, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with a clock-to-data relationship as shown in Figure 14. The receiving device should send an acknowledge (ACK) after each byte received. There is no CS pin. Pins AD0 and AD1 form the partial chip address and should be tied to VLC or GND as required. The upper five bits of the 7-bit address field must be 10011. DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 25 CS4398 5.4.1 Writing in I²C Format To communicate with the CS4398, initiate a START condition of the bus (see Figure 14.). Next, send the chip address. The eighth bit of the address byte is the R/W bit (low for a write). The next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be written. To write multiple registers, continue providing a clock and data, waiting for the CS4398 to acknowledge between each byte. To end the transaction, send a STOP condition. 5.4.2 Reading in I²C Format To communicate with the CS4398, initiate a START condition of the bus (see Figure 14.). Next, send the chip address. The eighth bit of the address byte is the R/W bit (high for a read). The contents of the register pointed to by the MAP will be output after the chip address. To read multiple registers, continue providing a clock and issue an ACK after each byte. To end the transaction, send a STOP condition. N o te 1 SDA 10011 AD 1 AD 0 R /W ACK D AT A 1-8 ACK D A TA 1-8 ACK SCL S ta rt S top N o te : If o p e ra tio n is a w rite , th is b y te c o n ta in s th e M e m o ry A d d re s s P o in te r, M A P . Figure 14. Control Port Timing, I²C Format 5.5 SPI Format In SPI format, CS is the CS4398 chip select signal; CCLK is the Control Port bit clock; CDIN is the input data line from the microcontroller; CDOUT is the output data line and the chip address is 1001100. CS, CCLK, and CDIN are all inputs, and data is clocked in on the rising edge of CCLK. CDOUT is an output and is high-impedance when not actively outputting data. 5.5.1 Writing in SPI Figure 15 shows the operation of the Control Port in SPI format. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001100. The eighth bit is a read/write indicator (R/W), which must be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data that will be placed into register designated by the MAP. To write multiple registers, keep CS low and continue providing clocks on CCLK. End the read transaction by setting CS high. 26 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 CS CCLK CHIP ADDRESS CDIN 1 00 1 1 00 MAP DATA LSB MSB R/W byte 1 byte n MAP = Memory Address Pointer Figure 15. Control Port Timing, SPI Format (Write) 5.5.2 Reading in SPI Figure 16 shows the operation of the Control Port in SPI format. To read to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001100. The eighth bit is a read/write control (R/W), which must be high to read. The CDOUT line will then output the data from the register designated by the MAP. To read multiple registers, keep CS low and continue providing clocks on CCLK. End the read transaction by setting CS high. The CDOUT line will go to a high-impedance state once CS goes high. CS CC LK C H IP AD D R ES S C D IN 1001100 R /W D AT A CDOUT LSB M SB byte 1 byte n Figure 16. Control Port Timing, SPI Format (Read) DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 27 CS4398 6. Addr REGISTER QUICK REFERENCE Function 1h Chip ID default 2h Mode Control default 3h Volume, Mixing, and Inversion Control default 4h Mute Control default 5h Channel A Volume Control default 6h Channel B Volume Control default 7h Ramp and Filter Control default 8h Misc. Control default 9h Misc. Control 2 default 28 7 6 5 4 3 2 1 0 PART4 PART3 PART2 PART1 PART0 REV2 REV1 REV0 0 1 1 1 0 - - - DSD_SRC DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0 0 0 0 0 0 0 0 0 VOLB=A INVERTA INVERTB ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 0 0 0 0 1 0 0 1 PAMUTE DAMUTE MUTEC A=B MUTE_A MUTE_B Reserved MUTEP1 MUTEP0 1 1 0 0 0 0 0 0 VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 0 0 0 0 0 0 0 0 VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 0 0 0 0 0 0 0 0 SZC1 SZC0 RMP_UP RMP_DN 1 Reserved FILT_SEL Reserved 1 0 1 PDN CPEN FREEZE 0 1 0 0 0 0 Reserved Reserved Reserved Reserved STATIC_ DSD 0 0 0 0 1 0 MCLKDIV2 MCLKDIV3 Reserved DIR_DSD 0 0 Reserved Reserved 0 0 0 INVALID_ DSD_PM_ DSD_PM_ DSD MODE EN 0 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 0 0 DS568F3 CS4398 7. REGISTER DESCRIPTION ** All register access is R/W unless specified otherwise** 7.1 Chip ID - Register 01h 7 PART4 6 PART3 5 PART2 4 PART1 3 PART0 2 REV2 1 REV1 0 REV0 0 1 1 1 0 - - - Function: This register is Read-Only. Bits 7 through 3 are the part number ID, which is 01110b (14h), and the remaining Bits (2 through 0) are for the chip revision (Rev. A = 000, Rev. B = 001, ...) 7.2 Mode Control 1 - Register 02h 7 6 5 4 3 2 1 0 DSD_SRC 0 DIF2 0 DIF1 0 DIF0 0 DEM1 0 DEM0 0 FM1 0 FM0 0 7.2.1 DSD Input Source Select (DSD_SRC) BIT 7 Function: When set to 0 (default), the dedicated DSD pins will be the active DSD inputs. When set to 1, the source for DSD inputs will be as follows: DSDA input on SDATA pin DSDB input on LRCK pin DSD_SCLK input on SCLK pin The dedicated DSD pins must be tied low while not in use. 7.2.2 Digital Interface Format (DIF2:0) BITs 6-4 Function: These bits select the interface format for the serial audio input. The Functional Mode bits determine whether PCM or DSD mode is selected. PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format, and the options are detailed in Figures 3 through 5. DIF2 DIF1 DIF0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Description Left-Justified, up to 24-bit data I²S, up to 24-bit data Right-Justified, 16-bit data Right-Justified, 24-bit data Right-Justified, 20-bit data Right-Justified, 18-bit data Reserved Reserved Format Figure 0 (Default) 1 2 3 4 5 3 4 5 5 5 5 Table 5. Digital Interface Formats - PCM Mode DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 29 CS4398 DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required Master Clock to DSD data rate is defined by the Digital Interface Format pins. DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIF0 0 1 0 1 0 1 0 1 Description 64x oversampled DSD data with a 4x MCLK to DSD data rate (Default) 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate Table 6. Digital Interface Formats - DSD Mode 7.2.3 De-Emphasis Control (DEM1:0) BITs 3-2. Gain dB Default = 0 00 - No De-emphasis 01 - 44.1 kHz De-emphasis 10 - 48 kHz De-emphasis 11 - 32 kHz De-emphasis T1=50 µs 0dB T2 = 15 µs -10dB Function: Selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Figure 17) F1 3.183 kHz F2 Frequency 10.61 kHz Figure 17. De-Emphasis Curve Notes: De-emphasis is only available in Single-Speed Mode. 7.2.4 Functional Mode (FM1:0) BITs 1-0 Default = 00 00 - Single-Speed Mode (30 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) 11 - Direct Stream Digital Mode Function: Selects the required range of input sample rates or DSD Mode. 7.3 30 Volume Mixing and Inversion Control - Register 03h 7 VOLB=A 6 INVERT A 5 INVERT B 4 ATAPI4 3 ATAPI3 2 ATAPI2 1 ATAPI1 0 ATAPI0 0 0 0 0 1 0 0 1 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 7.3.1 Channel B Volume = Channel A Volume (VOLB=A) Bit 7 Function: When set to 0 (default), the AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes. When set to 1, the volume on both AOUTA and AOUTB are determined by the A Channel Attenuation and Volume Control Bytes, and the B Channel Bytes are ignored. 7.3.2 Invert Signal Polarity (Invert_A) Bit 6 Function: When set to 1, this bit inverts the signal polarity of channel A. When set to 0 (default), this function is disabled. 7.3.3 Invert Signal Polarity (Invert_B) Bit 5 Function: When set to 1, this bit inverts the signal polarity of channel B. When set to 0 (default), this function is disabled. 7.3.4 ATAPI Channel Mixing and Muting (ATAPI4:0) Bits 4-0 Default = 01001 - AOUTA=aL, AOUTB=bR (Stereo) Function: The CS4398 implements the channel-mixing functions of the ATAPI CD-ROM specification. Refer to Table and Figure 18 for additional information. A Channel Volume Control Left Channel Audio Data  Right Channel Audio Data MUTE AoutA MUTE AoutB  B Channel Volume Control Figure 18. ATAPI Block Diagram DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 31 CS4398 32 ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTA AOUTB 0 0 0 0 0 MUTE MUTE 0 0 0 0 1 MUTE bR 0 0 0 1 0 MUTE bL 0 0 0 1 1 MUTE b[(L+R)/2] 0 0 1 0 0 aR MUTE 0 0 1 0 1 aR bR 0 0 1 1 0 aR bL 0 0 1 1 1 aR b[(L+R)/2] 0 1 0 0 0 aL MUTE 0 1 0 0 1 aL bR 0 1 0 1 0 aL bL 0 1 0 1 1 aL b[(L+R)/2] 0 1 1 0 0 a[(L+R)/2] MUTE 0 1 1 0 1 a[(L+R)/2] bR 0 1 1 1 0 a[(L+R)/2] bL 0 1 1 1 1 a[(L+R)/2] b[(L+R)/2] 1 0 0 0 0 MUTE MUTE 1 0 0 0 1 MUTE bR 1 0 0 1 0 MUTE bL 1 0 0 1 1 MUTE [(bL+aR)/2] 1 0 1 0 0 aR MUTE 1 0 1 0 1 aR bR 1 0 1 1 0 aR bL 1 0 1 1 1 aR [(aL+bR)/2] 1 1 0 0 0 aL MUTE 1 1 0 0 1 aL bR 1 1 0 1 0 aL bL 1 1 0 1 1 aL [(aL+bR)/2] 1 1 1 0 0 [(aL+bR)/2] MUTE 1 1 1 0 1 [(aL+bR)/2] bR 1 1 1 1 0 [(bL+aR)/2] bL 1 1 1 1 1 [(aL+bR)/2] [(aL+bR)/2] Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 7.4 Mute Control - Register 04h 7 6 5 4 3 2 1 0 PAMUTE 1 DAMUTE 1 MUTEC A=B 0 MUTE_A 0 MUTE_B 0 Reserved 0 MUTEP1 0 MUTEP0 0 7.4.1 PCM Auto-Mute (PAMUTE) Bit 7 Function: When set to 1 (default), the Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained, and the Mute Control pin will go active during the mute period. When set to 0, this function is disabled. 7.4.2 DSD Auto-Mute (DAMUTE) Bit 6 Function: When set to 1 (default), the Digital-to-Analog converter output will mute following the reception of 256 repeated 8-bit DSD mute patterns (as defined in the SACD specification). A single bit not fitting the repeated mute pattern (mentioned above) will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained, and the Mute Control pin will go active during the mute period. When set to 0, this function is disabled. 7.4.3 AMUTEC = BMUTEC (MUTEC A=B) Bit 5 Function: When set to 0 (default), the AMUTEC and BMUTEC pins operate independently. When set to 1, the individual controls for AMUTEC and BMUTEC are internally connected through an AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins will go active only when the requirements for both AMUTEC and BMUTEC are valid. 7.4.4 A Channel Mute (MUTE_A) Bit 4 B Channel Mute (MUTE_B) Bit 3 Function: When set to 1, the Digital-to-Analog converter output will mute. The quiescent voltage on the output will be retained. The muting function is affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. The corresponding MUTEC pin will go active following any ramping due to the soft and zero cross function. When set to 0 (default), this function is disabled. DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 33 CS4398 7.4.5 MUTE Polarity and DETECT (MUTEP1:0) Bits 1-0 Default = 00 00 - Auto polarity detect, selected from AMUTEC pin 01 - Reserved 10 - Active low mute polarity 11 - Active high mute polarity Function: Auto mute polarity detect (00) See section 4.3 on page 20 for description. Active low mute polarity (10) When RST is low, the outputs are high-impedance and will need to be biased active. Once reset has been released and after this bit is set, the MUTEC output pins will be active low polarity. Active high mute polarity (11) At reset time, the outputs are high-impedance and will need to be biased active. Once reset has been released and after this bit is set, the MUTEC output pins will be active high polarity. 7.5 Channel A Volume Control - Register 05h 7.6 Channel B Volume Control - Register 06h 7 VOL7 0 7.6.1 6 VOL6 0 5 VOL5 0 4 VOL4 0 3 VOL3 0 2 VOL2 0 1 VOL1 0 0 VOL0 0 Digital Volume Control (VOL7:0) Bits 7-0 Default = 00h (0 dB) Function: The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments from 0 to -127.5 dB. Volume settings are decoded as shown in Table 7. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. Note that the values in the volume setting column in Table 7 are approximate. The actual attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/12. Binary Code Decimal Value Volume Setting 00000000 00000001 00000110 11111111 0 1 6 255 0 dB -0.5 dB -3.0 dB -127.5 dB Table 7. Example Digital Volume Settings 34 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 7.7 Ramp and Filter Control - Register 07h 7 6 5 4 3 2 1 0 SZC1 1 SZC0 0 RMP_UP 1 RMP_DN 1 Reserved 0 FILT_SEL 0 Reserved 0 DIR_DSD 0 7.7.1 Soft Ramp AND Zero Cross CONTROL (SZC1:0) Bits 7-6 Default = 10 SZC1 SZC0 PCM Description DSD Description 0 0 Immediate Change Immediate Change 0 1 Zero Cross 1 0 Soft Ramp 1 1 Soft Ramp on Zero Crossings Soft Ramp Function: Immediate Change When Immediate Change is selected, all level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level-change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp PCM Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp DSD Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 512 DSD_SCLK periods (1024 periods if 128x DSD_SCLK is used). Soft Ramp and Zero Cross Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 35 CS4398 7.7.2 Soft Volume Ramp-Up after Error (RMP_UP) Bit 5 Function: An un-mute will be performed after executing an LRCK/MCLK ratio change or error, and after changing the Functional Mode. When set to 1 (default), this un-mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. When set to 0, an immediate un-mute is performed in these instances. Notes: 7.7.3 For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit. Soft Ramp-Down before Filter Mode Change (RMP_DN) Bit 4 Function: If either the FILT_SEL or DEM bits are changed the DAC will stop conversion for a period of time to change its filter values. This bit selects how the data is affected prior to and after the change of the filter values. When set to 1 (default), a mute will be performed prior to executing a filter mode change and an un-mute will be performed after executing the filter mode change. This mute and un-mute are affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. When set to 0, an immediate mute is performed prior to executing a filter mode change. Notes: 7.7.4 For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit. Interpolation Filter Select (FILT_SEL) Bit 2 Function: When set to 0 (default), the Interpolation Filter has a fast roll off. When set to 1, the Interpolation Filter has a slow roll off. The specifications for each filter can be found in the Analog characteristics table, and response plots can be found in figures 20 to 43 found in the “Appendix” on page 41. 7.7.5 Direct DSD Conversion (DIR_DSD) Bit 0 Function: When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control functions. When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion. In this mode, the full-scale DSD and PCM levels will not be matched (see Section 2), the dynamic range performance may be reduced, the volume control is inactive, and the 50 kHz low pass filter is not available (see Section 2 for filter specifications). 36 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 7.8 Misc. Control - Register 08h 7 6 5 4 3 2 1 0 PDN 1 CPEN 0 FREEZE 0 MCLKDIV2 0 MCLKDIV3 0 Reserved 0 Reserved 0 Reserved 0 7.8.1 Power Down (PDN) Bit 7 Function: When set to 1 (default), the entire device enters a low-power state, and the contents of the control registers is retained. The power-down bit defaults to ‘1’ on power-up and must be disabled before normal operation in Control Port mode can occur. This bit is ignored if CPEN is not set. 7.8.2 Control Port Enable (CPEN) Bit 6 Function: This bit is set to 0 by default, allowing the device to power-up in Stand-Alone Mode. Control Port Mode can be accessed by setting this bit to 1. This allows operation of the device to be controlled by the registers, and the pin definitions will conform to Control Port Mode. 7.8.3 Freeze Controls (Freeze) Bit 5 Function: When set to 1, this function allows modifications to be made to the registers without the changes taking effect until FREEZE is set back to 0. To make multiple changes in the Control Port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. When set to 0 (default), register changes take effect immediately. 7.8.4 Master Clock Divide-by-2 ENABLE (MCLKDIV2) Bit 4 Function: When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry. When set to 0 (default), MCLK is unchanged. 7.8.5 Master Clock Divide-by-3 ENABLE (MCLKDIV3) Bit 3 Function: When set to 1, the MCLKDIV bit enables a circuit that divides the externally applied MCLK signal by 3 prior to all other internal circuitry. When set to 0 (default), MCLK is unchanged. DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 37 CS4398 7.9 Misc. Control - Register 09h 7 6 5 4 3 2 Reserved Reserved Reserved Reserved STATIC_DSD INVALID_DSD 0 0 0 0 1 0 7.9.1 1 0 DSD_PM_MODE 0 DSD_PM_EN 0 Static DSD Detect (Static_DSD) Bit 3 Function: When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected, sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE register. When set to 0, this function is disabled. 7.9.2 Invalid DSD Detect (Invalid_DSD) Bit 2 Function: When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if detected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE register. When set to 0 (default), this function is disabled. 7.9.3 DSD Phase Modulation Mode Select (DSD_PM_mode) Bit 1 Function: When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for phase modulation mode. (See Figure 13 on page 24) When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for phase modulation mode. 7.9.4 DSD Phase Modulation Mode Enable (DSD_PM_EN) Bit 0 Function: When set to 1, DSD phase modulation input mode is enabled and the DSD_PM_MODE bit should be set accordingly. When set to 0 (default), this function is disabled (DSD normal mode). 38 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 8. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) THD+N is the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 9. REFERENCES 1. CDB4398 Evaluation Board Datasheet 2. “Design Notes for a 2-Pole Filter with Differential Input”. Cirrus Logic Application Note AN48 3. The I²C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998. http://www.semiconductors.philips.com “ DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 39 CS4398 10.PACKAGE DIMENSIONS 10.1 28-TSSOP N D E11 A2 E A  e b2 A1 SIDE VIEW L END VIEW SEATING PLANE 1 2 3 TOP VIEW DIM A A1 A2 b D E E1 e L µ MIN -0.002 0.03150 0.00748 0.378 BSC 0.248 0.169 -0.020 0° Inches NOM -0.004 0.035 0.0096 0.382 BSC 0.2519 0.1732 0.026 BSC 0.024 4° MAX 0.47 0.006 0.04 0.012 0.386 BSC 0.256 0.177 -0.029 8° MIN -0.05 0.80 0.19 9.60 BSC 6.30 4.30 -0.50 0° Millimeters NOM -0.10 0.90 0.245 9.70 BSC 6.40 4.40 0.65 BSC 0.60 4° Note MAX 1.20 0.15 1.00 0.30 9.80 BSC 6.50 4.50 -0.75 8° 2,3 1 1 JEDEC #: MO-153 Controlling Dimension is Millimeters. Figure 19. 28L TSSOP (4.4 mm Body) Package Drawing Notes: 1. “D” and “E1” are reference datums and do not include mold flash or protrusions, but do include mold mismatch and are measured at the parting line. Mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. THERMAL CHARACTERISTICS AND SPECIFICATIONS Parameters Package Thermal Resistance (Note 1) 28-TSSOP Symbol JA JC Min - Typ 37 13 Max - Units °C/Watt °C/Watt 1. JA is specified according to JEDEC specifications for multi-layer PCBs. 40 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 0 0 −20 −20 −40 −40 Amplitude (dB) Amplitude (dB) 11.APPENDIX −60 −60 −80 −80 −100 −100 −120 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 −120 0.4 1 Figure 20. Single-Speed (fast) Stopband Rejection 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 21. Single-Speed (fast) Transition Band 0.02 0 −1 0.015 −2 0.01 −3 0.005 Amplitude (dB) Amplitude (dB) −4 −5 −6 0 −0.005 −7 −0.01 −8 −0.015 −9 −10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 −0.02 0.55 0 0 −20 −20 −40 −40 −60 −80 −100 −100 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 1 Figure 24. Single-Speed (slow) Stopband Rejection DS568F3 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 −60 −80 −120 0.4 0.05 Figure 23. Single-Speed (fast) Passband Ripple Amplitude (dB) Amplitude (dB) Figure 22. Single-Speed (fast) Transition Band (detail) 0 −120 0.4 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 25. Single-Speed (slow) Transition Band Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 41 CS4398 0.02 0 −1 0.015 −2 0.01 0.005 −4 Amplitude (dB) Amplitude (dB) −3 −5 −6 0 −0.005 −7 −0.01 −8 −0.015 −9 −10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 −0.02 0.55 Figure 26. Single-Speed (slow) Transition Band (detail) 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 0 20 20 40 40 Amplitude (dB) Amplitude (dB) 0.05 Figure 27. Single-Speed (slow) Passband Ripple 0 60 60 80 80 100 100 120 0 120 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 1 Figure 28. Double-Speed (fast) Stopband Rejection 0.4 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 29. Double-Speed (fast) Transition Band 0 0.02 1 0.015 2 0.01 0.005 4 Amplitude (dB) Amplitude (dB) 3 5 6 0 0.005 7 0.01 8 0.015 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 Figure 30. Double-Speed (fast) Transition Band (detail) 42 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 Figure 31. Double-Speed (fast) Passband Ripple Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 0 20 20 40 40 Amplitude (dB) Amplitude (dB) 0 60 60 80 80 100 100 120 120 0.2 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 1 Figure 32. Double-Speed (slow) Stopband Rejection 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 Figure 33. Double-Speed (slow) Transition Band 0 0.02 1 0.015 2 0.01 0.005 4 Amplitude (dB) Amplitude (dB) 3 5 6 0 0.005 7 0.01 8 0.015 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.02 0.55 Figure 34. Double-Speed (slow) Transition Band (detail) 40 40 Amplitude (dB) Amplitude (dB) 20 60 0.15 0.2 Frequency(normalized to Fs) 0.25 0.3 0.35 60 80 80 100 100 120 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 1 Figure 36. Quad-Speed (fast) Stopband Rejection DS568F3 0.1 0 20 0.2 0.05 Figure 35. Double-Speed (slow) Passband Ripple 0 120 0 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 Figure 37. Quad-Speed (fast) Transition Band Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 43 CS4398 0.2 0 1 0.15 2 0.1 3 Amplitude (dB) Amplitude (dB) 0.05 4 5 6 0 0.05 7 0.1 8 0.15 9 10 0.45 0.2 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 0 0.05 Figure 38. Quad-Speed (fast) Transition Band (detail) 0.1 0.15 Frequency(normalized to Fs) 0.2 0.25 Figure 39. Quad-Speed (fast) Passband Ripple 0 0 20 40 40 Amplitude (dB) Amplitude (dB) 20 60 60 80 80 100 100 120 120 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 1 0.1 Figure 40. Quad-Speed (slow) Stopband Rejection 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 0.9 Figure 41. Quad-Speed (slow) Transition Band 0.02 0 1 0.015 2 0.01 0.005 4 Amplitude (dB) Amplitude (dB) 3 5 6 0 0.005 7 0.01 8 0.015 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 Figure 42. Quad-Speed (slow) Transition Band (detail) 44 0.02 0 0.02 0.04 0.06 0.08 Frequency(normalized to Fs) 0.1 0.12 Figure 43. Quad-Speed (slow) Passband Ripple Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. DS568F3 CS4398 Release Date Changes F1 July 2005 Changed datasheet status to Final. Updated legal text. F2 Mar 2015 Added order numbers for QFN packages on Ordering Information. Added pinout figures and numbers for QFN package in Section 1 “Pinout Drawing.” Updated footnote in Analog Characteristics table. Added package dimensions figure and table in Section 10.2. Added QFN entry in Thermal Characteristics and Specifications table. Updated legal text. F3 May 2021 Corrected DSD_SCLK pulse width spec in Switching Characteristics- DSD. Removed QFN package. Updated the important notice section on the last page. Table 8. Revision Table Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. 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DS568F3 Copyright  2005–2021 Cirrus Logic, Inc. and Cirrus Logic International Semiconductor Ltd. 45