CS4525_08

CS4525 30 W Digital Audio Amplifier with Integrated ADC Digital Amplifier Features Fully Integrated Power MOSFETs No Heatsink Required – Programmable Power Foldback on Thermal Warning – High Efficiency > 100 dB Dynamic Range < 0.1% THD+N @ 1 W Configurable Outputs (10% THD+N) – 1 x 30 W into 4 Ω, Parallel Full-Bridge – 2 x 15 W into 8 Ω, Full-Bridge – 2 x 7 W into 4 Ω, Half-Bridge + 1 x 15 W into 8 Ω, Full-Bridge Built-In Protection with Error Reporting – Overcurrent / Undervoltage / Thermal Overload Shutdown – Thermal Warning Reporting PWM Popguard® for Half-Bridge Mode Click-free Start-up Programmable Channel Delay for System Noise & Radiated Emissions Management 2.5 V to 5 V ADC Features Stereo, 24-bit, 48 kHz Conversion Multi-bit Architecture 95 dB Dynamic Range (A-wtd) -86 dB THD+N Supports 2 Vrms Input with Passive Components System Features Asynchronous 2-channel Digital Serial Port 32 kHz to 96 kHz Input Sample Rates Operation with On-chip Oscillator Driver or Applied SYS_CLK at 18.432, 24.576 or 27.000 MHz Integrated Sample Rate Converter (SRC) – Eliminates Clock-jitter Effects – Input Sample Rate Independent Operation – Simplifies System Integration Spread Spectrum PWM Modulation – Reduces EMI Radiated Energy Low Quiescent Current (Features continued on page 2) 8 V to 18 V VP System Clock Crystal Driver I/O Stereo Analog In Serial Audio Clocks & Data Serial Audio Data I/O Serial Audio Clocks & Data HP Detect/Mute Reset Interrupt I²C or Hardware Configuration Crystal Oscillator Driver Audio Processing Parametric EQ High-Pass PWM Gate Drive Gate Drive Amplifier Out 1 Multi-bit ∆Σ ADC Serial Audio Input Port Serial Audio Delay Interface Auxiliary Serial Port Bass/Treble Adaptive Loudness Compensation 2-Ch Mixer 2.1 Bass Mgr Linkwitz-Riley Crossover De-Emphasis Volume Multi-bit ∆Σ Modulator with Integrated Sample Rate Converter Amplifier Out 2 Gate Drive Amplifier Out 3 Gate Drive Amplifier Out 4 PGND Error Protection Register /Hardware Configuration Thermal Warning Thermal Feedback Over Current Under Voltage PWM Modulator Output 1 PWM Modulator Output 2 Preliminary Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved) JUL '08 DS726PP3 CS4525 Software Mode System Features Digital Audio Processing – 5 Programmable Parametric EQ Filters – Selectable High-pass Filter – Bass/Treble Tone Control – Adaptive Loudness Compensation – 2-channel Mixer – 2.1 Bass Management – 24 dB/octave Linkwitz-Riley Crossover Filters – De-emphasis Filter Selectable Serial Audio Interface Formats – Left-justified up to 24-bit – I²S up to 24-bit – Right-justified 16-, 18-, 20-, 24-bits Digital Serial Connection to Additional CS4525 or DACs for Subwoofer Digital Interface to External Lip-sync Delay PWM Switch Rate Shifting Eliminates AM Frequency Interference Digital Volume Control with Soft Ramp – +24 to -103 dB in 0.5 dB steps Programmable Peak Detect and Limiter 2-Channel Logic-level PWM Output – Programmable Channel Mapping – Can Drive an External PWM Amplifier, Headphone Amplifier, or Line-out Amplifier – Integrated Headphone Detection Flexible Power Output Configurations Thermal Foldback for Interruption-free Power-stage Protection – Supports Internal and External Power Stages Operation from On-chip Oscillator Driver or Applied Systems Clock Supports I²C® Host Control Interface Common Applications Integrated Digital TV’s Flat Panel TV Monitors Computer/TV Monitors Mini/Micro Shelf Systems Digital Powered Speakers Portable Docking Stations Computer Desktop Audio General Description The CS4525 is a stereo analog or digital input PWM high efficiency Class D amplifier audio system with an integrated stereo analog-to-digital (A/D) converter. The stereo power amplifiers can deliver up to 15 W per channel into 8 Ω speakers from a small space-saving 48-pin QFN package. The PWM amplifier can achieve greater than 85% efficiency. The package is thermally enhanced for optimal heat dissipation which eliminates the need for a heatsink. The power stage outputs can be configured as two fullbridge channels for 2 x 15 W operation, two half-bridge channels and one full-bridge channel for 2 x 7 W + 1 x 15 W operation, or one parallel full-bridge channel for 1 x 30 W operation. The CS4525 integrates on-chip over-current, under-voltage, and over-temperature protection and error reporting as well as a thermal warning indicator and programmable foldback of the output power to allow cooling. The main digital serial port on the CS4525 can support asynchronous operation with the integrated on-chip sample rate converter (SRC) which eases system integration. The SRC allows for a fixed PWM switching frequency regardless of incoming sample rate as well as optimal clocking for the A/D modulators. An on-chip oscillator driver eliminates the need for an external crystal oscillator circuit, reducing overall design cost and conserving circuit board space. The CS4525 automatically uses the on-chip oscillator driver in the absence of an applied master clock. The CS4525 is available in a 48-pin QFN package in Commercial grade (0° to +70° C). The CRD4525-Q1 4layer, 1 oz. copper and CRD4525-D1 2-layer, 1 oz. copper customer reference designs are also available. Please refer to “Ordering Information” on page 97 for complete ordering information. Hardware Mode System Features 2-Channel Stereo Full Bridge Power Outputs Analog and Digital Inputs I²S and Left-justified Serial Input Formats Thermal Foldback for Interruption-free Protection of Internal Power Stage Operation from Applied Systems Clock External Mute Input 2 DS726PP3 CS4525 TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE MODE .......................................................................................... 8 2. PIN DESCRIPTIONS - HARDWARE MODE ....................................................................................... 10 2.1 Digital I/O Pin Characteristics ........................................................................................................ 12 3. TYPICAL CONNECTION DIAGRAMS ................................................................................................. 13 4. TYPICAL SYSTEM CONFIGURATION DIAGRAMS ........................................................................... 15 5. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 18 6. APPLICATIONS ................................................................................................................................... 26 6.1 Software Mode ............................................................................................................................... 26 6.1.1 System Clocking ................................................................................................................... 26 6.1.1.1 SYS_CLK Input Clock Mode .................................................................................... 26 6.1.1.2 Crystal Oscillator Mode ............................................................................................ 27 6.1.2 Power-Up and Power-Down ................................................................................................. 28 6.1.2.1 Power-Up Sequence ................................................................................................ 28 6.1.2.2 Power-Down Sequence ............................................................................................ 28 6.1.3 Input Source Selection .......................................................................................................... 29 6.1.4 Digital Sound Processing ...................................................................................................... 29 6.1.4.1 Pre-Scaler ................................................................................................................. 30 6.1.4.2 Digital Signal Processing High-Pass Filter ............................................................... 30 6.1.4.3 Channel Mixer .......................................................................................................... 30 6.1.4.4 De-Emphasis ............................................................................................................ 31 6.1.4.5 Tone Control ............................................................................................................. 31 6.1.4.6 Parametric EQ .......................................................................................................... 33 6.1.4.7 Adaptive Loudness Compensation ........................................................................... 34 6.1.4.8 Bass Management .................................................................................................... 35 6.1.4.9 Volume and Muting Control ...................................................................................... 36 6.1.4.10 Peak Signal Limiter ................................................................................................. 37 6.1.4.11 Thermal Limiter ....................................................................................................... 39 6.1.4.12 Thermal Foldback ................................................................................................... 40 6.1.4.13 2-Way Crossover & Sensitivity Control ................................................................... 42 6.1.5 Auxiliary Serial Output .......................................................................................................... 43 6.1.6 Serial Audio Delay & Warning Input Port .............................................................................. 44 6.1.6.1 Serial Audio Delay Interface ..................................................................................... 44 6.1.6.2 External Warning Input Port ..................................................................................... 44 6.1.7 Powered PWM Outputs ........................................................................................................ 45 6.1.7.1 Output Channel Configurations ................................................................................ 45 6.1.7.2 PWM Popguard Transient Control ............................................................................ 45 6.1.8 Logic-Level PWM Outputs .................................................................................................... 46 6.1.8.1 Recommended PWM_SIG Power-Up Sequence for an External PWM Amplifier .... 47 6.1.8.2 Recommended PWM_SIG Power-Down Sequence for an External PWM Amplifier 47 6.1.8.3 Recommended PWM_SIG Power-Up Sequence for Headphone & Line-Out .......... 48 6.1.8.4 Recommended PWM_SIG Power-Down Sequence for Headphone & Line-Out ..... 48 6.1.8.5 PWM_SIG Logic-Level Output Configurations ......................................................... 49 6.1.9 PWM Modulator Configuration .............................................................................................. 50 6.1.9.1 PWM Channel Delay ................................................................................................ 50 6.1.9.2 PWM AM Frequency Shift ........................................................................................ 51 6.1.10 Headphone Detection & Hardware Mute Input ................................................................... 51 6.1.11 Interrupt Reporting .............................................................................................................. 53 6.1.12 Automatic Power Stage Shut-Down ................................................................................... 53 6.2 Hardware Mode ............................................................................................................................. 54 6.2.1 System Clocking ................................................................................................................... 54 6.2.2 Power-Up and Power-Down ................................................................................................. 54 6.2.2.1 Power-Up Sequence ................................................................................................ 54 DS726PP3 3 CS4525 6.2.2.2 Power-Down Sequence ............................................................................................ 55 6.2.3 Input Source Selection .......................................................................................................... 55 6.2.4 PWM Channel Delay ............................................................................................................ 55 6.2.5 Digital Signal Flow ................................................................................................................ 56 6.2.5.1 High-Pass Filter ........................................................................................................ 56 6.2.5.2 Mute Control ............................................................................................................. 56 6.2.5.3 Warning and Error Reporting .................................................................................... 56 6.2.6 Thermal Foldback ................................................................................................................. 57 6.2.7 Automatic Power Stage Shut-Down ..................................................................................... 58 6.3 PWM Modulators and Sample Rate Converters ............................................................................ 58 6.4 Output Filters ................................................................................................................................. 59 6.4.1 Half-Bridge Output Filter ....................................................................................................... 59 6.4.2 Full-Bridge Output Filter (Stereo or Parallel) ........................................................................ 60 6.5 Analog Inputs ................................................................................................................................. 61 6.6 Serial Audio Interfaces ................................................................................................................... 62 6.6.1 I²S Data Format .................................................................................................................... 62 6.6.2 Left-Justified Data Format .................................................................................................... 62 6.6.3 Right-Justified Data Format .................................................................................................. 63 6.7 Integrated VD Regulator ................................................................................................................ 63 6.8 I²C Control Port Description and Timing ........................................................................................ 64 7. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 65 7.1 Power Supply, Grounding .............................................................................................................. 65 7.2 Output Filter Layout ....................................................................................................................... 65 7.3 QFN Thermal Pad .......................................................................................................................... 65 8. REGISTER QUICK REFERENCE ........................................................................................................ 66 9. REGISTER DESCRIPTIONS ................................................................................................................ 69 9.1 Clock Configuration (Address 01h) ................................................................................................ 69 9.1.1 SYS_CLK Output Enable (EnSysClk) ................................................................................... 69 9.1.2 SYS_CLK Output Divider (DivSysClk) .................................................................................. 69 9.1.3 Clock Frequency (ClkFreq[1:0]) ............................................................................................ 69 9.1.4 HP_Detect/Mute Pin Active Logic Level (HP/MutePol) ......................................................... 70 9.1.5 HP_Detect/Mute Pin Mode (HP/Mute) .................................................................................. 70 9.1.6 Modulator Phase Shifting (PhaseShift) ................................................................................. 70 9.1.7 AM Frequency Shifting (FreqShift) ....................................................................................... 70 9.2 Input Configuration (Address 02h) ................................................................................................. 71 9.2.1 Input Source Selection (ADC/SP) ......................................................................................... 71 9.2.2 ADC High-Pass Filter Enable (EnAnHPF) ............................................................................ 71 9.2.3 Serial Port Sample Rate (SPRate[1:0]) - Read Only ............................................................ 71 9.2.4 Input Serial Port Digital Interface Format (DIF [2:0]) ............................................................ 71 9.3 AUX Port Configuration (Address 03h) .......................................................................................... 72 9.3.1 Enable Aux Serial Port (EnAuxPort) ..................................................................................... 72 9.3.2 Delay & Warning Port Configuration (DlyPortCfg[1:0]) ......................................................... 72 9.3.3 Aux/Delay Serial Port Digital Interface Format (AuxI²S/LJ) .................................................. 72 9.3.4 Aux Serial Port Right Channel Data Select (RChDSel[1:0]) ................................................. 72 9.3.5 Aux Serial Port Left Channel Data Select (LChDSel[1:0]) .................................................... 73 9.4 Output Configuration (Address 04h) ............................................................................................. 73 9.4.1 Output Configuration (OutputCfg[1:0]) .................................................................................. 73 9.4.2 PWM Signals Output Data Select (PWMDSel[1:0]) .............................................................. 73 9.4.3 Channel Delay Settings (OutputDly[3:0]) .............................................................................. 73 9.5 Foldback and Ramp Configuration (Address 05h) ......................................................................... 74 9.5.1 Select VP Level (SelectVP) .................................................................................................. 74 9.5.2 Enable Thermal Foldback (EnTherm) ................................................................................... 74 9.5.3 Lock Foldback Adjust (LockAdj) ........................................................................................... 74 9.5.4 Foldback Attack Delay (AttackDly[1:0]) ................................................................................ 75 4 DS726PP3 CS4525 9.5.5 Enable Foldback Floor (EnFloor) .......................................................................................... 75 9.5.6 Ramp Speed (RmpSpd[1:0]) ................................................................................................ 75 9.6 Mixer / Pre-Scale Configuration (Address 06h) ............................................................................. 75 9.6.1 Pre-Scale Attenuation (PreScale[2:0]) .................................................................................. 75 9.6.2 Right Channel Mixer (RChMix[1:0]) ...................................................................................... 76 9.6.3 Left Channel Mixer (LChMix[1:0]) ......................................................................................... 76 9.7 Tone Configuration (Address 07h) ................................................................................................. 76 9.7.1 De-Emphasis Control (DeEmph) .......................................................................................... 76 9.7.2 Adaptive Loudness Compensation Control (Loudness) ....................................................... 76 9.7.3 Digital Signal Processing High-Pass Filter (EnDigHPF) ....................................................... 77 9.7.4 Treble Corner Frequency (TrebFc[1:0]) ................................................................................ 77 9.7.5 Bass Corner Frequency (BassFc[1:0]) ................................................................................. 77 9.7.6 Tone Control Enable (EnToneCtrl) ....................................................................................... 77 9.8 Tone Control (Address 08h) ........................................................................................................... 78 9.8.1 Treble Gain Level (Treb[3:0]) ................................................................................................ 78 9.8.2 Bass Gain Level (Bass[3:0]) ................................................................................................. 78 9.9 2.1 Bass Manager/Parametric EQ Control (Address 09h) ............................................................. 78 9.9.1 Freeze Controls (Freeze) ...................................................................................................... 78 9.9.2 Hi-Z PWM_SIG Outputs (HiZPSig) ....................................................................................... 79 9.9.3 Bass Cross-Over Frequency (BassMgr[2:0]) ........................................................................ 79 9.9.4 Enable Channel B Parametric EQ (EnChBPEq) ................................................................... 79 9.9.5 Enable Channel A Parametric EQ (EnChAPEq) ................................................................... 79 9.10 Volume and 2-Way Cross-Over Configuration (Address 55h) ..................................................... 80 9.10.1 Soft Ramp and Zero Cross Control (SZCMode[1:0]) .......................................................... 80 9.10.2 Enable 50% Duty Cycle for Mute Condition (Mute50/50) ................................................... 80 9.10.3 Auto-Mute (AutoMute) ........................................................................................................ 80 9.10.4 Enable 2-Way Crossover (En2Way) ................................................................................... 81 9.10.5 2-Way Cross-Over Frequency (2WayFreq[2:0]) ................................................................. 81 9.11 Channel A & B: 2-Way Sensitivity Control (Address 56h) ............................................................ 81 9.11.1 Channel A and Channel B Low-Pass Sensitivity Adjust (LowPass[3:0]) ............................ 81 9.11.2 Channel A and Channel B High-Pass Sensitivity Adjust (HighPass[3:0]) ........................... 82 9.12 Master Volume Control (Address 57h) ........................................................................................ 82 9.12.1 Master Volume Control (MVol[7:0]) .................................................................................... 82 9.13 Channel A and B Volume Control (Address 58h & 59h) .............................................................. 83 9.13.1 Channel X Volume Control (ChXVol[7:0]) ........................................................................... 83 9.14 Sub Channel Volume Control (Address 5Ah) .............................................................................. 83 9.14.1 Sub Channel Volume Control (SubVol[7:0]) ....................................................................... 83 9.15 Mute/Invert Control (Address 5Bh) .............................................................................................. 84 9.15.1 ADC Invert Signal Polarity (InvADC) .................................................................................. 84 9.15.2 Invert Channel PWM Signal Polarity (InvChX) ................................................................... 84 9.15.3 Invert Sub PWM Signal Polarity (InvSub) ........................................................................... 84 9.15.4 ADC Channel Mute (MuteADC) .......................................................................................... 84 9.15.5 Independent Channel A & B Mute (MuteChX) .................................................................... 84 9.15.6 Sub Channel Mute (MuteSub) ............................................................................................ 85 9.16 Limiter Configuration 1 (Address 5Ch) ......................................................................................... 85 9.16.1 Maximum Threshold (Max[2:0]) .......................................................................................... 85 9.16.2 Minimum Threshold (Min[2:0]) ............................................................................................ 85 9.16.3 Peak Signal Limit All Channels (LimitAll) ............................................................................ 86 9.16.4 Peak Detect and Limiter Enable (EnLimiter) ....................................................................... 86 9.17 Limiter Configuration 2 (Address 5Dh) ......................................................................................... 87 9.17.1 Limiter Release Rate (RRate[5:0]) ...................................................................................... 87 9.18 Limiter Configuration 3 (Address 5Eh) ......................................................................................... 87 9.18.1 Enable Thermal Limiter (EnThLim) ..................................................................................... 87 9.18.2 Limiter Attack Rate (ARate[5:0]) ......................................................................................... 87 DS726PP3 5 CS4525 9.19 Power Control (Address 5Fh) ...................................................................................................... 88 9.19.1 Automatic Power Stage Retry (AutoRetry) ......................................................................... 88 9.19.2 Enable Over-Current Protection (EnOCProt) ...................................................................... 88 9.19.3 Select VD Level (SelectVD) ................................................................................................ 88 9.19.4 Power Down ADC (PDnADC) ............................................................................................. 88 9.19.5 Power Down PWM Power Output X (PDnOutX) ................................................................. 89 9.19.6 Power Down (PDnAll) ......................................................................................................... 89 9.20 Interrupt (Address 60h) ............................................................................................................... 89 9.20.1 SRC Lock State Transition Interrupt (SRCLock) ................................................................ 90 9.20.2 ADC Overflow Interrupt (ADCOvfl) ..................................................................................... 90 9.20.3 Channel Overflow Interrupt (ChOvfl) .................................................................................. 90 9.20.4 Amplifier Error Interrupt Bit (AmpErr) .................................................................................. 91 9.20.5 Mask for SRC State (SRCLockM) ...................................................................................... 91 9.20.6 Mask for ADC Overflow (ADCOvflM) .................................................................................. 91 9.20.7 Mask for Channel X and Sub Overflow (ChOvflM) ............................................................. 91 9.20.8 Mask for Amplifier Error (AmpErrM) ................................................................................... 92 9.21 Interrupt Status (Address 61h) - Read Only ................................................................................. 92 9.21.1 SRC State Transition (SRCLockSt) .................................................................................... 92 9.21.2 ADC Overflow (ADCOvflSt) ................................................................................................ 92 9.21.3 Sub Overflow (SubOvflSt) ................................................................................................... 92 9.21.4 Channel X Overflow (ChXOvflSt) ........................................................................................ 93 9.21.5 Ramp-Up Cycle Complete (RampDone) ............................................................................ 93 9.22 Amplifier Error Status (Address 62h) - Read Only ....................................................................... 93 9.22.1 Over-Current Detected On Channel X (OverCurrX) ........................................................... 93 9.22.2 External Amplifier State (ExtAmpSt) ................................................................................... 93 9.22.3 Under Voltage / Thermal Error State (UVTE[1:0]) .............................................................. 94 9.23 Device I.D. and Revision (Address 63h) - Read Only .................................................................. 94 9.23.1 Device Identification (DeviceID[4:0]) ................................................................................... 94 9.23.2 Device Revision (RevID[2:0]) .............................................................................................. 94 10. PARAMETER DEFINITIONS .............................................................................................................. 95 11. REFERENCES .................................................................................................................................... 95 12. PACKAGE DIMENSIONS .................................................................................................................. 96 13. THERMAL CHARACTERISTICS ....................................................................................................... 97 13.1 Thermal Flag ................................................................................................................................ 97 14. ORDERING INFORMATION .............................................................................................................. 97 15. REVISION HISTORY .......................................................................................................................... 98 LIST OF FIGURES Figure 1.Typical Connection Diagram - Software Mode ........................................................................... 13 Figure 2.Typical Connection Diagram - Hardware Mode .......................................................................... 14 Figure 3.Typical System Configuration 1 .................................................................................................. 15 Figure 4.Typical System Configuration 2 .................................................................................................. 15 Figure 5.Typical System Configuration 3 .................................................................................................. 16 Figure 6.Typical System Configuration 4 .................................................................................................. 17 Figure 7.Serial Audio Input Port Timing .................................................................................................... 21 Figure 8.AUX Serial Port Interface Master Mode Timing .......................................................................... 22 Figure 9.SYS_CLK Timing from Reset ..................................................................................................... 23 Figure 10.PWM_SIGX Timing ................................................................................................................... 23 Figure 11.Control Port Timing - I²C ........................................................................................................... 24 Figure 12.Typical SYS_CLK Input Clocking Configuration ....................................................................... 26 Figure 13.Typical Crystal Oscillator Clocking Configuration ..................................................................... 27 Figure 14.Digital Signal Flow .................................................................................................................... 29 Figure 15.De-Emphasis Filter ................................................................................................................... 31 6 DS726PP3 CS4525 Figure 16.Bi-Quad Filter Architecture ........................................................................................................ 33 Figure 17.Peak Signal Detection & Limiting .............................................................................................. 37 Figure 18.Foldback Process ..................................................................................................................... 40 Figure 19.Popguard Connection Diagram ................................................................................................. 46 Figure 20.2-Channel Full-Bridge PWM Output Delay ............................................................................... 50 Figure 21.3-Channel PWM Output Delay .................................................................................................. 50 Figure 22.Typical SYS_CLK Input Clocking Configuration ....................................................................... 54 Figure 23.Hardware Mode PWM Output Delay ......................................................................................... 55 Figure 24.Hardware Mode Digital Signal Flow .......................................................................................... 56 Figure 25.Foldback Process ..................................................................................................................... 57 Figure 26.Output Filter - Half-Bridge ......................................................................................................... 59 Figure 27.Output Filter - Full-Bridge .......................................................................................................... 60 Figure 28.Recommended Unity Gain Input Filter ...................................................................................... 61 Figure 29.Recommended 2 VRMS Input Filter ........................................................................................... 61 Figure 30.I²S Serial Audio Formats ........................................................................................................... 62 Figure 31.Left-Justified Serial Audio Formats ........................................................................................... 62 Figure 32.Right-Justified Serial Audio Formats ......................................................................................... 63 Figure 33.Control Port Timing, I²C Write ................................................................................................... 64 Figure 34.Control Port Timing, I²C Read ................................................................................................... 64 LIST OF TABLES Table 1. I/O Power Rails ........................................................................................................................... 12 Table 2. Bass Shelving Filter Corner Frequencies .................................................................................... 31 Table 3. Treble Shelving Filter Corner Frequencies ................................................................................. 32 Table 4. Bass Management Cross-Over Frequencies .............................................................................. 35 Table 5. 2-Way Cross-Over Frequencies .................................................................................................. 42 Table 6. Auxiliary Serial Port Data Output ................................................................................................ 43 Table 7. Nominal Switching Frequencies of the Auxiliary Serial Output ................................................... 43 Table 8. PWM Power Output Configurations ............................................................................................ 45 Table 9. Typical Ramp Times for Various VP Voltages ............................................................................ 46 Table 10. PWM Logic-Level Output Configurations .................................................................................. 49 Table 11. PWM Output Switching Rates and Quantization Levels ........................................................... 51 Table 12. Output of PWM_SIG Outputs .................................................................................................... 52 Table 13. SYS_CLK Frequency Selection ................................................................................................ 54 Table 14. Input Source Selection .............................................................................................................. 55 Table 15. Serial Audio Interface Format Selection .................................................................................... 55 Table 16. Thermal Foldback Enable Selection ......................................................................................... 57 Table 17. PWM Output Switching Rates and Quantization Levels ........................................................... 58 Table 18. Low-Pass Filter Components - Half-Bridge ............................................................................... 59 Table 19. DC-Blocking Capacitors Values - Half-Bridge ........................................................................... 59 Table 20. Low-Pass Filter Components - Full-Bridge ............................................................................... 60 Table 21. Power Supply Configuration and Settings ................................................................................. 63 DS726PP3 7 CS4525 1. PIN DESCRIPTIONS - SOFTWARE MODE DLY_SDIN/EX_TWR AUX_LRCK/AD0 AUX_SDOUT DLY_SDOUT PWM_SIG1 AUX_SCLK SYS_CLK PWM_SIG2 PGND 38 XTO XTI 48 47 46 45 44 43 42 41 40 39 PGND 37 INT SCL SDA LRCK SCLK SDIN HP_DETECT/MUTE RST LVD DGND VD_REG VD 1 2 3 4 5 6 36 35 34 33 32 31 VP OUT1 PGND PGND OUT2 VP VP OUT3 PGND PGND OUT4 VP Thermal Pad 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Top-Down (Through Package) View 48-Pin QFN Package 30 29 28 27 26 25 AINL OCREF AFILTR PGND Pin Name INT SCL SDA LRCK SCLK SDIN HP_DETECT/ MUTE RST Pin # 1 2 3 4 5 6 7 8 Pin Description Interrupt (Output) - Indicates an interrupt condition has occurred. Serial Control Port Clock (Input) - Serial clock for the I²C control port. Serial Control Data (Input/Output) - Bi-directional data I/O for the I²C control port. Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Clock (Input) - Serial bit clock for the serial audio interface. Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Headphone Detect / Mute (Input) - Headphone detection or mute input signal as configured via the I²C control port. Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when this pin is driven low. 8 RAMP_CAP AGND FILT+ AFILTL AINR VQ VA_REG PGND DS726PP3 CS4525 LVD DGND VD_REG VD VA_REG AGND FILT+ VQ AFILTL AFILTR AINL AINR OCREF 9 10 11 12 13 14 15 16 17 18 19 20 21 VD Voltage Level Indicator (Input) - Identifies the voltage level attached to VD. When applying 5.0 V to VD, LVD must be connected to VD. When applying 2.5 V or 3.3 V to VD, LVD must be DGND. Digital Ground (Input) - Ground for the internal logic and digital I/O. Core Logic Power (Output) - Internally generated low voltage power supply for digital logic. Power (Input) - Positive power supply for the internal regulators and digital I/O. Analog Power (Output) - Internally generated positive power for the analog section and I/O. Analog Ground (Input) - Ground reference for the internal analog section and I/O. Positive Voltage Reference (Output) - Positive reference voltage for the internal ADC sampling circuits. Common Mode Voltage (Output) - Filter connection for internal common mode voltage. Antialias Filter Connection (Output) - Antialias filter connection for ADC inputs. Analog Input (Input) - The full-scale input level is specified in the ADC Analog Characteristics specification table. Over Current Reference Setting (Input) - Sets the reference for over current detection. PGND 22,23 27,28 Power Ground (Input) - Ground for the individual output power half-bridge devices. 33,34 37,38 24 Output Ramp Capacitor (Input) - Used by the PWM Popguard Transient Control to suppress the initial pop in half-bridge-configured outputs. RAMP_CAP VP OUT4 OUT3 OUT2 OUT1 PWM_SIG2 PWM_SIG1 DLY_SDOUT DLY_SDIN/ EX_TWR AUX_SDOUT AUX_SCLK AUX_LRCK/ AD0 SYS_CLK XTO XTI Thermal Pad 25,30, High Voltage Power (Input) - High voltage power supply for the individual half-bridge devices. 31,36 26 29 32 35 39 40 41 42 PWM Output (Output) - Amplified PWM power outputs. Logic Level PWM Output (Output) - Logic Level PWM switching signals. Delay Serial Audio Data Out (Output) - Output for two’s complement serial audio data. Delay Serial Audio Data Input (Input) - Input for two’s complement serial audio data. External Thermal Warning (Input) - Input for an external thermal warning signal. Configurable via the I²C control port. Auxiliary Port Serial Audio Data Out (Output) - Output for two’s complement auxiliary port serial data. Auxiliary Port Serial Clock (Output) - Serial clock for the auxiliary port serial interface. Auxiliary Port Left Right Clock (Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. AD0 (Input) - Sets the LSB of the I²C device address. Sensed on the release of RST. System Clock (Input/Output) -Clock source for the internal logic, processing, and modulators. This pin should be connected to through a 10kΩ to ground when unused. Crystal Oscillator Output (Output) - Crystal oscillator driver output. Crystal Oscillator Input (Input) - Crystal oscillator driver input. Thermal Pad - Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page 65 for more information. 43 44 45 46 47 48 - DS726PP3 9 CS4525 2. PIN DESCRIPTIONS - HARDWARE MODE SYS_CLK ERRUVTE EN_TFB ERROC PGND 38 I2S/LJ TSTO TSTI 48 47 46 45 44 43 42 41 40 39 PGND 37 TSTO TSTO TWR CLK_FREQ0 CLK_FREQ1 ADC/SP LRCK SCLK SDIN MUTE RST LVD DGND VD_REG VD 1 2 3 4 5 6 36 35 34 33 32 31 VP OUT1 PGND PGND OUT2 VP VP OUT3 PGND PGND OUT4 VP Thermal Pad 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Top-Down (Through Package) View 48-Pin QFN Package 30 29 28 27 26 25 AINL OCREF AFILTR PGND Pin Name CLK_FREQ0 CLK_FREQ1 ADC/SP LRCK SCLK SDIN MUTE RST Pin # 1 2 3 4 5 6 7 8 Pin Description Clock Frequency (Input) - Determines the frequency of the clock expected to be driven into the SYS_CLK pin. CLK_FREQ1 must be connected to DGND. ADC/Serial Port (Input) - Selects between the Analog to Digital Converter and the Serial Port for audio input. Selects the ADC when high or the serial port when low. Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Clock (Input) - Serial bit clock for the serial audio interface. Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Mute (Input) - The PWM outputs will output silence as a 50% duty cycle signal when this pin is driven low. Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when this pin is driven low. 10 RAMP_CAP AGND FILT+ AFILTL AINR VQ VA_REG PGND DS726PP3 CS4525 LVD DGND VD_REG VD VA_REG AGND FILT+ VQ AFILTL AFILTR AINL AINR OCREF 9 10 11 12 13 14 15 16 17 18 19 20 21 VD Voltage Level Indicator (Input) - Identifies the voltage level attached to VD. When applying 5.0 V to VD, LVD must be connected to VD. When applying 2.5 V or 3.3 V to VD, LVD must be connected to DGND. Digital Ground (Input) - Ground for the internal logic and I/O. Core Logic Power (Output) - Internally generated low voltage power supply for digital logic. Digital Power (Input) - Positive power supply for the internal regulators and digital I/O. Analog Power (Output) - Internally generated positive power for the analog section and I/O. Analog Ground (Input) - Ground reference for the internal analog section and I/O. Positive Voltage Reference (Output) - Positive reference voltage for the internal ADC sampling circuits. Common Mode Voltage (Output) - Filter connection for internal common mode voltage. Antialias Filter Connection (Output) - Antialias filter connection for ADC inputs. Analog Input (Input) - The full-scale input level is specified in the ADC Analog Characteristics specification table. Over Current Reference Setting (Input) - Sets the reference for over current detection. PGND 22,23 27,28 Power Ground (Input) - Ground for the individual output power half-bridge devices. 33,34 37,38 24 Output Ramp Capacitor (Input) - This pin should be connected directly to VP in hardware mode. 25,30, High Voltage Power (Input) - High voltage power supply for the individual half-bridge devices. 31,36 26 29 32 35 39 40 41 42 43 44 45 46 47 48 - RAMP_CAP VP OUT4 OUT3 OUT2 OUT1 TSTO TWR ERRUVTE ERROC EN_TFB I2S/LJ SYS_CLK TSTO TSTI Thermal Pad PWM Output (Output) - Amplified PWM power outputs. Test Output (Output) - These pins are outputs used for the Logic Level PWM switching signals available only in software mode. They must be left unconnected for hardware mode operation. Thermal Warning Output (Output) - Thermal warning output. Thermal and Undervoltage Error Output (Output) - Error flag for thermal shutdown and undervoltage. Overcurrent Error Output (Output) - Overcurrent error flag. Enable Thermal Feedback (Input) - Enables the thermal foldback feature when high. I²S/Left Justified (Input) - Selects between I²S and Left-Justified data format for the serial input port. Selects I²S when high and LJ when low. System Clock (Input/Output) -Clock source for the delta-sigma modulators. Test Output (Output) - This pin is an output used for the crystal oscillator driver available only in software mode. It must be left unconnected for normal hardware mode operation. Test Input (Input) - This pin is an input used for the crystal oscillator driver available only in software mode. It must be tied to digital ground for normal hardware mode operation. Thermal Pad - Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page 65 for more information. DS726PP3 11 CS4525 2.1 Digital I/O Pin Characteristics Pin Name I/O Driver Receiver The logic level for each input is set by its corresponding power supply and should not exceed the maximum ratings. Power Pin Supply Number Software Mode VD 1 2 3 7 41 42 43 44 45 39 40 1 2 3 7 41 42 43 44 45 4 5 6 8 9 46 26 29 32 35 VD_REG INT SCL SDA HP_DETECT MUTE DLY_SDOUT DLY_SDIN EX_TWR AUX_SDOUT AUX_SCLK AUX_LRCK PWM_SIG2 PWM_SIG1 CLK_FREQ0 CLK_FREQ1 ADC/SP MUTE TWR ERRUVTE ERROC EN_TFB I²S/LJ LRCK SCLK SDIN RST LVD SYS_CLK OUT4 OUT3 OUT2 OUT1 Output Input Input/Output Input Input Output Input Input Output Output Output Output Output Input Input Input Input Output Output Output Input Input Input Input Input Input Input Input/Output Output Output Output Output 2.5 V-5.0 V, Open Drain 2.5 V-5.0 V, Open Drain 2.5 V-5.0 V, CMOS 2.5 V-5.0 V, CMOS 2.5 V-5.0 V, CMOS 2.5 V-5.0 V, CMOS 2.5 V, CMOS 2.5 V, CMOS 2.5 V-5.0 V, Open Drain 2.5 V-5.0 V, Open Drain 2.5 V-5.0 V, Open Drain 2.5 V-5.0 V, CMOS 8.0 V-18.0 V Power MOSFET 8.0 V-18.0 V Power MOSFET 8.0 V-18.0 V Power MOSFET 8.0 V-18.0 V Power MOSFET 2.5 V-5.0 V, with Hysteresis 2.5 V-5.0 V, with Hysteresis 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V - Hardware Mode VD All Modes VD VP Table 1. I/O Power Rails 12 DS726PP3 CS4525 3. TYPICAL CONNECTION DIAGRAMS +3.3 or +5 V 10 µF 0.1 µF 470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 470 µF +8 V to +18 V 12 25 30 31 36 VP VP VP Analog Audio Inputs VD RAMP_CAP 35 Analog Audio Switch 19 20 AINL AINR OUT1 35 OUT2 32 VP Analog Monitor Output Output Filter CS4525 Crystal 24.576 MHz 48 47 XTI XTO OUT3 29 MPEG Audio Processor - or HDMI Receiver 22 kΩ 46 SYS_CLK SCLK LRCK SDIN HP_DETECT/MUTE OUT4 26 Output Filter 5 4 6 7 PWM_SIG1 40 43 Line Output - or - AUX_SDOUT AUX_LRCK/AD0 AUX_SCLK DLY_SDOUT DLY_SDIN LVD 9 45 PWM_SIG2 39 Lip-Synch Delay NJU26902 Headphone Output 44 41 42 22 kΩ† VD or GND 16.2 kΩ OCREF 21 +2.5V 0.1 µF 11 VD_REG FILT+ 15 VA_REG 13 0.1 µF 10 µF 10 µF 10 µF VD 2 kΩ* 22 kΩ 2 kΩ* AGND 14 SCL SDA INT RST D D D D D D D D D G N PG N PG N PG N PG N PG N PG N PG N PG N D 150 pF 150 pF 1 µF 2 AFILTA 17 AFILTB 18 VQ 16 MicroController 3 1 8 *Note: Resistors are required for I²C control port operation. † Note: On release of RST, AD0 is read as input on the AUX_LRCK line. 10 22 23 27 28 33 34 37 38 Figure 1. Typical Connection Diagram - Software Mode DS726PP3 13 CS4525 +8 V to +18 V 10 µF 0.1 µF 470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 470 µF +3.3 or +5 V 12 25 30 31 36 VP VP VP Analog Audio Inputs VD RAMP_CAP 35 Analog Audio Switch 19 20 AINL OUT1 35 AINR OUT2 32 VP Output Filter Analog Monitor Output CS4525 5 SCLK LRCK SDIN OUT3 29 OUT4 26 Audio Processor 4 6 Output Filter Clock 24.576 MHz 46 SYS_CLK CLK_FREQ0 CLK_FREQ1 TSTO 40 1 2 VD 22 kΩ 22 kΩ 22 kΩ TSTO 39 41 42 43 TWR ERRUVTE ERROC EN_TFB I²S/LJ ADC/SP MUTE RST AGND 14 FILT+ 15 VA_REG 13 0.1 µF 10 µF 10 µF LVD 9 VD or GND 16.2 kΩ MicroController 44 45 3 7 8 OCREF 21 47 48 TSTO TSTI 150 pF 150 pF 1 µF AFILTA 17 AFILTB 18 11 VD_REG VQ 16 10 µF 0.1 µF D D D D D D PG N 37 38 D N PG N PG N PG N N D 10 22 23 27 28 33 34 Figure 2. Typical Connection Diagram - Hardware Mode 14 PG N N D G PG PG PG N D DS726PP3 CS4525 4. TYPICAL SYSTEM CONFIGURATION DIAGRAMS 2 x 7 W Stereo + 1 x 15 W Subwoofer Main Tuner Monitor Out PIP Tuner CS4525 Analog In Digital In Control Port Audio Delay Delay Port Aux Out SYS_CLK Power Foldback PWM_SIG1 PWM_SIG2 Gate Drive Gate Drive A/V In 1 Digital Out Control Port Left Speaker Right Speaker A/V In 2 A/V Switch MPEG Decoder Clock Out 27 MHz Gate Drive Gate Drive Subwoofer Crystal In Crystal Out A/V In X HP/ Line Out Figure 3. Typical System Configuration 1 2 x 15 W Stereo + 1 x 30 W Subwoofer Main Tuner Analog Out Monitor Out PIP Tuner Var/Fixed Out A/V In 1 Sound Processor A/V Switch Analog In Control Port Audio Delay CS4525 Analog In Digital In Control Port Delay Port Aux Out Gate Drive A/V In 2 Left Speaker Gate Drive A/V In X 27 MHz Crystal In Crystal Out Clock Out Gate Drive SYS_CLK Power Foldback PWM_SIG1 PWM_SIG2 Gate Drive Right Speaker Analog Out CS4412A PWM In 22 kΩ Gate Drive Gate Drive Subwoofer Gate Drive Status Out Gate Drive Figure 4. Typical System Configuration 2 DS726PP3 15 CS4525 2 x 30 W Stereo + 1 x 30 W Subwoofer Main Tuner Analog Out Monitor Out PIP Tuner Var/Fixed Out A/V In 1 Sound Processor A/V Switch Analog In Control Port Audio Delay CS4525 Analog In Digital In Control Port Delay Port Aux Out Gate Drive A/V In 2 Gate Drive Left Speaker Gate Drive A/V In X 18.432 MHz Crystal In Crystal Out Clock Out SYS_CLK Gate Drive Power Foldback PWM_SIG1 PWM_SIG2 Analog Out CS4412A PWM In 22 kΩ Gate Drive Gate Drive Right Speaker Gate Drive Status Out Gate Drive CS4412A PWM In 22 kΩ Gate Drive Gate Drive Subwoofer Gate Drive Status Out Gate Drive Figure 5. Typical System Configuration 3 16 DS726PP3 CS4525 2 x 15 W Bi-Amp Stereo with Subwoofer Output Main Tuner Analog Out Monitor Out PIP Tuner Var/Fixed Out A/V In 1 Sound Processor A/V Switch Analog In Digital Out Control Port Audio Delay CS4525 Analog In Digital In Control Port Delay Port Aux Out Gate Drive A/V In 2 Left Tweeter Gate Drive A/V In X 18.432 MHz Crystal In Crystal Out Clock Out Gate Drive SYS_CLK Power Foldback PWM_SIG1 PWM_SIG2 Gate Drive Left Woofer Analog Out Sub Out CS4525 Analog In Digital In Control Port Delay Port Aux Out SYS_CLK Gate Drive Power Foldback PWM_SIG1 PWM_SIG2 Gate Drive Right Tweeter Gate Drive Gate Drive Right Woofer Figure 6. Typical System Configuration 4 DS726PP3 17 CS4525 5. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS AGND = DGND = PGND = 0 V; all voltages with respect to ground. Parameters DC Power Supply Digital and Analog Core (Note 1) VD VD VD Amplifier Outputs VP TA TJ 2.375 3.135 4.75 8.0 0 0 2.5 3.3 5.0 2.625 3.465 5.25 18.0 +70 +125 V V V V °C °C Symbol Min Nom Max Units Temperature Ambient Temperature Junction Temperature Notes: 1. For VD = 2.5 V, VA_REG and VD_REG must be connected to VD. See section 6.7 on page 63 for details. ABSOLUTE MAXIMUM RATINGS AGND = DGND = PGND = 0 V; all voltages with respect to ground. Parameters DC Power Supply Power Stage Power Stage Digital and Analog Core Outputs Switching and Under Load No Output Switching VP VP VD -0.3 -0.3 -0.3 19.8 23.0 6.0 V V V Symbol Min Max Units Inputs Input Current Analog Input Voltage Digital Input Voltage (Note 2) (Note 3) (Note 3) Iin VINA VIND AGND - 0.7 -0.3 ±10 VA_REG + 0.7 VD + 0.4 mA V V Temperature Ambient Operating Temperature - Power Applied Commercial Storage Temperature TA Tstg -20 -65 +85 +150 °C °C WARNING: Operation at conditions beyond the Recommended Operating Conditions may affect device reliability, and functional operation beyond Recommended Operating Conditions is not implied. Notes: 2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current. 18 DS726PP3 CS4525 ANALOG INPUT CHARACTERISTICS Test Conditions (unless otherwise specified): AGND = DGND = PGND = 0 V; All voltages with respect to ground; TA = 25°C; VD = 3.3 V; Input Signal: 1 kHz sine wave through the recommended passive input filter shown in Figure 28 on page 61; Capacitor values connected to AFILTA, AFILTB, FILT+, VQ, VD_REG, and VA_REG as shown in Figure 1 on page 13; Sample Frequency = 48 kHz; 10 Hz to 20 kHz Measurement Bandwidth; Power outputs in power-down state (PDnOut1 = 1, PDnOut2 = 1, PDnOut3/4 = 1). Parameter Dynamic Range (Note 4) Total Harmonic Distortion + Noise A-weighted unweighted -1 dB -20 dB -60 dB Min 90 87 0.786*VD 0.590*VD 0.398*VD 40 Typ 95 92 -86 -72 -32 0.05 ±100 90 0.827*VD 0.621*VD 0.419*VD - Max -77 0.868*VD 0.652*VD 0.440*VD - Unit dB dB dB dB dB dB ppm/°C dB Vpp Vpp Vpp kΩ DC Accuracy Interchannel Gain Mismatch Gain Drift Interchannel Isolation Full-scale Input Voltage Input Impedance VD = 2.5V (Note 5) VD = 3.3V VD = 5.0V (Note 6) Notes: 4. Referred to the typical full-scale voltage 5. For VD = 2.5 V, VA_REG and VD_REG must be connected to VD. See section 6.7 on page 63 for details. 6. Measured between AINx and AGND. ADC DIGITAL FILTER CHARACTERISTICS Parameter Passband (Frequency Response) (Note 7) Passband Ripple Stopband Stopband Attenuation Total Group Delay to -0.1 dB corner Min 0 -0.09 (Note 7) 0.6677 48.4 -3.0 dB -0.13 dB 20 Hz - Typ 2.7/Fs 3.7 24.2 10 105/Fs Max 0.4948 0 0.17 - Unit Fs dB Fs dB s Hz Hz Deg dB s High-Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time Notes: 7. Filter response is clock dependent and scales with the ADC sampling frequency (Fs). With a 27.000 MHz or 24.576 MHz XTAL/SYS_CLK, Fs is equal to the applied clock divided by 512. With an 18.432 MHz XTAL/SYS_CLK, Fs is equal to the applied clock divided by 384. DS726PP3 19 CS4525 PWM POWER OUTPUT CHARACTERISTICS Test Conditions (unless otherwise specified): AGND = DGND = PGND = 0 V; All voltages with respect to ground; TA = 25°C; VD = 3.3 V; VP = 18 V; RL = 8 Ω for full-bridge, RL = 4 Ω for half-bridge and parallel full-bridge; OutputDly[3:0] = 1111; PhaseShift = 1 for half-bridge, PhaseShift = 0 for full-bridge and parallel full-bridge; Input Signal: full-scale 997 Hz sine wave through serial audio input port, 48 kHz sample rate; Capacitor values connected to AFILTA, AFILTB, FILT+, VQ, VD_REG, and VA_REG as shown in Figure 1 on page 13; PWM Switch Rate = 384 kHz; 10 Hz to 20 kHz Measurement Bandwidth; Performance measurements taken through AES17 filter. Parameters Power Output per Channel Stereo Full-Bridge Half-Bridge Parallel Full-Bridge Total Harmonic Distortion + Noise Stereo Full-Bridge Half-Bridge Parallel Full-Bridge Dynamic Range Stereo Full-Bridge Half-Bridge Parallel Full-Bridge MOSFET On Resistance Efficiency Minimum Output Pulse Width Rise Time of OUTx Fall Time of OUTx PWM Output Over-Current Error Trigger Point ICE Junction Thermal Warning Trigger Point Junction Thermal Error Trigger Point VP Under-Voltage Error Falling Trigger Point VP Under-Voltage Error Rising Trigger Point TTW TTE VUVFALL VUVRISE TA = 25°C TA = 25°C RDS(ON) h PWmin tr tf DYR THD+N PO Symbol Conditions THD+N < 10% THD+N < 1% THD+N < 10% THD+N < 1% THD+N < 10% THD+N < 1% PO = 1 W PO = 0 dBFS = 11.3 W PO = 1 W PO = 0 dBFS = 5.0 W PO = 1 W PO = 0 dBFS = 22.6 W PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted Id = 0.5 A, TJ = 50°C PO = 2 x 15 W, RL = 8 Ω No Load Resistive Load Resistive Load TA = 25°C, OCREF = 16.2 kΩ TA = 25°C, OCREF = 18 kΩ TA = 25°C, OCREF = 22 kΩ Min - Typ 15 12 7 5.5 30 23.5 0.05 0.10 0.12 0.28 0.1 0.3 102 99 99 96 102 99 280 85 50 20 20 2.5 2.1 1.7 105 125 4.7 4.95 Max 4.9 5.4 Units W W W W W W % % % % % % dB dB dB dB dB dB mΩ % ns ns ns A A A °C °C V V 20 DS726PP3 CS4525 SERIAL AUDIO INPUT PORT SWITCHING SPECIFICATIONS AGND = DGND = PGND = 0 V; TA = 25°C; VD = 3.3 V; Inputs: Logic 0 = DGND; Logic 1 = VD. Parameters Supported Input Sample Rates LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Setup Time Before SCLK Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge RST pin Low Pulse Width (Note 10) ts(LK-SK) ts(SD-SK) th (Note 8),(Note 9) 1/tp Symbol FSI Min 28.5 39.5 39.5 86.4 45 FSI*2*Nbits 45 40 25 10 1 Nominal 32 44.1 48 96 - Max 35.2 52.8 52.8 105.6 55 FCLK/3 55 - Units kHz kHz kHz kHz % Hz % ns ns ns ms Notes: 8. FCLK is the frequency of the crystal connected to the XTI/XTO pins or the input SYS_CLK signal. 9. Nbits is the number of bits per sample of the serial digital input. 10. After powering up the CS4525, RST should be held low until the power supplies and clocks are stable. // LRCK ts(LK-SK) // // tr ts(SD-SK) tf th MSB-1 // tP SCLK SDIN // MSB // Figure 7. Serial Audio Input Port Timing DS726PP3 21 CS4525 AUX SERIAL AUDIO I/O PORT SWITCHING SPECIFICATIONS AGND = DGND = PGND = 0 V; TA = 25°C; VD = 3.3 V; AUX_SDOUT & DLY_SDOUT CL = 15 pF; Inputs: Logic 0 = DGND; Logic 1 = VD; (Note 11). Parameters Input Source: Analog Inputs (Internal ADC) Output Sample Rate (Note 16) AUX_LRCK Duty Cycle AUX_LRCK Period AUX_SCLK Frequency (Note 16) AUX_SCLK Duty Cycle AUX_SCLK Period ClkFreq[1:0] = ‘00’ ClkFreq[1:0] = ‘01’ FSCLKO ClkFreq[1:0] = ‘10’ ClkFreq[1:0] = ‘00’ ClkFreq[1:0] = ‘01’ ClkFreq[1:0] = ‘10’ FSO FS-In = 32kHz, 44.1 kHz, 48 kHz FS-In = 96 kHz (Note 13) (Note 12, 13) FS-In = 32kHz, 44.1 kHz, 48 kHz FS-In = 96 kHz FS-In = 32kHz, 44.1 kHz, 48 kHz FS-In = 96 kHz tLTSF tSRDV tDIS tDIH 45 TSI - TCLK 30 TSCLKI - TCLK 2*TSCLKI - TCLK 25 10 FCLK/384 FCLK/512 FCLK/512 50 1/FSO 48*FSO 64*FSO 64*FSO 50 1/FSCLKO FSI FSI/2 TSI FSCLKI FSCLKI/2 TSCLKI 2*TSCLKI 55 TSI + TCLK 70 TSCLKI + TCLK 2*TSCLKI + TCLK 20 TCLK + 20 Hz Hz Hz % s Hz Hz Hz % s Hz Hz % s Hz Hz % s s Symbol Min Typ Max Units Input Source: Serial Audio Input Port Output Sample Rate AUX_LRCK Duty Cycle AUX_LRCK Period AUX_SCLK Frequency (Note 14) AUX_SCLK Duty Cycle AUX_SCLK Period (Note 13, 14) FSO Input Source: Analog Inputs or Serial Audio Input Port AUX_LRCK Rising Edge to AUX_SCLK Falling Edge AUX_SCLK Rising Edge to Data Output Valid DLY_SDIN Setup Time Before AUX_SCLK Rising Edge DLY_SDIN Hold Time After AUX_SCLK Rising Edge ns ns ns ns Notes: 11. FCLK is the frequency of the crystal connected to the XTI/XTO pins or the input SYS_CLK signal. TCLK = 1/FCLK. 12. FSI is the frequency of the input LRCK signal. TSI = 1/FSI 13. May vary during normal operation. 14. FSCLKI is the frequency of the input SCLK signal. TSCLKI = 1/FSCLKI. AUX_LRCK AUX_SCLK tLTSF tSRDV AUX_SDOUT DLY_SDOUT LSB MSB MSB - 1 tDISU DLY_SDIN LSB MSB tDIH MSB - 1 Figure 8. AUX Serial Port Interface Master Mode Timing 22 DS726PP3 CS4525 XTI SWITCHING SPECIFICATIONS Parameter External Crystal Operating Frequency (Notes 15, 16) XTI Duty Cycle ClkFreq[1:0] = ‘00’ ClkFreq[1:0] = ‘01’ ClkFreq[1:0] = ‘10’ Symbol FCLK Min 18.240 24.330 26.730 45 Typ 18.432 24.576 27.000 50 Max 18.617 24.822 27.270 55 Unit MHz MHz MHz % Notes: 15. External crystal oscillator mode only available in Software Mode. SYS_CLK SWITCHING SPECIFICATIONS AGND = DGND = PGND = 0 V; TA = 25°C; VD = 3.3 V; Input: Logic 0 = DGND; Logic 1 = VD, SYS_CLK Output: CL = 20 pF. Parameter External Clock Operating Frequency (Note 16) Rising Edge RST to start of SYS_CLK SYS_CLK Period SYS_CLK Duty Cycle SYS_CLK high time SYS_CLK low time tclkih tclkil ClkFreq[1:0] = ‘00’ ClkFreq[1:0] = ‘01’ ClkFreq[1:0] = ‘10’ Symbol FCLK tsclko tsclki Min 18.240 24.330 26.730 37.04 45 16.67 16.67 Typ 18.432 24.576 27.000 1024*tsclki 50 - Max 18.617 24.822 27.270 54.25 55 29.84 29.84 Unit MHz MHz MHz ns % ns ns Notes: 16. ClkFreq[1:0] = ‘10’ mode only in Software Mode. See “Clock Frequency (ClkFreq[1:0])” on page 69 for software mode configuration settings. See “System Clocking” on page 54 for hardware mode configuration settings. SYS_CLK (output) ___ RST tsclko Figure 9. SYS_CLK Timing from Reset PWM_SIGX SWITCHING SPECIFICATIONS AGND = DGND = PGND = 0 V; TA = 25°C; VD = 3.3 V; Load = 10 pF. Parameter Rise Time of PWM_SIGx Fall Time of PWM_SIGx Symbol tr tf Min - Typ 2.1 1.4 Max - Unit ns ns tr PWM_SIGx tf Figure 10. PWM_SIGX Timing DS726PP3 23 CS4525 I²C CONTROL PORT SWITCHING SPECIFICATIONS AGND = DGND = PGND = 0 V; TA = 25°C; VD = 3.3 V; Inputs: Logic 0 = DGND; Logic 1 = VD; SDA CL = 30 pF. Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 17) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 10 250 4.7 300 Max 100 1 300 1000 Unit kHz ns µs µs µs µs µs ns ns µs ns µs ns Notes: 17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. RST t irs Stop SDA t buf SCL Repeated Start Start Stop t hdst t high t hdst tf t susp t low t hdd t sud t sust tr Figure 11. Control Port Timing - I²C 24 DS726PP3 CS4525 DC ELECTRICAL CHARACTERISTICS AGND = DGND = PGND = 0 V; All voltages with respect to ground; PWM switch rate = 384 kHz; Unless otherwise specified. Parameters Normal Operation (Note 18) Power Supply Current Power Dissipation VD = 3.3 V VD = 3.3 V VD = 3.3 V 2.25 2.25 (Note 20) 1 kHz 60 Hz 54 180 2.8 2.5 2.5 0.5*VA_REG 23 VA_REG 60 40 2.75 3 2.75 1 10 mA mW mA V mA V mA V kΩ µA V dB dB Min Typ Max Units Power-Down Mode (Note 19) Power Supply Current VD_REG Characteristics Nominal Voltage DC current source VA_REG Characteristics Nominal Voltage DC current source VQ Characteristics Nominal Voltage Output Impedance DC current source/sink Filt+ Nominal Voltage Power Supply Rejection Ratio (Note 21) Notes: 18. Normal operation is defined as RST = HI. 19. Power-Down Mode is defined as RST = LOW with all input lines held static. 20. The DC current drain represents the allowed current from the VQ pin due to typical leakage through the electrolytic de-coupling capacitors. 21. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will increase the PSRR. DIGITAL INTERFACE SPECIFICATIONS AGND = DGND = PGND = 0 V; All voltages with respect to ground; Unless otherwise specified. Parameters Digital Interface Signal Characteristics (Note 22) High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current Input Capacitance Io=2 mA Io=2 mA VIH VIL VOH VOL Iin 0.75*VD_REG 0.90*VD Io=2 mA Io=2 mA VOHPS VOLPS 0.90*VD_REG 0.20*VD_REG 0.2 ±10 8 0.2 V V V V uA pF V V Symbol Min Max Units PWM_SIGx Characteristics High-Level PWM_SIGx Output Voltage Low-Level PWM_SIGx Output Voltage Notes: 22. Digital interface signals include all pins sourced from the VD supply as shown in “Digital I/O Pin Characteristics” on page 12. 25 DS726PP3 CS4525 6. APPLICATIONS 6.1 Software Mode Maximum device flexibility and features are available when the CS4525 is used in software mode. The available features are described in the following sections. All device configuration is achieved via the I²C control port as described in the I²C Control Port Description and Timing section on page 64. 6.1.1 System Clocking In software mode, the CS4525 can be clocked by a stable external clock source input on the SYS_CLK pin or by a clock internally generated through the use of its internal oscillator driver circuit in conjunction with an external crystal oscillator. The device automatically selects which of these clocks to use within 10 ms of the release of RST. The internal clock is used to synchronize the input serial audio signals with the internal clock domain and to clock the internal digital processing, sample-rate converter, and PWM modulators. It is also used to determine the sample rate of the serial audio input signals in order to automatically configure the various internal filter coefficients. To ensure proper operation, the CS4525 must be informed of the nominal frequency of the supplied SYS_CLK signal or the attached crystal via the ClkFreq[1:0] bits in the Clock Config register. These bits must be set to the appropriate value before the PDnAll bit is cleared to initiate a power-up sequence. See the SYS_CLK Switching Specifications and XTI Switching Specifications tables on page 23 for complete input frequency range specifications. WARNING: The system clock source must never be removed or stopped while any of the power output stages are powered-up (the PDnAll bit and any of the PDnOut1, PDnOut2, or PDnOut3/4 bits are cleared) and connected to a load. Doing so may result in permanent damage to the CS4525 and connected transducers. Referenced Control Register Location ClkFreq[1:0]......................... “Clock Frequency (ClkFreq[1:0])” on page 69 PDnAll ................................. “Power Down (PDnAll)” on page 89 PDnOutX ............................. “Power Down PWM Power Output X (PDnOutX)” on page 89 6.1.1.1 SYS_CLK Input Clock Mode If an input clock is detected on the SYS_CLK pin following the release of RST, the device will automatically use the SYS_CLK input as its clock source. The applied SYS_CLK clock signal must oscillate within the frequency ranges specified in the SYS_CLK switching specifications table on page 23. In this mode, XTI should be connected to ground and XTO should be left unconnected. Figure 12 below demonstrates a typical clocking configuration using the SYS_CLK input. Clock Clock_In SYS_CLK XTI DSP Reset_Out RST CS4525 XTO Figure 12. Typical SYS_CLK Input Clocking Configuration 26 DS726PP3 CS4525 6.1.1.2 Crystal Oscillator Mode To use an external crystal in conjunction with the internal crystal driver, a 20 pF fundamental mode parallel resonant crystal must be connected between the XTI and XTO pins. This crystal must oscillate within the frequency ranges specified in the XTI switching specifications table on page 23. Nothing other than the crystal and its load capacitors should be connected to XTI and XTO. The SYS_CLK pin should be connected to ground through a 22 kΩ pull-down resistor to prevent the CS4525 from recognizing system noise on the SYS_CLK pin as a valid clocking signal. In this mode, the CS4525 will automatically drive the generated internal clock out of the SYS_CLK pin. This can be disabled with the EnSysClk bit which will cause the SYS_CLK pin to become high-impedance. Also, the DivSysClk bit allows the frequency of the generated internal clock to be divided by 2 prior to being driven out of the SYS_CLK. It should be noted that the internal oscillator driver is disabled when the CS4525 is in reset (RST is low). Any external devices connected to the SYS_CLK output will not receive a clock signal until the CS4525 is taken out of reset. If an external crystal is connected to the XTI/XTO pins while an input clock signal is present on the SYS_CLK pin following the release of RST, then the CS4525 will automatically use the SYS_CLK pin for its internal clock. Refer to Section 6.1.1.1 for a details about this mode of operation. Figure 13 below demonstrates a typical clocking configuration using the crystal oscillator. Reset RST XTI XTO RST CS4525 SYS_CLK Clock_In DSP Figure 13. Typical Crystal Oscillator Clocking Configuration Referenced Control Register Location EnSysClk............................. “SYS_CLK Output Enable (EnSysClk)” on page 69 DivSysClk............................ “SYS_CLK Output Divider (DivSysClk)” on page 69 DS726PP3 27 CS4525 6.1.2 Power-Up and Power-Down The CS4525 will remain in a completely powered-down state with the control port inaccessible until the RST pin is brought high. Once RST is high, the control port will be accessible, but all other internal blocks will remain powered-down until they are powered-up via the control port or until hardware mode is entered. When an external crystal is present on the XTI/XTO pins, software mode will be automatically entered 10 ms after the release of RST. If SYS_CLK is used as an input, software mode is entered by writing to the control port within 10 ms after the release of RST. If the control port is not written within this time, the device will begin to operate in hardware mode. 6.1.2.1 Power-Up Sequence 1. Hold RST low until the power supplies and the input SYS_CLK (if used) are stable. 2. Bring RST high. The device will remain in a low-power state and the control port will be accessible. The device will automatically enter software mode after 10 ms if an external crystal is present on the XTI/XTO pins, at which time the output SYS_CLK signal will become active. 3. If SYS_CLK is used as an input, initiate a control port write to set the PDnAll bit in register 5Fh within 10 ms following the release of RST. This operation causes the device to enter software mode and places it in power-down mode. 4. If the LVD pin is tied low and VD, VD_REG, and VA_REG are connected to 2.5 V, clear the SelectVD bit in the Power Ctrl register to indicate the 2.5 V VD supply level. See section 6.7 on page 63 for details. 5. If VP is connected to a supply voltage less than or equal to 14 V nominal, clear the SelectVP bit in the Foldback Cfg register to indicate the VP supply level. 6. Write the following initialization sequence to the CS4525 registers: – 55h to register 64h. – 08h to register 69h. – 00h to register 64h. 7. Other desired register settings can be loaded while keeping the PDnAll bit set. Typical initialization settings include Input Configuration, Output Configuration, Master Volume, and Clock Frequency. 8. Clear the PDnAll bit to initiate the power-up sequence. 6.1.2.2 Power-Down Sequence 1. Set the MuteChA, MuteChB, and MuteSub bits in the Mute Control register to mute the audio output. 2. Set the PDnAll bit to power-down the device. 3. If the SYS_CLK input clock mode is used, the SYS_CLK signal may now be removed. See section 6.1.1 on page 26 for more information. 4. Bring RST low to bring the device’s power consumption to an absolute minimum. 5. Remove power. Referenced Control Register Location PDnAll ................................. “Power Down (PDnAll)” on page 89 SelectVD ............................. “Select VD Level (SelectVD)” on page 88 SelectVP ............................. “Select VP Level (SelectVP)” on page 74 MuteChX ............................. “Independent Channel A & B Mute (MuteChX)” on page 84 MuteSub.............................. “Sub Channel Mute (MuteSub)” on page 85 Input Configuration.............. “Input Configuration (Address 02h)” on page 71 Output Configuration ........... “Output Configuration (Address 04h)” on page 73 Master Volume .................... “Master Volume Control (Address 57h)” on page 82 Clock Frequency ................. “Clock Frequency (ClkFreq[1:0])” on page 69 28 DS726PP3 CS4525 6.1.3 Input Source Selection The CS4525 can accept analog or digital audio input signals. Digital audio input signals are supplied through the serial audio input port as outlined in “Serial Audio Interfaces” on page 62. Analog audio input signals are supplied through the internal ADC as outlined in “Analog Inputs” on page 61. The input source is selected by the ADC/SP bit in the Input Config register. In software mode, the serial audio input port supports I²S, Left-Justified and Right-Justified data formats. The serial audio input port digital interface format is configured by the DIF[2:0] bits in the Input Config register. The CS4525 internal ADC includes a dedicated high-pass filter to remove any DC content from the ADC output signal prior to the internal ADC/serial audio input port input multiplexor. This high-pass filter can be bypassed by clearing the EnAnHPF bit. Referenced Control Register Location ADC/SP ............................... “Input Source Selection (ADC/SP)” on page 71 DIF[2:0] ............................... “Input Serial Port Digital Interface Format (DIF [2:0])” on page 71 EnAnHPF ............................ “ADC High-Pass Filter Enable (EnAnHPF)” on page 71 6.1.4 Digital Sound Processing The CS4525 implements flexible digital sound processing operations including bass management crossover, 2-way speaker crossovers, high- and low-pass shelving filters, programmable parametric EQ filters, adaptive loudness compensation, channel mixers, and volume controls. The digital signal flow is shown in Figure 14 below. The signal processing blocks are described in detail in the following sections. Stereo Analog In ADC HighPass Audio Processing Parametric EQ Ch. 1 Sample Rate Converter PWM Modulator Gate Drive Gate Drive Power Stage Power Stage Power Stage Power Stage Amplifier Out 1 Amplifier Out 2 Amplifier Out 3 Amplifier Out 4 PWM Modulator Output 1 PWM Modulator Output 2 Serial Audio Clocks & Data Serial Audio Input Port High-Pass Bass/Treble Adaptive Loudness Compensation 2-Ch Mixer 2.1 Bass Mgr Linkwitz-Riley Crossover De-Emphasis Volume Sub Ch. 2 Sample Rate Converter PWM Modulator Serial Audio Data I/O Serial Audio Clocks & Data Serial Audio Delay Interface Auxiliary Serial Port PWM Output Config Gate Drive Gate Drive Sample Rate Converter PWM Modulator Temperature Sense Temperature Sense Thermal Foldback Master Vol Control Ch. A Thermal Limiter Ch. A Sensitivity Treble Tone Ctrl High-Pass Filter Param. EQ Pre-Scaler Ch. A De-Emphasis Left Ch. Vol Control Bass Tone Ctrl Bass Manager X-Over Ch. A HPF Ch. A LPF Ch. B HPF Ch. B LPF Ch. A HPF Ch. A LPF Ch. B Ch. 1 Ch. 2 Sub Serial Audio Data In Right Mixer Ch. B Ch. B Sub Limiter Ch. B HPF Ch. B LPF Loudness Aux Serial Data Select Data to Aux Port Figure 14. Digital Signal Flow DS726PP3 29 CS4525 6.1.4.1 Pre-Scaler Applying any gain to a full-scale signal in the digital domain will cause the signal to clip. To prevent this, a pre-scaler block is included prior to the internal digital signal processing blocks. This allows the input signal to be attenuated before processing to ensure that any signal boosting, such as gain in a shelving filter, will not cause a channel to clip. The pre-scaler block allows up to -14.0 dB of attenuation in 2.0 dB increments and is controlled with the PreScale[2:0] bits. Referenced Control Register Location PreScale[2:0]....................... “Pre-Scale Attenuation (PreScale[2:0])” on page 75 6.1.4.2 Digital Signal Processing High-Pass Filter The CS4525 includes a high-pass filter at the beginning of the digital signal processing chain to remove any DC content from the input signal prior to the remaining internal digital signal processing blocks. The high-pass filter operates by continuously subtracting a measure of the DC offset from the input signal and may be used regardless of the input data source. The digital signal processing high-pass filter can be disabled by clearing the EnDigHPF bit. Referenced Control Register Location EnDigHPF ........................... “Digital Signal Processing High-Pass Filter (EnDigHPF)” on page 77 6.1.4.3 Channel Mixer The CS4525 implements independent channel mixers to provide for both mono mixes and channel swaps for the left and right channels. The channel mixers are controlled by the LChMix[1:0] and RChMix[1:0] bits in the Mixer Config register. To allow stereo operation when a mono mix is configured, when the HP_DETECT/MUTE pin is configured for headphone detection (the HP/Mute bit is set), the operation of the left channel mixer is affected by the active state of the headphone detection input signal. In this configuration, when the left channel mixer is configured for a mono mix (LChMix[1:0] = 01 or 10) and the headphone detection input signal becomes active, the left channel mixer will be automatically reconfigured to output the left channel, thereby disabling the mono mix. When the headphone detection input signal becomes inactive, the mixer will be automatically reconfigured to operate as dictated by the LChMix[1:0] bits. It should be noted that the right channel mixer output is unaffected by the headphone detection input signal and will always operate as dictated by the RChMix[1:0] bits. Referenced Control Register Location LChMix[1:0] ......................... “Left Channel Mixer (LChMix[1:0])” on page 76 RChMix[1:0] ........................ “Right Channel Mixer (RChMix[1:0])” on page 76 HP/Mute .............................. “HP_Detect/Mute Pin Mode (HP/Mute)” on page 70 30 DS726PP3 CS4525 6.1.4.4 De-Emphasis The CS4525 includes an on-chip digital de-emphasis filter optimized for a sample rate of 44.1 kHz to accommodate audio recordings that utilize 50/15 µs pre-emphasis equalization as a means of noise reduction. The filter response is shown in Figure 15. The de-emphasis filter is enabled and disabled by the DeEmph bit in the Tone Config register. Gain (dB) T1=50 µs 0 dB T2 = 15 µs -10 dB Frequency (Hz) Nominal Sample Rate 32 kHz, 44.1 kHz, 48 kHz 96 kHz F1 0.07218 Fs 0.03609 Fs F2 0.24059 Fs 0.12030 Fs Normalized to Fs Figure 15. De-Emphasis Filter Referenced Control Register Location DeEmph .............................. “De-Emphasis Control (DeEmph)” on page 76 6.1.4.5 Tone Control The CS4525 implements configurable bass and treble shelving filters to easily accommodate system tone control requirements. Each shelving filter has 4 selectable corner frequencies, and provides a cut/boost range from -10.5 dB to +12.0 dB in 1.5 dB increments. The tone control is enabled by the EnToneCtrl bit in the Tone Config register. Each tone control is implemented with one of two preset internal filter sets. One set is optimized for a 32 kHz sample rate, and the other is optimized for 44.1 kHz, 48 kHz, and 96 kHz sample rates. The CS4525 automatically detects the input sample rate and chooses the appropriate filter set to apply. The available corner frequencies are shown in tables 2 and 3 below and are configured with the BassFc[1:0] and TrebFc[1:0] bits in the Tone Config register. Note that the corner frequency of each filter set scales linearly with the input sample rate. When the internal ADC is used as the serial audio data source, the input sample rate is nominally 48 kHz and the corresponding shelving frequency corners are available. Input Sample Rate 32 kHz 44.1 kHz 48 kHz, 96 kHz Bass Fc 0 50 Hz 48 Hz 52 Hz Bass Fc 1 100 Hz 96 Hz 104 Hz Bass Fc 2 200 Hz 192 Hz 208 Hz Bass Fc 3 250 Hz 240 Hz 260 Hz Table 2. Bass Shelving Filter Corner Frequencies DS726PP3 31 CS4525 Input Sample Rate 32 kHz 44.1 kHz 48 kHz, 96 kHz Treble Fc 0 5.0 kHz 4.8 kHz 5.2 kHz Treble Fc 1 7.0 kHz 6.7 kHz 7.3 kHz Treble Fc 2 10.0 kHz 9.6 kHz 10.4 kHz Treble Fc 3 15.0 kHz 14.4 kHz 15.6 kHz Table 3. Treble Shelving Filter Corner Frequencies The cut/boost level of the bass and treble shelving filters are set by the Bass[3:0] and Treble[3:0] bits in the Tone Control register. Referenced Control Register Location EnToneCtrl .......................... “Tone Control Enable (EnToneCtrl)” on page 77 TrebFc[1:0] .......................... “Treble Corner Frequency (TrebFc[1:0])” on page 77 BassFc[1:0] ......................... “Bass Corner Frequency (BassFc[1:0])” on page 77 Treble[3:0] ........................... “Treble Gain Level (Treb[3:0])” on page 78 Bass[3:0] ............................. “Bass Gain Level (Bass[3:0])” on page 78 32 DS726PP3 CS4525 6.1.4.6 Parametric EQ The CS4525 implements 5 fully programmable parametric EQ filters. The filters are implemented in the bi-quad form shown below. x[n] b0 y[n] Z -1 Z -1 b1 a1 Z -1 Z -1 b2 a2 Figure 16. Bi-Quad Filter Architecture This architecture is represented by the equation shown below where y[n] represents the output sample value and x[n] represents the input sample value. y[n] = b0x[n] + b1x[n-1] + b2x[n-2] + a1y[n-1] + a2y[n-2] Equation 1. Bi-Quad Filter Equation The coefficients are represented in binary form by 24-bit signed values stored in 3.21 two’s complement format. The 3 MSB’s represent the sign bit and the whole-number portion of the decimal coefficient, and the 21 LSB’s represent the fractional portion of the decimal coefficient. The coefficient values must be in the range of -4.00000 decimal (80 00 00 hex) to 3.99996 decimal (7F FF FF hex). The binary coefficient values are stored in registers 0Ah - 54h. Each 24-bit coefficient is split into 3 bytes, each of which is mapped to an individually accessible register location. See the “Register Quick Reference” section beginning on page 66 for the specific register locations for each coefficient. By default, all b0 coefficients are set to 1 decimal, and all other coefficients are set to 0 decimal. This implements a pass-through function. The parametric equalizers be independently enabled and disabled for channels A and B with the EnChAPEq and EnChBPEq bits located in the EQ Config register. Referenced Control Register Location EnChAPEq .......................... “Enable Channel A Parametric EQ (EnChAPEq)” on page 79 EnChBPEq .......................... “Enable Channel B Parametric EQ (EnChBPEq)” on page 79 DS726PP3 33 CS4525 6.1.4.7 Adaptive Loudness Compensation The CS4525 includes adaptive loudness compensation to enhance the audibility of program material at low volume levels. The adaptive loudness compensation feature operates by varying the bass and treble boost of the tone control shelving filters as the volume level changes. The level of boost added to the shelving filters is determined by the average of the effective volume settings of channels A and B after the master volume control. As this average volume setting decreases from 0 dB, the boost of the bass and treble shelving filters is gradually increased until it reaches the maximum boost level of 12.0 dB. As the volume is increased, the boost applied due to the adaptive loudness compensation feature will be gradually removed until it reaches the level specified by the Treble[3:0] and Bass[3:0] bits in the Tone Control register. The adaptive loudness compensation feature is enabled by setting the Loudness bit in the Tone Config register. When the loudness feature is enabled, it immediately evaluates the effective average volume and applies bass and treble boost accordingly. When disabled, any treble or bass boost applied due to the loudness feature will be removed. Because the adaptive loudness compensation filter operates by adjusting the boost level of the tone control shelving filters, it is necessary that they be enabled with the EnToneCtrl bit in the Tone Config register in order for the loudness feature to be operational. If the tone control filters are disabled, the adaptive loudness compensation feature will not be functional. Referenced Control Register Location Loudness............................. “Adaptive Loudness Compensation Control (Loudness)” on page 76 EnToneCtrl .......................... “Tone Control Enable (EnToneCtrl)” on page 77 TrebFc[1:0] .......................... “Treble Corner Frequency (TrebFc[1:0])” on page 77 BassFc[1:0] ......................... “Bass Corner Frequency (BassFc[1:0])” on page 77 Treble[3:0] ........................... “Treble Gain Level (Treb[3:0])” on page 78 Bass[3:0] ............................. “Bass Gain Level (Bass[3:0])” on page 78 34 DS726PP3 CS4525 6.1.4.8 Bass Management The CS4525 implements a dedicated stereo 24 dB/octave Linkwitz-Riley crossover with adjustable crossover frequency to achieve bass management for 2.1 configurations. The filter’s stereo high-pass outputs are used to drive the full-range speakers, and its stereo low-pass outputs are each attenuated by 6 dB and summed to drive the sub channel. The bass management crossover is implemented with one of two preset internal filter sets. One set is optimized for a 32 kHz sample rate, and the other is optimized for 44.1 kHz, 48 kHz, and 96 kHz sample rates. The CS4525 automatically detects the input sample rate and chooses the appropriate filter set to apply. The available bass management cross-over frequencies are shown in Table 4 below and are configured with the BassMgr[2:0] bits in the EQ Config register. Note that the corner frequency of each filter set scales linearly with the input sample rate. When the internal ADC is used as the serial audio data source, the input sample rate is nominally 48 kHz and the corresponding shelving frequency corners are available. Input Sample Rate 44.1 kHz 77 Hz 115 Hz 153 Hz 192 Hz 230 Hz 268 Hz 307 Hz Bass Manager Freq 1 Bass Manager Freq 2 Bass Manager Freq 3 Bass Manager Freq 4 Bass Manager Freq 5 Bass Manager Freq 6 Bass Manager Freq 7 32 kHz 80 Hz 120 Hz 160 Hz 200 Hz 240 Hz 280 Hz 320 Hz 48 kHz, 96 kHz 83 Hz 125 Hz 167 Hz 209 Hz 250 Hz 292 Hz 334 Hz Table 4. Bass Management Cross-Over Frequencies The BassMgr[2:0] bits also allow the bass manager to be disabled. When disabled, the bass management crossover is bypassed and no signal is presented on the sub channel. To allow full-range headphone operation, when the HP_DETECT/MUTE pin is configured for headphone detection (the HP/Mute bit is set), the operation of the bass manager is affected by the active state of the headphone detection input signal. In this configuration, when the bass manager is enabled, (BassMgr[2:0] bits not equal to ‘000’) and the headphone detection input signal becomes active, the bass manager will be automatically disabled. When the headphone detection input signal becomes inactive, the bass manager will be automatically reconfigured to operate as dictated by the BassMgr[2:0] bits. Referenced Control Register Location BassMgr[2:0] ....................... “Bass Cross-Over Frequency (BassMgr[2:0])” on page 79 HP/Mute .............................. “HP_Detect/Mute Pin Mode (HP/Mute)” on page 70 DS726PP3 35 CS4525 6.1.4.9 Volume and Muting Control The CS4525’s volume control architecture provides the ability to control the level of each output channel on both an individual and master basis. Individual control allows the volume and mute state of a single channel to be changed independently from the other channels within the device. The CS4525 provides three individual volume and muting controls, each permanently assigned to one channel within the device. The three individual volume controls, ChAVol, ChBVol, and SubVol, can gain or attenuate channel A, channel B, or the sub channel (respectively) from +24 dB to -103 dB in 0.5 dB steps. The three individual mute controls, MuteChA, MuteChB, and MuteSub bits, can mute channel A, channel B, or the sub channel (respectively). Master control allows the volume of all channels to be changed simultaneously by offsetting each channel’s individual volume setting by an additional +24 dB to -103 dB in 0.5 dB steps. By default, master volume is set to +3dB; if the CS4525 is being used to control the application’s master volume, then it is recommended to change this value to a comfortable listening level before enabling the PWM powered outputs. Master volume control is accomplished via the Master Vol register. The PWM outputs can be configured to output silence as a modulated signal or an non-modulated 50% duty cycle signal during a mute condition. This selection is achieved via the Mute50/50 bit in the Volume Cfg register. The AutoMute bit in the same register dictates whether the device will automatically mute after the reception of 8192 consecutive samples of static 0 or -1. When the AutoMute function is enabled, a single sample of non-static data will cause the automatic mute to be released. The CS4525 implements soft-ramp and zero-crossing detection capabilities to provide noise-free level transitions. When the zero-crossing function is enabled, all volume and muting changes are made on an output signal zero-crossing. The zero-crossing detection function is implemented independently for each channel. When the soft-ramp function is enabled, the volume is ramped from its initial to its final level at a rate of ½ dB every 4 samples for 32, 44.1, and 48 kHz sample rates, and ½ dB every 8 samples for a 96 kHz sampling rate. All volume and muting changes are implemented as dictated by the soft-ramp and zero-cross settings configured by the SZCMode[1:0] bits in the Volume Cfg register. Referenced Control Register Location ChXVol ................................ “Channel A and B Volume Control (Address 58h & 59h)” on page 83 SubVol................................. “Sub Channel Volume Control (Address 5Ah)” on page 83 MuteChX ............................. “Independent Channel A & B Mute (MuteChX)” on page 84 MuteSub.............................. “Sub Channel Mute (MuteSub)” on page 85 Master Vol ........................... “Master Volume Control (Address 57h)” on page 82 Mute50/50 ........................... “Enable 50% Duty Cycle for Mute Condition (Mute50/50)” on page 80 AutoMute............................. “Auto-Mute (AutoMute)” on page 80 SZCMode ............................ “Soft Ramp and Zero Cross Control (SZCMode[1:0])” on page 80 36 DS726PP3 CS4525 6.1.4.10 Peak Signal Limiter When enabled, the limiter monitors the digital output following the volume control block, detects when peak levels exceed a selectable maximum threshold level and lowers the volume at a programmable attack rate until the signal peaks fall below the maximum threshold. When the signal level falls below a selectable minimum threshold, the volume returns to its original level (as determined by the individual and master volume control registers) at a programmable release rate. Attack and release rates are affected by the soft ramp/zero cross settings and sample rate, Fs. Recommended settings: Best limiting performance may be realized with the fastest attack and slowest release setting with soft ramp enabled in the control registers. Use the “minimum” bits to set a threshold slightly below the maximum threshold to cushion the sound as the limiter attacks and releases. Input Max[2:0] Limiter Attack/Release Sound Cushion Volume Attack/Release Sound Cushion Output (after Limiter) Min[2:0] ARate[5:0] RRate[5:0] Figure 17. Peak Signal Detection & Limiting By default, the limiter affects all channels when the maximum threshold is exceeded on any single channel. This default functionality is designed to keep all output channels at the same volume level while the limiter is in use. This behavior can be disabled by clearing the LimitAll bit in the Limiter Cfg 1 register. DS726PP3 37 CS4525 When the LimitAll feature is activated, attenuation will be applied to all channels when a single channel exceeds the maximum threshold and released when the level of all channels is below the minimum threshold. When the LimitAll feature is de-activated, limiter attenuation will be applied and released on a per-channel basis and will only affect the channel on which the limiter event occurred. The limiter can be enabled by setting the EnLimiter bit in the Limiter Cfg 1 register The limiter can also be used in conjunction with the thermal limiter function to provide thermal error protection to the CS4525. The thermal limiter function is described in Thermal Limiter on page 39. Referenced Control Register Location EnLimiter ............................. “Peak Detect and Limiter Enable (EnLimiter)” on page 86 LimitAll................................. “Peak Signal Limit All Channels (LimitAll)” on page 86 Max[2:0] .............................. “Maximum Threshold (Max[2:0])” on page 85 Min[2:0] ............................... “Minimum Threshold (Min[2:0])” on page 85 ARate[5:0] ........................... “Limiter Attack Rate (ARate[5:0])” on page 87 RRate[5:0] ........................... “Limiter Release Rate (RRate[5:0])” on page 87 38 DS726PP3 CS4525 6.1.4.11 Thermal Limiter The CS4525 implements a thermal limiter function to provide a quick corrective response to potentially damaging thermal overload conditions. The thermal limiter feature operates by sensing the presence of a thermal warning condition and, in response, utilizes the peak signal limiter to dynamically limit the signal amplitude prior to the PWM modulators. This effectively limits the output power capability of the device, thereby allowing the temperature to reduce to acceptable levels without fully interrupting operation. The thermal limiter is enabled by the EnThLim bit in the Limiter Configuration 3 register. When enabled, the thermal limiter will trigger once when either of the following conditions is met: 1. The junction temperature crosses the thermal warning threshold for the first time after the thermal limiter function is enabled. 2. The junction temperature is greater than the thermal warning threshold at the time the thermal limiter function is enabled. Once triggered, the thermal limiter will remain in a triggered state until the RST pin is driven low. When in the triggered state, the thermal limiter will engage whenever the EnThLim bit is set. While engaged, the thermal limiter utilizes the peak signal limiter function to dynamically limit the signal amplitude prior to the PWM modulators via the peak signal limiter; the characteristics of this limiting function are described in Section 6.1.4.10 on page 37. If the thermal limiter is engaged and the peak signal limiter is disabled via the EnLimiter bit, the peak signal limiter will be automatically enabled and its minimum and maximum thresholds will be set to -3 dB. If the thermal limiter is engaged and the peak signal limiter is enabled, an additional -3dB will be automatically applied to the minimum and maximum thresholds established in the Limiter Cfg 1 register. The automatic enabling of the peak signal limiter and the automatic application of additional attenuation to its thresholds is done internal to the CS4245; the values of the EnLimiter, Min[2:0], and Max[2:0] bits in the Limiter Cfg 1 register are not affected by the engagement of the thermal limiter function. It should be noted that the thermal limiter can only be triggered once following the release of the RST signal. Once it has triggered, the thermal limiter’s attenuation will always be implemented while the thermal limiter is enabled. If the thermal limiter is disabled after it has triggered, the internal enabling of the peak signal limiter and the additional -3 dB attenuation applied to its minimum and maximum thresholds will be released. In this state, the peak signal limiter’s operation will follow the EnLimiter, Min[2:0], and Max[2:0] bits with no internal modification. If EnThLim is set again before the CS4525 has been reset (by toggling the RST pin low and then high), thermal limiting will engage immediately. Referenced Control Register Location EnThLim.............................. “Enable Thermal Limiter (EnThLim)” on page 87 EnLimiter ............................. “Peak Detect and Limiter Enable (EnLimiter)” on page 86 Max[2:0] .............................. “Maximum Threshold (Max[2:0])” on page 85 Min[2:0] ............................... “Minimum Threshold (Min[2:0])” on page 85 DS726PP3 39 CS4525 6.1.4.12 Thermal Foldback The CS4525 implements comprehensive thermal foldback features to guard against damaging thermal overload conditions. Thermal foldback is similar to the thermal limiting described on page 39 in that both features attenuate the output signal in response to thermal warnings conditions; however, thermal foldback will attenuate as a function of how long thermal warning has been active whereas thermal limiter always limits by a constant amount. Also, the thermal foldback feature will deactivate once the thermal warning condition ceases while the thermal limiter will remain active once triggered until the RST pin is driven low. The thermal foldback algorithm begins limiting the volume of the digital audio input to the amplifier stage as the junction temperatures rise above the maximum safe operating range specified by the thermal warning trigger point listed in the PWM Power Output Characteristics table on page 20. This effectively limits the output power capability of the device, thereby allowing the temperature to reduce to acceptable levels without fully interrupting operation. As the device cools, the applied attenuation is gradually released until a new thermal equilibrium is reached or all applied attenuation has been released thereby allowing the device to again achieve its full output power capability. Attenuation applied due to thermal foldback reduces the audio output level in a linear manner. Figure 18 below demonstrates the foldback process. Foldback Attack Delay AttackDly[1:0] tdelay tdelay 2 2 2 Thermal Warning Threshold tdelay tdelay tdelay 1 2 3 1 1 2 When the junction temperature crosses the thermal warning threshold, the foldback attack delay timer is started. When the foldback attack delay timer reaches tdelay seconds, the junction temperature is checked. If the junction temperature is above the thermal warning threshold, the output volume level is lowered by 0.5 dB and the foldback attack timer is restarted. The junction temperature is checked after each foldback attack timer timeout, and if necessary, the output volume level is lowered accordingly. If the junction temperature is found to be below the thermal warning threshold, the foldback attack timer is restarted once again, but the output volume level is not altered. The foldback algorithm then proceeds to step 3. 3 The junction temperature is checked once again after the next foldback attack timer timeout. If it has remained below the thermal warning threshold since the last check, the device will begin to release any attenuation applied as a result of the foldback event. Setting the LockAdj bit will prevent the device from removing the applied attenuation when the thermal overload condition has cleared. If the junction temperature crosses the thermal warning threshold again, the foldback algorithm will once again enter step 1. Figure 18. Foldback Process 40 DS726PP3 CS4525 The AttackDly[1:0] bits in the Foldback Cfg register allow the foldback attack delay timeout period to be adjusted from approximately 0.5 seconds to approximately 2.0 seconds. The maximum attenuation applied by the thermal foldback algorithm can be restricted to -30 dB by setting the EnFloor bit in the same register. The foldback adjustment lock feature causes the attenuation applied by the foldback algorithm to be maintained after the foldback condition has subsided. The applied attenuation will continue to be applied until the master volume or all active channel volume controls are lowered below the foldback attenuation level, or until a subsequent foldback condition occurs causing the applied attenuation to be lowered further. If the foldback algorithm applies attenuation while this feature is enabled, when the feature is subsequently disabled, the applied attenuation will be gradually released as long as the temperature remains within the safe operating range. This foldback lock adjustment feature is enabled by the LockAdj bit in the Foldback Cfg register. Thermal warnings will only affect the foldback algorithm and cause attenuation to be applied when enabled by the EnTherm bit in the Foldback Cfg register. The CS4525 can be configured to accept an external thermal warning indicator input. When in this configuration, an active input signal indicates that a thermal warning threshold has been exceeded. If thermal foldback is enabled, the foldback algorithm will respond as described above making no distinction between an internal or external thermal warning condition. See “External Warning Input Port” on page 44 for more information. Referenced Control Register Location EnTherm ............................. “Enable Thermal Foldback (EnTherm)” on page 74 AttackDly[1:0] ...................... “Foldback Attack Delay (AttackDly[1:0])” on page 75 EnFloor................................ “Enable Foldback Floor (EnFloor)” on page 75 LockAdj ............................... “Lock Foldback Adjust (LockAdj)” on page 74 DS726PP3 41 CS4525 6.1.4.13 2-Way Crossover & Sensitivity Control The CS4525 implements a dedicated stereo 24 dB/octave Linkwitz-Riley crossover filter with adjustable cross-over frequency and sensitivity control to facilitate 2-way speaker configurations. The filter’s highpass output can be used to drive the tweeter, and its low-pass output can be used to drive the midrange/woofer. The sensitivity control is included to adjust the level of the high-pass and low-pass outputs to compensate for differences in the tweeter and mid-range/woofer sensitivity. The two-way crossover is implemented with one of two preset internal filter sets. One set is optimized for a 32 kHz sample rate, and the other is optimized for 44.1 kHz, 48 kHz, and 96 kHz sample rates. The CS4525 automatically detects the input sample rate and chooses the appropriate filter set to apply. The available cross-over frequencies are shown in Table 5 below and are configured with the 2WayFreq[2:0] bits in the Volume Cfg register. Note that the corner frequency of each filter set scales linearly with the input sample rate. When the internal ADC is used as the serial audio data source, the input sample rate is nominally 48 kHz and the corresponding shelving frequency corners are available. Input Sample Rate 44.1 kHz 1.92 kHz 2.11 kHz 2.30 kHz 2.49 kHz 2.68 kHz 2.88 kHz 3.07 kHz 3.26 kHz X-Over Freq 0 X-Over Freq 1 X-Over Freq 2 X-Over Freq 3 X-Over Freq 4 X-Over Freq 5 X-Over Freq 6 X-Over Freq 7 32 kHz 2.0 kHz 2.2 kHz 2.4 kHz 2.6 kHz 2.8 kHz 3.0 kHz 3.2 kHz 3.4 kHz 48 kHz, 96 kHz 2.09 kHz 2.30 kHz 2.50 kHz 2.71 kHz 2.92 kHz 3.13 kHz 3.34 kHz 3.55 kHz Table 5. 2-Way Cross-Over Frequencies The sensitivity level of the high- and low-pass outputs of the crossovers can be independently adjusted from 0 dB to -7.5 dB in 0.5 dB increments. The maximum attenuation level of -7.5 dB will compensate for an approximate 4 dB difference in sound pressure level (SPL) between the tweeter and the midrange/woofer drivers. The sensitivity is adjusted using the HighPass[3:0] and LowPass[3:0] bits in the Sensitivity register. Note that these bits affect the sensitivity of both channel A and channel B high- and low-pass outputs. The 2-way crossover can be enabled by setting the En2Way bit in the Volume Cfg register. Referenced Control Register Location En2Way............................... “Enable 2-Way Crossover (En2Way)” on page 81 2WayFreq[2:0]..................... “2-Way Cross-Over Frequency (2WayFreq[2:0])” on page 81 HighPass[3:0]...................... “Channel A and Channel B High-Pass Sensitivity Adjust (HighPass[3:0])” on page 82 LowPass[3:0]....................... “Channel A and Channel B Low-Pass Sensitivity Adjust (LowPass[3:0])” on page 81 42 DS726PP3 CS4525 6.1.5 Auxiliary Serial Output The CS4525 includes a stereo auxiliary serial output which allows an external device to leverage on its internal signal processing and routing capabilities. The auxiliary serial output can receive its data from any of the sources shown in the Digital Signal Flow diagram on page 29. The supported output data routing configurations are shown in Table 6 below. By default, the serial port is configured to output channels A and B on the auxiliary output data left and right channels respectively. LChDSel[1:0] 00 01 10 11 Aux Left Channel Data Channel A Channel B Sub Channel Channel B X-Over LPF RChDSel[1:0] 00 01 10 11 Aux Right Channel Data Channel A Channel B Sub Channel Channel B X-Over HPF Table 6. Auxiliary Serial Port Data Output The data output on each channel of AUX_SDOUT is set by the LChDSel[1:0] and RChDSel[1:0] bits in the Aux Port Configuration register. The frequencies of AUX_LRCK and AUX_SCLK will vary based upon the whether the serial input or analog input is being used and the frequency of the system clock for the CS4525; the nominal values for these clocks are listed in Table 7. The characteristics of AUX_SCLK, AUX_LRCK, and AUX_SDOUT are described in the AUX Serial Audio I/O Port Switching Specifications table on page 22. Signal Applied System Clock from either SYS_CLK or External Crystal Frequency of LRCK Input ADC/SP = 0 (Digital Input Mode) 18.432, 24.576, or 27.000MHz 96kHz Frequency of SCLK Input / 2 Frequency of LRCK Input / 2 ADC/SP = 1 (Analog Input Mode) 18.432MHz 24.576MHz Not Applicable 2.304MHz 48kHz 3.072MHz 48kHz 3.375MHz 52.734kHz 27.000MHz 32kHz, 44.1kHz, or 48kHz Nominal Frequency of AUX_SCLK Frequency of Output SCLK Input Nominal Frequency of AUX_LRCK Frequency of Output LRCK Input Table 7. Nominal Switching Frequencies of the Auxiliary Serial Output The auxiliary port can be enabled using the EnAuxPort bit. When enabled, the port operates as a master and clocks out data in the format dictated by the AuxI²S/LJ bit. When disabled, the AUX_LRCK, AUX_SCLK, and AUX_SDOUT pins continuously drive a logic ‘0’. It should be noted that when the CS4525 is configured for analog input, the AUX_LRCK, AUX_SCLK, and AUX_SDOUT pins will continuously drive a logic ‘0’ if either the PDnADC bit or PDnAll bit is set. Referenced Control Register Location EnAuxPort ........................... “Enable Aux Serial Port (EnAuxPort)” on page 72 LChDSel[1:0]....................... “Aux Serial Port Left Channel Data Select (LChDSel[1:0])” on page 73 RChDSel[1:0] ...................... “Aux Serial Port Right Channel Data Select (RChDSel[1:0])” on page 72 AuxI²S/LJ............................. “Aux/Delay Serial Port Digital Interface Format (AuxI²S/LJ)” on page 72 PDnADC.............................. “Power Down ADC (PDnADC)” on page 88 PDnAll ................................. “Power Down (PDnAll)” on page 89 DS726PP3 43 CS4525 6.1.6 Serial Audio Delay & Warning Input Port The CS4525 includes a configurable delay and warning port to allow easy system integration of external lip-sync delay devices or warning inputs from external amplifiers. The port can be configured as a serial audio delay interface, an external warning input port, or disabled by the DlyPortCfg[1:0] bits in the Aux Config register. When disabled, the DLY_SDOUT and DLY_SDIN/EX_TWR pins become high-impedance. Referenced Control Register Location DlyPortCfg........................... “Delay & Warning Port Configuration (DlyPortCfg[1:0])” on page 72 6.1.6.1 Serial Audio Delay Interface Video processing and reproduction circuitry in digital video display devices can often introduce noticeably more delay than is introduced by the device’s audio processing and reproduction circuitry. This can result in a phenomenon known as lip-synch delay - a delay present between the video and audio content being reproduced. To help overcome this problem, the CS4525 delay and warning port can be configured as serial audio delay interface. This interface consists of a serial audio input/output port to facilitate the use of an external serial audio delay device. The port routes the serial data from the selected input source (the ADC or the serial input port) out to an external serial audio delay device, and then back in to the CS4525 internal digital sound processing blocks. The delay serial audio interface signals include DLY_SDOUT and DLY_SDIN/EX_TWR and are clocked from AUX_LRCK and AUX_SCLK. The serial data is output on the DLY_SDOUT pin and input on the DLY_SDIN/EX_TWR in the format specified by the AuxI²S/LJ bits in the Aux Config register. Because the delay interface uses the auxiliary port clock signals, the auxiliary serial port must be enabled using the EnAuxPort bit in the Aux Port Configuration register to allow the delay interface to operate properly. Referenced Control Register Location AuxI²S/LJ............................. “Aux/Delay Serial Port Digital Interface Format (AuxI²S/LJ)” on page 72 EnAuxPort ........................... “Enable Aux Serial Port (EnAuxPort)” on page 72 6.1.6.2 External Warning Input Port When implementing external PWM power stage devices with thermal warning indicator outputs, it can be useful to provide these warning signals as an input to the internal thermal foldback algorithm. This allows the CS4525 to automatically respond to the external devices’ thermal warning conditions without completely disrupting the system’s operation. When configured as an external warning input port, the DLY_SDIN/EX_TWR is an active-low thermal warning input to the foldback algorithm and the DLY_SDOUT pin becomes high-impedance. In order for the foldback algorithm to act on the external thermal warning input signal, the thermal foldback algorithm must be enabled by the EnTherm bit in the Foldback Cfg register. See “Thermal Foldback” on page 40 for more information. Referenced Control Register Location EnTherm ............................. “Enable Thermal Foldback (EnTherm)” on page 74 44 DS726PP3 CS4525 6.1.7 Powered PWM Outputs The CS4525’s 3 internal modulators can be used to generate multiple powered PWM output configurations to enable a wide variety of system implementations. The CS4525 also implements PWM Popguard to minimize output transients in half-bridge configurations. 6.1.7.1 Output Channel Configurations Three PWM power output configurations are supported as shown in Table 8 below. The configurations support stereo full-bridge, stereo half-bridge with full-bridge sub, and mono parallel full-bridge output. OutputCfg[1:0] 00 Power Configuration 2 Ch. Full-Bridge Output Signal Channel 1 + Channel 1 Channel 2 + Channel 2 Channel 1 + Channel 2 + Sub Channel + Sub Channel Channel 1 + Channel 1 Output Pin(s) OUT1 OUT2 OUT3 OUT4 OUT1 OUT2 OUT3 OUT4 OUT1, OUT2 OUT3, OUT4 01 2 Ch. Half-Bridge + 1 Ch. Full-Bridge 1 Ch. Parallel Full-Bridge 10 Table 8. PWM Power Output Configurations The configurations are selected by the OutputCfg[1:0] bits in the Output Cfg register and must only be changed when the device is in power-down mode (the PDnAll bit is set). Any attempt to write the OutputCfg[1:0] bits while the device is powered-up will be ignored. It should be noted that signals on channels 1, 2 and the sub channel are dependent upon the digital sound processing blocks being used. For instance, if the 2-way crossover is enabled, channel 1 and 2 contain the 2-way crossover channel A high- and low-pass outputs respectively. For more information, see the Digital Sound Processing section and Figure 14 on page 29. Referenced Control Register Location OutputCfg[1:0]..................... “Output Configuration (OutputCfg[1:0])” on page 73 PDnAll ................................. “Power Down (PDnAll)” on page 89 6.1.7.2 PWM Popguard Transient Control The CS4525 uses Popguard technology to minimize the effects of power-up and power-down output transients commonly produced by half-bridge, single supply amplifiers implemented with external DC-blocking capacitors connected in series with the audio outputs. The PWM Popguard feature operates by linearly ramping the PWM power outputs up to and down from their bias point of VP/2 when a channel is powered up and down respectively using the PDnOutX or PDnAll bits. This gradual voltage ramp minimizes output transients while the DC blocking capacitor is DS726PP3 45 CS4525 charged and discharged. The Popguard technology has no effect on the PWM_SIG outputs nor the auxiliary serial output. +8V to +18V 0.033 uF M RA P CA OUT1 P_ Halfbridge Filter Halfbridge Filter Left Speaker Right Speaker VP OUT2 CS4525 OUT3 Fullbridge Filter Subwoofer OUT4 Figure 19. Popguard Connection Diagram The PWM Popguard feature is disabled by default; to enable it, the RmpSpd[1:0] register must be set to any value other than 11. The PWM Popguard feature should only be used when the power outputs are configured for stereo half-bridge with full-bridge sub per Section 6.1.7.1. The RAMP_CAP pin must be connected to the VP supply through a 0.033 µF capacitor whenever the PWM Popguard technology is enabled, as shown in Figure 19. Typical Ramp Up Times VP Voltage 12 V 15 V 18 V RmpSpd[1:0] = 00 2.16 seconds 1.74 seconds 1.40 seconds RmpSpd[1:0] = 01 2.20 seconds 1.76 seconds 1.42 seconds RmpSpd[1:0] = 10 2.20 seconds 1.78 seconds 1.44 seconds RmpSpd[1:0] = 11 Instant (No Ramp) Instant (No Ramp) Instant (No Ramp) Table 9. Typical Ramp Times for Various VP Voltages The output ramp time will vary depending on the voltage applied to VP and the value of the RmpSpd[1:0] bits; typical ramp times are listed in Table 9. All output channels are affected by the RmpSpeed[1:0] bits, and PWM Popguard feature is disabled by default. Referenced Control Register Location RmpSpeed[1:0] ................... “Ramp Speed (RmpSpd[1:0])” on page 75 PDnAll ................................. “Power Down (PDnAll)” on page 89 PDnOutX ............................. “Power Down PWM Power Output X (PDnOutX)” on page 89 6.1.8 Logic-Level PWM Outputs The CS4525 has two configurable logic-level PWM outputs, PWM_SIG1 and PWM_SIG2. These outputs can be used as either digital input to an external PWM amplifier such as the CS4412, or as an analog input to a headphone amplifier or a line-out amplifier. To eliminate power-up pops when used to supply an external PWM amplifier, the CS4525 implements the same click-free start-up function on the PWM_SIG outputs as it does for its own powered PWM outputs. This function can only be utilized if the PWM amplifier has an initial transition delay feature, such as the CS4412A. To eliminate power-up and power-down pops when used to supply an analog output circuit, the PWM_SIG outputs support a high-impedance state that is controlled by the HiZPSig bit in the EQ Config register. This bit is active-low and cleared by default. To use the PWM_SIG outputs, the HiZPSig bit must be set to enable the PWM_SIG output drivers. 46 DS726PP3 CS4525 6.1.8.1 Recommended PWM_SIG Power-Up Sequence for an External PWM Amplifier 1. 2. 3. 4. 5. Engage the reset/power-down feature of the external PWM amplifier. Set the PDnAll bit in the Power Ctrl register to stop the PWM modulators if it is not already set. Configure the PWM_SIG outputs as desired via the PWMDSel[1:0] bits in the Output Cfg register. Set the HiZPSig bit in the EQ Config register to activate the PWM_SIG output drivers. Disengage the reset/power-down feature of the external PWM amplifier if it has an initial transition delay feature, such as the CS4412A. WARNING:Releasing the external amplifier from reset/power-down before PWM modulators have started will cause a DC output on the speakers unless the external amplifier has an initial transition delay feature. 6. Clear the PDnAll bit in the Power Ctrl register to start the PWM modulators. 7. Disengage the reset/power-down feature of the external PWM amplifier if it has not been yet disengaged. 6.1.8.2 Recommended PWM_SIG Power-Down Sequence for an External PWM Amplifier 1. Mute the PWM_SIG outputs to a 50% duty-cycle by either setting Master Volume to 1111 1111h (Master Mute) or through use of the HP_DETECT/MUTE input pin as described in the Headphone Detection & Hardware Mute Input section on page 51. 2. Engage the reset/power-down feature of the external PWM amplifier. 3. Set the PDnAll bit in the Power Ctrl register to disable the PWM modulators and set the PWM_SIG outputs to a drive a logic ‘0’. 4. Power down the remainder of the system (if applicable). DS726PP3 47 CS4525 6.1.8.3 Out 1. 2. 3. 4. 5. Recommended PWM_SIG Power-Up Sequence for Headphone & Line- Set the PDnAll bit in the Power Ctrl register to stop the PWM modulators if it is not already set. Configure the PWM_SIG outputs as desired via the PWMDSel[1:0] bits in the Output Cfg register. Clear the PDnAll bit in the Power Ctrl register to start the PWM modulators. Wait 500 ms to allow the internal sample rate converters to achieve lock. Set the HiZPSig bit in the EQ Config register to activate the PWM_SIG outputs. 6.1.8.4 Recommended PWM_SIG Power-Down Sequence for Headphone & Line-Out 1. Mute the PWM_SIG outputs to a 50% duty-cycle by either setting Master Volume to 1111 1111h (Master Mute) or through use of the HP_DETECT/MUTE input pin as described in the Headphone Detection & Hardware Mute Input section on page 51. 2. Clear the HiZPSig bit in the EQ Config register to put the PWM_SIG output drivers in a high-impedance state. 3. Power down the remainder of the system (if applicable). Referenced Control Register Location PDnAll ................................. “Power Down (PDnAll)” on page 89 HiZPSig ............................... “Hi-Z PWM_SIG Outputs (HiZPSig)” on page 79 PWMDSel[1:0]..................... “PWM Signals Output Data Select (PWMDSel[1:0])” on page 73 Master Volume .................... “Master Volume Control (MVol[7:0])” on page 82 48 DS726PP3 CS4525 6.1.8.5 PWM_SIG Logic-Level Output Configurations Four channel mapping output configurations are supported for the PWM_SIG output pins as shown in Table 10 below. The configurations support stereo, channel 1 with sub, and channel 2 with sub applications. When disabled, the PWM_SIG pins will continuously drive a logic ‘0’ if the HiZPSig bit is set and will be held in a high-impedance state if the HiZPSig bit is clear. The configurations are selected by the PWMDSel[1:0] bits in the Output Cfg register. The PWM_SIG2 can be configured to output the sub channel even if the Bass Manager is not enabled; however, its signal will be muted unless the Bass Manager is enabled by the BassMgr[2:0] bits. It should be noted that the HiZPSig bit must be set to enable the PWM_SIG output drivers. PWMDSel[1:0] 00 01 10 11 PWM_SIG1 Disabled. Channel 1 Channel 1 Channel 2 PWM_SIG2 Disabled. Channel 2 Sub Channel Sub Channel Table 10. PWM Logic-Level Output Configurations To allow stereo headphone operation when the PWM logic-level outputs are mapped in a non-stereo output configuration, if the HP_DETECT/MUTE pin is configured for headphone detection (the HP/Mute bit is set), the PWM logic-level output mapping can be affected by the active state of the headphone detection input signal. See the Headphone Detection & Hardware Mute Input section on page 51 for more information. It should be noted that signal on channels 1, 2, and the sub channel are dependent upon the digital sound processing blocks being used. For instance, if the 2-way crossover is enabled, channel 1 and 2 contain the 2-way crossover channel A high- and low-pass outputs respectively. For more information, see the Digital Sound Processing section and Figure 14 on page 29. Referenced Control Register Location PWMDSel[1:0]..................... “PWM Signals Output Data Select (PWMDSel[1:0])” on page 73 HiZPSig ............................... “Hi-Z PWM_SIG Outputs (HiZPSig)” on page 79 HP/Mute .............................. “HP_Detect/Mute Pin Mode (HP/Mute)” on page 70 BassMgr[2:0] ....................... “Bass Cross-Over Frequency (BassMgr[2:0])” on page 79 DS726PP3 49 CS4525 6.1.9 PWM Modulator Configuration The CS4525 PWM modulators support flexible configuration options designed to simplify system integration. Delays may be inserted between the switching edges on adjacent channels to manage noise, and the PWM switching frequency can be easily modified to eliminate interference with AM tuners. 6.1.9.1 PWM Channel Delay The CS4525 includes a PWM output signal delay mechanism. This mechanism allows the PWM switching edges to be offset between channels as a method of managing switching noise and reducing radiated emissions. The OutputDly[3:0] bits in the Output Cfg register are used to adjust the channel delay amount from 0 to 15 SYS_CLK or crystal input clock cycles, whichever is used as the input clock source. The absolute delay time is calculated by multiplying the setting of the OutputDly[3:0] bits by the period of the input clock source. By default, no delay is inserted. When the power outputs are configured for 2-channel full-bridge operation, the OUT3/OUT4 signal pair is delayed from the OUT1/OUT2 signal pair by the delay amount as shown in Figure 20. OUT1 OUT2 tchdly OUT3 OUT4 Figure 20. 2-Channel Full-Bridge PWM Output Delay When the power outputs are configured for 3-channel (2-channel half-bridge and 1-channel full-bridge) operation, OUT2 is delayed from OUT1 by the delay amount, and the OUT3/OUT4 pair is delayed from OUT2 by the delay amount as shown in Figure 21. OUT1 tch dly OUT2 tch dly OUT3 OUT4 Figure 21. 3-Channel PWM Output Delay The OutputDly[3:0] bits can only be changed when all modulators and associated logic are in the powerdown state by setting the PDnAll bit. Attempts to write these bits while the PDnAll bit is cleared will be ignored. Referenced Control Register Location OutputDly[3:0] ..................... “Channel Delay Settings (OutputDly[3:0])” on page 73 50 DS726PP3 CS4525 6.1.9.2 PWM AM Frequency Shift When using a PWM amplifier in a system containing an AM tuner, it is possible that the PWM switch rate conflicts with the desired tuning frequency of the AM tuner. To overcome this effect, the CS4525 includes a PWM switch rate shift feature. The feature adjusts the PWM switching frequency and quantization levels to remove interference when the desired tuning frequency of an AM tuner is positioned near a harmonic of the PWM switching rate. This feature is enabled by setting the FreqShift bit in the Clock Config register. When this feature is enabled, the output switch rate is lowered and the quantization levels are increased as shown in Table 11 below. Supplied XTAL or SYS_CLK Frequency 18.432 MHz 24.576 MHz 27.000 MHz PWM Switch Rate 329.143 kHz 341.300 kHz 375 kHz Quantization Levels 56 72 72 Table 11. PWM Output Switching Rates and Quantization Levels The nominal PWM switching frequencies and quantization levels are discussed in “PWM Modulators and Sample Rate Converters” on page 58. Referenced Control Register Location FreqShift.............................. “AM Frequency Shifting (FreqShift)” on page 70 6.1.10 Headphone Detection & Hardware Mute Input The CS4525 includes a configurable HP_DETECT/MUTE input pin which can be used as a hardware mute input or a headphone detection input. The function of this pin is set by the HP/Mute bit in the Clock Config register. When configured as a mute input pin, all PWM modulators and the AUX_SDOUT signal will be placed in a mute state when the pin is active. When configured as a headphone detect input pin and the HP_DETECT/MUTE input is active, the PWM_SIG1 and PWM_SIG2 output pins can output audio from channel 1 and channel 2 respectively regardless of the setting of the PWMDSel[1:0] bits. The OUT1 - OUT4 PWM driver outputs will mute by outputting a non-modulated 50% duty cycle signal. While the headphone detect input signal is active, the channel mixing, 2-way crossover, and bass management features will all be disabled regardless of the settings of the LChMix[1:0], En2Way, and BassMgr[2:0] bits, respectively. It should be noted that the right channel’s channel mixing is not affected by the headphone detection input signal and will always output as dictated by the RChMix[1:0] bits. See “Channel Mixer” on page 30, “2-Way Crossover & Sensitivity Control” on page 42, and “Bass Management” on page 35 for more information. When configured as a headphone detect input pin and the HP_DETECT/MUTE input is inactive, the OUT1 - OUT4 driver outputs will output audio according to the channel mixer and bass manager bits’ settings, and the PWM_SIG output pins will mute by outputting a non-modulated 50% duty cycle. DS726PP3 51 CS4525 HiZPSig Setting 0 HP/Mute Setting X X HP_DETECT BassMgr [2:0] PWMDSel [1:0] /MUTE Input Setting Setting X X X X 000 (Disabled) Not Active 001 through 111 1 Active Not Active 1 (Headphone Mode) X X 000 (Disabled) 001 through 111 X 00 (Disabled) 01 10 11 01 10 11 01, 10, or 11 01, 10, or 11 01 Active 10 11 01, 10, or 11 0 (Mute Mode) PWM_SIG1 Output PWM_SIG2 Output High Impedance High Impedance Driven Low Channel 1 Channel 1 Channel 2 Channel 1 Channel 1 Channel 2 Mute Mute Channel 1* Channel 1* Channel 2** Channel 1* Driven Low Channel 2 Mute Mute Channel 2 Sub Channel Sub Channel Mute Mute Channel 2** Mute Mute Channel 2** *Signals denoted with one asterisk do not have Bass Manager, 2-Way Crossover, or Channel Mix applied. **Signals denoted with two asterisks do not have Bass Manager or 2-Way Crossover applied. Table 12. Output of PWM_SIG Outputs Table 12 describes the exact output of the PWM_SIG output pins based on the input to the HP_DETECT/MUTE pin and the settings of the HiZPSig, HP/Mute, BassMgr[2:0], and PWMDSel[1:0] bits. In all configurations, the active logic input level is determined by the HP/MutePol bit. Referenced Control Register Location HP/Mute .............................. “HP_Detect/Mute Pin Mode (HP/Mute)” on page 70 HP/MutePol ......................... “HP_Detect/Mute Pin Active Logic Level (HP/MutePol)” on page 70 PWMDSel[1:0]..................... “PWM Signals Output Data Select (PWMDSel[1:0])” on page 73 LChMix[1:0] ......................... “Left Channel Mixer (LChMix[1:0])” on page 76 RChMix[1:0] ........................ “Right Channel Mixer (RChMix[1:0])” on page 76 En2Way............................... “Enable 2-Way Crossover (En2Way)” on page 81 BassMgr[2:0] ....................... “Bass Cross-Over Frequency (BassMgr[2:0])” on page 79 HiZPSig ............................... “Hi-Z PWM_SIG Outputs (HiZPSig)” on page 79 52 DS726PP3 CS4525 6.1.11 Interrupt Reporting The CS4525 has comprehensive interrupt reporting capabilities. Many conditions including SRC lock, ADC overflow, digital data path overflow, and amplifier errors can cause an interrupt. The INT output pin is intended to drive an interrupt input pin on a host microcontroller. The INT pin is an open-drain active-low output and requires an external pull-up for proper operation. If an interrupt source is un-masked, its occurrence will cause the interrupt output pin to become active. To enhance flexibility, each interrupt source may be masked such that its occurrence does not cause the interrupt output pin to become active. This masking function is accomplished by clearing an interrupt’s respective mask bit located in the 4 LSB’s of the Interrupt register. When a specific interrupt condition occurs, its respective bit located in the 4 MSB’s of the Interrupt register will be set to indicate that a change has occurred for the associated interrupt type. When the interrupt register is read, the contents of the 4 MSB’s will be cleared. The Int Status register may then be read to determine the current state of the interrupt source. For specific information regarding interrupt types and reporting, see the Interrupt, Int Status and Amp Error register descriptions. Referenced Control Register Location Interrupt Register ................ “Interrupt (Address 60h)” on page 89 Int Status Register............... “Interrupt Status (Address 61h) - Read Only” on page 92 Amp Error Register ............. “Amplifier Error Status (Address 62h) - Read Only” on page 93 6.1.12 Automatic Power Stage Shut-Down To prevent permanent damage, the CS4525 will automatically shut down its internal PWM power output stages when a thermal error, PWM power output over-current error, or VP under-voltage condition occurs. In the shut-down state, all digital functions of the device will operate as normal, however the PWM power output pins become high-impedance. The levels of the over-current error, thermal error, and VP under-voltage trigger points are listed in the PWM Power Output Characteristics table on page 20. Automatic shut-down will occur whenever any of these preset thresholds are crossed. Once in the shut-down state, each powered PWM outputs will remain as high-impedance and will not resume normal operation until either the PDnAll bit or the PDnOutX bit for the channel in error is set and then cleared. If the AutoRetry bit is set, the CS4525 will attempt to automatically resume power output operation after an over-current error is encountered and before entering the shut-down state. With the AutoRetry function enabled, the CS4525 will place the PWM power outputs in a high-impedance state upon the sensing of an over-current condition, wait approximately 85 ms, and then re-engage the power outputs in an attempt to resume normal operation. If another over-current condition is immediately detected, the PWM power outputs will again be placed in a high-impedance state before retrying to resume normal operation a second time. It will continue this sequence for a maximum of five attempts. After the fifth unsuccessful attempt, the outputs will remain in a high-impedance state until the PDnAll bit is set and then cleared. Referenced Control Register Location AutoRetry ............................ “Automatic Power Stage Retry (AutoRetry)” on page 88 PDnAll ................................. “Power Down (PDnAll)” on page 89 PDnOutX ............................. “Power Down PWM Power Output X (PDnOutX)” on page 89 DS726PP3 53 CS4525 6.2 Hardware Mode A limited feature set is available when the CS4525 powers up in hardware mode. The available features are described in the following sections. All device configuration is achieved via hardware control input pins. 6.2.1 System Clocking In hardware mode, the CS4525 must be clocked by a stable external clock source input on the SYS_CLK pin. This input clock is used to synchronize the input serial audio signals with the internal clock domain and to clock the internal digital processing, sample-rate converter, and PWM modulators. It is also used to determine the sample rate of the serial audio input signals in order to automatically configure the various internal filter coefficients. To ensure proper operation, the CS4525 must be informed of the nominal frequency of the supplied SYS_CLK signal via the ClkFreq0 hardware control pin. This pin must be set to the appropriate level before the RST signal is released to initiate a power-up sequence. The ClkFreq1 pin must always be connected to DGND. The nominal clock frequencies indicated by the state of the ClkFreq0 pin are shown in Table 13 below. See the SYS_CLK Switching Specifications table on page 23 for complete input frequency range specifications. ClkFreq1 Low Low ClkFreq0 Low High Nominal SYS_CLK Frequency 18.432 MHz 24.576 MHz Table 13. SYS_CLK Frequency Selection WARNING: The SYS_CLK signal must never be removed or stopped while the RST pin is high and any of the power output stages are connected to a load. Doing so may result in permanent damage to the CS4525 and connected transducers. Figure 22 below demonstrates a typical clocking configuration using the SYS_CLK input. Clock Clock_In SYS_CLK XTI DSP Reset_Out RST CS4525 XTO Figure 22. Typical SYS_CLK Input Clocking Configuration 6.2.2 Power-Up and Power-Down The CS4525 will remain in a completely powered-down state until the RST pin is brought high. 6.2.2.1 Power-Up Sequence 1. Apply the SYS_CLK signal. 2. Hold RST low until the power supplies and the input SYS_CLK signal are stable. 3. Bring RST high. Hardware mode will be entered after approximately 10 ms. 54 DS726PP3 CS4525 6.2.2.2 Power-Down Sequence 1. Bring MUTE low to mute the device’s outputs and minimize audible pops. 2. Bring RST low to halt the operation of the device. The device’s power consumption will be brought to an absolute minimum. 3. The SYS_CLK signal may now be removed. See section 6.2.1 on page 54 for more information. 4. Remove power. 6.2.3 Input Source Selection The CS4525 can accept analog or digital audio input signals. Digital audio input signals are supplied through the serial audio input port as outlined in “Serial Audio Interfaces” on page 62. Analog audio input signals are supplied through the internal ADC as outlined in “Analog Inputs” on page 61. The input source is selected by the ADC/SP pin as shown in Table 14 below and can be changed at any time without causing any audible pops or clicks. ADC/SP Low High Selected Input Source Digital Audio Inputs (Serial Port) Analog Audio Inputs (ADC) Table 14. Input Source Selection In hardware mode, the serial audio input port supports both I²S and left-justified formats. The serial audio interface format is selected by the I2S/LJ pin as shown in Table 15 below. I2S/LJ Low High Selected Serial Audio Interface Format Left-Justified I²S Table 15. Serial Audio Interface Format Selection 6.2.4 PWM Channel Delay In hardware mode, the CS4525 offsets the PWM switching edges between channels as a method of managing switching noise and reducing radiated emissions. The OUT3/OUT4 signal pair is delayed from the OUT1/OUT2 signal pair by 4 SYS_CLK cycles as shown in Figure 23 below. The absolute delay time is calculated by multiplying the period SYS_CLK by 4. OUT1 OUT2 4 x TSYS_CLK OUT3 OUT4 Figure 23. Hardware Mode PWM Output Delay DS726PP3 55 CS4525 6.2.5 Digital Signal Flow In hardware mode, the CS4525 operates as a 2-channel full-bridge PWM amplifier with analog or digital inputs. Both the PWM outputs and the auxiliary serial outputs are unavailable in hardware mode. To protect against over-temperature conditions, thermal foldback is included for the internal power stages. The digital signal flow is shown in Figure 24 below. MUTE ADC/SP Stereo Analog In Multi-Bit ∆Σ ADC +3dB Thermal Foldback High-Pass Sample Rate Converter Mute PWM Modulator Gate Drive Gate Drive Gate Drive Gate Drive Power Stage Power Stage Power Stage Power Stage Left Full-Bridge Amplifier Output Serial Audio Clocks & Data I²S/LJ Serial Audio Input Port +3dB Sample Rate Converter PWM Modulator Right Full-Bridge Amplifier Output TWR ERROC ERRUVTE EN_TFB Thermal Foldback Temp & Current Sense Figure 24. Hardware Mode Digital Signal Flow 6.2.5.1 High-Pass Filter The CS4525 includes a high-pass filter at the beginning of the digital signal processing chain to remove any DC content from the input signal prior to the remaining internal digital signal processing blocks. The high-pass filter operates by continuously subtracting a measure of the DC offset from the input signal; it is always enabled. 6.2.5.2 Mute Control The CS4525 includes a dedicated MUTE input pin. When low, the PWM outputs will output silence as modulated signal. When high, the selected input source will be presented at the amplifier outputs. It should be noted that the auto-mute, soft-ramp, and zero-crossing detection features are active in hardware mode. 6.2.5.3 Warning and Error Reporting The CS4525 is capable of reporting various error and warning conditions on its TWR, ERROC, and ERRUVTE pins. • • • The TWR pin indicates the presence of a thermal warning condition. When active concurrently with the ERRUVTE pin, indicates a thermal error condition. The ERROC pin indicates the presence of an over-current condition on one or both of the output channels. The ERRUVTE pin indicates the presence of a VP undervoltage condition. When active concurrently with the TWR pin, indicates a thermal error condition. The trigger point for each warning and error condition is defined in the PWM Power Output Characteristics table on page 20. Each pin implements an active-low open-drain driver and requires an external pull-up for proper operation. 56 DS726PP3 CS4525 6.2.6 Thermal Foldback In hardware mode, the CS4525 implements a thermal foldback feature to guard against damaging thermal overload conditions. The thermal foldback feature begins limiting the volume of the digital audio input to the amplifier stage as the junction temperatures rise above the maximum safe operating range specified by the thermal warning trigger point listed in the PWM Power Output Characteristics table on page 20. This effectively limits the output power capability of the device, thereby allowing the temperature to reduce to acceptable levels without fully interrupting operation. As the device cools, the applied attenuation is gradually released until a new thermal equilibrium is reached or all applied attenuation has been released thereby allowing the device to again achieve its full output power capability. Attenuation applied due to thermal foldback reduces the audio output level in a linear manner. Figure 18 below demonstrates the foldback process. Foldback Attack Delay Approximately 2 sec. tdelay tdelay 2 2 2 Thermal Warning Threshold tdelay tdelay tdelay 1 2 3 1 1 2 When the junction temperature crosses the thermal warning threshold, the foldback attack delay timer is started. When the foldback attack delay timer reaches tdelay seconds, the junction temperature is checked. If it is above the thermal warning threshold, the output volume level is lowered by 0.5 dB and the foldback attack timer is restarted. The junction temperature is checked after each foldback attack timer timeout, and if necessary, the output volume level is lowered accordingly. If the junction temperature is found to be below the thermal warning threshold, the foldback attack timer is restarted once again, but the output volume level is not altered. The foldback algorithm then proceeds to step 3. 3 The junction temperature is checked once again after the next foldback attack timer timeout. If is has remained below the thermal warning threshold since the last check, the device will begin to release any attenuation applied as a result of the foldback event. If the junction temperature crosses the thermal warning threshold again, the foldback algorithm will once again enter step 1. Figure 25. Foldback Process Thermal warning conditions will only affect the foldback algorithm and cause attenuation to be applied if enabled by the EN_TFB pin as shown in Table 16 below. EN_TFB Low High Selected Thermal Foldback Enable State Thermal foldback disabled. Thermal foldback enabled. Table 16. Thermal Foldback Enable Selection DS726PP3 57 CS4525 6.2.7 Automatic Power Stage Shut-Down To protect itself from permanent damage, the CS4525 will automatically shut down its internal PWM power output stages when a thermal error, PWM power output over-current error, or VP under-voltage condition occurs. In the shut-down state, all digital functions of the device will operate as normal, however the PWM power output pins become high-impedance. The levels of the over-current error, thermal error, and VP under-voltage trigger points are listed in the PWM Power Output Characteristics table on page 20. Shut-down will occur automatically whenever the preset thresholds for thermal error or under-voltage are crossed. When the over-current threshold is crossed, the CS4525 will attempt to automatically resume power output operation after an over-current error is encountered and before placing its PWM power outputs in the shut-down state. Upon the detection of an over-current condition, the CS4525 will place the PWM power outputs in a high-impedance state, wait approximately 85 ms, and then re-engage the power outputs in an attempt to resume normal operation. If another over-current condition is immediately detected, the PWM power outputs will again be placed in a high-impedance state before retrying to resume normal operation a second time. It will continue this sequence for a maximum of five attempts. After the fifth unsuccessful attempt, the outputs will remain in the high-impedance shut-down state. Once in the shut-down state, the RST signal must be toggled low and then high to resume normal device operation. 6.3 PWM Modulators and Sample Rate Converters The CS4525 includes three PWM modulators and three corresponding sample rate converters, each clocked from the external crystal or system clock applied at power-up. All three modulator and sample rate converter pairs are available in software mode (see Figure 14 on page 29), and two pairs are used in hardware mode (see Figure 24 on page 56). One of the characteristics of a PWM modulator is that the frequency content of the out-of-band noise generated is dependent on the PWM switching frequency. As the power stage external LC and snubber filter component values are used to attenuate this out-of band energy, their component values are also based on this switching frequency. To easily accommodate input sample rates ranging from 32 kHz to 96 kHz without requiring the adjustment of output filter component values, the CS4525 utilizes a sample rate converter (SRC) to keep the PWM switching frequency fixed regardless of the input sample rate. The SRC operates by upsampling the variable input sample rate to a fixed output switching rate, typically 384 kHz for most audio applications. Table 17 below shows the PWM output switching rate and quantization levels as a function of the supplied external crystal or system clock. Additionally, as the output of the SRC is clocked from a very stable crystal or oscillator, the SRC also allows the PWM modulator output to be independent of the input serial audio clock jitter. This results in very low jitter PWM output and higher dynamic range. Supplied XTAL or SYS_CLK Frequency 18.432 MHz 24.576 MHz 27.000 MHz PWM Switch Rate 384 kHz 384 kHz 421.875 kHz Quantization Levels 48 64 64 Table 17. PWM Output Switching Rates and Quantization Levels 58 DS726PP3 CS4525 6.4 Output Filters The output filter configuration of the CS4525 can greatly affect device performance. These components reduce radiated EMI, protect the output transistors of the device, attenuate the high frequency content of the output signal, and, in the half bridge configuration, block DC current from reaching the loudspeaker. 6.4.1 Half-Bridge Output Filter Figure 26 shows the output filter for a half-bridge configuration. A transient voltage suppression circuit is implemented as an RC snubber network comprised of a resistor Rs (5.6 Ω, 1/8 W) and a capacitor Cs (680 pF). This should be placed as close as possible to the corresponding output pin. This circuit decreases the slew rate of the output signal and reduces high frequency ringing which can lead to increased EMI. The Schottky diodes protect the body diodes of the output devices by conducting load current during switching transitions; these diodes must be present to ensure proper device operation. VP CS4525 D1* L1 C2 OUTx Cs 680 pF Rs 5.6 Ω D2* * ROHM RB160 M-30 or equivalent C1 Figure 26. Output Filter - Half-Bridge The inductor L1 and capacitor C1 form a low-pass filter to remove high frequency switching content from the output signal. These values combine with the nominal load impedance of the speaker to set the cutoff frequency of the filter. Table 18 shows the component values for L1 and C1 based on nominal speaker impedance for a corner frequency of approximately 35 kHz (-3 dB). Load 4Ω 6Ω 8Ω L1 22 µH 33 µH 47 µH C1 1.0 µF 0.68 µF 0.47 µF Table 18. Low-Pass Filter Components - Half-Bridge C2 serves to block DC from the output. Table 19 shows the component values for C2 based on desired corner frequency (-3 dB) and nominal speaker impedances of 4 Ω, 6 Ω, and 8 Ω. This capacitor should be chosen to have a ripple current rating higher than the amount of current that will pass through it. Load 4Ω Corner Frequency 40 Hz 58 Hz 120 Hz 39 Hz 68 Hz 120 Hz 42 Hz 60 Hz 110 Hz C2 1000 µF 680 µF 330 µF 680 µF 390 µF 220 µF 470 µF 330 µF 180 µF 6Ω 8Ω Table 19. DC-Blocking Capacitors Values - Half-Bridge DS726PP3 59 CS4525 6.4.2 Full-Bridge Output Filter (Stereo or Parallel) Figure 27 shows the output filter for stereo full-bridge and parallel full-bridge output configurations. Transient voltage suppression circuits are implemented as a RC snubber networks comprised of resistors Rs (5.6 Ω, 1/8 W) and capacitors Cs (680 pF). These should be placed as close as possible to the corresponding output pin. These circuits decrease the slew rate of the output signal and reduce high frequency ringing which can lead to increased EMI. The Schottky diodes protect the body diodes of the output devices by conducting load current during switching transitions; these diodes must be present to ensure proper device operation. VP CS4525 D1* L1 OUT+ Cs 680 pF Rs 5.6 Ω D2* * ROHM RB160 M-30 or equivalent C1 VP D3* L2 OUTCs 680 pF Rs 5.6 Ω D4* Figure 27. Output Filter - Full-Bridge The inductors L1 and L2 along with capacitor C1 form the low-pass filter. These values combine with the nominal load impedance of the speaker to set the cut-off frequency of the filter. Table 20 shows the component values based on nominal speaker impedance for a corner frequency of approximately 35 kHz (-3 dB). Load 4Ω 6Ω 8Ω L1, L2 10 µH 15 µH 22 µH C1 1.0 µF 0.47 µF 0.47 µF Table 20. Low-Pass Filter Components - Full-Bridge 60 DS726PP3 CS4525 6.5 Analog Inputs Very few components are required to interface between the audio source and the CS4525’s analog inputs, AINL and AINR. A single order passive low-pass filter is recommended to prevent high-frequency content from aliasing into the audio band due to the analog-to-digital conversion process. Also, a DC-blocking capacitor is required as the CS4525’s analog inputs are internally biased to VQ. The recommended analog input circuit is shown in Figure 28 below will accommodate full-scale input voltages as defined in the Analog Input Characteristics table on page 19. This circuit provides the necessary high-frequency filtering with a first-order passive low-pass filter that has less than 0.05 dB of attenuation at 24 kHz. It also includes a DC blocking capacitor to accommodate the analog input pins’ bias level. CS4525 1 µF Left Input 100 k Ω 365 Ω 1800 pF C0G AINL 1 µF Right Input 100 k Ω 365 Ω 1800 pF C0G AINR Figure 28. Recommended Unity Gain Input Filter To interface 2 VRMS input signals with the CS4525’s analog inputs, an external resistor divider is required. Figure 29 shows the recommended input circuit for 2 VRMS inputs. It includes a -8.4 dB passive attenuator to condition the input signal for the CS4525’s full-scale input voltage, a first-order passive low-pass filter that has less than 0.05 dB of attenuation at 24 kHz, and a DC blocking capacitor to accommodate for the analog input pins’ bias level. The passive attenuator network should be placed as close as possible to the CS4525’s analog input pins to reduce the potential for noise and signal coupling into the analog input traces. CS4525 Left Input 8.06 kΩ 5.62 k Ω 1 µF AINL 100 pF C0G Right Input 8.06 kΩ 5.62 k Ω 1 µF AINR 100 pF C0G Figure 29. Recommended 2 VRMS Input Filter It should be noted that the external DC blocking capacitor forms a high-pass filter with the CS4525’s input impedance. Both filters shown above have less than 0.2 dB attenuation at 20 Hz due to this effect. Increasing the value of this capacitor will lower this high-pass corner frequency, and decreasing it’s value will increase the corner frequency. DS726PP3 61 CS4525 6.6 Serial Audio Interfaces The CS4525 interfaces to external digital audio devices via the serial audio input port and the auxiliary/delay serial ports. The serial audio input port provides support for I²S, Left-Justified and Right-Justified data formats and operates in slave mode only, with LRCK and SCLK as inputs. The input LRCK signal must be equal to the sample rate, Fs and must be synchronous to the serial bit clock, SCLK, which is used to sample the data bits. The auxiliary/delay serial port (available in software mode only) supports I²S and Left-Justified data formats and operates in master mode only, with AUX_LRCK and AUX_SCLK as outputs. Each of the supported formats is described in detail in sections 6.6.1 - 6.6.3 below. Please refer to the Serial Audio Input Port Switching Specifications and AUX Serial Audio I/O Port Switching Specifications on page 21 and page 22 (respectively) for the precise timing and tolerances of each signal. For additional information, application note AN282 presents a tutorial of the 2-channel serial audio interface. AN282 can be downloaded from the Cirrus Logic web site at http://www.cirrus.com. 6.6.1 I²S Data Format In I²S format, data is received most significant bit first one SCLK delay after the transition of LRCK and is valid on the rising edge of SCLK. The left channel data is presented when LRCK is low; the right channel data is presented when LRCK is high. LRCK Left Channel Right Channel SCLK SDIN MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 30. I²S Serial Audio Formats 6.6.2 Left-Justified Data Format In Left-Justified format, data is received most significant bit first on the first SCLK after a LRCK transition and is valid on the rising edge of SCLK. The left channel data is presented when LRCK is high and the right channel data is presented when LRCK is low. LRCK Left Channel Right Channel SCLK SDIN MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 31. Left-Justified Serial Audio Formats 62 DS726PP3 CS4525 6.6.3 Right-Justified Data Format In Right-Justified format, data is received most significant bit first and with the least significant bit presented on the last SCLK before the LRCK transition and is valid on the rising edge of SCLK. For the RightJustified format, the left channel data is presented when LRCK is high and the right channel data is presented when LRCK is low. 16, 18, 20, and 24 bits per sample are supported. LRCK Left Channel Right Channel SCLK SDIN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 65 4 3 2 1 0 Figure 32. Right-Justified Serial Audio Formats 6.7 Integrated VD Regulator The CS4525 includes two internal linear regulators, one from the VD supply voltage to provide a fixed 2.5 V supply to its internal digital blocks, and another from the VD supply voltage to provide a fixed 2.5 V supply to its internal analog blocks. The LVD pin must be set to indicate the voltage present on the VD pin as shown in Table 21 below. VD Connection 5 V Supply 3.3 V Supply 2.5 V Supply VD_REG Connection Bypass Capacitors Only Bypass Capacitors Only VD and Bypass Capacitors VA_REG Connection Bypass Capacitors Only Bypass Capacitors Only VD and Bypass Capacitors LVD Connection VD DGND DGND SelectVD Bit Setting Software Mode Only ‘1’ - Default ‘1’ - Default ‘0’ Table 21. Power Supply Configuration and Settings The output of the digital regulator is presented on the VD_REG pin and may be used to provide an external device with up to 3 mA of current at its nominal output voltage of 2.5 V. The output of the analog regulator is presented on the VA_REG pin and must only be connected to the bypass capacitors as shown in the typical connection diagrams. If a nominal supply voltage of 2.5 V is used as the VD supply (see the Recommended Operating Conditions table on page 18), the VD, VD_REG, and VA_REG pins must all be connected to the VD supply source. In this configuration, the internal regulators are bypassed and the external supply source is used to directly drive the internal digital and analog sections. Referenced Control Register Location SelectVD ............................. “Select VD Level (SelectVD)” on page 88 DS726PP3 63 CS4525 6.8 I²C Control Port Description and Timing The control port is used to access the registers allowing the CS4525 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample serial port. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates in I²C Mode, with the CS4525 acting as a slave device. SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. A 47 kΩ pull-up or pull-down on the AUX_LRCK/AD0 pin will set AD0, the least significant bit of the device address. A pullup to VD will set AD0 to ‘1’ and a pull-down to DGND will set AD0 to ‘0’. The state of AUX_LRCK/AD0 is sensed, and AD0 is set upon the release of RESET. The signal timings for a read and write cycle are shown in Figure 33 and Figure 34. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4525 after a Start condition consists of a 7 bit device address field and a R/W bit (high for a read, low for a write). The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a CS4525, the device address field, which is the first byte sent to the CS4525, should match 100101 followed by the setting of AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the memory address pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS4525 after each input byte is read, and is input to the CS4525 from the microcontroller after each transmitted byte. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) MAP BYTE 0 INCR DATA 1 0 7 6 1 0 7 DATA +1 6 1 0 7 DATA +n 6 1 0 SDA 1 0 0 1 0 1 AD0 6 5 4 3 2 ACK START ACK ACK ACK STOP Figure 33. Control Port Timing, I²C Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) MAP BYTE INCR STOP 1 0 1 CHIP ADDRESS (READ) 0 0 1 0 1 AD0 1 DATA 7 0 DATA +1 7 0 DATA + n 7 0 SDA 1 0 0 1 0 1 AD0 0 6 5 4 3 2 ACK START ACK START ACK ACK NO ACK STOP Figure 34. Control Port Timing, I²C Read Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown in Figure 34, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 100101x0 (device address and write operation). Receive acknowledge bit. Send MAP byte, auto increment off. Receive acknowledge bit. Send stop condition, aborting write. (Optional.) Send start condition. Send 100101x1(device address and read operation). 64 DS726PP3 CS4525 Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. (Optional.) 7. PCB LAYOUT CONSIDERATIONS 7.1 Power Supply, Grounding The CS4525 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS4525 as possible. The lowest value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the CS4525 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and AGND. The CRD4525 reference design demonstrates the optimum layout and power supply arrangements. 7.2 Output Filter Layout The CS4525 also requires careful attention to the layout of the output filter. This will ensure optimum device performance and EMI standards compliance. The CRD4525 customer reference designs incorporate many techniques and practices that should be followed in any design using this device and should be referred to as a guide during the PCB design process. The output components should be placed as close as possible to the device with the following priority listed from the CS4525 outward: 1. The small value VP bypass capacitors must be placed on the same layer as the CS4525 immediately adjacent to the each of the device’s VP pins. 2. Following the small value VP bypass capacitors, the RC snubber circuits must be placed on the same layer as the CS4525 and as close to the device's output pins as possible. 3. The Schottky protection diodes must be placed on the same layer as the CS4525 adjacent to and immediately following the RC snubber components. 4. The LC output filters must be placed on the same layer as the CS4525 adjacent to and immediately following the Schottky protection diodes, keeping the trace length as short as possible to reduce radiated EMI. Avoid any breaks in the ground and power planes beneath high-frequency switching signals. Parasitic inductances should be reduced by the use of multiple smaller vias instead of a single large via when connecting a output filter and power supply bypass capacitors to a ground or power plane. In addition to improving the thermal performance of the design, filling all unused areas with copper will help reduce both EMI emissions and coupling between adjacent signals. Finally, 150 pF capacitors should be placed directly across the speaker outputs to shunt remaining high frequency energy prior to the output cables. Any proposed layout should be directly compared to the CRD4525 customer reference designs before manufacture. 7.3 QFN Thermal Pad The underside of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of thermal vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers. The CRD4525 reference design demonstrates the optimum thermal pad and via configuration. DS726PP3 65 CS4525 8. REGISTER QUICK REFERENCE This table shows the register names and their associated default values. Adr Name 7 6 5 4 3 2 1 0 FreqShift 0 DIF0 0 LChDSel0 0 OutputDly0 0 RmpSpd0 1 LChMix0 0 EnToneCtrl 0 Bass0 0 EnChAPEq 0 MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB 01h Clock Config EnSysClk DivSysClk ClkFreq1 ClkFreq0 HP/MutePol HP/Mute PhaseShift page 69 1 0 0 1 0 0 0 EnAnHPF Reserved SPRate1 SPRate0 DIF2 DIF1 02h Input Config ADC/SP page 71 0 1 0 x x 0 0 03h Aux Config EnAuxPort DlyPortCfg1 DlyPortCfg0 AuxI²S/LJ RChDSel1 RChDSel0 LChDSel1 page 72 0 0 0 0 0 1 0 04h Output Cfg OutputCfg1 OutputCfg0 PWMDSel1 PWMDSel0 OutputDly3 OutputDly2 OutputDly1 page 73 0 0 0 0 0 0 0 05h Foldback Cfg SelectVP EnTherm LockAdj AttackDly1 AttackDly0 EnFloor RmpSpd1 page 74 1 0 0 0 1 0 1 06h Mixer Config PreScale2 PreScale1 PreScale0 Reserved RChMix1 RChMix0 LChMix1 page 75 0 0 0 0 0 0 0 07h Tone Config DeEmph Loudness EnDigHPF TrebFc1 TrebFc0 BassFc1 BassFc0 page 76 0 0 0 0 0 0 1 08h Tone Control Treble3 Treble2 Treble1 Treble0 Bass3 Bass2 Bass1 page 78 1 0 0 0 1 0 0 BassMgr2 BassMgr1 BassMgr0 Reserved EnChBPEq 09h EQ Config Freeze HiZPSig page 78 0 0 0 0 0 0 0 0Ah MSB ............................................................................................................................. BiQuad 1 0Bh MSB-8 ............................................................................................................................. A1 Coeff 0Ch LSB+7 ............................................................................................................................. 0Dh MSB ............................................................................................................................. BiQuad 1 0Eh MSB-8 ............................................................................................................................. A2 Coeff 0Fh LSB+7 ............................................................................................................................. 10h MSB ............................................................................................................................. BiQuad 1 11h MSB-8 ............................................................................................................................. B0 Coeff 12h LSB+7 ............................................................................................................................. 13h MSB ............................................................................................................................. BiQuad 1 14h MSB-8 ............................................................................................................................. B1 Coeff 15h LSB+7 ............................................................................................................................. 16h MSB ............................................................................................................................. BiQuad 1 17h MSB-8 ............................................................................................................................. B2 Coeff 18h LSB+7 ............................................................................................................................. 19h MSB ............................................................................................................................. BiQuad 2 1Ah MSB-8 ............................................................................................................................. A1 Coeff 1Bh LSB+7 ............................................................................................................................. 1Ch MSB ............................................................................................................................. BiQuad 2 1Dh MSB-8 ............................................................................................................................. A2 Coeff 1Eh LSB+7 ............................................................................................................................. 1Fh MSB ............................................................................................................................. BiQuad 2 20h MSB-8 ............................................................................................................................. B0 Coeff 21h LSB+7 ............................................................................................................................. 22h MSB ............................................................................................................................. BiQuad 2 23h MSB-8 ............................................................................................................................. B1 Coeff 24h LSB+7 ............................................................................................................................. 66 DS726PP3 CS4525 Adr 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h Name BiQuad 2 B2 Coeff BiQuad 3 A1 Coeff BiQuad 3 A2 Coeff BiQuad 3 B0 Coeff BiQuad 3 B1 Coeff BiQuad 3 B2 Coeff BiQuad 4 A1 Coeff BiQuad 4 A2 Coeff BiQuad 4 B0 Coeff BiQuad 4 B1 Coeff BiQuad 4 B2 Coeff BiQuad 5 A1 Coeff BiQuad 5 A2 Coeff BiQuad 5 B0 Coeff BiQuad 5 B1 Coeff BiQuad 5 B2 Coeff 7 MSB MSB-8 LSB+7 MSB MSB-8 LSB+7 MSB MSB-8 LSB+7 MSB MSB-8 LSB+7 MSB MSB-8 LSB+7 MSB MSB-8 LSB+7 MSB MSB-8 LSB+7 MSB MSB-8 LSB+7 MSB MSB-8 LSB+7 MSB MSB-8 LSB+7 MSB MSB-8 LSB+7 MSB MSB-8 LSB+7 MSB MSB-8 LSB+7 MSB MSB-8 LSB+7 MSB MSB-8 LSB+7 MSB MSB-8 LSB+7 6 5 4 3 2 1 0 MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB MSB-7 LSB+8 LSB ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. ............................................................................................................................. DS726PP3 67 CS4525 Adr Name 7 6 5 Mute50/50 0 LowPass1 0 MVol5 1 ChAVol5 1 ChBVol5 1 SubVol5 1 InvCh2 0 Max0 0 RRate5 1 ARate5 0 SelectVD 1 ChOvfl x SubOvflSt x OverCurr2 x DeviceID2 1 4 AutoMute 1 LowPass0 0 MVol4 0 ChAVol4 1 ChBVol4 1 SubVol4 1 InvCh1 0 Min2 0 RRate4 1 ARate4 0 PDnADC 1 AmpErr x Ch2OvflSt x OverCurr1 x DeviceID1 1 3 2 1 0 55h Volume Cfg page 80 56h Sensitivity page 81 57h Master Vol page 82 58h Ch A Vol page 83 59h Ch B Vol page 83 5Ah Sub Vol page 83 5Bh Mute Control page 84 5Ch Limiter Cfg 1 page 85 5Dh Limiter Cfg 2 page 87 5Eh Limiter Cfg 3 page 87 5Fh Power Ctrl page 88 60h Interrupt page 89 61h Int Status page 92 62h Amp Error page 93 63h Device ID page 94 SZCMode1 SZCMode0 1 0 LowPass3 LowPass2 0 0 MVol7 MVol6 0 0 ChAVol7 ChAVol6 0 0 ChBVol7 ChBVol6 0 0 SubVol7 SubVol6 0 0 InvADC InvSub 0 0 Max2 Max1 0 0 Reserved Reserved 0 0 EnThLim Reserved 0 0 AutoRetry EnOCProt 1 1 SRCLock ADCOvfl x x SRCLockSt ADCOvflSt x x OverCurr4 OverCurr3 x x DeviceID4 DeviceID3 1 1 En2Way 2WayFreq2 2WayFreq1 2WayFreq0 0 0 0 0 HighPass3 HighPass2 HighPass1 HighPass0 0 0 0 0 MVol3 MVol2 MVol1 MVol0 1 0 1 0 ChAVol3 ChAVol2 ChAVol1 ChAVol0 0 0 0 0 ChBVol3 ChBVol2 ChBVol1 ChBVol0 0 0 0 0 SubVol3 SubVol2 SubVol1 SubVol0 0 0 0 0 MuteADC MuteSub MuteChB MuteChA 0 0 0 0 Min1 Min0 LimitAll EnLimiter 0 0 1 0 RRate3 RRate2 RRate1 RRate0 1 1 1 1 ARate3 ARate2 ARate1 ARate0 0 0 0 0 PDnOut3/4 PDnOut2 PDnOut1 PDnAll 1 1 1 1 SRCLockM ADCOvflM ChOvflM AmpErrM 0 0 0 0 Ch1OvflSt RampDone Reserved Reserved x x 0 0 ExtAmpSt Reserved UVTE1 UVTE0 x 0 x x DeviceID0 RevID2 RevID1 RevID0 1 x x x 68 DS726PP3 CS4525 9. REGISTER DESCRIPTIONS All registers are read/write unless otherwise stated. All “Reserved” bits must maintain their default state. 9.1 Clock Configuration (Address 01h) 6 DivSysClk 5 ClkFreq1 4 ClkFreq0 3 HP/MutePol 2 HP/Mute 1 PhaseShift 0 FreqShift 7 EnSysClk 9.1.1 SYS_CLK Output Enable (EnSysClk) Default = 1 Function: This bit controls the output driver for the SYS_CLK signal. When cleared, the output driver is disabled and the SYS_CLK pin is high-impedance. When set, the output driver is enabled. If the SYS_CLK output is unused, this bit should be set to ‘0’b to disable the driver. EnSysClk Setting Output Driver State 0 ..........................................Output driver disabled. 1 ..........................................Output driver enabled. 9.1.2 SYS_CLK Output Divider (DivSysClk) Default = 0 Function: This bit determines the divider for the XTAL clock signal for generating the SYS_CLK signal. This divider is only available if the clock source is an external crystal attached to XTI/XTO and the SYS_CLK output is enabled. DivSysClk Setting SYS_CLK Output Frequency 0 ..........................................FSYS_CLK = FXTAL 1 ..........................................FSYS_CLK = FXTAL/2 9.1.3 Clock Frequency (ClkFreq[1:0]) Default = 01 Function: These bits must be set to identify the nominal clock frequency of the crystal attached to the XTI/XTO pins or that of the input SYS_CLK signal. See the XTI Switching Specifications table on page 23 and the SYS_CLK Switching Specifications table on page 23 for complete input frequency range specifications. ClkFreq[1:0] Setting Specified Nominal Input Clock Frequency 00 ........................................18.432 MHz 01 ........................................24.576 MHz 10 ........................................27.000 MHz 11.........................................Reserved DS726PP3 69 CS4525 9.1.4 HP_Detect/Mute Pin Active Logic Level (HP/MutePol) Default = 0 Function: This bit determines the active logic level for the HP_DETECT/MUTE input signal. HP/MutePol Setting Headphone Detect/Mute Input Polarity 0 .......................................... Active low. 1 .......................................... Active high. 9.1.5 HP_Detect/Mute Pin Mode (HP/Mute) Default = 0 Function: Configures the function of HP_DETECT/MUTE input pin. See “Headphone Detection & Hardware Mute Input” on page 51 for more information. HP/Mute Setting HP_DETECT/MUTE Pin Function 0 .......................................... Mute input signal. 1 .......................................... Headphone detect input signal. 9.1.6 Modulator Phase Shifting (PhaseShift) Default = 0 Function: When enabled, forces the output of the PWM modulator to output differential signals which are the inverse of each other and have been phase shifted by 180 degrees. This causes, for instance, the differential signal pair to be exactly in phase with one another during a mute condition, thereby reducing the amount of switching current through the load. PhaseShift Setting Modulator Phase Shift State 0 .......................................... 180º phase shift disabled. 1 .......................................... 180º phase shift enabled. 9.1.7 AM Frequency Shifting (FreqShift) Default = 0 Function: Controls the state of the PWM AM frequency shift feature. See “PWM AM Frequency Shift” on page 51 for more information. FreqShift Setting AM Frequency Shift State 0 .......................................... Frequency shift disabled. 1 .......................................... Frequency shift enabled. 70 DS726PP3 CS4525 9.2 Input Configuration (Address 02h) 6 EnAnHPF 5 Reserved 4 SPRate1 3 SPRate0 2 DIF2 1 DIF1 0 DIF0 7 ADC/SP 9.2.1 Input Source Selection (ADC/SP) Default = 0 Function: This bit selects the audio input source. ADC/SP Setting Audio Input Source 0 ..........................................Digital input from the serial audio input port. 1 ..........................................Analog input from the internal ADC. 9.2.2 ADC High-Pass Filter Enable (EnAnHPF) Default = 1 Function: Controls the operation of the ADC high-pass filter. EnAnHPF Setting ADC High-Pass Filter State 0 ..........................................ADC high-pass filter disabled. 1 ..........................................ADC high-pass filter enabled. 9.2.3 Serial Port Sample Rate (SPRate[1:0]) - Read Only Function: Identifies the sample rate of the incoming LRCK signal on the serial audio input port based on the setting of the ClkFreq[1:0] bits in Register 01h, the frequency of the internal system clock, and the frequency of the input LRCK signal. SPRate[1:0] Setting Identified Input Sample Rate 00 ........................................32 kHz 01 ........................................44.1 kHz 10 ........................................48 kHz 11.........................................96 kHz 9.2.4 Input Serial Port Digital Interface Format (DIF [2:0]) Default = 000 Function: Selects the serial audio interface format used for the data in on SDIN. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in the section “Serial Audio Interfaces” on page 62. DIF[2:0] Setting Input Serial Port Serial Audio Interface Format 000 ......................................Left-Justified, up to 24-bit data. 001 ......................................I²S, up to 24-bit data. 010 ......................................Right-Justified, 24-bit data. 011.......................................Right-Justified, 20-bit data. 100 ......................................Right-Justified, 18-bit data. 101 ......................................Right-Justified, 16-bit data. 110.......................................Reserved. 111 .......................................Reserved. DS726PP3 71 CS4525 9.3 AUX Port Configuration (Address 03h) 6 DlyPortCfg1 5 DlyPortCfg0 4 AuxI²S/LJ 3 RChDSel1 2 RChDSel0 1 LChDSel1 0 LChDSel0 7 EnAuxPort 9.3.1 Enable Aux Serial Port (EnAuxPort) Default = 0 Function: Controls the operation of the auxiliary serial port. EnAuxPort Setting Auxiliary Port State 0 .......................................... Auxiliary port disabled. 1 .......................................... Auxiliary port enabled. 9.3.2 Delay & Warning Port Configuration (DlyPortCfg[1:0]) Default = 00 Function: Controls the operation of the delay and warning port. See “Serial Audio Delay & Warning Input Port” on page 44 for more information. DlyPortCfg[1:0] Setting Delay Port Configuration 00 ........................................ Port disabled. 01 ........................................ Port configured as serial audio delay interface. 10 ........................................ Port configured as an external thermal warning indicator for the foldback algorithm. 11......................................... Port disabled. 9.3.3 Aux/Delay Serial Port Digital Interface Format (AuxI²S/LJ) Default = 0 Function: Selects the serial audio interface format for the data on AUX_SDOUT, DLY_SDIN, DLY_SDOUT. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in the “Serial Audio Interfaces” on page 62. AuxI²S/LJ Setting Auxiliary/Delay Port Serial Audio Interface Format 0 .......................................... Left-Justified, up to 24-bit. 1 .......................................... I²S, up to 24-bit. 9.3.4 Aux Serial Port Right Channel Data Select (RChDSel[1:0]) Default = 01 Function: Selects the data to be sent over the right channel of the auxiliary port serial data output signal. RChDSel[1:0] Setting Aux Serial Port Right Channel Output Data Source 00 ........................................ Channel A. 01 ........................................ Channel B. 10 ........................................ Sub Channel. 11......................................... Channel B crossover high-pass output. 72 DS726PP3 CS4525 9.3.5 Aux Serial Port Left Channel Data Select (LChDSel[1:0]) Default = 00 Function: Selects the data to be sent over the left channel of the auxiliary port serial data output signal. LChDSel[1:0] Setting Aux Serial Port Left Channel Output Data Source 00 ........................................Channel A. 01 ........................................Channel B. 10 ........................................Sub Channel. 11.........................................Channel B crossover low-pass output. 9.4 Output Configuration (Address 04h) 6 OutputCfg0 5 PWMDSel1 4 PWMDSel0 3 OutputDly3 2 OutputDly2 1 OutputDly1 0 OutputDly0 7 OutputCfg1 9.4.1 Output Configuration (OutputCfg[1:0]) Default = 00 Function: Identifies the power output configuration. This parameter can only be changed when all modulators and associated logic are in the power-down state (the PDnAll bit is set). Attempts to write this register while the PDnAll is cleared will be ignored. See “Output Channel Configurations” on page 45 for more information. OutputCfg[1:0] Setting Power Output Configuration 00 ........................................Channel 1 & 2 Full-Bridge. 01 ........................................Channel 1 & 2 Half-Bridge + Sub Channel Full-Bridge. 10 ........................................Channel 1 Parallel Full-Bridge. 11.........................................Reserved. 9.4.2 PWM Signals Output Data Select (PWMDSel[1:0]) Default = 00 Function: Selects the PWM data output on the PWM_SIG1 and PWM_SIG2 output signals.See “PWM_SIG LogicLevel Output Configurations” on page 49 for more information. PWMDSel Setting PWM Signal Output Mapping 00 ........................................PWM_SIG1 output disabled. PWM_SIG2 output disabled. 01 ........................................Channel 1 output on PWM_SIG1. Channel 2 output on PWM_SIG2. 10 ........................................Channel 1 output on PWM_SIG1. Sub Channel output on PWM_SIG2. 11.........................................Channel 2 output on PWM_SIG1. Sub Channel output on PWM_SIG2. 9.4.3 Channel Delay Settings (OutputDly[3:0]) Default = 0000 Function: The channel delay bits allow delay adjustment of each of the power output audio channels. The value of this register determines the amount of delay inserted in the output path. The delay time is calculated by multiplying the register value by the period of the SYS_CLK or crystal input clock source. These bits can DS726PP3 73 CS4525 only be changed while all modulators and associated logic are in the power-down state (the PDnAll bit is set). Attempts to write these bits while the PDnAll bit is cleared will be ignored. See “PWM Channel Delay” on page 55 for more information. OutputDly[3:0] Setting Output Delay in Input Clock Source Cycles 0000 .................................... 0 - No Delay 0001 .................................... 1 0010 .................................... 2 .................................... 1000 .................................... 8 .................................... 1111 ..................................... 15 - Max Delay 9.5 Foldback and Ramp Configuration (Address 05h) 6 EnTherm 5 LockAdj 4 AttackDly1 3 AttackDly0 2 EnFloor 1 RmpSpeed1 0 RmpSpeed0 7 SelectVP 9.5.1 Select VP Level (SelectVP) Default = 1 Function: Adjusts the PWM modulation index to maximize output power for applications with a nominal VP voltage of less than or equal to 14 V. This bit must remain set for applications with a nominal VP voltage greater than 14 V. SelectVP Setting Selected VP Level 0 .......................................... VP ≤ 14 Volts 1 .......................................... VP > 14 Volts. 9.5.2 Enable Thermal Foldback (EnTherm) Default = 0 Function: Enables the thermal foldback feature. See “Thermal Foldback” on page 40 for more information. EnTherm Setting Thermal Foldback State 0 .......................................... Disabled. 1 .......................................... Enabled. 9.5.3 Lock Foldback Adjust (LockAdj) Default = 0 Function: Controls the operation of the foldback lock adjustment feature. See “Thermal Foldback” on page 40 for more information. LockAdj Setting Foldback Adjustment Lock State 0 .......................................... Attenuation lock disabled. 1 .......................................... Attenuation lock enabled. 74 DS726PP3 CS4525 9.5.4 Foldback Attack Delay (AttackDly[1:0]) Default = 01 Function: Controls the foldback attack delay. See “Thermal Foldback” on page 40 for more information. AttackDly[1:0] Setting Foldback Attack Time 00 ........................................Approximately 0.5 seconds. 01 ........................................Approximately 1.0 seconds. 10 ........................................Approximately 1.5 seconds. 11.........................................Approximately 2.0 seconds. 9.5.5 Enable Foldback Floor (EnFloor) Default = 0 Function: Controls the foldback attenuation floor feature. See “Thermal Foldback” on page 40 for more information. EnFloor Setting Attenuation Floor 0 ..........................................No foldback attenuation floor imposed. 1 ..........................................Maximum foldback attenuation limited to -30 dB. 9.5.6 Ramp Speed (RmpSpd[1:0]) Default = 11 Function: Controls the PWM output ramp speed. See “PWM Popguard Transient Control” on page 45 for more information. RmpSpd[1:0] Setting Ramp Speed 00 ........................................Fastest Ramp Speed 10 ........................................Slowest Ramp Speed 11.........................................Immediate. PWM Popguard Disabled. 9.6 Mixer / Pre-Scale Configuration (Address 06h) 6 PreScale1 5 PreScale0 4 Reserved 3 RChMix1 2 RChMix0 1 LChMix1 0 LChMix0 7 PreScale2 9.6.1 Pre-Scale Attenuation (PreScale[2:0]) Default = 000 Function: Controls the pre-scale attenuation level. See “Pre-Scaler” on page 30 for more information. PreScale[2:0] Setting Pre-Scale Attenuation Setting 000 ......................................No pre-scale attenuation applied. 001 ......................................-2.0 dB 010 ......................................-4.0 dB ...................................... 100 ......................................-8.0 dB ...................................... 111 .......................................-14.0 dB DS726PP3 75 CS4525 9.6.2 Right Channel Mixer (RChMix[1:0]) Default = 00 Function: Controls the right channel mixer output. See “Channel Mixer” on page 30 for more information. RChMix[1:0] Setting Right Channel Mixer Output on Channel B 00 ........................................ Right Channel 01 ........................................ (Left Channel + Right Channel) / 2 10 ........................................ (Left Channel + Right Channel) / 2 11......................................... Left Channel 9.6.3 Left Channel Mixer (LChMix[1:0]) Default = 00 Function: Controls the left channel mixer output. See “Channel Mixer” on page 30 for more information. LChMix[1:0] Setting Left Channel Mixer Output on Channel A 00 ........................................ Left Channel 01 ........................................ (Left Channel + Right Channel) / 2 10 ........................................ (Left Channel + Right Channel) / 2 11......................................... Right Channel 9.7 Tone Configuration (Address 07h) 6 Loudness 5 EnDigHPF 4 TrebFc1 3 TrebFc0 2 BassFc1 1 BassFc0 0 EnToneCtrl 7 DeEmph 9.7.1 De-Emphasis Control (DeEmph) Default = 0 Function: Controls the operation of the internal de-emphasis filter. See “De-Emphasis” on page 31 for more information. DeEmph Setting De-Emphasis State 0 .......................................... No de-emphasis applied. 1 .......................................... 44.1 kHz 50/15 µs de-emphasis filter applied. 9.7.2 Adaptive Loudness Compensation Control (Loudness) Default = 0 Function: Controls the operation of the adaptive loudness compensation feature. See “Adaptive Loudness Compensation” on page 34 for more information. Loudness Setting Adaptive Loudness Compensation State 0 .......................................... Disabled. 1 .......................................... Enabled. 76 DS726PP3 CS4525 9.7.3 Digital Signal Processing High-Pass Filter (EnDigHPF) Default = 0 Function: Controls the operation of the digital signal processing high-pass filter. See “Digital Signal Processing High-Pass Filter” on page 30 for more information. EnDigHPF Setting Digital Signal Processing High-Pass Filter State 0 ..........................................Digital signal processing high-pass filter disabled. 1 ..........................................Digital signal processing high-pass filter enabled. 9.7.4 Treble Corner Frequency (TrebFc[1:0]) Default = 00 Function: Sets the corner frequency for the treble shelving filter as shown below. TrebFc[1:0] Setting Treble Corner Frequency 00 ........................................Selects Treble Fc 0 - Approximately 5 kHz 01 ........................................Selects Treble Fc 1 - Approximately 7 kHz 10 ........................................Selects Treble Fc 2 - Approximately 10 kHz 11.........................................Selects Treble Fc 3 - Approximately 15 kHz 9.7.5 Bass Corner Frequency (BassFc[1:0]) Default = 01 Function: Sets the corner frequency for the bass shelving filter as shown below. BassFc[1:0] Setting Bass Corner Frequency 00 ........................................Selects Bass Fc 0 - Approximately 50 Hz 01 ........................................Selects Bass Fc 1 - Approximately 100 Hz 10 ........................................Selects Bass Fc 2 - Approximately 200 Hz 11.........................................Selects Bass Fc 3 - Approximately 250 Hz 9.7.6 Tone Control Enable (EnToneCtrl) Default = 0 Function: When set, enables the bass and treble shelving filters. When cleared, disables the bass and treble shelving filters. EnToneCtrl Setting Tone Control Filter State 0 ..........................................Bass and treble shelving filters disabled. 1 ..........................................Bass and treble shelving filters enabled. DS726PP3 77 CS4525 9.8 Tone Control (Address 08h) 6 Treble2 5 Treble1 4 Treble0 3 Bass3 2 Bass2 1 Bass1 0 Bass0 7 Treble3 9.8.1 Treble Gain Level (Treb[3:0]) Default = 1000 Function: Sets the gain/attenuation level of the treble shelving filter.The level can be adjusted in 1.5 dB steps from +12.0 to -10.5 dB. Treb[3:0] Setting Treble Shelving Filter Gain/Attenuation 0000 .................................... +12 dB 0001 .................................... +10.5 dB ..................................... 1000 .................................... 0 dB ..................................... 1110 ..................................... -9.0 dB 1111 ..................................... -10.5 dB 9.8.2 Bass Gain Level (Bass[3:0]) Default = 1000 Function: Sets the gain/attenuation level of the bass shelving filter. The level can be adjusted in 1.5 dB steps from +12.0 to -10.5 dB. Bass[3:0] Setting Bass Shelving Filter Gain/Attenuation 0000 .................................... +12 dB 0001 .................................... +10.5 dB ..................................... 1000 .................................... 0 dB ..................................... 1110 ..................................... -9.0 dB 1111 ..................................... -10.5 dB 9.9 2.1 Bass Manager/Parametric EQ Control (Address 09h) 7 Freeze 6 HiZPSig 5 BassMgr2 4 BassMgr1 3 BassMgr0 2 Reserved 1 EnChBPEq 0 EnChAPEq 9.9.1 Freeze Controls (Freeze) Default = 0 Function: This function will freeze the previous output of, and allow modifications to be made to the master volume control (address 57h), channel X volume control (address 58h - 5Ah), and bi-quad coefficient registers for channel A, and channel B (address 0Ah - 54h) without the changes taking effect until the Freeze bit is disabled. To make multiple changes in these control port registers take effect simultaneously, enable the Freeze bit, make all register changes, then disable the Freeze bit. Freeze Setting Register Freeze State 0 .......................................... Register freeze disabled. 1 .......................................... Register freeze enabled. 78 DS726PP3 CS4525 9.9.2 Hi-Z PWM_SIG Outputs (HiZPSig) Default = 0 Function: When cleared, the PWM_SIG1 and PWM_SIG2 output drivers are placed in a high-impedance state. When set, the PWM_SIG1 and PWM_SIG2 output drivers are active. It should be noted that the function of the PWM_SIG outputs is determined by the PWMDSel[1:0] bits in Register 04h. HiZPSig Setting PWM_SIG Output Driver State 0 ..........................................High impedance. 1 ..........................................Drivers active. 9.9.3 Bass Cross-Over Frequency (BassMgr[2:0]) Default = 000 Function: Controls the operation and cross-over frequency of the bass manager. See “Bass Management” on page 35 for more information. BassMgr[2:0] Setting Bass Manager Crossover Setting 000 ......................................Bass manager disabled. 001 ......................................Selects Bass Manager Frequency 1 - Approximately 80 Hz 010 ......................................Selects Bass Manager Frequency 2 - Approximately 120 Hz 011.......................................Selects Bass Manager Frequency 3 - Approximately 160 Hz 100 ......................................Selects Bass Manager Frequency 4 - Approximately 200 Hz 101 ......................................Selects Bass Manager Frequency 5 - Approximately 240 Hz 110.......................................Selects Bass Manager Frequency 6 - Approximately 280 Hz 111 .......................................Selects Bass Manager Frequency 7 - Approximately 320 Hz 9.9.4 Enable Channel B Parametric EQ (EnChBPEq) Default = 0 Function: Enables the parametric EQ bi-quad filters for channel B. EnChBPEq Setting Channel B Parametric EQ State 0 ..........................................Disabled. 1 ..........................................Enabled. 9.9.5 Enable Channel A Parametric EQ (EnChAPEq) Default = 0 Function: Enables the parametric EQ bi-quad filters for channel A. EnChAPEq Setting Channel A Parametric EQ State 0 ..........................................Disabled. 1 ..........................................Enabled. DS726PP3 79 CS4525 9.10 Volume and 2-Way Cross-Over Configuration (Address 55h) 6 SZCMode0 5 Mute50/50 4 AutoMute 3 En2Way 2 2WayFreq2 1 2WayFreq1 0 2WayFreq0 7 SZCMode1 9.10.1 Soft Ramp and Zero Cross Control (SZCMode[1:0]) Default = 10 Function: Sets the soft ramp and zero crossing detection modes by which volume and muting changes will be implemented. SZCMode[1:0] Setting Soft Ramp & Zero Crossing Mode 00 ........................................ Immediate Change When immediate change is selected, all level changes will take effect immediately in one step. 01 ........................................ Zero Cross Zero cross dictates that signal level changes, both muting and attenuation, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period (approximately 18.7 ms for a PWM switch rate of 384/768 kHz and 17.0 ms for a PWM switch rate of 421.875/843.75 kHz) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. 10 ........................................ Soft Ramp Soft ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in ½ dB steps, from the current level to the new level at a rate of ½ dB per 4 sample periods for 32, 44.1, and 48 kHz, and ½ dB per 8 sample periods for 96 kHz. 11......................................... Soft Ramp on Zero Cross Soft ramp on zero cross dictates that signal level changes, both muting and attenuation, will occur in ½ dB steps and be implemented on a signal zero crossing. The ½ dB level change will occur after a timeout period (approximately 18.7 ms for a PWM switch rate of 384/768 kHz and 17.0 ms for a PWM switch rate of 421.875/843.75 kHz) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. 9.10.2 Enable 50% Duty Cycle for Mute Condition (Mute50/50) Default = 0 Function: When set, the amplifiers will output a non-modulated 50%-duty-cycle signal for all mute conditions. This bit does not cause a mute condition to occur. The Mute50/50 bit only defines operation during a normal mute condition. Mute50/50 Setting 50% Duty Cycle Mute State 0 .......................................... 50% duty cycle for mute conditions disabled. 1 .......................................... 50% duty cycle for mute conditions enabled. 9.10.3 Auto-Mute (AutoMute) Default = 1 Function: When enabled, the outputs of the CS4525 will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. See “Volume and Muting Control” on page 36 for more information. AutoMute Setting AutoMute State 0 .......................................... Auto-mute on static 0’s or -1’s disabled. 1 .......................................... Auto-mute on static 0’s or -1’s enabled. 80 DS726PP3 CS4525 9.10.4 Enable 2-Way Crossover (En2Way) Default = 0 Function: Enables the 2-way crossover filters for channel 1 and channel 2. En2Way Setting 2-Way Crossover State 0 ..........................................2-way crossover disabled. 1 ..........................................2-way crossover enabled. 9.10.5 2-Way Cross-Over Frequency (2WayFreq[2:0]) Default = 000 Function: Selects the cross-over frequency for the 2-Way Linkwitz-Riley filters. 2WayFreq Setting 2-Way Crossover Frequency 000 ......................................Selects X-Over Freq 0 - Approximately 2.0 kHz 001 ......................................Selects X-Over Freq 1 - Approximately 2.2 kHz 010 ......................................Selects X-Over Freq 2 - Approximately 2.4 kHz 011.......................................Selects X-Over Freq 3 - Approximately 2.6 kHz 100 ......................................Selects X-Over Freq 4 - Approximately 2.8 kHz 101 ......................................Selects X-Over Freq 5 - Approximately 3.0 kHz 110.......................................Selects X-Over Freq 6 - Approximately 3.2 kHz 111 .......................................Selects X-Over Freq 7 - Approximately 3.4 kHz 9.11 Channel A & B: 2-Way Sensitivity Control (Address 56h) 6 LowPass2 5 LowPass1 4 LowPass0 3 HighPass3 2 HighPass2 1 HighPass1 0 HighPass0 7 LowPass3 9.11.1 Channel A and Channel B Low-Pass Sensitivity Adjust (LowPass[3:0]) Default = 0000 Function: Controls the 2-way cross-over low-pass sensitivity adjustment. See “2-Way Crossover & Sensitivity Control” on page 42 for more information. LowPass[3:0] Setting Sensitivity Compensation Level 0000 ....................................0.0 dB 0001 ....................................-0.5 dB 0010 ....................................-1.0 dB ..................................... 1000 ....................................-4.0 dB ..................................... 1110 .....................................-7.0 dB 1111 .....................................-7.5 dB DS726PP3 81 CS4525 9.11.2 Channel A and Channel B High-Pass Sensitivity Adjust (HighPass[3:0]) Default = 0000 Function: Controls the 2-way cross-over high-pass sensitivity adjustment. See “2-Way Crossover & Sensitivity Control” on page 42 for more information. HighPass[3:0] Setting Sensitivity Compensation Level 0000 .................................... 0.0 dB 0001 .................................... -0.5 dB 0010 .................................... -1.0 dB ..................................... 1000 .................................... -4.0 dB ..................................... 1110 ..................................... -7.0 dB 1111 ..................................... -7.5 dB 9.12 Master Volume Control (Address 57h) 6 MVol6 5 MVol5 4 MVol4 3 MVol3 2 MVol2 1 MVol1 0 MVol0 7 MVol7 9.12.1 Master Volume Control (MVol[7:0]) Default = 2Ah Function: Sets the gain/attenuation level of the master volume control. See “Volume and Muting Control” on page 36 for more information. MVol[7:0] Setting Master Volume Setting 0000 0000 ........................... +24 dB ............................ 0010 1010 ........................... +3 dB ............................ 0011 0000............................ 0.0 dB 0011 0001............................ -0.5 dB 0011 0010............................ -1.0 dB ............................ 1111 1110............................. -103.0 dB 1111 1111 ............................. Master Mute 82 DS726PP3 CS4525 9.13 Channel A and B Volume Control (Address 58h & 59h) 6 ChXVol6 5 ChXVol5 4 ChXVol4 3 ChXVol3 2 ChXVol2 1 ChXVol1 0 ChXVol0 7 ChXVol7 9.13.1 Channel X Volume Control (ChXVol[7:0]) Default = 30h Function: Sets the gain/attenuation levels of channel A and channel B. See “Volume and Muting Control” on page 36 for more information. ChXVol[7:0] Setting Channel X Volume Setting 0000 0000 ...........................+24 dB ............................ 0011 0000............................0.0 dB 0011 0001............................-0.5 dB 0011 0010............................-1.0 dB ............................ 1111 1110.............................-103.0 dB 1111 1111 .............................Channel Mute 9.14 Sub Channel Volume Control (Address 5Ah) 6 SubVol6 5 SubVol5 4 SubVol4 3 SubVol3 2 SubVol2 1 SubVol1 0 SubVol0 7 SubVol7 9.14.1 Sub Channel Volume Control (SubVol[7:0]) Default = 30h Function: Sets the gain/attenuation levels of the sub channel. See “Volume and Muting Control” on page 36 for more information. SubVol[7:0] Setting Sub Channel Volume Setting 0000 0000 ...........................+24 dB ............................ 0011 0000............................0.0 dB 0011 0001............................-0.5 dB 0011 0010............................-1.0 dB ............................ 1111 1110.............................-103.0 dB 1111 1111 .............................Channel Mute DS726PP3 83 CS4525 9.15 Mute/Invert Control (Address 5Bh) 6 InvSub 5 InvCh2 4 InvCh1 3 MuteADC 2 MuteSub 1 MuteChB 0 MuteChA 7 InvADC 9.15.1 ADC Invert Signal Polarity (InvADC) Default = 0 Function: When set, the signal polarity of the ADC will be inverted. InvADC Setting ADC Signal Inversion State 0 .......................................... ADC signal polarity not inverted. 1 .......................................... ADC signal polarity inverted. 9.15.2 Invert Channel PWM Signal Polarity (InvChX) Default = 0 Function: When set, the respective channel’s power and logic-level PWM output signal polarity will be inverted. The serial output on the auxiliary and delay ports are unaffected. InvChX Setting Channel X PWM Signal Inversion State 0 .......................................... Channel X PWM signal polarity not inverted. 1 .......................................... Channel X PWM signal polarity inverted. 9.15.3 Invert Sub PWM Signal Polarity (InvSub) Default = 0 Function: When set, the Sub channel’s power and logic-level PWM output polarity will be inverted. The serial output on the auxiliary port is unaffected. InvSub Setting Sub Channel PWM Signal Inversion State 0 .......................................... Sub channel PWM signal polarity not inverted. 1 .......................................... Sub channel PWM signal polarity inverted. 9.15.4 ADC Channel Mute (MuteADC) Default = 0 Function: The output of the ADC will mute when enabled. MuteADC Setting ADC Mute State 0 .......................................... ADC un-muted. 1 .......................................... ADC muted. 9.15.5 Independent Channel A & B Mute (MuteChX) Default = 0 Function: The respective channel’s power PWM, logic-level PWM, and auxiliary serial data outputs will enter a mute state when enabled. The delay serial output will be unaffected if the delay port is enabled. The muting 84 DS726PP3 CS4525 function is affected, similar to attenuation changes, by the soft and zero cross bits (SZCMode[1:0]). See “Volume and Muting Control” on page 36 for more information. MuteChX Setting Channel X PWM Mute State 0 ..........................................Channel X PWM outputs un-muted. 1 ..........................................Channel X PWM outputs muted. 9.15.6 Sub Channel Mute (MuteSub) Default = 0 Function: The sub channel’s power PWM, logic-level PWM, and auxiliary serial data outputs will enter a mute state when enabled. The muting function is affected, similar to attenuation changes, by the soft and zero cross bits (SZCMode[1:0]). See “Volume and Muting Control” on page 36 for more information. MuteSub Setting Sub Channel PWM Mute State 0 ..........................................Sub channel PWM outputs un-muted. 1 ..........................................Sub channel PWM outputs muted. 9.16 Limiter Configuration 1 (Address 5Ch) 6 Max1 5 Max0 4 Min2 3 Min1 2 Min0 1 LimitAll 0 EnLimiter 7 Max2 9.16.1 Maximum Threshold (Max[2:0]) Default = 000 Function: Sets the maximum level, below full scale, at which to limit and attenuate the output signal at the limiter attack rate. Max[2:0] Setting Maximum Threshold Setting 000 ......................................0.0 dB 001 ......................................-3.0 dB 010 ......................................-6.0 dB 011.......................................-9.0 dB 100 ......................................-12.0 dB 101 ......................................-18.0 dB 110.......................................-24.0 dB 111 .......................................-30.0 dB 9.16.2 Minimum Threshold (Min[2:0]) Default = 000 Function: Sets a minimum level below full scale at which the limiter will begin to release its applied attenuation. Min[2:0] Setting Minimum Threshold Setting 000 ......................................0.0 dB 001 ......................................-3.0 dB 010 ......................................-6.0 dB 011.......................................-9.0 dB 100 ......................................-12.0 dB 101 ......................................-18.0 dB 110.......................................-24.0 dB 111 .......................................-30.0 dB DS726PP3 85 CS4525 9.16.3 Peak Signal Limit All Channels (LimitAll) Default = 1 Function: When cleared, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the specific channel indicating clipping. The other channels will not be affected. When set, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on all channels in response to any single channel indicating clipping. See “Peak Signal Limiter” on page 37 for more information. LimitAll Setting Limit All Channels Configuration 0 .......................................... Only individual channels affected by any limiter event. 1 .......................................... All channels affected by any limiter event. 9.16.4 Peak Detect and Limiter Enable (EnLimiter) Default = 0 Function: Limits the maximum signal amplitude to prevent clipping when this function is enabled. Peak signal limiting is performed by digital attenuation. EnLimiter Setting Peak Signal Limiter State 0 .......................................... Peak signal limiter disabled. 1 .......................................... Peak signal limiter enabled. 86 DS726PP3 CS4525 9.17 Limiter Configuration 2 (Address 5Dh) 6 Reserved 5 RRate5 4 RRate4 3 RRate3 2 RRate2 1 RRate1 0 RRate0 7 Reserved 9.17.1 Limiter Release Rate (RRate[5:0]) Default = 111111 Function: Sets the rate at which the limiter releases the digital attenuation from levels below the minimum setting in the limiter threshold register. The limiter release rate is a function of the sampling frequency, Fs, and the soft and zero cross setting. RRate[5:0] Setting Limiter Release Rate 000000 ................................Fastest release. ................................... 111111..................................Slowest release. 9.18 Limiter Configuration 3 (Address 5Eh) 6 Reserved 5 ARate5 4 ARate4 3 ARate3 2 ARate2 1 ARate1 0 ARate0 7 EnThLim 9.18.1 Enable Thermal Limiter (EnThLim) Default = 0 Function: When set, enables the thermal limiter function. The thermal limiter function adds an additional -3dB of attenuation to the min and max settings of the peak signal limiter the first time a thermal warning is detected after the thermal limiter function has been enabled. For more details, see the “Thermal Limiter” section on page 39. EnThLim Setting Thermal Limiter State 0 ..........................................Thermal limiter disabled. 1 ..........................................Thermal limiter enabled. 9.18.2 Limiter Attack Rate (ARate[5:0]) Default = 000000 Function: Sets the rate at which the limiter attenuates the analog output from levels above the maximum setting in the limiter threshold register. The limiter attack rate is a function of the sampling frequency, Fs, and the soft and zero cross setting. ARate[5:0] Setting Limiter Attack Rate 00000 ..................................Fastest attack. ................................... 11111....................................Slowest attack. DS726PP3 87 CS4525 9.19 Power Control (Address 5Fh) 6 EnOCProt 5 SelectVD 4 PDnADC 3 PDnOut3/4 2 PDnOut2 1 PDnOut1 0 PDnAll 7 AutoRetry 9.19.1 Automatic Power Stage Retry (AutoRetry) Default = 1 Function: Enables the Auto-Retry function upon over-current error. See “Automatic Power Stage Shut-Down” on page 53. AutoRetry Setting Auto-Retry State 0 .......................................... Auto-Retry feature disabled. 1 .......................................... Auto-Retry feature enabled. 9.19.2 Enable Over-Current Protection (EnOCProt) Default = 1 Function: Enables the PWM power output over-current protection feature described in “Automatic Power Stage Shut-Down” on page 53. WARNING: The EnOCProt bit must never to changed from its default value of 1. Doing so will disable the over-current protection feature and may result in permanent damage to the CS4525. 9.19.3 Select VD Level (SelectVD) Default = 1 Function: This bit selects between a VD of 2.5 V, 3.3 V, or 5.0 V. SelectVD Setting Selected VD Level 0 .......................................... VD = 2.5 V. 1 .......................................... VD = 3.3 V or 5.0 V. 9.19.4 Power Down ADC (PDnADC) Default = 1 Function: The ADC will enter a power down state when this bit is enabled. PDnADC Setting ADC Power-Down State 0 .......................................... Normal ADC operation. 1 .......................................... ADC power-down enabled. 88 DS726PP3 CS4525 9.19.5 Power Down PWM Power Output X (PDnOutX) Default = 1 Function: When set, the specific PWM power output will enter a power-down state. Only the output power stage is powered down. The PWM modulator is not affected, nor is the setup or delay register values. When set to normal operation, the specific output will power up according to the state of the RmpSpd[1:0] bits and the channel output configuration selected. When transitioning from normal operation to power down, the specific output will power down according to the state of the RmpSpd[1:0] bits and the channel output configuration selected. PDnChX Setting Power Output X Power-Down State 0 ..........................................Normal power output X operation. 1 ..........................................Power output X power-down enabled. The entire divide will enter a low-power state when this function is enabled: 9.19.6 Power Down (PDnAll) Default = 1 Function: The CS4525 will enter a power-down state when this function is enabled: 1. The power PWM outputs will be held in a high-impedance state. 2. The logic-level PWM outputs will continuously drive a logic ‘0’ if the HiZPSig bit is set and will be held in a high-impedance state if the HiZPSig bit is clear. 3. AUX_SDOUT, the auxiliary serial data output, will be driven to a digital-low. AUX_LRCK and AUX_SCLK, the auxiliary serial output’s clocks, will continue to operate if the EnAuxPort bit is set, ADC/SP is cleared, and the serial audio input receives a valid SCLK and LRCK; otherwise they will also be driven to a digital-low voltage. 4. DLY_SDOUT, the delay serial data output, will output the unprocessed audio data from SDATA if EnAuxPort is set, DlyPortCfg[1:0] is configured for serial output delay interface, ADC/SP is cleared, and the serial audio input port receives a valid SCLK, LRCK, and SDATA. Otherwise, it will drive a low voltage. The contents of the control registers are retained in this state. Once the PDnAll bit is disabled, the powered and logic-level PWM outputs will first perform a click-free start-up function and then resume normal operation. The PDnAll bit defaults to ‘enabled’ on power-up and must be disabled before normal operation can occur. PDnAll Setting Device Power-Down State 0 ..........................................Normal device operation. 1 ..........................................Device power-down enabled. 9.20 Interrupt (Address 60h) 6 ADCOvfl 5 ChOvfl 4 AmpErr 3 SRCStateM 2 ADCOvflM 1 ChOvflM 0 AmpErrM 7 SRCLock Bits [7:4] in this register are read only. A ‘1’b in these bit positions indicates that the associated condition has occurred at least once since the register was last read. A ‘0’b indicates that the associated condition has not occurred since the last reading of the register. Reading the register resets bits to [7:4] ‘0’b. These bits are considered “edgetriggered” events. The operation of these 4 bits is not affected by the interrupt mask bits and the condition of each bit can be polled instead of generating an interrupt as required. DS726PP3 89 CS4525 9.20.1 SRC Lock State Transition Interrupt (SRCLock) Function: This bit is read only. When set, indicates that the SRC has transitioned from an unlock to lock state or from a lock state to an unlock state since the last read of this register. Conditions which cause the SRC to transition states, such as loss of LRCK, SCLK, an LRCK ratio change, or the SRC achieving lock, will cause this bit to be set. This interrupt bit is an edge-triggered event and will be cleared following a read of this register. If this bit is set, indicating a SRC state change condition, and the SRCLockM bit is set, the INT pin will go active. To determine the current lock state of the SRC, read the SRCLockSt bit in the interrupt status register. SRCLock Setting SRC Lock State Change Status 0 .......................................... SRC lock state unchanged since last read of this register. 1 .......................................... SRC lock state changed since last read of this register. 9.20.2 ADC Overflow Interrupt (ADCOvfl) Function: This bit is read only. When set, indicates that an over-range condition occurred anywhere in the CS4525 ADC signal path and has been clipped to positive or negative full scale as appropriate since the last read of this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this register. If this bit is set, indicating an ADC over-range condition, and the ADCOvflM bit is set, the INT pin will go active. To determine the current overflow state of the ADC, read the ADCOvflSt bit in the interrupt status register. ADCOvfl Setting ADC Overflow Event Status 0 .......................................... ADC overflow condition has not occurred since last read of this register. 1 .......................................... ADC overflow condition has occurred since last read of this register. 9.20.3 Channel Overflow Interrupt (ChOvfl) Function: This bit is read only. When set, indicates that the magnitude of an output sample on channel 1, 2, or the Sub channel has exceeded full scale and has been clipped to positive or negative full scale as appropriate since the last read of this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this register. If this bit is set, indicating a channel over-range condition, and the ChOvflM bit is set, the INT pin will go active. To determine the current overflow state of each channel, read the ChXOvflSt and SubOvflSt bits in the interrupt status register. ChOvfl Setting Channel Overflow Event Status 0 .......................................... A channel overflow condition has not occurred since last read of this register. 1 .......................................... A channel overflow condition has occurred since last read of this register. 90 DS726PP3 CS4525 9.20.4 Amplifier Error Interrupt Bit (AmpErr) Function: This bit is read only. When set, indicates that an error was detected in the power amplifier section since the last read of this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this register. This bit is the logical OR of all the bits in the amplifier error status register. Read the amplifier error status register to determine which condition occurred. If this bit is set, indicating an amplifier stage error condition, and the AmpErrM bit is set to a ‘1’b, the INT pin will go active. To determine the actual current state of the amplifier error condition, read the amplifier error status register. AmpErr Setting Amplifier Error Event Status 0 ..........................................An amplifier error condition has not occurred since last read of this register. 1 ..........................................An amplifier error condition has occurred since last read of this register. 9.20.5 Mask for SRC State (SRCLockM) Default = 0 Function: This bit serves as a mask for the SRC status interrupt source. If this bit is set, the SRCLock interrupt is unmasked, meaning that if the SRCLock bit is set, the INT pin will go active. If the SRCLockM bit is cleared, the SRCLock condition is masked, meaning that its occurrence will not affect the INT pin. However, the SRCLock and SRCLockSt bits will continue to reflect the lock status of the SRC. SRCLockM Setting SRCLock INT Pin Mask State 0 ..........................................SRCLock condition masked. 1 ..........................................SRCLock condition un-masked. 9.20.6 Mask for ADC Overflow (ADCOvflM) Default = 0 Function: This bit serves as a mask for the ADC overflow interrupt source. If this bit is set, the ADCOvfl interrupt is unmasked, meaning that if the ADCOvfl bit is set, the INT pin will go active. If the ADCOvflM bit is cleared, the ADCOvfl condition is masked, meaning that its occurrence will not affect the INT pin. However, the ADCOvfl and ADCOvflSt bits will continue to reflect the overflow state of the ADC. ADCOvflM Setting ADCOvfl INT Pin Mask State 0 ..........................................ADCOvfl condition masked. 1 ..........................................ADCOvfl condition un-masked. 9.20.7 Mask for Channel X and Sub Overflow (ChOvflM) Default = 0 Function: This bit serves as a mask for the channel 1, 2, and Sub overflow interrupt source. If this bit is set, the ChOvfl interrupt is unmasked, meaning that if the ChOvfl bit is set, the INT pin will go active. If the ChOvflM bit is cleared, the ChOvfl condition is masked, meaning that its occurrence will not affect the INT pin. However, the ChOvfl, ChXOvflSt, and SubOvflSt bits will continue to reflect the overflow state of the individual channels. ChOvflM Setting ChOvfl INT Pin Mask State 0 ..........................................ChOvfl condition masked. 1 ..........................................ChOvfl condition un-masked. DS726PP3 91 CS4525 9.20.8 Mask for Amplifier Error (AmpErrM) Default = 0 Function: This bit serves as a mask for the amplifier error interrupt sources. If this bit is set, the AmpErr interrupt is unmasked, meaning that if the AmpErr bit is set, the INT pin will go active. If the AmpErrM bit is cleared, the AmpErr condition is masked, meaning that its occurrence will not affect the INT pin. However, the AmpErr and the amplifier error bits in the amplifier error status register will continue to reflect the status of the amplifier error conditions. AmpErrM Setting AmpErr INT Pin Mask State 0 .......................................... AmpErr condition masked. 1 .......................................... AmpErr condition un-masked. 9.21 Interrupt Status (Address 61h) - Read Only 6 ADCOvflSt 5 SubOvflSt 4 Ch2OvflSt 3 Ch1OvflSt 2 RampDone 1 Reserved 0 Reserved 7 SRCLockSt All bits in this register are considered “level-triggered” events, meaning as long as a condition continues, the corresponding bit will remain set. These status bits are not affected by the interrupt mask bit and the condition of each bit can be polled. These bits will not be cleared following a read to this register, nor can they be written to cause an interrupt condition. 9.21.1 SRC State Transition (SRCLockSt) Function: This bit is read only and reflects the current lock state of the SRC. When set, indicates the SRC is currently locked. When cleared, indicates the SRC is currently unlocked. SRCLockSt Setting SRC Lock State 0 .......................................... SRC is currently unlocked. 1 .......................................... SRC is currently locked. 9.21.2 ADC Overflow (ADCOvflSt) Function: This bit is read only and will identify the presence of an overflow condition within the ADC. When set, indicates that an over-range condition is currently occurring in the CS4525 ADC signal path and has been clipped to positive or negative full scale. ADCOvflSt Setting ADC Overflow State 0 .......................................... An ADC overflow condition is not currently present. 1 .......................................... An ADC overflow condition is currently present. 9.21.3 Sub Overflow (SubOvflSt) Function: This bit is read only and will identify the presence of an overflow condition anywhere in the Sub channel’s signal path. When set, indicates that an over-range condition is currently occurring in the Sub channel’s signal path and has been clipped to positive or negative full scale. SubOvflSt Setting Sub Overflow State 0 .......................................... An overflow condition is not currently present on the Sub channel. 1 .......................................... An overflow condition is currently present on the Sub channel. 92 DS726PP3 CS4525 9.21.4 Channel X Overflow (ChXOvflSt) Function: These bits are read only and will identify the presence of an overflow condition anywhere in the associated channel’s signal path. When set, indicates that an over-range condition is currently occurring in the channel’s signal path and has been clipped to positive or negative full scale. ChXOvflSt Setting Channel X Overflow State 0 ..........................................An overflow condition is not currently present on channel X. 1 ..........................................An overflow condition is currently present on channel X. 9.21.5 Ramp-Up Cycle Complete (RampDone) Function: When set, indicates that all active channels have completed the configured ramp-up interval. RampDone Setting Ramp Completion State 0 ..........................................Ramp-up interval not completed on all channels. 1 ..........................................Ramp-up interval completed on all channels. 9.22 Amplifier Error Status (Address 62h) - Read Only 6 OverCurr3 5 OverCurr2 4 OverCurr1 3 ExtAmpErr 2 Reserved 1 UVTE1 0 UVTE0 7 OverCurr4 All bits in this register are considered “level-triggered” events, meaning as long as a condition continues, the corresponding bit will remain set. These status bits are not affected by the interrupt mask bit and the condition of each bit can be polled. These bits will not be cleared following a read to this register, nor can they be written to cause an interrupt condition. 9.22.1 Over-Current Detected On Channel X (OverCurrX) Function: When set, indicates an over current condition is currently present on the corresponding amplifier output. OverCurrX Setting Amplifier Over-Current Status 0 ..........................................An over current condition is not currently present on amplifier output X. 1 ..........................................An over current condition is currently present on amplifier output X. 9.22.2 External Amplifier State (ExtAmpSt) Function: When set, indicates a thermal warning condition is currently being reported by an external amplifier. For proper operation, the delay serial port must be configured to support an external thermal warning input signal. This status bit reflects the active state of the external thermal warning input signal. ExtAmpSt Setting External Amplifier Status 0 ..........................................A thermal warning condition is not currently being reported by an external amplifier. 1 ..........................................A thermal warning condition is currently being reported by an external amplifier. DS726PP3 93 CS4525 9.22.3 Under Voltage / Thermal Error State (UVTE[1:0]) Function: Indicates the operational status of the amplifier. These bits can identify a Thermal Warning condition, a Thermal Error condition, or an Under Voltage condition. The thresholds for each of these conditions is listed in the PWM Power Output Characteristics table on page 20. UVTE[1:0] Setting Under Voltage & Thermal Error Status 00 ........................................ The device is operating normally. 01 ........................................ The device is operating normally; however a Thermal Warning condition is being reported. 10 ........................................ An Under Voltage condition is currently present. 11......................................... A Thermal Error condition is currently present. 9.23 Device I.D. and Revision (Address 63h) - Read Only 6 DeviceID3 5 DeviceID2 4 DeviceID1 3 DeviceID0 2 RevID2 1 RevID1 0 RevID0 7 DeviceID4 9.23.1 Device Identification (DeviceID[4:0]) Default =11111 Function: Identification code for the CS4525. DeviceID[4:0] Setting Device ID Notes 11111.................................... Permanent device identification code. 9.23.2 Device Revision (RevID[2:0]) Function: Identifies the CS4525 device revision. RevID[2:0] Setting Device Revision 000 ...................................... Revision A0 and B0. 010 ...................................... Revision C0. 94 DS726PP3 CS4525 10.PARAMETER DEFINITIONS Dynamic Range (DYR) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth, typically 20 Hz to 20 kHz. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured as suggested in AES17-1991 Annex A. Frequency Response FR is the deviation in signal level verses frequency. The 0 dB reference point is 1 kHz. The amplitude corner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz reference point. The listed minimum and maximum frequencies are guaranteed to be within the Ac from minimum frequency to maximum frequency inclusive. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/°C. Fs Sampling Frequency. Resolution The number of bits in a serial audio data word. SRC Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. 11.REFERENCES 1. Cirrus Logic, “AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,” Version 6.0, February 1998. 2. Cirrus Logic, “AN22: Overview of Digital Audio Interface Data Structures, Version 2.0”, February 1998.; A useful tutorial on digital audio specifications. 3. Philips Semiconductor, “The I²C-Bus Specification: Version 2,” Dec. 1998. http://www.semiconductors.philips.com DS726PP3 95 CS4525 12.PACKAGE DIMENSIONS 48L QFN (9 × 9 MM BODY) PACKAGE DRAWING D b e Pin #1 ID Pin #1 ID E E2 A1 A Top View Side View L D2 Bottom View DIM A A1 b D D2 E E2 e L MIN -0.0000 0.0118 0.2618 0.2618 0.0177 INCHES NOM --0.0138 0.3543 BSC 0.2677 0.3543 BSC 0.2677 0.0256 BSC 0.0217 MAX 0.0354 0.0020 0.0157 0.2736 0.2736 0.0276 MIN -0.00 0.30 6.65 6.65 0.45 MILLIMETERS NOM --0.35 9.00 BSC 6.80 9.00 BSC 6.80 0.65 BSC 0.55 NOTE MAX 0.90 0.05 0.40 6.95 6.95 0.70 1 1 1,2 1 1 1 1 1 1 JEDEC #: MO-220 Controlling Dimension is Millimeters. Table 22: Notes: 1. Dimensioning and tolerance per ASME Y4.5M - 1994. 2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. 96 DS726PP3 CS4525 13.THERMAL CHARACTERISTICS Parameter Junction to Case Thermal Impedance Symbol θJC Min - Typ 1 Max - Units °C/Watt 13.1 Thermal Flag This device is designed to have the metal flag on the bottom of the device soldered directly to a metal plane on the PCB. To enhance the thermal dissipation capabilities of the system, this metal plane should be coupled with vias to a large metal plane on the backside (and inner ground layer, if applicable) of the PCB. In either case, it is beneficial to use copper fill in any unused regions inside the PCB layout, especially those immediately surrounding the CS4525. In addition to improving in electrical performance, this practice also aids in heat dissipation. The heat dissipation capability required of the metal plane for a given output power can be calculated as follows: θCA = [(TJ(MAX) - TA) / PD] - θJC where, θCA = Thermal resistance of the metal plane in °C/Watt TJ(MAX) = Maximum rated operating junction temperature in °C, equal to 150 °C TA = Ambient temperature in °C PD = RMS power dissipation of the device, equal to 0.176*PRMS-OUT (assuming 85% efficiency) θJC = Junction-to-case thermal resistance of the device in °C/Watt 14.ORDERING INFORMATION Product CS4525 Description Digital Audio Amp with Integrated ADC 4 Layer / 1oz. Copper Reference Design Board 2 Layer / 1oz. Copper Reference Design Board Package Pb-Free 48-QFN Yes Grade Commercial Temp Range Container Rail 0° to +70°C Tape and Reel - Order# CS4525-CNZ CS4525-CNZR CRD4525-Q1 CRD4525-Q1 - - - - CRD4525-D1 - - - - - CRD4525-D1 DS726PP3 97 CS4525 15.REVISION HISTORY Release Changes The following items were updated: “Analog Input Characteristics” on page 19 “PWM Power Output Characteristics” on page 20 “XTI Switching Specifications” on page 23 “SYS_CLK Switching Specifications” on page 23 “Digital Interface Specifications” on page 25 Section 6.4.1 “Half-Bridge Output Filter” on page 59 Section 6.4.2 “Full-Bridge Output Filter (Stereo or Parallel)” on page 60 Table 21, “Power Supply Configuration and Settings,” on page 63 Section 9.19.3 “Select VD Level (SelectVD)” on page 88 Added Section 9.19.2 “Enable Over-Current Protection (EnOCProt)” on page 88 Updated the temperature range shown in the General Description on page 2, in the Recommended Operating Conditions table on page 18, and in the Ordering Information table on page 97. Updated the description of the CLK_FREQ1 pin in Section 2. “Pin Descriptions - Hardware Mode” on page 10. Added reference to Note 16 to the Output Sample Rate and AUX_SCLK Frequency specifications in the AUX Serial Audio I/O Port Switching Specifications table on page 22. Updated Note 15 on page 23. Added Note 16 on page 23. Updated the Software Mode Power-Up and Power-Down sequences in sections 6.1.2.1 and 6.1.2.2. Updated Section 6.2.1 “System Clocking” on page 54 to reflect the requirement for the CLK_FREQ1 pin to be connected to DGND. Updated the Hardware Mode Power-Up and Power-Down sequences in sections 6.2.2.1 and 6.2.2.2. Updated Section 6.4.1 “Half-Bridge Output Filter” on page 59 Updated Section 6.4.2 “Full-Bridge Output Filter (Stereo or Parallel)” on page 60 Added Section 7.2 “Output Filter Layout” on page 65 Re-defined PD in terms of PRMS-OUT in the “Thermal Flag” section on page 97. PP1 PP2 PP3 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor. 98 DS726PP3