CS47028C-CQZ

CS470xx Data Sheet FEATURES Cost-effective, High-performance 32-bit DSP — — — — 300,000,000 MAC/S (multiply accumulates per second) Dual MAC cycles per clock 72-bit accumulators are the highest precision in the industry 32K x 32-bit SRAM with three 2K blocks assignable to either Y data or program memory Integrated DAC & ADC Functionality — 8† Channels of DAC output: 108dB DR, -98dB THD+N — 4† Channels of ADC input: 105dB DR, -98dB THD+N — Integrated 5:1 analog mux feeds one stereo ADC Configurable Serial Audio Inputs/Outputs — — — — Integrated 192 kHz S/PDIF Rx† Integrated 192 kHz S/PDIF Tx Supports 32-bit Serial Data @ 192 kHz Supports 32-bit audio sample I/O between DSP chips — TDM I/O† modes (Up to 10/8 channels per line) Supports Different Fs Sample Rates — Three† integrated hardware SRC blocks — Output can be master or slave — Supports dual-domain Fs on S/PDIF vs. I2S inputs DSP Tool Set w/ Private Keys Protect Customer IP Integrated Clock Manager/PLL — Flexibility to operate from internal PLL, external crystal, external oscillator Input Fs Auto Detection w/ µC Acknowledgement Host Control & Boot via I2C™ or SPI™ Serial Interface Configurable GPIOs and External Interrupt Input 1.8V Core and a 3.3V I/O that is tolerant to 5V input Low-power Mode “†” Feature may differ on CS47024 or CS47028, see p. 8. D ADC’s & DAC’s operate in Single ended or Differential mode FI N O Memory Bus 4ch PIC ROM RAM C MUX ADC2/3 P SPI / I2C Control 32K x 32-bit SRAM with three 2K blocks Assignable to Program or Y Data memory P reliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright 2009 Cirrus Logic CONFIDENTIAL AUG ’09 DS787PP1 http://www.cirrus.com X Stereo Inputs On Analog in S R C 1 DMA ROM RAM ROM Y Peripheral Bus EN D TIA EL L PH D R I A Ordering Information: See p. 33 for ordering information. DBC (I2C Slave) The CS470xx family is a new generation of audio system-ona-chip (ASOC) processors targeted at high fidelity, cost sensitive designs. Derived from the highly successful CS48500 32-bit fixed point audio enhancement processor family, the CS470xx further simplifies system design and reduces total system cost by integrating the S/PDIF Rx, S/PDIF Tx, analog inputs, analog outputs, and SRCs. For example, a hardware SRC can down-sample a 192 kHz S/PDIF stream to a lower Fs to reduce memory and MIPS requirements for processing. This integration effectively reduces the chip count from 3 to 1 which allows smaller, less expensive board designs. Target applications are: — Automotive Head Units & Outboard Amplifiers — Automotive Processors & Automotive Integration Hubs — Digital TV — MP3 Docking Stations — AVR and DVD RX — DSP Controlled Speakers (e.g. Subwoofers, Sound Bars) The CS470xx is programmed using the simple yet powerful Cirrus proprietary DSP Composer™ GUI development and pre-production tuning tool. Processing chains may be designed using a drag-and-drop interface to place/utilize functional macro audio DSP primitives and custom audio filtering blocks. The end result is a software image that is downloaded to the DSP via serial control port. The Cirrus Framework™ programming environment offers Assembly and C language compilers and other software development tools for porting existing code to the CS470xx family platform. The CS470xx is available in a 100-pin LQFP package with exposed pad for better thermal characteristics. Both Commercial (0°C to +70°C) and Automotive (-40°C to +85°C) temperature grades. PLL Clock Manager Timers GPIO I2S / TDM / SPDIF I2S / TDM 8ch x4 S R C 2 Crystal® 32-bit Core text in the CS47048 DSP DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 ADC0/1 x8 8ch S R C 3 SRC3 has 8 independent Channels for In or Out x2 I2S / TDM x2 RAM I2S / TDM / SPDIF FT CS470xx Data Sheet Audio SOC Processor Family Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com. IMPORTANT NOTICE SPI is a trademark of Motorola, Inc. I2C is a trademark of Philips Semiconductor. DTS and DTS NEO6 are registered trademarks of the Digital Theater Systems, Inc. It is hereby notified that a third-party license from DTS is necessary to distribute software of DTS in any finished end-user or ready-to-use final product. Dolby, Pro Logic, Dolby Headphone, Virtual Speaker and the double-D symbol are registered trademarks of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories. Adobe Reader is a trademark of Adobe Systems, Inc. 2 C Cirrus Logic, Cirrus, the Cirrus Logic logo designs, Crystal, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. O CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. N FI “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. D EN D TI EL A L PH D I RA Copyright 2009 Cirrus Logic FT DS787PP1 CS470xx Data Sheet Audio SOC Processor Family Table of Contents FEATURES ......................................................................................................................... 1 1. Documentation Strategy .........................................................................................................6 2. Overview ..................................................................................................................................6 2.1 Licensing ............................................................................................................................................... 6 3. Code Overlays .........................................................................................................................7 4. Hardware Functional Description .......................................................................................10 4.1 Crystal 32-bit DSP Core ...................................................................................................................... 12 4.2 DSP Memory ....................................................................................................................................... 12 4.2.1 DMA Controller ....................................................................................................................... 12 4.3 On-chip DSP Peripherals .................................................................................................................... 13 4.3.1 Analog to Digital Converter Port (ADC) .................................................................................. 13 4.3.2 Digital to Analog Converter Port (DAC) .................................................................................. 13 4.3.3 Digital Audio Input Port (DAI) .................................................................................................. 13 4.3.4 S/PDIF RX Input Port (DAI) .................................................................................................... 13 4.3.5 Digital Audio Output Port (DAO) ............................................................................................. 13 4.3.6 S/PDIF TX Output Port (DAO) ................................................................................................ 14 4.3.7 Sample Rate Converters (SRC) ............................................................................................. 14 4.3.8 Serial Control Port (I2C or SPI) ............................................................................................... 14 4.3.9 GPIO ....................................................................................................................................... 14 4.3.10 PLL-based Clock Generator ................................................................................................. 14 4.3.11 Hardware Watchdog Timer ................................................................................................... 14 4.4 DSP I/O Description ............................................................................................................................ 15 4.4.1 Multiplexed Pins ..................................................................................................................... 15 4.4.2 Termination Requirements ...................................................................................................... 15 4.4.3 Pads ....................................................................................................................................... 15 4.5 Application Code Security ................................................................................................................... 15 5. Characteristics and Specifications .....................................................................................16 5.1 Absolute Maximum Ratings ................................................................................................................. 16 5.2 Recommended Operating Conditions ................................................................................................. 16 5.3 Digital DC Characteristics ................................................................................................................... 16 5.4 Power Supply Characteristics ............................................................................................................. 17 5.5 Thermal Data (100-Pin LQFP with Exposed Pad) ............................................................................... 17 5.6 Digital Switching Characteristics— RESET ......................................................................................... 18 5.7 Digital Switching Characteristics — XTI ............................................................................................. 19 5.8 Digital Switching Characteristics — Internal Clock .............................................................................. 19 5.9 Digital Switching Characteristics — Serial Control Port - SPI Slave Mode ......................................... 20 5.10 Digital Switching Characteristics — Serial Control Port - SPI Master Mode ..................................... 21 5.11 Digital Switching Characteristics — Serial Control Port - I2C Slave Mode ........................................ 22 5.12 Digital Switching Characteristics — Serial Control Port - I2C Master Mode ...................................... 23 5.13 Digital Switching Characteristics — Digital Audio Slave Input Port ................................................... 24 5.14 Digital Switching Characteristics — Digital Audio Output Port .......................................................... 25 5.15 Digital Switching Characteristics — S/PDIF RX Port (Not available on CS47024) ........................... 26 5.16 ADC Characteristics .......................................................................................................................... 27 5.16.1 Analog Input Characteristics (Commercial) .......................................................................... 27 5.16.2 Analog Input Characteristics (Automotive) ........................................................................... 28 5.16.3 ADC Digital Filter Characteristics ......................................................................................... 30 5.17 DAC Characteristics .......................................................................................................................... 30 5.17.1 Analog Output Characteristics (Commercial) ....................................................................... 30 DS787PP1 C O N FI D EN D TI EL A L PH D I RA Copyright 2009 Cirrus Logic FT 3 CS470xx Data Sheet Audio SOC Processor Family 5.17.2 Analog Output Characteristics (Automotive) ........................................................................ 31 5.17.3 Combined DAC Interpolation & On-chip Analog Filter Response ........................................ 32 6. Ordering Information ............................................................................................................33 7. Environmental, Manufacturing, & Handling Information ..................................................33 8. Device Pinout Diagram .........................................................................................................34 8.1 CS47048, 100-Pin LQFP Pinout Diagram ........................................................................................... 34 8.2 CS47028, 100-Pin LQFP Pinout Diagram ........................................................................................... 35 8.3 CS47024, 100-Pin LQFP Pinout Diagram ........................................................................................... 36 9. 100-pin LQFP with Exposed Pad Package Drawing .........................................................36 10. Parameter Definitions .........................................................................................................38 10.1 Dynamic Range ................................................................................................................................. 38 10.2 Total Harmonic Distortion + Noise ..................................................................................................... 38 10.3 Frequency Response ........................................................................................................................ 38 10.4 Interchannel Isolation ........................................................................................................................ 38 10.5 Interchannel Gain Mismatch .............................................................................................................. 38 10.6 Gain Error .......................................................................................................................................... 38 10.7 Gain Drift ........................................................................................................................................... 38 11. Revision History ..................................................................................................................38 Figures Figure 1. CS47048 Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 2. CS47028 Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3. CS47024 Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. RESET Timing at Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5. RESET Timing after Power is Stable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. Serial Control Port - SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8. Serial Control Port - SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. Serial Control Port - I2C Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10. Serial Control Port - I2C Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 12. Digital Audio Output Port Timing, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 13. Digital Audio Output Port Timing, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 14. ADC Single-Ended Input Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 15. ADC Differential Input Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 16. DAC Single-Ended Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 17. DAC Differential Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4 Copyright 2009 Cirrus Logic DS787PP1 C O Figure 11. Digital Audio Input (DAI) Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 24 N FI D Figure 6. XTI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 EN D TI EL A L PH D I RA FT CS470xx Data Sheet Audio SOC Processor Family Figure 18. Maximum Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 19. CS47048 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 20. CS47028 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 21. CS47024 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 22. 100-Pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Tables Table 1. CS470xx Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. CS470xx Device Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. CS470xx Channel Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 6. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . . . . 33 Table 4. Memory Configurations for CS470xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DS787PP1 C O N FI D EN D TI EL A L PH D I RA Copyright 2009 Cirrus Logic FT 5 CS470xx Data Sheet Audio SOC Processor Family 1. Documentation Strategy The CS470xx Data Sheet describes the CS47048, CS47028, and CS47024 audio processors. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS470xx processors Table 1. CS470xx Related Documentation Document Name CS470xx Data Sheet CS470xx Hardware User’s Manual Guide Description This document Includes detailed system design information such as typical connection diagrams, bootprocedures, and pin descriptions DSP Composer User’s Manual CDB470xx User’s Manual The scope of the CS470xx Data Sheet is primarily the hardware specifications of the CS470xx family of devices. This includes hardware functionality, characteristic data, pinout, and packaging information. The intended audience for the CS470xx Data Sheet is the system PCB designer, MCU programmer, and the quality control engineer. 2. Overview 2.1 Licensing 6 C Licenses are required for any 3rd party audio processing algorithms provided for the CS470xx. Please contact your local Cirrus Logic Sales representative for more information. O N The CS470xx DSP is designed to provide high-performance post-processing and mixing of analog and digital audio. Dual clock domains are supported when the DAI and SPDIF RX inputs are used together. Integrated sample rate converters (SRCs) allow audio streams with different sample rates to be mixed. The low-power standby preserves battery life for applications which are always on, but not necessarily processing audio, such as automotive audio systems. The CS470xx utilizes voltage-out DACs and is capable of supporting dual input clock domains through the use of the internal SRCs. The CS470xx is available in a 100-pin LQFP package. Refer to Table 2 and Table 3 for the input, output, and firmware configurations for the CS470xx DSP. FI D EN D TI EL A L PH D I RA Copyright 2009 Cirrus Logic AN333 - CS470xx Firmware User’s Manual Includes a list of firmware modules available on the CS470xx family platform and detailed firmware design information including signal processing flow diagrams and control API information Includes detailed configuration and usage information for the GUI development tool Includes detailed instructions on the use of the CDB470xx development board FT DS787PP1 CS470xx Data Sheet Audio SOC Processor Family 3. Code Overlays The suite of software available for the CS470xx family consists of an operating system (OS) and a library of overlays. The software components for the CS470xx family include: 1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external serial memory, processing host messages, calling audio-processing subroutines, error concealment, etc. 2. Matrix-processor- Any Module that performs a matrix decode on PCM data to produce more output channels than input channels (2→n channels). Examples are Dolby® Pro Logic® IIx and DTS Neo:6®. Generally speaking, these modules increase the number of valid channels in the audio I/O buffer. 3. Virtualizer-processor - Any module that encodes PCM data into fewer output channels than input channels (n→2 channels) with the effect of providing “phantom” speakers to represent the physical audio channels that were eliminated. Examples are Dolby Headphone® 2 and Dolby® Virtual Speaker® 2. Generally speaking, these modules reduce the number of valid channels in the audio I/O buffer. 4. Post-processors - Any module that processes audio I/O buffer PCM data. Examples are bass management, audio manager, tone control, EQ, delay, customer-specific effects, and any postprocessing algorithms available for the CS485xx DSP. The bulk of standard overlays are stored in ROM within the CS470xx, but a small image is required to configure the overlays and boot the DSP. This small image can either be stored in an external serial FLASH/EEPROM, or downloaded via a host controller through the SPI™/I2C™ serial port. The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a different post-processor is selected, the OS, does not need to be reloaded — only the new post-processor. Table 2 lists the different configuration options available. Please refer to the CS470xx Firmware User’s Manual for the latest listing of application codes and Cirrus Framework™ modules available. See Table 3 which provides a summary of the available channels for each type of input and output communication mode for members of the CS470xx family of DSPs. DS787PP1 C O N FI D EN D TI EL A L PH D I RA Copyright 2009 Cirrus Logic FT 7 CS470xx Data Sheet Audio SOC Processor Family Table 2. CS470xx Device Selection Guide Features CS47048-CQZ CS47048-DQZ • 4-In/8-Out Car Audio Primary Applications • High-end Digital TV • Dual Source/Dual Zone CS47028-CQZ CS47028-DQZ • 2-In/8-Out Car Audio • Sound Bar • DVD Receiver CS47024-CQZ CS47024-DQZ • 2-In/4-Out Car Audio • Digital TV • Portable Audio Docking Station • Portable DVD • DVD Mini / Receiver • Multimedia PC Speakers Package DSP Core SRAM • 2 Channels of ADC input: with integrated 5:1 analog mux • 2 additional channels of ADC input: without mux 100-pin LQFP with Exposed Pad 32K x 32-bit SRAM with three 2K blocks x 32-bit SRAM, assignable to either Y data or program memory • 2 channels of ADC input: with integrated 5:1 analog mux • 8 channels of DAC output • 2 channels of ADC input: with integrated 5:1 analog mux • 4 channels of DAC output Integrated DAC and ADC • 8 channels of DAC output Configurable Serial Audio Inputs/Outputs • Integrated 192 kHz S/PDIF Rx, 2 Integrated 192 kHz S/PDIF Tx • I2S support for 32-bit Samples @ 192 kHz • TDM Input modes (Up to 10 channels) • TDM Output modes (Up to 8 channels) Supports Different Fs Sample Rates • Integrated hardware SRC blocks for all ADC and DAC channels • Additional 8 channel hardware SRC block • Output can be master or slave • Dual-domain Fs on inputs (I2S and S/PDIF Rx) • Integrated Clock Manager/PLL with flexibility to operate from internal PLL, external crystal, external oscillator Other Features • Host Control & Boot via SPI / I2C Serial Interface • DSP Tool Set w/ Private Keys Protect Customer IP • Configurable GPIOs and External Interrupts • Hardware Watchdog Timer 8 C O N FI D EN D TI EL A L PH D I RA Copyright 2009 Cirrus Logic • 2 Integrated 192 kHz S/PDIF Tx • I2S support for 32-bit Samples @ 192 kHz • TDM Input modes (Up to 10 channels) • Integrated hardware SRC blocks for all ADC and DAC channels • Output can be master or slave FT Crystal 32-bit Core DS787PP1 CS470xx Data Sheet Audio SOC Processor Family Table 3. CS470xx Channel Count PCM/TDM TDM Out PCM Out In Up to 10 PCM / TDM Up to 10 PCM / TDM Up to 10 PCM / TDM Product ADC with 5:1 Input Mux 2 2 2 ADC without Mux 2 0 0 DAC Out S/PDIF In (Stereo Pairs) 1 1 0 S/PDIF Out (Stereo Pairs) 2 2 2 CS47048 CS47028 CS47024 Up to 8 Up to 8 0 8 8 8 8 8 4 DS787PP1 C O N FI D EN D TI EL A L PH D I RA Copyright 2009 Cirrus Logic 9 FT CS470xx Data Sheet Audio SOC Processor Family 4. Hardware Functional Description The CS470xx family, which includes the CS47048, CS47028, and CS47024 DSPs, is a true system-on-a-chip that combines a powerful 32-bit DSP engine with analog/digital audio inputs and analog/digital audio outputs. It can be integrated into a complex multi-DSP processing system, or stand alone in an audio product that requires analog-in and analog-out. A top level block diagram for the CS47048, CS47028, and CS47024 products are shown in Figure 1, Figure 2, and Figure 3 respectively. (I2C Slave) x4 I2S / TDM Memory Bus 4ch PIC MUX ADC2/3 ROM RAM P N 10 C O FI D SPI / I2C Control 32K x 32-bit SRAM with three 2K blocks Assignable to Program or Y Data memory Figure 1. CS47048 Top-Level Block Diagram Copyright 2009 Cirrus Logic X Stereo Inputs On Analog in S R C 1 DMA ROM RAM Peripheral Bus ADC0/1 EN D TI EL A L PH D I RA 8ch I2 S / TDM / SPDIF Crystal® 32-bit Core text in the CS47048 DSP S R C 2 x8 8ch S R C 3 ROM RAM Y FT DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 SRC3 has 8 independent Channels for In or Out x2 ADC’s & DAC’s operate in Single ended or Differential mode DBC PLL Clock Manager Timers GPIO I2S / TDM x2 I2S / TDM / SPDIF DS787PP1 CS470xx Data Sheet Audio SOC Processor Family ADC’s & DAC’s operate in Single ended or Differential mode DBC (I2C Slave) PLL Clock Manager Timers GPIO DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 I2 S / TDM / SPDIF x4 8ch S R C 2 I2S / TDM Crystal® 32-bit Core text in the CS47028 DSP x8 Memory Bus 4ch ADC2/3 SPI / I2C Control Figure 2. CS47028 Top-Level Block Diagram ADC’s & DAC’s operate in Single ended or Differential mode I2S / TDM x4 D I2S / TDM FI N Memory Bus 4ch O PIC ROM RAM MUX ADC2/3 C P SPI / I C Control 2 32K x 32-bit SRAM with three 2K blocks Assignable to Program or Y Data memory Figure 3. CS47024 Top-Level Block Diagram DS787PP1 Copyright 2009 Cirrus Logic 11 X Stereo Inputs On Analog in S R C 1 DMA ROM RAM ROM Y RAM x2 Peripheral Bus EN D TI EL A L PH D I RA x2 PIC MUX ROM RAM P 32K x 32-bit SRAM with three 2K blocks Assignable to Program or Y Data memory DBC (I2C Slave) PLL Clock Manager Crystal® 32-bit Core text In CS47024 DSP x8 X Stereo Inputs On Analog in S R C 1 DMA ROM RAM ROM RAM Peripheral Bus 8ch S R C 3 SRC3 has 8 independent Channels for In or Out Y I2S / TDM x2 I2S / TDM / SPDIF Timers GPIO 8ch S R C 2 I2S / SPDIF FT DAC0 DAC1 DAC2 DAC3 CS470xx Data Sheet Audio SOC Processor Family 4.1 Crystal 32-bit DSP Core The CS470xx comes with a Crystal® 32-bit core with separate X and Y data and P code memory spaces. The DSP core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has eight 72-bit accumulators, four X-data and four Y-data registers, and 12 index registers. The DSP core is coupled to a flexible 8-channel DMA engine. The DMA engine can move data between peripherals such as the serial control port (SCP), digital audio input (DAI) and digital audio output (DAO), sample rate converters (SRC), analog-to-digital converters (ADC), digital-to-analog converters (DAC), or any DSP core memory, all without the intervention of the DSP. The DMA engine off-loads data move instructions from the DSP core, leaving more MIPS available for signal processing instructions. CS470xx functionality is controlled by application codes that are stored in on-chip ROM or downloaded to the CS470xx from a host controller or external serial FLASH/EEPROM. Users can develop their applications using DSP ComposerTM to create the processing chain and then compile the image into a series of commands that are sent to the CS470xx through the SCP. The processing application can either load modules (post-processors) from the DSP’s on-chip ROM, or custom firmware can be downloaded through the SCP. The CS470xx is suitable for a variety of audio post-processing applications where sound quality via sound enhancement and speaker/cabinet tuning is required to achieve the sound quality consumers expect. Examples of such applications include automotive head-ends, automotive amplifiers, docking stations, sound bars, subwoofers, and boom boxes. 4.2 DSP Memory The DSP core has its own on-chip data and program RAM and ROM and does not require external memory for post-processing applications. The Y-RAM and P-RAM share a single block of memory that includes three 2K word blocks (32 bits/word) that are assignable to either Y-RAM or P-RAM as shown in Table 4. Table 4. Memory Configurations for CS470xx P-RAM X-RAM 14K words 12K words 10K words 8K words D FI 4.2.1 DMA Controller 12 C The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment controls. The service intervals for each DMA channel, as well as up to 6 interrupt events, are programmable. O N EN D TI EL A L PH D I RA Y-RAM 10K words 8K words 10K words 10K words 10K words 10K words 12K words 14K words Copyright 2009 Cirrus Logic FT DS787PP1 CS470xx Data Sheet Audio SOC Processor Family 4.3 On-chip DSP Peripherals 4.3.1 Analog to Digital Converter Port (ADC) The ADCs in the CS470xx devices feature dynamic range performance in excess of 100 dB. Please see Section 5.16 “ADC Characteristics” on page 27 for more details on CS470xx ADC performance. The CS47024 and CS47028 devices support up to 2 simultaneous channels of analog-to-digital conversion with the input source selectable using an integrated 5:1 stereo analog mux (analog inputs AIN_2A/B through AIN_6A/B). The CS47048 device adds a second pair of ADCs that are directly connected to input pins AIN_1A/B providing a total of 4 simultaneous channels of analog-to-digital conversion. This feature gives the CS47048 the ability to select from a total of six stereo pairs of analog input. A single programmable bit selects single-ended or differential mode signals for all inputs. The conversions are performed with either Fs=96 kHz or Fs=192 kHz. 4.3.2 Digital to Analog Converter Port (DAC) 4.3.3 Digital Audio Input Port (DAI) 4.3.4 S/PDIF RX Input Port (DAI) 4.3.5 Digital Audio Output Port (DAO) DS787PP1 C DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as 192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or as a clock slave if an external MCLK or SCLK/LRCLK source is available. On the CS47028 and CS47048 devices the DAO also supports a time division multiplexed (TDM) mode, that packs up to 8 channels of PCM audio on a single data line. O On the CS47048 and CS47028, one of the PCM pins of the DAI can also be used as a DC-coupled, TTL-level S/PDIF Rx input capable of receiving and demodulating bi-phase encoded S/PDIF signals with Fs ≤ 192 kHz. N FI The input capabilities for each version of the CS470xx are summarized in Table 2 and Table 3. Up to five DAI ports are available. Two of the DAI ports can be programmed to implement other functions. If the SPI mode is used, the DAI_DATA4 pin becomes the SCP_CS input. The CS47028 and CS47048 devices have an integrated S/PDIF receiver which, if used, takes over the DAI_DATA3 pin. The DAI port PCM inputs have a single slave-only clock domain. The S/PDIF receiver, if used, is a separate clock domain. The output of the S/PDIF Rx can then be converted through one of the internal SRC blocks to synchronize with the PCM input. The sample rate of the input clock domains can be determined automatically by the DSP, off-loading the task of monitoring the S/PDIF Rx from the host. A time-stamping feature provides the ability to also sample-rate convert the input data via software.The DAI port supports PCM format with word lengths up to 32 bits and sample rates as high as 192 kHz. The DAI also supports a time division multiplexed (TDM) mode that packs up to 10 PCM audio channels on a single data line. D EN D TI EL A L PH D I RA Copyright 2009 Cirrus Logic The DACs in the CS470xx devices feature dynamic range performance in excess of 100 dB. Please see Section 5.17 “DAC Characteristics” on page 30 for more details on CS470xx DAC performance. The CS47024 device supports four simultaneous channels of digital-to-analog conversion. The CS47028 and CS47048 devices provide eight simultaneous channels of digital-toanalog conversion. The DACs have voltage mode outputs that can be connected either as singleended or differential signals. The conversions are performed with Fs=96 kHz. FT 13 CS470xx Data Sheet Audio SOC Processor Family 4.3.6 S/PDIF TX Output Port (DAO) Two of the serial audio pins can be re-configured as S/PDIF TX pins that drive a bi-phase encoded S/PDIF signal (data with embedded clock on a single line). 4.3.7 Sample Rate Converters (SRC) All CS470xx devices have at least two internal hardware SRC modules. One is directly associated with the ADCs and normally serves to convert data from the 96/192 kHz sampling rate of the ADCs to another Fs appropriate for mixing with other audio in the system. If the ADCs are not being used, this SRC can convert up to 4 channels of audio data from one input sample rate (Fsi) to another output sample rate (Fso). The other SRC module is directly associated with the DACs and normally serves to convert data from the DSP into the 96kHz sample rate needed by the DACs. If the DACs are not being used, this SRC can convert up to 8 channels of audio data from the one input sample rate (Fsi) to another output sample rate (Fso). The CS47028 and CS47048 devices have an additional stand-alone 8-channel SRC module.This SRC module can be used to make independent input clock domains synchronous (different Fs on PCM input and S/PDIF Rx). 4.3.8 Serial Control Port (I2C™ or SPI™) The on-chip serial control port is capable of operating as master or slave in either SPI™ or I2C™ modes. Master/Slave operation is chosen by mode select pins when the CS470xx comes out of reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode (SPI clock speed must always be ≤ (DSP Core Frequency/2)). The CS470xx serial control port also includes a pin for flow control of the communications interface (SCP_BSY) and a pin to indicate when the DSP has a message for the host (SCP_IRQ). 4.3.9 GPIO Many of the CS470xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high. 4.3.10 PLL-based Clock Generator The CS470xx has an integrated watchdog timer that acts as a “health” monitor for the DSP. The watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This peripheral ensures that the CS470xx will reset itself in the event of a temporary system failure. In stand-alone mode (i.e. no host MCU), the DSP will reboot from external FLASH. In slave mode (i.e. host MCU present) a GPIO will be used to signal the host that the watchdog has expired and the DSP should be rebooted and re-configured. 14 C O 4.3.11 Hardware Watchdog Timer N The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS470xx defaults to running from the external reference frequency and is switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1. FI D EN D TI EL A L PH D I RA Copyright 2009 Cirrus Logic FT DS787PP1 CS470xx Data Sheet Audio SOC Processor Family 4.4 DSP I/O Description 4.4.1 Multiplexed Pins Many of the CS470xx pins are multi-functional. For details on pin functionality please refer to the CS470xx Hardware User’s Manual. 4.4.2 Termination Requirements Open-drain pins on the CS470xx must be pulled high for proper operation. Please refer to the CS470xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. Mode select pins on CS470xx are used to select the boot mode upon the rising edge from reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS470xx Hardware User’s Manual. 4.4.3 Pads The CS470xx Digital I/Os operate from the 3.3 V supply and are 5 V tolerant. 4.5 Application Code Security The external program code may be encrypted by the programmer to protect any intellectual property it may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device. Please contact your local Cirrus representative for details. DS787PP1 C O N FI D EN D TI EL A L PH D I RA Copyright 2009 Cirrus Logic FT 15 CS470xx Data Sheet Audio SOC Processor Family 5. Characteristics and Specifications Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C, VDD = 1.8 V, VDDIO = VDDA =3.3 V, GND = GNDIO = GNDA = 0 V. 5.1 Absolute Maximum Ratings (GND = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Parameter DC power supplies: Core supply Analog supply I/O supply |VDDA – VDDIO| Symbol VDD VDDA VDDIO Iin Vfilt Vinio Vin Tstg Min –0.3 –0.3 –0.3 -0.3 -0.3 Max 2.0 3.6 3.6 0.3 Unit V V V V mA V V V °C Input pin current, any pin except supplies Input voltage on PLL_REF_RES Input voltage on digital I/O pins Analog Input Voltage Storage temperature EN D TI EL A L PH D I RA AGND - 0.7 –65 Symbol VDD VDDA VDDIO TA Min Typ 1.8 3.3 3.3 0 Core supply Analog supply I/O supply |VDDA – VDDIO| 1.71 3.13 3.13 Commercial - CQZ Automotive - DQZ 0 - 40 Symbol VIH VIL VILXTI Vhys VOH VOL ILXTI ILEAK VDDIO * 0.9 Min 2.0 Typ 0.4 Copyright 2009 Cirrus Logic Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 5.2 Recommended Operating Conditions Parameter DC power supplies: (GND = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) FT +/- 10 3.6 5.0 VA + 0.7 150 Max 1.89 3.46 3.46 + 70 + 85 Max 0.8 0.6 VDDIO * 0.1 5 70 Unit V V V V °C Ambient operating temperature Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply. (Measurements performed under static conditions.) N Parameter FI 5.3 Digital DC Characteristics D Unit V V V V V V μA μA Low-level input voltage, except XTI Input Hysteresis High-level output voltage (IO = -2mA), except XTO Low-level output voltage (IO = 2mA), except XTO Input leakage XTI Input leakage current (all digital pins with internal pull-up resistors enabled) 16 C Low-level input voltage, XTI O High-level input voltage DS787PP1 CS470xx Data Sheet Audio SOC Processor Family 5.4 Power Supply Characteristics Note: Measurements performed under operating conditions) Parameter Operational Power Supply Current: VDD: Core and I/O operating1 VDDA: PLL operating current VDDA: DAC operating current (all 8 channels enabled) VDDA: ADC operating current (all 4 channels enabled) VDDIO: With most ports operating Total Operational Power Dissipation: Standby Power Supply Current: VDD: Core and I/O not clocked VDDA: PLLs halted VDDA: DAC disabled VDDA: ADC disabled VDDIO: All connected I/O pins 3-stated by other ICs in system Total Standby Power Dissipation: Min Typ 325 16 56 34 27 1025 Max Unit mA mA mA mA mA mW μA μA μA μA μA μW 1. Dependent on application firmware and DSP clock speed. 5.5 Thermal Data (100-Pin LQFP with Exposed Pad) Parameter EN D TI EL A L PH D I RA 1745 Symbol Min Typ 34 18 - 410 26 40 24 215 FT Max - Unit °C / Watt Thermal Resistance (Junction to Ambient) Two-layer Board1 Four-layer Board2 Thermal Resistance (Junction to Top of Package) Two-layer Board1 Four-layer Board2 θja ψjt °C / Watt 0.54 .28 1. To calculate the die temperature for a given power dissipation: 2. To calculate the case temperature for a given power dissipation: Note: Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20% Note: Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20% of the top & bottom layers and 0.5-oz. copper covering 90% of the internal power plane & ground plane layers. DS787PP1 C O of the top & bottom layers. N Τc = Τj - [ (Power Dissipation in Watts) * ψ jt ] FI Τj = Ambient temperature + [ (Power Dissipation in Watts) * θja ] D Copyright 2009 Cirrus Logic 17 CS470xx Data Sheet Audio SOC Processor Family 5.6 Digital Switching Characteristics— RESET Parameter RESET minimum pulse width low1 All bidirectional pins high-Z after RESET low Configuration pins setup before RESET high Configuration pins hold after RESET high Symbol Trstl Trst2z Trstsu Trsthld Min 1 50 20 Max 200 Unit μs ns ns ns 1.The rising edge of RESET must not occur before the power supplies are stable at their recommended operating values as described in Section 5.2. In addition, for the configuration pins to be read correctly, the RESET Trstl requirement must be met. VDD2 RESET HS[3:0] 2 Refers to all power supplies. N O C All Bidirectional Pins Trst2z Trstl FI RESET HS[3:0] D Figure 5. RESET Timing after Power is Stable 18 EN D TI EL A L PH D I RA Trstl Trstsu Trsthld Figure 4. RESET Timing at Power-On All supplies at recommended operating values. Trstsu Trsthld Copyright 2009 Cirrus Logic FT DS787PP1 CS470xx Data Sheet Audio SOC Processor Family 5.7 Digital Switching Characteristics — XTI Parameter Symbol 1 Min Max Unit External Crystal operating frequency XTI period XTI high time XTI low time External Crystal Load Capacitance (parallel resonant)2 External Crystal Equivalent Series Resistance Fxtal Tclki Tclkih Tclkil CL ESR 12.288 41 13.3 13.3 10 24.576 81 18 50 MHz ns ns ns pF Ω X TI 5.8 Digital Switching Characteristics — Internal Clock Parameter EN D TI EL A L PH D I RA t clkih t clkil Tclki Figure 6. XTI Timing Symbol Min FT Max 1. Part characterized with the following crystal frequency values: 12.288 and 24.576 MHz 2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside this range should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer’s recommendation for load capacitor selection. Unit Internal DSP_CLK frequency1 Fdclk MHz 150 150 150 150 150 150 ns 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal FI Internal DSP_CLK period1 D CS47048-CQZ CS47048-DQZ CS47028-CQZ CS47028-DQZ CS47024-CQZ CS47024-DQZ CS47048-CQZ CS47048-DQZ CS47028-CQZ CS47028-DQZ CS47024-CQZ CS47024-DQZ Fxtal2 Fxtal Fxtal Fxtal Fxtal Fxtal 6.7 6.7 6.7 6.7 6.7 6.7 DCLKP DS787PP1 C 1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until the next power-on reset. 2.See Section 5.7. for all references to Fxtal. O N Copyright 2009 Cirrus Logic 19 CS470xx Data Sheet Audio SOC Processor Family 5.9 Digital Switching Characteristics — Serial Control Port - SPI Slave Mode Parameter Symbol Min Typical Max Units SCP_CLK frequency1 SCP_CS falling to SCP_CLK rising SCP_CLK low time SCP_CLK high time Setup time SCP_MOSI input Hold time SCP_MOSI input SCP_CLK low to SCP_MISO output valid SCP_CLK falling to SCP_IRQ rising SCP_CS rising to SCP_IRQ falling SCP_CLK low to SCP_CS rising fspisck tspicss tspickl tspickh tspidsu tspidh tspidov tspiirqh tspiirql 24 20 20 5 5 0 25 - MHz ns ns ns ns ns ns ns ns ns ns ns EN D TI EL A L PH D I RA tspicsh 24 tspicsdz 20 tspicbsyl 3*DCLKP+20 tspickl 2 6 7 0 5 6 7 tspickh A0 R/W tspidov MSB tspiirqh LSB MSB LSB tspibsyl SCP_CS rising to SCP_MISO output high-Z SCP_CLK rising to SCP_BSY falling 1. fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is Fxtal/3. tspicss SCP_CS 0 1 1/ fspisck SCP_MOSI N FI A6 tspidsu D SCP_CLK A5 tspidh O SCP_MISO SCP_BSY C SCP_IRQ Figure 7. Serial Control Port - SPI Slave Mode Timing 20 Copyright 2009 Cirrus Logic DS787PP1 FT 11 27 tspicsh tspicsdz tspiirql CS470xx Data Sheet Audio SOC Processor Family 5.10 Digital Switching Characteristics — Serial Control Port - SPI Master Mode Parameter Symbol Min Typical Max Units SCP_CLK frequency1,2 EE_CS falling to SCP_CLK rising 3 SCP_CLK low time SCP_CLK high time Setup time SCP_MISO input Hold time SCP_MISO input SCP_CLK low to SCP_MOSI output valid SCP_CLK low to EE_CS falling SCP_CLK low to EE_CS rising fspisck tspicss tspickl tspickh tspidsu tspidh tspidov tspicsl 18 18 9 5 7 11*DCLKP + (SCP_CLK PERIOD)/2 Fxtal/2 - MHz ns ns ns ns ns ns ns ns ns ns EN D TI EL A L PH D I RA tspicsh tspicsx tspidz 11*DCLKP + (SCP_CLK PERIOD)/2 3*DCLKP tspickl 1 2 6 7 0 5 6 7 tspickh A5 tspidh A0 R/W tspidov MSB LSB MSB LSB Bus free time between active EE_CS SCP_CLK falling to SCP_MOSI output high-Z 1. fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. 2. See Section 5.7. 3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter tspicss D EE_CS tspicsl SCP_CLK O N SCP_MISO C FI 0 1/ fspisck A6 tspidsu SCP_MOSI Figure 8. Serial Control Port - SPI Master Mode Timing DS787PP1 Copyright 2009 Cirrus Logic FT 8 20 tspicsx tspicsh tspidz 21 CS470xx Data Sheet Audio SOC Processor Family 5.11 Digital Switching Characteristics — Serial Control Port - I2C Slave Mode? Parameter Symbol Min Typical Max Units SCP_CLK frequency1 SCP_CLK rise time SCP_CLK fall time SCP_CLK low time SCP_CLK high time SCP_CLK rising to SCP_SDA rising or falling for START or STOP condition START condition to SCP_CLK falling SCP_CLK falling to STOP condition fiicck tiicr tiicf tiicckl tiicckh tiicckcmd tiicstscl tiicstp tiicbft tiicsu tiich - 400 150 150 kHz ns ns µs µs µs µs µs µs ns 1.25 1.25 1.25 1.25 2.5 3 - EN D TI EL A L PH D I RA 110 100 tiicdov tiicirqh tiicirql 3*DCLKP + 20 3*DCLKP + 20 tiicbsyl tiicckl tiicr tiicf 1 6 7 8 0 1 6 7 8 tiicckh tiicdov A0 R/W ACK MSB tiicirqh 1/ fiicck LSB tiiccbsyl Bus free time between STOP and START conditions Setup time SCP_SDA input valid to SCP_CLK rising Hold time SCP_SDA input after SCP_CLK falling SCP_CLK low to SCP_SDA out valid SCP_CLK falling to SCP_IRQ rising NAK condition to SCP_IRQ low SCP_CLK rising to SCB_BSY low FT 18 3*DCLKP + 40 tiicckcmd Stop Condition ns ns ns ns ns 1. fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer. I2C Slave Address = 0x82 tiicckcmd Start Condition SCP_CLK FI 0 D N tiicstscl tiicstp tiicbft O SCP_SDA A6 ACK tiicirql C 22 tiicsu tiich SCP_IRQ SCP_BSY Figure 9. Serial Control Port - I2C Slave Mode Timing Copyright 2009 Cirrus Logic DS787PP1 CS470xx Data Sheet Audio SOC Processor Family 5.12 Digital Switching Characteristics — Serial Control Port - I2C Master Mode Parameter Symbol Min Max Units EN D TI EL A L PH D I RA tiicckl tiicr tiicf 6 7 8 0 1 6 7 tiicckh tiicdov 1/ fiicck A0 R/W ACK MSB LSB SCP_CLK SCP_CLK rise time SCP_CLK fall time SCP_CLK low time SCP_CLK high time SCP_CLK rising to SCP_SDA rising or falling for START or STOP condition START condition to SCP_CLK falling SCP_CLK falling to STOP condition Bus free time between STOP and START conditions Setup time SCP_SDA input valid to SCP_CLK rising Hold time SCP_SDA input after SCP_CLK falling SCP_CLK low to SCP_SDA out valid frequency1 fiicck tiicr tiicf tiicckl tiicckh tiicckcmd tiicstscl tiicstp tiicbft tiicsu tiich tiicdov 1.25 1.25 1.25 1.25 2.5 3 110 100 - 400 150 150 - kHz ns ns µs µs µs µs µs µs ns ns ns 1.fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. tiicckcmd 0 1 SCP_CLK tiicstscl FT 36 tiicckcmd 8 tiicstp ACK tiicbft SCP_SDA A6 tiicsu DS787PP1 C Copyright 2009 Cirrus Logic O N FI Figure 10. Serial Control Port - I2C Master Mode Timing D tiich 23 CS470xx Data Sheet Audio SOC Processor Family 5.13 Digital Switching Characteristics — Digital Audio Slave Input Port Parameter Symbol Min Max Unit DAI_SCLK period DAI_SCLK duty cycle Setup time DAI_DATAn Hold time DAI_DATAn Tdaiclkp tdaidsu tdaidh 20 45 8 5 55 - ns % ns ns DAI_SCLK tdaidsu DAI_DATAn tdaidh Figure 11. Digital Audio Input (DAI) Port Timing Diagram 24 C O N FI D EN D TI EL A L PH D I RA Copyright 2009 Cirrus Logic DS787PP1 FT CS470xx Data Sheet Audio SOC Processor Family 5.14 Digital Switching Characteristics — Digital Audio Output Port Parameter Symbol Min Max Unit DAO_MCLK period DAO_MCLK duty cycle DAO_SCLK period for Master or Slave mode1 DAO_SCLK duty cycle for Master or Slave mode1 Master Mode (Output A1 Mode)1,2 Tdaomclk Tdaosclk tdaomsck tdaomlrts tdaomstlr tdaomdv tdaoslrts 20 45 20 40 - 55 60 19 ns % ns % ns ns ns ns ns ns ns DAO_LRCLK to DAO_SCLK non-active edge3,5 See Figure 13A. DAO_SCLK non-active edge3, 5 to DAO_LRCLK, See Figure 13B.. DAO1_DATA[3..0] delay from DAO_SCLK non-active edge3 EN D TI EL A L PH D I RA tdaosstlr tdaosdv Slave Mode (Output A0 Mode)4 1. Master mode timing specifications are characterized, not production tested. 2. Master mode is defined as the CS47048 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_LRCLK. 3. The DAO_LRCLK transition may occur on either side of the non-active edge of DAO_LRCLK. The active edge of DAO_SCLK is the point at which the data is valid. 4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source. 5. These Max values for tdaoslrts and tdaosstlr apply to applications where a 1/2 period of DAO_SCLK exceeds one of the maximum delays. tdaomclk DAO_MCLK tdaomclk D DAO_MCLK FI tdaomsck DAO_SCLK tdaomsck N DAO_SCLK O tdaomlrts DAO_LRCLK tdaomstlr DAO_LRCLK C tdaomdv DAO_DATAn tdaomdv DAO_DATAn A. DAO_LRCLK transition before DAO_SCLK non-active edge. See Footnote 3 on page 25. B. DAO_LRCLK transition after DAO_SCLK non-active edge. See Footnote 3 on page 25. Figure 12. Digital Audio Output Port Timing, Master Mode DS787PP1 Copyright 2009 Cirrus Logic 25 FT 15 30 8 DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an input DAO_LRCLK to DAO_SCLK non-active edge3, See Figure 12A. DAO_SCLK non-active edge3 to DAO_LRCLK, See Figure 12B. DAO_DATA[3..0] delay from DAO_SCLK non-active edge3 8 8 8 CS470xx Data Sheet Audio SOC Processor Family tdaosclk D AO_SCLK tdaoslrts D AO_LRCLK tdaosdv D AOn_DATAn A. DAO_LRCLK transition before DAO_SCLK non-active edge. See Footnote 3 on page 25. t dao sclk D AO _SCLK t daosstlr DAO _LRC LK t d aosdv DAO _D ATAn Figure 13. Digital Audio Output Port Timing, Slave Mode 5.15 Digital Switching Characteristics — S/PDIF RX Port (Not available on CS47024) (Inputs: Logic 0 = VIL, Logic 1 = VIH; CL = 20 pF) Parameter EN D TI EL A L PH D I RA Symbol Min Typ B. DAO_LRCLK transition after DAO_SCLK nonactive edge. See Footnote 3 on page 25. FT Max Units PLL Clock Recovery Sample Rate Range 30 - 200 kHz 26 C Copyright 2009 Cirrus Logic O N FI D DS787PP1 CS470xx Data Sheet Audio SOC Processor Family 5.16 ADC Characteristics 5.16.1 Analog Input Characteristics (Commercial) Test Conditions (unless otherwise specified): TA = 0 to +70°C; VDD = 1.8V±5%, VDDA (VA)= 3.3V±5%; 1 kHz sine wave driven through the passive input filter (Ri=10 kΩ) in Figure 14 on page 29 or Figure 15 on page 29; DSP running test application; Measurement Bandwidth is 10 Hz to 20 kHz. Differential Parameter Fs= 96 kHz Dynamic Range1,6,7 Min Typ Max Min Single-Ended Typ Max Unit EN D TI EL A L PH D I RA 0.1 ±120 0.1 ±120 3.3 3.7•VA 400 60 3.9 20 1.65 1.85•VA 200 Copyright 2009 Cirrus Logic A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise6,7 -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB 10 AIN_1A/B Interchannel Isolation AIN_[2..6]A/B MUX Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Input Full-Scale Input Voltage2,3 Differential Input Impedance4 Single-Ended Input Impedance5 Common Mode Rejection Ratio (CMRR)8 Parasitic Load Capacitance (CL)9 99 96 - 105 102 99 -98 -82 -42 -90 95 95 -92 - - FT 1.95 20 96 93 102 99 96 -95 -79 -39 -90 95 95 -89 - dB dB dB dB dB dB dB dB dB dB ppm/°C VPP Ω Ω dB pF 1. dB units referred to the typical full-scale voltage. 2. These full-scale values were measured with Ri=10k for both the single-ended and differential mode input circuits. 3. The full-scale voltage can be changed be scaling Ri. Differential Full-Scale (Vpp) =3.7*VDDA*(Ri+200)/(10k+200) Single-Ended Full-Scale (Vpp) = 1.85*VDDA*(Ri+200)/(10k+200) 8. This number was measured using perfectly matched external resistors (Ri). Mismatch in the external resistors will DS787PP1 C typically reduce CMRR by 20 log (|ΔRi|/Ri + 0.001). 9. CL represents the parasitic load capacitance between Ri on the input circuit and the input pin of the CS47048 package. 10. This measurement is not applicable to the CS47028 and CS47024 devices. O 7. Common mode input current should be kept to less than +/- 160uA to avoid performance degradation: |(Iip+Iin)/2| < 160uA. This corresponds to +/- 1.6V for Ri=10 kΩ in the differential case. N 4. Measured between AIN_xx+ and AN_xx-. 5. Measured between AIN_xx+ and AGND. 6. Decreasing Full-Scale voltage by reducing Ri will cause the noise floor to increase. FI D 27 CS470xx Data Sheet Audio SOC Processor Family 5.16.2 Analog Input Characteristics (Automotive) Test Conditions (unless otherwise specified): TA = -40 to +85°C; VDD = 1.8V±5%, VDDA (VA)= 3.3V±5%; 1 kHz sine wave driven through the passive input filter (Ri=10 kΩ) in Figure 14 on page 29 or Figure 15 on page 29; DSP running test application; Measurement Bandwidth is 10 Hz to 20 kHz. Differential Parameter Min Typ Max Min Single-Ended Typ Max Unit Fs=96 kHz Dynamic Range1,6,7 EN D TI EL A L PH D I RA 0.1 ±120 0.1 ±120 3.3 3.7•VA 400 60 3.9 20 1.65 1.85•VA 200 Copyright 2009 Cirrus Logic A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise6,7 -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB AIN_1A/B Interchannel Isolation10 AIN_[2..6]A/B MUX Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Input Full-Scale Input Voltage2,3 Differential Input Impedance4 Single-Ended Input Impedance5 Common Mode Rejection Ratio (CMRR)8 Parasitic Load Capacitance (CL)9 Notes: 97 94 - 105 102 99 -98 -82 -42 -90 95 95 -90 - 94 91 - 102 99 96 -95 -79 -39 -90 95 95 -87 - dB dB dB dB dB dB dB dB dB dB ppm/°C VPP Ω Ω dB pF 1. dB units referred to the typical full-scale voltage. 2. These full-scale values were measured with Ri=10k for both the single-ended and differential mode input circuits. 8. This number was measured using perfectly matched external resistors (Ri). Mismatch in the external resistors will typically reduce CMRR by 20 log (|ΔRi|/Ri + 0.001). 28 C 9. CL represents the parasitic load capacitance between Ri on the input circuit and the input pin of the CS47048 package. 10. This measurement is not applicable to the CS47028 and CS47024 devices. O 7. Common mode input current should be kept to less than +/- 160uA to avoid performance degradation: |(Iip+Iin)/2| < 160uA. This corresponds to +/- 1.6V for Ri=1 0kΩ in the differential case. N 4. Measured between AIN_xx+ and AN_xx-. 5. Measured between AIN_xx+ and AGND. 6. Decreasing Full-Scale voltage by reducing Ri will cause the noise floor to increase. FI D 3. The full-scale voltage can be changed be scaling Ri. Differential Full-Scale (Vpp) = 3.7*VDDA*(Ri+200)/(10k+200) Single-Ended Full-Scale (Vpp) = 1.85*VDDA*(Ri+200)/(10k+200) FT 1.95 20 DS787PP1 CS470xx Data Sheet Audio SOC Processor Family 10µF AIN 100K + Ri AIN_xA+ or AIN_xB+ CL AIN- AIN+ Figure 15. ADC Differential Input Test Circuit DS787PP1 C O N FI D EN D TI EL A L PH D I RA 10µF + Ri 100K CL AIN_xAor AIN_xB10µF + Ri 100K CL AIN_xA+ or AIN_xB+ Copyright 2009 Cirrus Logic FT 29 Figure 14. ADC Single-Ended Input Test Circuit CS470xx Data Sheet Audio SOC Processor Family 5.16.3 ADC Digital Filter Characteristics Parameter1, 2 Fs = 96 kHz Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay High-Pass Filter Characteristics Frequency Response-3.0 dB -0.13 dB Phase Deviation @ 20 Hz Passband Ripple Filter Settling Time Min Typ Max Unit to -0.1 dB corner 0 0.5688 70 - 12/Fs 1 20 10 5/Fs 10 0.4896 0.08 0 0 Fs dB Fs dB s Hz Hz Deg dB s Notes: 1. Filter response is guaranteed by design. 2. Response is clock-dependent and will scale with Fs. 5.17 DAC Characteristics 5.17.1 Analog Output Characteristics (Commercial) Test Conditions (unless otherwise specified): TA = 0 to +70°C; VDD = 1.8V±5%, VDDA(VA) = 3.3V±5%; 1 kHz sine wave driven through a filter shown in Figure 16 on page 31 or Figure 17 on page 32; DSP running test application; Measurement Bandwidth is 20 Hz to 20 kHz. Differential Typ Single-Ended Typ Max Parameter Fs = 96 kHz Dynamic Range EN D TI EL A L PH D I RA Min Max Min FT 105 102 -95 -85 -45 95 0.70•VA 0.1 ±120 100 -87 0.80 10 100 Unit A-weighted unweighted Total Harmonic Distortion + Noise 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz) Analog Output Full-Scale Output Interchannel Gain Mismatch Gain Drift Output Impedance DC Current draw from an AOUT pin1 AC-Load Resistance (RL)2 Load Capacitance (CL)2 D 102 99 - 108 105 -98 -88 -48 95 - 99 96 - dB dB dB dB dB dB VPP dB ppm/°C Ω μA kΩ pF N -90 1.60 10 100 FI 1.20 3 - 1.40•VA 0.1 ±120 100 - 0.60 3 - 30 C O Copyright 2009 Cirrus Logic DS787PP1 CS470xx Data Sheet Audio SOC Processor Family 5.17.2 Analog Output Characteristics (Automotive) Test Conditions (unless otherwise specified): TA = -40 to +85°C; VDD = 1.8V±5%, VDDA(VA) = 3.3V±5%; 1 kHz sine wave driven through a filter shown in Figure 16 on page 31 or Figure 17 on page 32; DSP running test application; Measurement Bandwidth is 20 Hz to 20 kHz. Differential Typ Single-Ended Typ Max Parameter Fs = 96 kHz Dynamic Range Min Max Min Unit EN D TI EL A L PH D I RA 1.20 3 1.40•VA 0.1 ±120 100 1.60 10 100 0.60 3 0.70•VA 0.1 ±120 100 3.3 µF + CL 560 AOUT RL 10 k 2200 pF Copyright 2009 Cirrus Logic A-weighted unweighted Total Harmonic Distortion + Noise 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz) Analog Output Full-Scale Output Interchannel Gain Mismatch Gain Drift Output Impedance DC Current draw from an AOUT pin1 AC-Load Resistance (RL)2 Load Capacitance (CL)2 Notes: 100 97 - 108 105 -98 -88 -48 95 -90 - 97 94 - 105 102 -95 -85 -45 95 -87 - dB dB dB dB dB dB VPP dB ppm/°C Ω μA kΩ pF 1. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic DC-blocking capacitors. 2. Guaranteed by design. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL represents any capacitive loading that appears before the 560 Ω series resistor (typically parasitic), and will effectively move the dominant pole of the two-pole amp in the output stage. Increasing this value beyond the recommended 100 pF can cause the internal op-amp to become unstable. C O N DS787PP1 FI AOUT_x+ D Figure 16. DAC Single-Ended Output Test Circuit FT 0.80 10 100 31 CS470xx Data Sheet Audio SOC Processor Family 4.87 k 1800 pF 470 pF 2.43 k 953 1.96k + AOUT_xAOUT_x+ CL 4.87 k 1.96 k + 560 AOUT 22 µF 10 k CL 4700 pF + 22 µF 1200 pF P output: RL = 1.96k + ( [2πF*4700pF]-1 || (1.96k + [2πF*22µF- ]-1 ) || (953 + [2πF*1200pF ]-1 )) N output: RL = 4.87k + ( [2πF*1800pF]-1 || ((2.43k + [2πF*470pF]-1 ) || 4.87k )) Figure 17. DAC Differential Output Test Circuit 125 Capacitive Load -- C L (pF) 100 75 50 25 FI O 5.17.3 Combined DAC Interpolation & On-chip Analog Filter Response Parameter Min Typ Max Unit Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay 32 C Passband (Frequency Response) N D EN D TI EL A L PH D I RA Safe Operating Region 2.5 3 5 10 15 20 Resistive Load -- RL (kΩ ) Figure 18. Maximum Loading to 0.22 dB corner to -3 dB corner 0 0 -0.02 0.5465 100 - 10/Fs FT 0.4125 0.4979 +0.02 Fs Fs dB Fs dB s DS787PP1 Copyright 2009 Cirrus Logic CS470xx Data Sheet Audio SOC Processor Family 6. Ordering Information The CS470xx DSP part numbers are described as follows: Example: CS47048I-XYZR where I - ROM ID Letter X - Product Grade Y - Package Type Z - Lead (Pb) Free R - Tape and Reel Packaging Part No. CS47048C-CQZ CS47048C-DQZ CS47028C-CQZ CS47028C-DQZ CS47024C-CQZ CS47024C-DQZ NOTE: Please contact the factory for availability of the -D (automotive grade) package. 7. Environmental, Manufacturing, & Handling Information Table 6. Environmental, Manufacturing, & Handling Information CS47048C-CQZ FI Model Number D O N CS47048C-DQZ CS47028C-CQZ CS47028C-DQZ CS47024C-CQZ 260 °C 3 7 days C CS47024C-DQZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS787PP1 EN D TI EL A L PH D I RA Table 5. Ordering Information Grade Temp. Range Commercial Automotive 0 to +70 °C -40 to +85 °C 0 to +70 °C Commercial Automotive -40 to +85 °C 0 to +70 °C Commercial Automotive -40 to +85 °C Peak Reflow Temp MSL Rating* Max Floor Life 260 °C 3 260 °C 3 Copyright 2009 Cirrus Logic FT Package 100-pin LQFP 7 days 7 days 33 CS470xx Data Sheet Audio SOC Processor Family 8. Device Pinout Diagram 8.1 CS47048, 100-Pin LQFP Pinout Diagram AOUT_1+ AOUT_2+ AOUT_3+ AOUT_4+ AOUT_5+ AOUT_6+ AOUT_7+ AOUT_8+ AOUT_1AOUT_2AOUT_3AOUT_4AOUT_5AOUT_6AOUT_7100 RESET AOUT_876 75 VDD_DAC GND_DAC VDD_ADC_MON REXT 5 VQ 70 BIASREF_DAC GNDA7 GNDA6 GNDA5 GNDA4 VDDA7 VDDA6 VDDA5 VDDA4 95 90 85 DBCK DBDA GPIO15, DAI_LRCLK GPIO17, DAI_SCLK VDDIO1 GNDIO1 GPIO16, DAI_DATA0, TM0 GPIO0, DAI_DATA1, TM1 GPIO1, DAI_DATA2, TM2 GPIO2, DAI_DATA3, TM3, SPDIF RX VDD1 GND1 GPIO7, DAO_LRCLK GPIO14, DAO_SCLK GNDIO2 VDDIO2 GPIO18, DAO_MCLK, HS4 GPIO6, DAO_DATA0, HS0 GPIO3, DAO_DATA1, HS1 GPIO4, DAO_DATA2, HS2, S/PDIF TXb GPIO5, DAO_DATA3, HS3, S/PDIF TXa VDD2 GND2 GPIO9, SCP_MOSI GPIO10, SCP_MISO, SCP_SDA 1 80 10 EN D TI EL A L PH D I RA CS47048 100-Pin LQFP (Thermal Pad Package) VDDIO3 30 VDD3 35 VDDA_PLL 40 AIN_4B- 45 PLL_REF_RES XTAL_OUT GPIO13, SCP_BSY, EE_CS GND_SUB GNDA_PLL 15 20 25 26 GPIO12, SCP_IRQ GPIO8, SCP_CS, DAI_DATA4 GPIO11, SCP_CLK 34 C O N FI D Figure 19. CS47048 Pinout Diagram Copyright 2009 Cirrus Logic AIN_2B+ 50 AIN_4B+ AIN_5B- AIN_3B- AIN_6B+ AIN_5B+ AIN_3B+ GNDIO3 AIN_6B- AIN_2B- GND3 XTO XTI FT AIN_1A+ AIN_1AAIN_1B+ 65 AIN_1BVDDA3 BIASREF_ADC VDDA2 GNDA2 60 AIN_2A+ AIN_2AAIN_3A+ AIN_3AAIN_4A+ 55 AIN_4AAIN_5A+ AIN_5AAIN_6A+ 51 AIN_6A- GNDA3 DS787PP1 CS470xx Data Sheet Audio SOC Processor Family 8.2 CS47028, 100-Pin LQFP Pinout Diagram AOUT_1+ AOUT_2+ AOUT_3+ AOUT_4+ AOUT_5+ AOUT_6+ AOUT_7+ AOUT_8+ AOUT_1AOUT_2AOUT_3AOUT_4AOUT_5AOUT_6AOUT_7100 RESET AOUT_876 75 VDD_DAC GND_DAC VDD_ADC_MON REXT 5 VQ 70 BIASREF_DAC GNDA3 NC GNDA7 GNDA6 GNDA5 GNDA4 VDDA7 VDDA6 VDDA5 VDDA4 95 90 85 DBCK DBDA GPIO15, DAI_LRCLK GPIO17, DAI_SCLK VDDIO1 GNDIO1 GPIO16, DAI_DATA0, TM0 GPIO0, DAI_DATA1, TM1 GPIO1, DAI_DATA2, TM2 GPIO2, DAI_DATA3, TM3, SPDIF RX VDD1 GND1 GPIO7, DAO_LRCLK GPIO14, DAO_SCLK GNDIO2 VDDIO2 GPIO18, DAO_MCLK, HS4 GPIO6, DAO_DATA0, HS0 GPIO3, DAO_DATA1, HS1 GPIO4, DAO_DATA2, HS2, S/PDIF TXb GPIO5, DAO_DATA3, HS3, S/PDIF TXa VDD2 GND2 GPIO9, SCP_MOSI GPIO10, SCP_MISO, SCP_SDA 1 80 10 CS47028 15 EN D TI EL A L PH D I RA VDDIO3 30 VDD3 35 VDDA_PLL 40 AIN_4B- 45 GPIO13, SCP_BSY, EE_CS PLL_REF_RES AIN_6B+ AIN_5B+ AIN_4B+ GND_SUB GNDA_PLL AIN_3B+ GND3 AIN_5BAIN_3BXTAL_OUT GNDIO3 100-Pin LQFP (Thermal Pad Package) 20 25 26 GPIO12, SCP_IRQ GPIO8, SCP_CS, DAI_DATA4 GPIO11, SCP_CLK DS787PP1 C O N FI D Figure 20. CS47028 Pinout Diagram Copyright 2009 Cirrus Logic AIN_2B+ 50 AIN_6B- AIN_2B- XTO XTI FT NC 65 NC VDDA3 VDDA2 GNDA2 60 AIN_2A+ AIN_2AAIN_3A+ AIN_3AAIN_4A+ 55 AIN_4AAIN_5A+ AIN_5AAIN_6A+ 51 AIN_6A- NC BIASREF_ADC 35 CS470xx Data Sheet Audio SOC Processor Family 8.3 CS47024, 100-Pin LQFP Pinout Diagram AOUT_1+ AOUT_2+ AOUT_3+ AOUT_4+ AOUT_1AOUT_2AOUT_3AOUT_4GNDA7 GNDA6 GNDA5 100 RESET GNDA4 VDDA7 VDDA6 VDDA5 VDDA4 NC NC NC NC NC NC NC NC 76 75 VDD_DAC GND_DAC VDD_ADC_MON REXT 5 VQ 70 BIASREF_DAC GNDA3 NC 95 90 85 DBCK DBDA GPIO15, DAI_LRCLK GPIO17, DAI_SCLK VDDIO1 GNDIO1 GPIO16, DAI_DATA0, TM0 GPIO0, DAI_DATA1, TM1 GPIO1, DAI_DATA2, TM2 GPIO2, DAI_DATA3, TM3 VDD1 GND1 GPIO7, DAO_LRCLK GPIO14, DAO_SCLK GNDIO2 VDDIO2 GPIO18, DAO_MCLK, HS4 GPIO6, DAO_DATA0, HS0 GPIO3, DAO_DATA1, HS1 GPIO4, DAO_DATA2, HS2, S/PDIF TXb GPIO5, DAO_DATA3, HS3, S/PDIF TXa VDD2 GND2 GPIO9, SCP_MOSI GPIO10, SCP_MISO, SCP_SDA 1 80 10 CS47024 15 EN D TI EL A L PH D I RA VDDIO3 30 VDD3 35 VDDA_PLL 40 AIN_4B- 45 PLL_REF_RES XTAL_OUT AIN_4B+ AIN_5BAIN_3BGPIO12, SCP_IRQ AIN_6B+ AIN_5B+ GPIO13, SCP_BSY, EE_CS GND_SUB GNDA_PLL 100-Pin LQFP (Thermal Pad Package) 20 25 26 GPIO8, SCP_CS, DAI_DATA4 GPIO11, SCP_CLK 36 C O Figure 22 shows the 100-pin LQFP package with exposed pad for the CS47048, CS47028, and CS47024. N 9. 100-pin LQFP with Exposed Pad Package Drawing FI D Figure 21. CS47024 Pinout Diagram Copyright 2009 Cirrus Logic AIN_2B+ 50 AIN_3B+ GNDIO3 AIN_6B- AIN_2B- GND3 XTO XTI FT NC 65 NC VDDA3 VDDA2 GNDA2 60 AIN_2A+ AIN_2AAIN_3A+ AIN_3AAIN_4A+ 55 AIN_4AAIN_5A+ AIN_5AAIN_6A+ 51 AIN_6A- NC BIASREF_ADC DS787PP1 CS470xx Data Sheet Audio SOC Processor Family C DS787PP1 O N FI D R D AL H I TI LP EN E D Copyright 2009 Cirrus Logic Figure 22. 100-Pin LQFP Package Drawing 37 AF T CS470xx Data Sheet Audio SOC Processor Family 10. Parameter Definitions 10.1 Dynamic Range The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. 10.2 Total Harmonic Distortion + Noise The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. 10.3 Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. 10.4 Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. 10.5 Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. 10.6 Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. 10.7 Gain Drift 11. Revision History Revision N FI Date D The change in gain value with temperature. Units in ppm/°C. A7 A8 O October 16, 2008 March 22, 2009 38 C EN D TI EL A L PH D I RA Changes Copyright 2009 Cirrus Logic Initial Release Added CS47028 and CS47024 products to the data sheet. Changed name of data sheet to CS470xx Data Sheet. Added note regarding necessity of power supplies being stable before RESET goes high to Section 5.6. FT DS787PP1 CS470xx Data Sheet Audio SOC Processor Family Revision Date Changes A9 April 22, 2009 Updated Table 2 and Table 3. Updated timing diagram in Figure 4 and added Figure 5. Updated Figure 14, Figure 15, Figure 16, and Figure 17. Characterization data for Standby Power Supply Current: reported as TBD until final measurements are completed. Formula in Note 3 on p. 27 and Note 3 on p. 28 have been restated for greater clarity. Min and Max values for Full-Scale input Voltage in Section 5.16.1 and Section 5.16.2 reported as TBD until final measurements are completed. Updated Section 5.10, replacing references to SCP_CS with EE_CS. Updated ordering numbers in Table 5 and Table 6. Updated characterization data for Analog Full-Scale Output Voltage, Typical, for both Differential and Single-ended signals in Section 5.16.1, Section 5.16.2, Section 5.17.1, and Section 5.17.2. A10 A11 April 28, 2009 April 29, 2009 DS787PP1 C O N FI D EN D TI EL A L PH D I RA Copyright 2009 Cirrus Logic PP1 August 3, 2009 Updated Characterization data in Section 5.4, Section 5.7, Section 5.9, Section 5.11, Section 5.12, Section 5.16.1, Section 5.16.2, Section 5.16.3, Section 5.17.1, and Section 5.17.2. Modified Footnote 3 in both Section 5.16.1 and Section 5.16.2. Added Footnote 5 to Section 5.14. Updated Section 2.. Modified Section 4.3.6 and Section 4.3.8. Modified references to TDM in various sections of the data sheet. Use the search function in the Adobe PDF Reader™ to find all instances where TDM is described in this data sheet. FT 39 CS470xx Data Sheet Audio SOC Processor Family §§1 40 C 1. The “§§” symbol indicates the end of the content in this document. Copyright 2009 Cirrus Logic DS787PP1 O N FI D EN D TI EL A L PH D I RA FT