CS47048 Data Sheet
FEATURES
Cost-effective, High-performance 32-bit DSP
— — — — 300,000,000 MAC/S (multiply accumulates per second) Dual MAC cycles per clock 72-bit accumulators are the most accurate in the industry 32K x 32-bit SRAM with three 2K blocks assignable to either Y data or program memory.
Integrated DAC & ADC Functionality
— 8 Channels of DAC output: 108dB DR, 98dB THD+N — 4 Channels of ADC input: 105dB DR, 98dB THD+N — Integrated 5:1 analog mux feeds one stereo ADC
Configurable Serial Audio Inputs/Outputs
— — — — — Integrated 192 kHz S/PDIF Rx Integrated 192 kHz S/PDIF Tx Supports 32-bit Serial Data @ 192 kHz Supports 32-bit audio sample I/O between DSP chips TDM I/O modes (Up to 8 channels per line)
Supports Different Fs Sample Rates
— Three Integrated hardware SRC blocks — Output can be master or slave
— Supports dual-domain Fs on inputs (S/PDIF Rx and I2S)
— Supports dual-domain Fs on outputs (S/PDIF Tx and I2S)
DSP Tool Set w/ Private Keys Protect Customer IP Integrated Clock Manager/PLL
— Flexibility to operate from internal PLL, external crystal, external oscillator
Input Fs Auto Detection w/ µC Acknowledgement Host & Boot via SPI / I2C Serial Interface Configurable GPIOs and External Interrupt Input 1.8V Core and a 3.3V I/O that is tolerant to 5V input Low-power Mode: 620µW
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ADC’s & DAC’s operate in Single ended or Differential mode
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Memory Bus
4ch
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PIC ROM RAM
MUX
ADC2/3
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SPI / I2C Control
32K x 32-bit SRAM with three 2K blocks Assignable to Program or Y Data memory
Advance Product Information
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright 2008 Cirrus Logic CONFIDENTIAL OCT ’08 DS787A7
http://www.cirrus.com
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Stereo Inputs On Analog in
S R C 1
DMA
ROM RAM ROM
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Peripheral Bus
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Ordering Information:
See page 30 for ordering information
DBC
(I2C Slave)
The CS47048 family is a new generation of audio system-on-achip (ASOC) processors targeted at high fidelity, cost sensitive designs. Derived from the highly successful CS48500 32-bit fixed point audio enhancement processor family, the CS47048 further simplifies system design and reduces total system cost by integrating the S/PDIF Rx, S/PDIF Tx, analog inputs, analog outputs, and SRCs to simplify system design. For example, a hardware SRC can down-sample a 192kHz S/PDIF stream to a lower Fs to reduce memory and MIPS requirements for processing. This integration effectively reduces the chip count from 3 to 1 which allows smaller, less expensive board designs. Target applications are: — Automotive Head Units & Outboard Amplifiers — Automotive Processors & Automotive Integration Hubs — Digital TV — MP3 Docking Stations — AVR and DVD RX — DSP Controlled Speakers (e.g. Subwoofers, Sound Bars)
The CS47048 is programmed using the simple yet powerful Cirrus proprietary DSP Composer™ GUI development and preproduction tuning tool. Processing chains may be designed using a drag-and-drop interface to place/utilize functional macro audio DSP primitives and custom audio filtering blocks. The end result is a software image that is downloaded to the DSP via serial control port. DSP programming could not be easier for the novice or small engineering development group. DSP Composer provides the programmer with faster time-to-market opportunities and the ability to implement custom code. The CS47048 is available in a 100-pin LQFP package with exposed pad for better thermal characteristics. Both Commercial (0°C to +70°C) and Automotive (-40°C to +85°C) temperature grades.
PLL
Clock Manager
Timers
GPIO
I2S / TDM / SPDIF I2S / TDM
8ch
S R C 2
Coyote32 text 32-bit DSP
DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7
ADC0/1
x8 8ch
S R C 3
SRC3 has 8 independent Channels for In or Out
x2
I2S / TDM
x2
RAM I2S / TDM / SPDIF
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CS47048 Data Sheet Audio SOC Processor Family
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com.
IMPORTANT NOTICE
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. I2C is a registered trademark of Philips Semiconductor.
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“Advance” product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
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Table of Contents
FEATURES ......................................................................................................................... 1 1. Documentation Strategy .........................................................................................................6 2. Overview ..................................................................................................................................6
2.1 Licensing ............................................................................................................................................... 6
3. Code Overlays .........................................................................................................................7 4. Hardware Functional Description .........................................................................................8
4.1 DSP Core .............................................................................................................................................. 8 4.2 DSP Memory ......................................................................................................................................... 9 4.2.1 DMA Controller ......................................................................................................................... 9 4.3 On-chip DSP Peripherals ...................................................................................................................... 9 4.3.1 Analog to Digital Converter Port (ADC) .................................................................................... 9 4.3.2 Digital to Analog Converter Port (DAC) .................................................................................... 9 4.3.3 Digital Audio Input Port (DAI) .................................................................................................. 10 4.3.4 S/PDIF RX Input Port (DAI) .................................................................................................... 10 4.3.5 Digital Audio Output Port (DAO) ............................................................................................. 10 4.3.6 S/PDIF TX Output Port (DAO) ................................................................................................ 10 4.3.7 Sample Rate Converters (SRC) ............................................................................................. 10 4.3.8 Serial Control Port (I2C® or SPI™) .......................................................................................... 11 4.3.9 GPIO ....................................................................................................................................... 11 4.3.10 PLL-based Clock Generator ................................................................................................. 11 4.3.11 Hardware Watchdog Timer ................................................................................................... 11 4.4 DSP I/O Description .............................................................................................................................11 4.4.1 Multiplexed Pins ..................................................................................................................... 11 4.4.2 Termination Requirements ...................................................................................................... 11 4.4.3 Pads ....................................................................................................................................... 11 4.5 Application Code Security ................................................................................................................... 12
5. Characteristics and Specifications .....................................................................................13
5.1 Absolute Maximum Ratings ................................................................................................................. 13 5.2 Recommended Operating Conditions ................................................................................................. 13 5.3 Digital DC Characteristics ................................................................................................................... 13 5.4 Power Supply Characteristics ............................................................................................................. 14 5.5 Thermal Data (100-Pin LQFP with Exposed Pad) ............................................................................... 14 5.6 Digital Switching Characteristics— RESET ......................................................................................... 15 5.7 Digital Switching Characteristics — XTI .............................................................................................. 15 5.8 Digital Switching Characteristics — Internal Clock .............................................................................. 16 5.9 Digital Switching Characteristics — Serial Control Port - SPI Slave Mode ......................................... 17 5.10 Digital Switching Characteristics — Serial Control Port - SPI Master Mode ..................................... 18 5.11 Digital Switching Characteristics — Serial Control Port - I2C Slave Mode2 ....................................... 19 5.12 Digital Switching Characteristics — Serial Control Port - I2C Master Mode ...................................... 20 5.13 Digital Switching Characteristics — Digital Audio Slave Input Port ................................................... 21 5.14 Digital Switching Characteristics — Digital Audio Output Port .......................................................... 22 5.15 Digital Switching Characteristics — S/PDIF RX Port ........................................................................ 23 5.16 ADC Characteristics .......................................................................................................................... 24 5.16.1 Analog Input Characteristics (Commercial) .......................................................................... 24 5.16.2 Analog Input Characteristics (Automotive) ........................................................................... 25 5.16.3 ADC Digital Filter Characteristics ......................................................................................... 27 5.17 DAC Characteristics .......................................................................................................................... 27 5.17.1 Analog Output Characteristics (Commercial) ....................................................................... 27
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5.17.2 Analog Output Characteristics (Automotive) ........................................................................ 28 5.17.3 Combined DAC Interpolation & On-chip Analog Filter Response ........................................ 29
6. Ordering Information ............................................................................................................30 7. Environmental, Manufacturing, & Handling Information ..................................................30 8. Device Pinout Diagram .........................................................................................................31
8.1 CS47048, 100-Pin LQFP Pinout Diagram ........................................................................................... 31
9. 100-pin LQFP with Exposed Pad Package Drawing .........................................................31 10. Parameter Definitions .........................................................................................................33
10.1 Dynamic Range ................................................................................................................................. 33 10.2 Total Harmonic Distortion + Noise ..................................................................................................... 33 10.3 Frequency Response ........................................................................................................................ 33 10.4 Interchannel Isolation ........................................................................................................................ 33 10.5 Interchannel Gain Mismatch .............................................................................................................. 33 10.6 Gain Error .......................................................................................................................................... 33 10.7 Gain Drift ........................................................................................................................................... 33
11. Revision History ..................................................................................................................33
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Figure 1. CS47048 Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 3. XTI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 4. Serial Control Port - SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. Serial Control Port - SPI Master Mode Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. Serial Control Port - I2C Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. Serial Control Port - I2C Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8. Digital Audio Input (DAI) Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. Digital Audio Output Port Timing, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10. Digital Audio Output Port Timing, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 11. ADC Single-Ended Input Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 12. ADC Differential Input Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 13. DAC Single-Ended Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 14. DAC Differential Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 15. Maximum Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 16. CS47048 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 17. 100-Pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Tables
Table 1. CS47048 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Device Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Memory Configurations for CS47048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 5. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . . . . 30
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1. Documentation Strategy
The CS47048 Data Sheet describes the CS47048 audio processors. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS47048 processors Table 1. CS47048 Related Documentation
Document Name CS47048 Data Sheet CS47048 System Designer’s Guide Description This document Includes detailed system design information including Typical Connection Diagrams, BootProcedures, Pin Descriptions, Etc.
AN333 - CS47048 Firmware User’s Manual
DSP Composer User’s Manual
The scope of the CS47048 Data Sheet is primarily the hardware specifications of the CS47048 family of devices. This includes hardware functionality, characteristic data, pinout, and packaging information. The intended audience for the CS47048 Data Sheet is the system PCB designer, MCU programmer, and the quality control engineer.
2. Overview
2.1 Licensing
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Licenses are required for any 3rd party audio processing algorithms provided for the CS47048. Please contact your local Cirrus Logic Sales representative for more information.
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The CS47048 DSP is designed to provide high-performance post-processing and mixing of analog and digital audio. The dual clock domain provided on the PCM inputs allows for the mixing of audio streams with different sampling frequencies. The low-power standby preserves battery life for applications which are always on, but not necessarily processing audio, such as automotive audio systems. The CS47048 utilizes voltage-out DACs and is capable of supporting dual input clock domains and dual output clock domains through the use of the internal SRCs. The CS47048 is available in a 100-pin LQFP package. Refer to Table 2 on page 7 for the input, output, and firmware configurations for the CS47048 DSP.
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Includes detailed firmware design information including signal processing flow diagrams and control API information Includes detailed configuration and usage information for the GUI development tool.
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3. Code Overlays
The suite of software available for the CS47048 family consists of an operating system (OS) and a library of overlays. The overlays for the CS47048 are currently limited to post-processors. All software components are defined below: 1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external serial memory, processing host messages, calling audio-processing subroutines, error concealment, etc. 2. Post-processors - Any module that processes audio I/O buffer PCM data. Examples are bass management, audio manager, tone control, EQ, delay, customer-specific effects, and any postprocessing algorithms available for the CS485xx. The bulk of standard overlays are stored in ROM within the CS47048, but a small image is required to configure the overlays and boot the DSP. This small image can either be stored in an external serial FLASH/EEPROM, or downloaded via a host controller through the SPI™/I2C® serial port. The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a different post-processor is selected, the OS, does not need to be reloaded — only the new post-processor. Table 2 lists the different configuration options available. Please refer to the CS47048 Firmware User’s Manual for the latest listing of application codes and Cirrus Framework™ modules available.
Device
Suggested Application
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Table 2. Device Selection Guide
Channel Count Input/Output
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CS47048-CQZ CS47048-DQZ
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Automotive Head Units Automotive Outboard Amplifiers Automotive Processors Automotive Integration Hubs Digital TV MP3 Docking Stations AVR DVD Rx DSP Controlled Speakers
Up to 12 Channels Analog In (4 simultaneously) Up to 10 Channels PCM In (Stand-Alone) Up to 8 Channels PCM In (w/ Host) 100-pin Up to 40 Channels TDM In QFP Up to 8 Channels Analog Out Up to 8 Channels PCM Out Up to 32 Channels TDM Out
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CS47048 Data Sheet Audio SOC Processor Family
4. Hardware Functional Description
The CS47048 is a true system-on-a-chip that combines a powerful 32-bit DSP engine with analog/digital audio inputs and analog/digital audio outputs. It can be integrated into a complex multi-DSP processing system, or stand alone in an audio product that requires analog-in and analog-out. A top level block diagram is shown below in Figure 1.
ADC’s & DAC’s operate in Single ended or Differential mode
DBC
(I2C Slave)
PLL
Clock Manager
Timers
GPIO DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7
8ch
x4
I2S / TDM
Memory Bus
4ch
PIC
MUX
ADC2/3
ROM RAM
P
4.1 DSP Core
The CS47048 is a single-core DSP with separate X and Y data and P code memory spaces. The DSP core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has eight 72-bit accumulators, four X-data and four Y-data registers, and 12 index registers. The DSP core is coupled to a flexible 8-channel DMA engine. The DMA engine can move data between peripherals such as the serial control port (SCP), digital audio input (DAI) and digital audio output (DAO), sample rate converters (SRC), analog-to-digital converters (ADC), digital-to-analog converters (DAC), or any DSP core memory, all without the intervention of the DSP. The DMA engine off-loads data move instructions from the DSP core, leaving more MIPS available for signal processing instructions.
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SPI / I2C Control
32K x 32-bit SRAM with three 2K blocks Assignable to Program or Y Data memory
Figure 1. CS47048 Top-Level Block Diagram
X
Stereo Inputs On Analog in
S R C 1
DMA
ROM RAM
Peripheral Bus
ADC0/1
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Coyote32 text 32-bit DSP
x8 8ch
S R C 3
ROM RAM
Y
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x2
I2S / TDM / SPDIF
S R C 2
I2S / TDM
x2
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CS47048 Data Sheet Audio SOC Processor Family
CS47048 functionality is controlled by application codes that are stored in on-chip ROM or downloaded to the CS47048 from a host controller or external serial FLASH/EEPROM. Users can develop their applications using DSP ComposerTM to create the processing chain and then compile the image into a series of commands that are sent to the CS47048 through the SCP. The processing application can either load modules (post-processors) from the DSP’s on-chip ROM, or custom firmware can be downloaded through the SCP. The CS47048 is suitable for a variety of audio post-processing applications where sound quality via sound enhancement and speaker/cabinet tuning is required to achieve the sound quality consumers expect. Examples of such applications include automotive head-ends, automotive amplifiers, docking stations, sound bars, subwoofers, and boom boxes.
4.2 DSP Memory
The DSP core has its own on-chip data and program RAM and ROM and does not require external memory for post-processing applications. The Y-RAM and P-RAM share a single block of memory that includes three 2K word blocks (32 bits/word) that are assignable to either Y-RAM or P-RAM as shown in Table 3. Table 3. Memory Configurations for CS47048
P-RAM X-RAM
14K words 12K words 10K words 8K words
4.2.1 DMA Controller
The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment controls. The service intervals for each DMA channel, as well as up to 6 interrupt events, are programmable.
4.3.2 Digital to Analog Converter Port (DAC) The CS47048 can support up to 8 simultaneous channels of digital-to-analog conversion and features DACs with dynamic range performance in excess of 100 dB. The DACs have voltage mode outputs that can be connected either as single-ended or differential signals. The conversions are performed with Fs=96 kHz.
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The CS47048 features ADCs with dynamic range performance in excess of 100 dB, and they can support up to 4 simultaneous channels of analog-to-digital conversion. Analog inputs AIN_1A and AIN_1B are connected directly to one stereo ADC (ADC0-1). The analog input capability of the second stereo ADC (ADC2-3) is expanded through a 5:1 analog stereo mux (analog inputs AIN_2A/B through AIN_6A/B). This gives the CS47048 the ability to select from six stereo pairs of analog input. A single programmable bit selects single-ended or differential mode signals for all inputs. The conversions are performed with either Fs=96 kHz or Fs=192 kHz.
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Y-RAM 10K words 8K words 10K words 10K words 10K words 12K words 10K words 14K words
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4.3.3 Digital Audio Input Port (DAI) The input capabilities for each version of the CS47048 are summarized in Table 2 on page 7. Up to five DAI ports are available. Two of the DAI ports can be programmed to implement other functions. The S/PDIF Rx function, if used, takes over the DAI_DATA3 pin. If the SPI mode is used, the DAI_DATA4 pin becomes the SCP_CS input. The DAI port supports PCM format with word lengths up to 32 bits and sample rates as high as 192 kHz. The DAI also supports a time division multiplexed (TDM) one-line data mode that packs PCM audio on a single data line. The total number possible depends on the ratio of SCLK to LRCLK. The CS47048 hardware supports up to 40 channels in one line mode @ 48 kHz. There is also a practical limitation set by the amount of processing required per channel. The DAI port has two independent slave-only clock domains. The PCM inputs can be on one clock domain, and the S/PDIF Rx on another. The output of the S/PDIF Rx can then be converted through one of the internal SRC blocks to synchronize with the PCM input. The sample rate of the input clock domains can be determined automatically by the DSP, offloading the task of monitoring the S/PDIF Rx from the host. A time-stamping feature provides the ability to also sample-rate convert the input data via software. 4.3.4 S/PDIF RX Input Port (DAI)
One of the PCM pins of the DAI can also be used as a DC-coupled, TTL-level S/PDIF Rx input capable of receiving and demodulating bi-phase encoded S/PDIF signals with Fs ≤ 192 kHz. 4.3.5 Digital Audio Output Port (DAO) The output capabilities of the CS47048 are summarized in Table 2 on page 7. DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as 192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or as a clock slave if an external MCLK or SCLK/LRCLK source is available. The DAO also supports a time division multiplexed (TDM) one-line data mode, that packs multiple channels of PCM audio on a single data line. The total number possible depends on the ratio of SCLK to LRCLK and the version of chip. For example, the CS47048 hardware supports up to 32 channels in one line mode @ 48 kHz. There is also a practical limitation set by the amount of processing required per channel. 4.3.6 S/PDIF TX Output Port (DAO)
4.3.7 Sample Rate Converters (SRC) The CS47048 has 3 internal SRC modules. Two of the SRC modules are capable of converting 8 Channels, and one SRC has 4-Channel capability. The ADCs are directly associated with a 4-Channel SRC which is used to transfer data from the fixed 96/192 kHz Fs domain into an Fs appropriate for mixing with other audio in the system. When the Analog Inputs are not being used, this SRC can be used to convert digital data within the DSP from the input Fs (Fsi) to the output Fs (Fso). The DACs are directly associated with an 8-Channel SRC which is used to transfer data from the Fs being processed by the DSP to a fixed 96 kHz Fs domain for conversion to analog. When the Analog Outputs are not being used, this SRC can be used to convert digital data within the DSP from Fsi to Fso.
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Two of the serial audio pins can be re-configured as S/PDIF TX pins that drive a bi-phase encoded S/PDIF signal (data with embedded clock on a single line). The S/PDIF engine can be driven by a clock domain independent of the PCM output port by utilizing one of the internal SRCs.
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The second 8-Channel SRC is a stand-alone digital-to-digital conversion module. It can be used to make independent input clock domains synchronous (different Fs on PCM input and S/PDIF Rx) or to drive the S/PDIF Tx at a different Fs than the PCM output of the DSP. 4.3.8 Serial Control Port (I2C® or SPI™) The on-chip serial control port is capable of operating as master or slave in either SPI™ or I2C® modes. Master/Slave operation is chosen by mode select pins when the CS47048 comes out of reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode (SPI clock speed must always be ≤ (DSP Core Frequency/2)). The CS47048 serial control port also includes a pin for flow control of the communications interface (SCP_BSY) and a pin to indicate when the DSP has a message for the host (SCP_IRQ). 4.3.9 GPIO
4.3.10 PLL-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS47048 defaults to running from the external reference frequency and is switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1. 4.3.11 Hardware Watchdog Timer
The CS47048 has an integrated watchdog timer that acts as a “health” monitor for the DSP. The watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This peripheral ensures that the CS47048 will reset itself in the event of a temporary system failure. In stand-alone mode (i.e. no host MCU), the DSP will reboot from external FLASH. In slave mode (i.e. host MCU present) a GPIO will be used to signal the host that the watchdog has expired and the DSP should be rebooted and re-configured.
4.4 DSP I/O Description
4.4.1 Multiplexed Pins
4.4.2 Termination Requirements Open-drain pins on the CS47048 must be pulled high for proper operation. Please refer to the CS47048 System Designer’s Guide to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. Mode select pins on the CS47048 are used to select the boot mode upon the rising edge from reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS47048 System Designer’s Guide.
4.4.3 Pads The CS47048 Digital I/Os operate from the 3.3 V supply and are 5 V tolerant.
DS787A7
C
O
N
Many of the CS47048 pins are multi-functional. For details on pin functionality please refer to the CS47048 System Designer’s Guide.
FI
D
EN D TI EL A L PH D I RA
Copyright 2008 Cirrus Logic
Many of the CS47048 peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high.
FT
11
CS47048 Data Sheet Audio SOC Processor Family
4.5 Application Code Security
The external program code may be encrypted by the programmer to protect any intellectual property it may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device. Please contact your local Cirrus representative for details.
12
C
O
N
FI
D
EN D TI EL A L PH D I RA
Copyright 2008 Cirrus Logic DS787A7
FT
CS47048 Data Sheet Audio SOC Processor Family
5. Characteristics and Specifications
Note:
All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C, VDD = 1.8 V, VDDIO = VDDA =3.3 V, GND = GNDIO = GNDA = 0 V.
5.1 Absolute Maximum Ratings
(GND = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Parameter DC power supplies: Core supply Analog supply I/O supply |VDDA – VDDIO| Symbol VDD VDDA VDDIO Iin Vfilt Vinio Vin Tstg Min –0.3 –0.3 –0.3 -0.3 -0.3 Max 2.0 3.6 3.6 0.3 Unit V V V V mA V V V °C
Input pin current, any pin except supplies Input voltage on PLL_REF_RES Input voltage on digital I/O pins Analog Input Voltage Storage temperature
EN D TI EL A L PH D I RA
AGND - 0.7 –65 Symbol VDD VDDA VDDIO TA Min Typ 1.8 3.3 3.3 0 Core supply Analog supply I/O supply |VDDA – VDDIO| 1.71 3.13 3.13 Commercial - CQZ Automotive - DQZ 0 - 40 Symbol VIH VIL VILXTI Vhys VOH VOL ILXTI ILEAK VDDIO * 0.9 Min 2.0 Typ 0.4 Copyright 2008 Cirrus Logic
Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
5.2 Recommended Operating Conditions
Parameter DC power supplies:
(GND = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
FT
+/- 10 3.6 5.0 VA + 0.7 150 Max 1.89 3.46 3.46 + 70 + 85 Max 0.8 0.6 VDDIO * 0.1 5 70
Unit V V V V °C
Ambient operating temperature
Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.
(Measurements performed under static conditions.)
N
Parameter
FI
5.3 Digital DC Characteristics
D
Unit V V V V V V μA μA
Low-level input voltage, except XTI Input Hysteresis High-level output voltage (IO = -2mA), except XTO Low-level output voltage (IO = 2mA), except XTO Input leakage XTI Input leakage current (all digital pins with internal pull-up resistors enabled)
DS787A7
C
Low-level input voltage, XTI
O
High-level input voltage
13
CS47048 Data Sheet Audio SOC Processor Family
5.4 Power Supply Characteristics
Note: Measurements performed under operating conditions)
Parameter Operational Power Supply Current: VDD: Core and I/O operating1 VDDA: PLL operating current VDDA: DAC operating current (all 8 channels enabled) VDDA: ADC operating current (all 4 channels enabled) VDDIO: With most ports operating Total Operational Power Dissipation: Standby Power Supply Current: VDD: Core and I/O not clocked VDDA: PLLs halted VDDA: DAC disabled VDDA: ADC disabled VDDIO: All connected I/O pins 3-stated by other ICs in system Total Standby Power Dissipation: Min Typ 325 16 56 34 27 1025 Max Unit mA mA mA mA mA mW μA μA μA μA μA μW
1. Dependent on application firmware and DSP clock speed.
5.5 Thermal Data (100-Pin LQFP with Exposed Pad)
Parameter
EN D TI EL A L PH D I RA
620 Symbol Min Typ 34 18
-
140 1.2 100 10 0.4
FT
Max -
Unit °C / Watt
Thermal Resistance (Junction to Ambient) Two-layer Board1 Four-layer Board2 Thermal Resistance (Junction to Top of Package) Two-layer Board1 Four-layer Board2
θja
ψjt
°C / Watt
0.54 .28
1. To calculate the die temperature for a given power dissipation:
2. To calculate the case temperature for a given power dissipation:
Note: Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20% Note: Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20%
of the top & bottom layers and 0.5-oz. copper covering 90% of the internal power plane & ground plane layers.
14
C
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of the top & bottom layers.
N
Τc = Τj - [ (Power Dissipation in Watts) * ψ jt ]
FI
Τj = Ambient temperature + [ (Power Dissipation in Watts) * θja ]
D
Copyright 2008 Cirrus Logic
DS787A7
CS47048 Data Sheet Audio SOC Processor Family
5.6 Digital Switching Characteristics— RESET
Parameter RESET minimum pulse width low All bidirectional pins high-Z after RESET low Configuration pins setup before RESET high Configuration pins hold after RESET high
Symbol Trstl Trst2z Trstsu Trsthld
Min 1 50 20
Max 100 -
Unit μs ns ns ns
RESET
HS[3:0]
All Bidirectional Pins
5.7 Digital Switching Characteristics — XTI
Parameter XTI period XTI high time XTI low time External Crystal operating frequency1
EN D TI EL A L PH D I RA
Trst2z Trstl Trstsu Trsthld
Figure 2. RESET Timing
Symbol Fxtal Tclki
Min 37
FT
Max 27 89 18 50 Unit MHz ns ns ns pF Ω 11.2896 13.3 13.3 10 Tclkih Tclkil CL
2
External Crystal Load Capacitance (parallel resonant)
C
O
N
1. Part characterized with the following crystal frequency values: 11.2896, 12.288, 18.432, 24.576, & 27 MH.z 2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside this range should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer’s recommendation for load capacitor selection.
X TI
t clkih Tclki
Figure 3. XTI Timing
FI
External Crystal Equivalent Series Resistance
D
ESR
t clkil
DS787A7
Copyright 2008 Cirrus Logic
15
CS47048 Data Sheet Audio SOC Processor Family
5.8 Digital Switching Characteristics — Internal Clock
Parameter Internal DSP_CLK frequency1 CS47048-CQZ CS47048-DQZ Internal DSP_CLK period1 CS47048-CQZ CS47048-DQZ DCLKP Symbol Fdclk Min Fxtal2 Fxtal 6.7 6.7 Max 150 150 ns 1/Fxtal 1/Fxtal Unit MHz
16
C
O
N
FI
D
EN D TI EL A L PH D I RA
Copyright 2008 Cirrus Logic DS787A7
FT
1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until the next power-on reset. 2.See Section 5.7.
CS47048 Data Sheet Audio SOC Processor Family
5.9 Digital Switching Characteristics — Serial Control Port - SPI Slave Mode
Parameter SCP_CLK frequency1 SCP_CS falling to SCP_CLK rising SCP_CLK low time SCP_CLK high time Setup time SCP_MOSI input Hold time SCP_MOSI input SCP_CLK low to SCP_MISO output valid SCP_CLK falling to SCP_IRQ rising SCP_CS rising to SCP_IRQ falling SCP_CLK low to SCP_CS rising SCP_CLK rising to SCP_BSY falling SCP_CS rising to SCP_MISO output high-Z Symbol fspisck tspicss tspickl tspickh tspidsu tspidh tspidov tspiirqh tspiirql tspicsh tspicsdz Min 24 20 20 5 5 0 24 20 Typical Max 25 11 Units MHz ns ns ns ns ns ns ns ns ns ns ns
1. fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is
Fxtal/3.
tspicss
SCP_CS
0
EN D TI EL A L PH D I RA
tspicbsyl 3*DCLKP+20
tspickl 2 6 7 0 5 6 7 tspickh A0 R/W tspidov MSB tspiirqh LSB MSB LSB tspibsyl
1
SCP_CLK
1/ fspisck
FI
SCP_MOSI
A6
tspidsu
D
A5
SCP_MISO
O
N
tspidh
SCP_BSY
C
SCP_IRQ
Figure 4. Serial Control Port - SPI Slave Mode Timing
DS787A7 Copyright 2008 Cirrus Logic 17
FT
20 tspicsh tspicsdz tspiirql
CS47048 Data Sheet Audio SOC Processor Family
5.10 Digital Switching Characteristics — Serial Control Port - SPI Master Mode
Parameter SCP_CLK frequency1 SCP_CS falling to SCP_CLK rising SCP_CLK low time SCP_CLK high time Setup time SCP_MISO input Hold time SCP_MISO input SCP_CLK low to SCP_MOSI output valid SCP_CLK low to SCP_CS falling SCP_CLK low to SCP_CS rising Bus free time between active SCP_CS
3
Symbol fspisck tspicss tspickl tspickh tspidsu tspidh tspidov tspicsl tspicsh tspicsx tspidz
Min 18 18 9 5 7 -
Typical
Max Fxtal/22
Units MHz ns ns ns ns ns ns ns ns ns ns
11*DCLKP + (SCP_CLK PERIOD)/2
-
EN D TI EL A L PH D I RA
11*DCLKP + (SCP_CLK PERIOD)/2 3*DCLKP tspickl 1 2 6 7 0 5 6 7 tspickh A0 R/W tspidov MSB LSB MSB LSB A5 tspidh
SCP_CLK falling to SCP_MOSI output high-Z
1. fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. 2. See Section 5.7. 3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter
tspicss
EE_CS
tspicsl 0
D
N
SCP_MISO
O
FI
SCP_CLK
1/ fspisck
A6 tspidsu
C
SCP_MOSI
Figure 5. Serial Control Port - SPI Master Mode Timing.
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Copyright 2008 Cirrus Logic
FT
8 20
tspicsx tspicsh tspidz
-
DS787A7
CS47048 Data Sheet Audio SOC Processor Family
5.11 Digital Switching Characteristics — Serial Control Port - I2C Slave Mode2
Parameter SCP_CLK frequency SCP_CLK rise time SCP_CLK fall time SCP_CLK low time SCP_CLK high time SCP_CLK rising to SCP_SDA rising or falling for START or STOP condition START condition to SCP_CLK falling SCP_CLK falling to STOP condition Bus free time between STOP and START conditions Hold time SCP_SDA input after SCP_CLK falling SCP_CLK low to SCP_SDA out valid SCP_CLK falling to SCP_IRQ rising NAK condition to SCP_IRQ low SCP_CLK rising to SCB_BSY low Setup time SCP_SDA input valid to SCP_CLK rising
1
Symbol fiicck tiicr tiicf tiicckl tiicckh tiicckcmd tiicstscl tiicstp tiicbft tiicsu tiich
Min -
Typical
Max 400 150 150
Units kHz ns ns µs µs µs µs µs µs ns ns ns ns ns ns
1.25 1.25 1.25 1.25 2.5 3 100 20 -
-
EN D TI EL A L PH D I RA
tiicdov tiicirql tiicirqh 3*DCLKP + 20 tiicbsyl 3*DCLKP + 20
tiicckl tiicr tiicf 6 7 8 0 1 6 7 8 tiicckh A0 tiicdov R/W ACK MSB tiicirqh 1/ fiicck LSB
1. fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer. 2. I2C Slave Address = 0x82
tiicckcmd
Start Condition
D
0
1
SCP_CLK
tiicstscl
FI
FT
18 3*DCLKP + 40
tiicckcmd tiicstp ACK tiicirql tiiccbsyl
Stop Condition
tiicbft
N
SCP_SDA
A6
O C
SCP_IRQ SCP_BSY
DS787A7
tiicsu
tiich
Figure 6. Serial Control Port - I2C Slave Mode Timing
Copyright 2008 Cirrus Logic 19
CS47048 Data Sheet Audio SOC Processor Family
5.12 Digital Switching Characteristics — Serial Control Port - I2C Master Mode
Parameter SCP_CLK frequency1 SCP_CLK rise time SCP_CLK fall time SCP_CLK low time SCP_CLK high time SCP_CLK rising to SCP_SDA rising or falling for START or STOP condition START condition to SCP_CLK falling SCP_CLK falling to STOP condition Bus free time between STOP and START conditions Setup time SCP_SDA input valid to SCP_CLK rising Hold time SCP_SDA input after SCP_CLK falling SCP_CLK low to SCP_SDA out valid Symbol fiicck tiicr tiicf tiicckl tiicckh tiicckcmd tiicstscl tiicstp tiicbft tiicsu tiich Min 1.25 1.25 1.25 2.5 3 100 20 1.25 Max 400 150 150 Units kHz ns ns µs µs µs µs µs µs ns ns ns
EN D TI EL A L PH D I RA
tiicdov
tiicckl tiicr tiicf 6 7 8 0 1 6 7 tiicckh tiicdov 1/ fiicck A0 R/W ACK MSB LSB
1.fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application.
tiicckcmd 0 1
SCP_CLK
tiicstscl
FT
18
tiicckcmd 8 tiicstp ACK
tiicbft
SCP_SDA
A6
20
C
Copyright 2008 Cirrus Logic
O
N
FI
Figure 7. Serial Control Port - I2C Master Mode Timing
D
tiicsu
tiich
DS787A7
CS47048 Data Sheet Audio SOC Processor Family
5.13 Digital Switching Characteristics — Digital Audio Slave Input Port
Parameter DAI_SCLK period DAI_SCLK duty cycle Setup time DAI_DATAn Hold time DAI_DATAn Symbol Tdaiclkp tdaidsu tdaidh Min 20 45 8 5 Max 55 Unit ns % ns ns
DAI_SCLK tdaidsu DAI_DATAn tdaidh
Figure 8. Digital Audio Input (DAI) Port Timing Diagram
DS787A7
C
O
N
FI
D
EN D TI EL A L PH D I RA
Copyright 2008 Cirrus Logic 21
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CS47048 Data Sheet Audio SOC Processor Family
5.14 Digital Switching Characteristics — Digital Audio Output Port
Parameter DAO_MCLK period DAO_MCLK duty cycle DAO_SCLK period for Master or Slave mode1 DAO_SCLK duty cycle for Master or Slave mode1 Master Mode (Output A1 Mode)
1,2
Symbol Tdaomclk Tdaosclk tdaomsck tdaomlrts tdaomstlr tdaomdv tdaoslrts
Min 20 45 20 40 -
Max 55 60 19
Unit ns % ns % ns ns ns ns ns ns ns
DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an input DAO_LRCLK to DAO_SCLK non-active edge3, See Figure 9A. DAO_SCLK non-active edge3 to DAO_LRCLK, See Figure 9B DAO_DATA[3..0] delay from DAO_SCLK non-active Slave Mode (Output A0 DAO_SCLK non-active
.
edge3
DAO_LRCLK to DAO_SCLK non-active edge3, See Figure 10A. edge3
EN D TI EL A L PH D I RA
tdaosstlr tdaosdv
Mode)4
to DAO_LRCLK, See Figure 10B.
DAO1_DATA[3..0] delay from DAO_SCLK non-active edge3
1. Master mode timing specifications are characterized, not production tested.
2. Master mode is defined as the CS47048 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_LRCLK. 3. The DAO_LRCLK transition may occur on either side of the non-active edge of DAO_LRCLK. The active edge of DAO_SCLK is the point at which the data is valid. 4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
tdaomclk DAO_MCLK
tdaomclk
DAO_MCLK
D
tdaomsck
tdaomsck
DAO_SCLK
DAO_SCLK
FI
tdaomlrts
DAO_LRCLK
tdaomstlr
DAO_LRCLK
N
O
tdaomdv
DAO_DATAn
tdaomdv
C
DAO_DATAn
A. DAO_LRCLK transition before DAO_SCLK non-active edge. See Footnote 3 on page 22.
B. DAO_LRCLK transition after DAO_SCLK non-active edge. See Footnote 3 on page 22.
Figure 9. Digital Audio Output Port Timing, Master Mode
22
Copyright 2008 Cirrus Logic
FT
8 8 15 30 8
8
DS787A7
CS47048 Data Sheet Audio SOC Processor Family
tdaosclk D AO_SCLK tdaoslrts D AO_LRCLK tdaosdv D AOn_DATAn
A. DAO_LRCLK transition before DAO_SCLK non-active edge. See Footnote 3 on page 22.
t dao sclk D AO _SCLK t daosstlr DAO _LRC LK t d aosdv DAO _D ATAn
B. DAO_LRCLK transition after DAO_SCLK nonactive edge. See Footnote 3 on page 22.
Figure 10. Digital Audio Output Port Timing, Slave Mode
5.15 Digital Switching Characteristics — S/PDIF RX Port
(Inputs: Logic 0 = VIL, Logic 1 = VIH; CL = 20 pF) Parameter
EN D TI EL A L PH D I RA
Symbol Min 30 Typ Copyright 2008 Cirrus Logic
FT
Max 200 Units kHz
23
PLL Clock Recovery Sample Rate Range
DS787A7
C
O
N
FI
D
CS47048 Data Sheet Audio SOC Processor Family
5.16 ADC Characteristics
5.16.1 Analog Input Characteristics (Commercial)
(Test Conditions (unless otherwise specified): TA = 0 to +70°C; VDD = 1.8 V±5%, VDDA (VA)= 3.3 V±5%; 1 kHz sine wave driven through the passive input filter (Ri=10kΩ) in Figure 11 on page 26 or Figure 12 on page 26; DSP running test application; Measurement Bandwidth is 10 Hz to 20 kHz.)
Differential Parameter Fs= 96 kHz, 192 kHz Min Typ Max Min
Single-Ended Typ Max Unit
EN D TI EL A L PH D I RA
95 95 95 95 0.1 ±120 0.1 ±120 3.3•VA 3.5•VA 400 60 3.7•VA 200 20 Copyright 2008 Cirrus Logic
Total Harmonic Distortion + Noise6,7 -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB AIN_1A/B Interchannel Isolation AIN_[2..6]A/B MUX Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Input Full-Scale Input Voltage2,3 Differential Input Impedance4 Single-Ended Input Impedance5 Parasitic Load Capacitance (CL)9
-
-98 -82 -42 -90
-92 -
-
-95 -79 -39 -90
FT
-89 20
Dynamic Range1,6,7
A-weighted unweighted 40 kHz bandwidth unweighted
99 96 -
105 102 99
-
96 93
102 99 96
-
dB dB dB dB dB dB dB dB dB dB ppm/°C VPP
Ω Ω
1.65•VA 1.75•VA 1.85•VA
Common Mode Rejection Ratio (CMRR)8
dB pF
24
C
O
N
FI
D
DS787A7
CS47048 Data Sheet Audio SOC Processor Family
5.16.2 Analog Input Characteristics (Automotive)
(Test Conditions (unless otherwise specified): TA = -40 to +85°C; VDD = 1.8 V±5%, VDDA (VA)= 3.3 V±5%; 1 kHz sine wave driven through the passive input filter (Ri=10kΩ) in Figure 11 on page 26 or Figure 12 on page 26; DSP running test application; Measurement Bandwidth is 10 Hz to 20 kHz.)
Differential Parameter Fs=96 kHz, 192 kHz Min Typ Max Min
Single-Ended Typ Max Unit
Dynamic Range1,6,7
EN D TI EL A L PH D I RA
95 95 95 95 0.1 ±120 0.1 ±120 3.24•VA 3.5•VA 400 60 200 20 Copyright 2008 Cirrus Logic
Total Harmonic Distortion + Noise6,7 -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB AIN_1A/B Interchannel Isolation AIN_[2..6]A/B MUX Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Input Full-Scale Input Voltage2,3 Differential Input Impedance4 Single-Ended Input Impedance5 Parasitic Load Capacitance (CL)9 Notes:
-
-98 -82 -42 -90
-90 -
-
-95 -79 -39 -90
FT
-87 20
A-weighted unweighted 40 kHz bandwidth unweighted
97 94 -
105 102 99
-
94 91
102 99 96
-
dB dB dB dB dB dB dB dB dB dB ppm/°C VPP
Ω Ω
3.76•VA 1.62•VA 1.75•VA 1.88•VA
Common Mode Rejection Ratio (CMRR)8
dB pF
DS787A7
C
8. This number was measured using perfectly matched external resistors (Ri). Mismatch in the external resistors will typically reduce CMRR by 20 log (|ΔRi|/Ri + 0.001). 9. CL represents the parasitic load capacitance between Ri on the input circuit and the input pin of the CS47048 package.
O
7. Common mode input current should be kept to less than +/- 160uA to avoid performance degradation: |(Iip+Iin)/2| < 160uA. This corresponds to +/- 1.6V for Ri=10kΩ in the differential case.
N
4. Measured between AIN_xx+ and AN_xx-. 5. Measured between AIN_xx+ and AGND. 6. Decreasing Full-Scale voltage by reducing Ri will cause the noise floor to increase.
FI
3. The full-scale voltage can be changed be scaling Ri. Differential Full-Scale (Vpp) = (Ri+200)/(10k+200)*3.5*VDDA Single-Ended Full-Scale (Vpp) = (Ri+200)/(10k+200)*1.75*VDDA
D
1. dB units referred to the typical full-scale voltage. 2. These full-scale values were measured with Ri=10k for both the single-ended and differential mode input circuits.
25
CS47048 Data Sheet Audio SOC Processor Family
10µF AIN 100K Ri AIN_xA+ or AIN_xB+
CL
AIN-
AIN+
Figure 12. ADC Differential Input Test Circuit
26
C
O
N
FI
D
EN D TI EL A L PH D I RA
10µF Ri 100K CL AIN_xAor AIN_xB10µF Ri 100K CL AIN_xA+ or AIN_xB+
Copyright 2008 Cirrus Logic
FT
DS787A7
Figure 11. ADC Single-Ended Input Test Circuit
CS47048 Data Sheet Audio SOC Processor Family
5.16.3 ADC Digital Filter Characteristics
Parameter1, 2 Fs = 96 kHz, 192 kHz Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay High-Pass Filter Characteristics Frequency Response -3.0 dB -0.13 dB Phase Deviation @ 20 Hz Passband Ripple Filter Settling Time Min Typ Max Unit
to -0.1 dB corner
0 0.5688 70 -
12/Fs 1 20 10 5/Fs 10
0.4896 0.08 0 0
Fs dB Fs dB s Hz Hz Deg dB s
Notes:
1. Filter response is guaranteed by design. 2. Response is clock-dependent and will scale with Fs.
5.17 DAC Characteristics
5.17.1 Analog Output Characteristics (Commercial)
(Test Conditions (unless otherwise specified): TA = 0 to +70°C; VDD = 1.8V±5%, VDDA(VA) = 3.3V±5%; 1 kHz sine wave driven through a filter shown in Figure 13 on page 28 or Figure 14 on page 29; DSP running test application; Measurement Bandwidth is 20 Hz to 20 kHz.)
Differential Typ Single-Ended Typ Max
Parameter Fs = 96 kHz Dynamic Range
EN D TI EL A L PH D I RA
Min Max Min
FT
105 102 -95 -85 -45 95 0.68•VA 0.1 ±120 100 -87 TBD 10 100
Unit
DC Current draw from an AOUT pin1 AC-Load Resistance (RL)2 Load Capacitance (CL)2
C
A-weighted unweighted Total Harmonic Distortion + Noise 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz) Analog Output Full-Scale Output Interchannel Gain Mismatch Gain Drift Output Impedance
D
102 99 -
108 105 -98 -88 -48 95
-
99 96 -
dB dB dB dB dB dB VPP dB ppm/°C Ω μA kΩ pF
N
-90 TBD 10 100
FI
TBD 3 -
1.35•VA 0.1 ±120 100 -
TBD 3 -
DS787A7
O
Copyright 2008 Cirrus Logic
27
CS47048 Data Sheet Audio SOC Processor Family
5.17.2 Analog Output Characteristics (Automotive)
(Test Conditions (unless otherwise specified): TA = -40 to +85°C; VDD = 1.8V±5%, VDDA(VA) = 3.3V±5%; 1 kHz sine wave driven through a filter shown in Figure 13 on page 28 or Figure 14 on page 29; DSP running test application; Measurement Bandwidth is 20 Hz to 20 kHz.)
Differential Typ Single-Ended Typ Max
Parameter Fs = 96 kHz Dynamic Range
Min
Max
Min
Unit
EN D TI EL A L PH D I RA
TBD 3 1.35•VA 0.1 ±120 100 TBD 10 TBD 3 0.68•VA 0.1 ±120 100 100 3.3 µF 560 AOUT 2200pF CL RL 10k
Copyright 2008 Cirrus Logic
A-weighted unweighted Total Harmonic Distortion + Noise 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz) Analog Output Full-Scale Output Interchannel Gain Mismatch Gain Drift Output Impedance AC-Load Resistance (RL)2 Load Capacitance (CL)2 Notes:
100 97 -
108 105 -98 -88 -48 95
-90 -
97 94 -
105 102 -95 -85 -45 95
-87 -
dB dB dB dB dB dB VPP dB ppm/°C Ω μA kΩ pF
DC Current draw from an AOUT pin1
O
C
N
28
FI
AOUT_x+
D
1. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic DC-blocking capacitors. 2. Guaranteed by design. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL represents any capacitive loading that appears before the 560Ω series resistor (typically parasitic), and will effectively move the dominant pole of the two-pole amp in the output stage. Increasing this value beyond the recommended 100 pF can cause the internal op-amp to become unstable.
Figure 13. DAC Single-Ended Output Test Circuit
FT
TBD 10 100
DS787A7
CS47048 Data Sheet Audio SOC Processor Family
4.87k 1800pF 470pF 2.43k 953 1.96k
+
AOUT_xAOUT_x+ CL
4.87k 1.96k
+
560 AOUT
22µF 10k
CL 4700pF
+
22µF
1200pF
P output: RL = 1.96k + ( [2πF*4700-12 ]-1 || (1.96k + [2πF*22-6 ]-1 ) || (953 + [2πF*1200-12 ]-1 )) N output: RL = 4.87k + ( [2πF*1800-12 ]-1 || ((2.43k + [2πF*470-12 ]-1 ) || 4.87k ))
Figure 14. DAC Differential Output Test Circuit
125 Capacitive Load -- C L (pF) 100 75 50 25
FI
O
5.17.3 Combined DAC Interpolation & On-chip Analog Filter Response
Parameter Min Typ Max Unit
Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay
DS787A7
C
Passband (Frequency Response)
N
D
EN D TI EL A L PH D I RA
Safe Operating Region
2.5 3
5
10
15
20
Resistive Load -- RL (kΩ )
Figure 15. Maximum Loading
to 0.22 dB corner to -3 dB corner
0 0 -0.02 0.5465 100 -
10/Fs
FT
0.4125 0.4979 +0.02 Fs Fs dB Fs dB s
29
Copyright 2008 Cirrus Logic
CS47048 Data Sheet Audio SOC Processor Family
6. Ordering Information
The CS47048 DSP part numbers are described as follows:
CS47048I-XYZR
where
I - ROM ID Letter X - Product Grade Y - Package Type Z - Lead (Pb) Free
Table 4. Ordering Information
Part No. Grade Temp. Range
CS47048B-CQZ CS47048B-DQZ
NOTE: Please contact the factory for availability of the -D (automotive grade) package.
7. Environmental, Manufacturing, & Handling Information
Table 5. Environmental, Manufacturing, & Handling Information
Model Number Peak Reflow Temp MSL Rating*
CS47048B-CQZ CS47048B-DQZ
30
C
O
N
FI
D
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
EN D TI EL A L PH D I RA
Commercial Automotive 0 to +70 °C -40 to +85 °C
260 °C 3 Copyright 2008 Cirrus Logic
Max Floor Life
FT
Package
R - Tape and Reel Packaging
100-pin LQFP
7 days
DS787A7
CS47048 Data Sheet Audio SOC Processor Family
8. Device Pinout Diagram
8.1 CS47048, 100-Pin LQFP Pinout Diagram
AOUT_1+ AOUT_2+ AOUT_3+ AOUT_4+ AOUT_5+ AOUT_6+ AOUT_7+ AOUT_8+ AOUT_1AOUT_2AOUT_3AOUT_4AOUT_5AOUT_6AOUT_7100 RESET AOUT_876 75 VDD_DAC GND_DAC VDD_ADC_MON REXT 5 VQ 70 BIASREF_DAC GNDA3 GNDA7 GNDA6 GNDA5 GNDA4 VDDA7 VDDA6 VDDA5 VDDA4
95
90
85
DBCK DBDA GPIO15, DAI_LRCLK GPIO17, DAI_SCLK VDDIO1 GNDIO1 GPIO16, DAI_DATA0, TM0 GPIO0, DAI_DATA1, TM1 GPIO1, DAI_DATA2, TM2 GPIO2, DAI_DATA3, TM3, SPDIF RX VDD1 GND1 GPIO7, DAO_LRCLK GPIO14, DAO_SCLK GNDIO2 VDDIO2 GPIO18, DAO_MCLK, HS4 GPIO6, DAO_DATA0, HS0 GPIO3, DAO_DATA1, HS1 GPIO4, DAO_DATA2, HS2, S/PDIF TXb GPIO5, DAO_DATA3, HS3, S/PDIF TXa VDD2 GND2 GPIO9, SCP_MOSI GPIO10, SCP_MISO, SCP_SDA
1
80
EN D TI EL A L PH D I RA
CS47048
100-Pin LQFP
30 35 40 AIN_4B- 45 PLL_REF_RES XTAL_OUT AIN_4B+ XTO AIN_5BAIN_3BAIN_2BAIN_6B+ AIN_5B+ GPIO13, SCP_BSY, EE_CS GND_SUB GNDA_PLL VDDA_PLL
10
15
20
25 26
GPIO12, SCP_IRQ
GPIO8, SCP_CS, DAI_DATA4
GPIO11, SCP_CLK
N
9. 100-pin LQFP with Exposed Pad Package Drawing
DS787A7
C
Figure 17 shows the CS47048 100-pin LQFP package with exposed pad.
O
FI
D
Figure 16. CS47048 Pinout Diagram
Copyright 2008 Cirrus Logic
AIN_3B+
AIN_2B+
VDDIO3
GND3
VDD3
GNDIO3
AIN_6B-
XTI
50
FT
AIN_1A+ AIN_1AAIN_1B+ 65 AIN_1BVDDA3 VDDA2 GNDA2 60 AIN_2A+ AIN_2AAIN_3A+ AIN_3AAIN_4A+ 55 AIN_4AAIN_5A+ AIN_5AAIN_6A+ 51 AIN_6A-
BIASREF_ADC
31
CS47048 Data Sheet Audio SOC Processor Family
C
DS787A7
O
N
FI
D
R D AL H I TI LP EN E D
Copyright 2008 Cirrus Logic
Figure 17. 100-Pin LQFP Package Drawing
32
AF
T
CS47048 Data Sheet Audio SOC Processor Family
10. Parameter Definitions
10.1 Dynamic Range
The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
10.2 Total Harmonic Distortion + Noise
The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
10.3 Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels.
10.4 Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
10.5 Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
10.6 Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
10.7 Gain Drift
11. Revision History
Revision
N
FI
Date
D
The change in gain value with temperature. Units in ppm/°C.
A7
O
October 16, 2008
DS787A7
C
EN D TI EL A L PH D I RA
Changes
Initial Release
Copyright 2008 Cirrus Logic
FT
33
CS47048 Data Sheet Audio SOC Processor Family
34
C
O
N
FI
D
EN D TI EL A L PH D I RA
Copyright 2008 Cirrus Logic DS787A7
FT
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