CS48AU2B Data Sheet
FEATURES
World’s first cost-effective, high-performance 32-bit DSP that is solely dedicated to enable Audyssey Laboratories audio processing technologies for today’s high-volume consumer electronic products Features: Audyssey Dynamic VolumeTM, Audyssey Dynamic EQTM, Audyssey EQTM & Audyssey BassXTTM/BassXT-TVTM Audyssey Dynamic Volume eliminates the need for constant volume adjustments Audyssey Dynamic EQ enables a reference playback experience at any desired playback level Audyssey EQ removes much of the distortion caused by speaker enclosures and the typical room environment producing greatly improved sound compared to similar products without correction Audyssey BassXT and BassXT-TV are specifically calibrated to enhance the physical bass response of each product model Configurable Serial Audio Inputs/Outputs
— Maximum 32-bit @ 192 kHz (Note: Audyssey Laboratories algorithms support 48 kHz, 44.1 kHz and 32 kHz) — Integrated 192 kHz capable S/PDIF transmitter
The brand new CS48AU2B device is still based on the same high-performance 32-bit fixed point Digital Signal Processor core but instead is equipped with much less memory, tailoring it for more cost-effective applications which feature Audyssey Laboratories audio processing technologies. Target applications are:
— Digital Televisions — iPod® Docking Stations — Automotive Head Units (OEM and Aftermarket) — Automotive Outboard Amplifiers (OEM and Aftermarket) — Blu-ray® Disc Receivers — Soundbars / Sound Projectors
Integrated Clock Manager/PLL
— Can operate from external crystal, external oscillator
Input Fs Auto Detection & Coefficient Loading Host Control & Boot via Serial Interface Support for Master (Self) Boot via Serial EEPROM for single Fs applications (i.e. 48 kHz only via ADC input) Configurable GPIOs and External Interrupt Input 1.8V Core and a 3.3V I/O that is tolerant to 5V input Low-power Mode
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— “Energy Star® Ready” via low-power mode, 268 µW in standby
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Multichannel Audio In
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S/PD IF
Multichannel Audio O ut PLL
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Ordering Information: See page 21 for ordering information
Serial Control 1 GPIO Debug W atchdog 32-bit DSP P X Y D M A TM R1 TM R2
The following Audyssey Laboratories algorithms are currently supported on the CS48AU2B and more are in development:
While the individual Audyssey processing algorithms have already been implemented on this DSP, the CS48AU2B is programmed using the Cirrus proprietary DSP Composer™ GUI development tool. Processing chains combining both standard signal processing blocks (Tone Control, Bass Management, etc.) in combination with any combination of Audyssey Laboratories technology algorithm blocks may be designed using a simple drag-and-drop interface to create a custom signal flow specific to your product model. The end result of this is a software image that is down-loaded to the DSP via serial host (I2C® or SPITM ) or via a serial master (self) boot. Support for loading of the various Audyssey Laboratories algorithm coefficient files supplied by Audyssey Laboratories is easily supported via DSP Composer, enabling the OEM/ODM to quickly be able to generate the necessary files for the system microcontroller which have been custom tailored for each specific model based on the measurement and analysis performed by Audyssey Laboratories.
Copyright 2009 Cirrus Logic CONFIDENTIAL
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Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Audyssey, the Audyssey stylized logo and font, Audyssey Dynamic Volume, Audyssey Dynamic EQ, Audyssey EQ, and Audyssey BassXT ( implementations for both HTIB and TV) are either trademarks or registered trademarks of Audyssey Laboratories. Sale of the CS48AU2B is only authorized to licensees of Audyssey Laboratories deemed to be in good standing. SPI is a trademark of Motorola, Inc. I2C is a registered trademark of Philips Semiconductor. iPod is a registered trademark of Apple Computer, Inc. Blu-ray and Blu-ray Disc are trademarks of SONY KABUSHIKI KAISHA CORPORATION. Energy Star is a registered trademark of the Environmental Protection Agency, a federal agency of the United States government.
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
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Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
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Table of Contents
1. Documentation Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Code Overlays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. Hardware Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 On-chip DSP Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 DSP I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Application Code Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 9 9
5. Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8. Device Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.1 CS48AU2B, 48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9. Package Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.1 48-pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Digital DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Power Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5.5 Thermal Data (48-Pin LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5.6 Switching Characteristics— RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 Switching Characteristics — XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.8 Switching Characteristics — Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.10 Switching Characteristics — Serial Control Port - SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.11 Switching Characteristics — Serial Control Port - I2C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.12 Switching Characteristics — Serial Control Port - I2C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.13 Switching Characteristics — Digital Audio Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.14 Switching Characteristics — DSD Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.15 Switching Characteristics — Digital Audio Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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List of Figures
Figure 1. RESET Timing ......................................................................................................................................... 12 Figure 2. XTI Timing ............................................................................................................................................... 12 Figure 3. Serial Control Port - SPI Slave Mode Timing........................................................................................... 14 Figure 4. Serial Control Port - SPI Master Mode Timing......................................................................................... 15 Figure 5. Serial Control Port - I2C Slave Mode Timing ........................................................................................... 16 Figure 6. Serial Control Port - I2C Master Mode Timing ......................................................................................... 17 Figure 7. Digital Audio Input (DAI) Port Timing Diagram ........................................................................................ 17 Figure 8. Direct Stream Digital - Serial Audio Input Timing..................................................................................... 18 Figure 9. Digital Audio Output Port Timing, Master Mode....................................................................................... 19 Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) ............................................ 19 Figure 11. CS48AU2B, 48-Pin LQFP Pinout .......................................................................................................... 22 Figure 12. 48-Pin LQFP Package Drawing ............................................................................................................. 23
List of Tables
Table 1. CS48AU2B Related Documentation ........................................................................................................5 Table 2. Device and Firmware Selection Guide.....................................................................................................7 Table 3. Ordering Information ..............................................................................................................................20 Table 4. Environmental, Manufacturing, & Handling Information.........................................................................21
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1. Documentation Strategy
The CS48AU2B Data Sheet describes the CS48AU2B audio processor. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS48AU2B of processors.
Table 1. CS48AU2B Related Documentation
Document Name CS48AU2B Data Sheet CS485xx Hardware User’s Manual This document Includes detailed system design information including Typical Connection Diagrams, Boot-Procedures, Pin Descriptions, etc. Description
AN298 - CS485xx Firmware User’s Manual
DSP ComposerTM User’s Manual
AN298PPMQ, Audyssey Dynamic VolumeTM Audyssey Dynamic EQTM Firmware Module Application Note
AN298PPMR, Audyssey EQTM Firmware Module Application Note AN298PPMS, Audyssey BassXTTM Firmware Module Application Note
The scope of the CS48AU2B Data Sheet is primarily the hardware specifications of the CS48AU2B of devices. This includes hardware functionality, characteristic data, pinout, and packaging information. The intended audience for the CS48AU2B Data Sheet is the system PCB designer, MCU programmer, and the quality control engineer.
2. Overview
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2.1 Licensing
Licenses are required for any of the Audyssey Laboratories algorithms listed in Section 3. Please contact Audyssey Laboratories at sales@audyssey.com for more information on licensing their technology. Please send e-mail to trademark@audyssey.com for more information on Audyssey trademarks.
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The CS48AU2B DSP is designed to provide high-performance post-processing and mixing of digital audio. The low-power standby preserves battery life for applications which are always on, but not necessarily processing audio, such as automotive audio systems. The CS48AU2B is available in a 48-pin QFP package. Please refer to Table 2 on page 7 for the input, output and suggested applications for this device.
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Includes detailed firmware design information including signal processing flow diagrams and control API information for the operating system. Includes detailed configuration and usage information for the GUI development tool. Contains description of API used to control Audyssey Dynamic Volume and Audyssey Dynamic EQ firmware. Contains description of API used to control Audyssey EQ firmware. Contains description of API used to control Audyssey BassXT firmware. Copyright 2009 Cirrus Logic CONFIDENTIAL
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CS48AU2B Data Sheet Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
3. Code Overlays
The suite of software available for the CS48AU2B consists of an operating system (OS) and a library of overlays. The overlays have been divided into three main groups called Matrix-processors, Virtualizer-processors, and Post-processors. All software components are defined below: 1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-processing subroutines, error concealment, etc. 2. Matrix-processor- Any Module that performs a matrix decode on PCM data to produce more output channels than input channels (2 n channels). Generally speaking, these modules increase the number of valid channels in the audio I/O buffer. 3. Virtualizer-processor - Any module that encodes PCM data into fewer output channels than input channels (n 2 channels) with the effect of providing “phantom” speakers to represent the physical audio channels that were eliminated. Generally speaking, these modules reduce the number of valid channels in the audio I/O buffer. 4. Post-processors - Any module that processes audio I/O buffer PCM data in-place after the matrix- or virtualizer-processors. Examples are bass management, audio manager, tone control, Audyssey Dynamic Volume, Audyssey Dynamic EQ, Audyssey EQ, Audyssey BassXT, delay, & customer-specific effects, etc. The certified DSP firmware or application codes provided by Cirrus Logic (under a licensed to you from Audyssey Laboratories) may enable some or all of the Audyssey Laboratories algorithms. These licensed processing blocks can be used in combination with a host standard post-processing signal blocks (tone control, Bass Management, delays, etc.) or lower level primitives such as a filter or math function. A product-specific signal flow is generated by the designer using DSP Composer.
Once all of the custom coefficient files supplied by Audyssey Laboratories have been loaded and the signal flow has been set, the user can perform a “generate deliverables” inside DSP Composer. This generates a collection of files that can be easily converted to .c or .h files by the designer for storage inside the host controller OR can be converted into a small image that can either be stored in an external serial FLASH/EEPROM, or downloaded via a host controller through the SPI™/I2C® serial port. The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a new matrix-processor is selected, the OS, virtualizer-, and post-processors do not need to be reloaded — only the new matrix-processor (the same is true for the other overlays). Table 2 below lists the firmware available based on device selection. Please refer to AN298, CS485xx Firmware User’s Manual for the latest listing of application codes and Cirrus Framework™ modules available.
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Table 2. Device and Firmware Selection Guide
Device Suggested Application Digital TV Portable Audio Docking Station Portable DVD DVD Mini / Receiver Multimedia PC Speakers 8 Channel Car Audio DVD Receiver High-end Digital TV 12 channel Car Audio Channel Count Input/Output Package
CS48AU2B-CQZ
Up to 12 channel in /12 channel out
48-pin QFP
4. Hardware Functional Description
4.1 DSP Core
The CS48AU2B DSP is a single-core DSP with separate X and Y data and P code memory spaces. The DSP core is a high-performance, 32-bit, fully user-programmable, fixed-point DSP that is capable of performing two multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has eight 72-bit accumulators, four X- and four Y-data registers, and 12 index registers. The DSP core is coupled to a flexible DMA engine. The DMA engine can move data between peripherals such as the serial control port (SCP), digital audio input (DAI) and digital audio output (DAO), or any DSP core memory, all without the intervention of the DSP. The DMA engine off loads data move instructions from the DSP core, leaving more MIPS available for signal processing instructions. CS48AU2B functionality is controlled by DSP firmware or application codes that are downloaded to the CS48AU2B from a host controller or external serial FLASH/EEPROM. Users can develop their applications using DSP Composer to create the processing chain and then compile the image into a series of commands that are sent to the CS48AU2B through the SCP. The processing application can either load modules (matrix-processors, virtualizers, post-processors) from the DSPs on-board ROM, or custom firmware can be downloaded through the SCP. 4.1.1 DSP Memory
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4.1.2 DMA Controller The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment controls. The service intervals for each DMA channel, as well as up to 6 interrupt events, are programmable.
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The Y-RAM and P-RAM share a single block of memory that can be configured to make Y and P equal in size, or more memory can be allocated for Y-RAM in 2kword blocks.
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The DSP core has its own on-chip data and program RAM and ROM and does not require external memory for post-processing applications.
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4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI) The DAI port supports a wide variety of data input formats at sample rates (Fs) as high as 192 kHz. Up to 32-bit word lengths are supported. The DAI also supports a time division multiplexed (TDM) one-line data mode, that packs PCM audio on a single data line the total number possible depends on the ratio of SCLK to LRCLK. The CS48AU2B supports up to 8. The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, off-loading the task of monitoring the SPDIF receiver from the host. A timestamping feature allows the input data to be sample-rate converted via software. 4.2.2 Digital Audio Output Port (DAO)
DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as 192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or as a clock slave if an external MCLK or SCLK/LRCLK source is available. One of the serial audio pins can be re-configured as a SPDIF transmitter that drives a bi-phase encoded S/PDIF signal (data with embedded clock on a single line). The DAO also supports a time division multiplexed (TDM) one-line data mode, that packs multiple channels of PCM audio on a single data line. 4.2.3 Serial Control Port (I2C® or SPI™)
The on-chip serial control port is capable of operating as master or slave in either SPI™ or I2C® modes. Master/Slave operation is chosen by mode select pins when the CS48AU2B comes out of Reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode (SPI clock speed must always be ≤ (Fdclk/2)). The CS48AU2B serial control port also includes a pin for flow control of the communications interface (SCP_BSY) and a pin to indicate when the DSP has a message for the host (SCP_IRQ). 4.2.4 GPIO
4.2.6 Hardware Watchdog Timer The CS48AU2B has an integrated watchdog timer that acts as a “health” monitor for the DSP. The watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This peripheral ensures that the CS48AU2B will reset itself in the event of a temporary system failure. In stand-alone mode (that is, no host MCU), the DSP will reboot from external FLASH. In slave mode
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The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS48AU2B defaults to running from the external reference frequency and is switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.
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4.2.5 PLL-based Clock Generator
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Many of the CS48AU2B peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high.
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(that is, host MCU present) a GPIO will be used to signal the host that the watchdog has expired and the DSP should be rebooted and re-configured.
4.3 DSP I/O Description
4.3.1 Multiplexed Pins Many of the CS48AU2B pins are multi-functional. For details on pin functionality please refer to the CS485xx Hardware User’s Manual. 4.3.2 Termination Requirements Open-drain pins on the CS48AU2B must be pulled high for proper operation. Please refer to the CS485xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. Mode select pins in the CS48AU2B are used to select the boot mode upon the rising edge from reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS485xx Hardware User’s Manual. 4.3.3 Pads
The CS48AU2B I/Os operate from the 3.3 V supply and are 5 V tolerant.
4.4 Application Code Security
The external program code may be encrypted by the programmer to protect any intellectual property it may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device. Please contact your local Cirrus representative for details.
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CS48AU2B Data Sheet Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
5. Characteristics and Specifications
Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C, CL = 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.
5.1 Absolute Maximum Ratings
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0V) Parameter DC power supplies: Core supply PLL supply I/O supply |VDDA – VDDIO| Symbol VDD VDDA VDDIO Iin Min -0.3 -0.3 -0.3 -0.3 -0.3 -65 Max 2.0 3.6 3.6 0.3 Unit V V V V mA V V °C
Input pin current, any pin except supplies Input voltage on PLL_REF_RES Input voltage on I/O pins Storage temperature
Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
5.2 Recommended Operating Conditions
Parameter DC power supplies:
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0V) Core supply PLL supply I/O supply |VDDA – VDDIO|
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+/-10 3.6 5.0 Vfilt Vinio Tstg 150 Symbol VDD VDDA VDDIO TA Min Typ 1.8 3.3 3.3 0 Max 1.71 3.13 3.13 1.89 3.46 3.46 - CQZ - DQZ 0 -40 +70 +85 Symbol VIH VIL VILXTI Vhys VOH VOL ILXTI ILEAK VDDIO * 0.9 Min 2.0 Typ 0.4 VDDIO * 0.1 5 70 Max 0.8 0.6
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Unit V V V V °C
Ambient operating temperature
Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.
5.3 Digital DC Characteristics
Parameter
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(Measurements performed under static conditions.) Unit V V V V V V μA μA High-level input voltage
Low-level input voltage, except XTI Input Hysteresis
Low-level output voltage (IO = 2mA), except XTI Input leakage XTI Input leakage current (all digital pins with internal pull-up resistors enabled)
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High-level output voltage (IO = -2mA), except XTI
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Low-level input voltage, XTI
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5.4 Power Supply Characteristics
(Measurements performed under operating conditions) Parameter Operational Power Supply Current: VDD: Core and I/O operating1 VDDA: PLL operating VDDIO: With most ports operating Total Operational Power Dissipation: Standby Power Supply Current: VDD: Core and I/O not clocked VDDA: PLL halted VDDIO: All connected I/O pins 3-stated by other ICs in system Total Standby Power Dissipation:
1. Dependent on application firmware and DSP clock speed.
Min -
Typ 203 8 27 480
Max -
Unit mA mA mA mW
5.5 Thermal Data (48-Pin LQFP)
Parameter Junction Temperature
EN D TI EL A L PH D I RA FT
Symbol Tj Min Typ Max 125 -
-
100 1 50 348
-
μA μA μA μW
Unit °C
Thermal Resistance (Junction to Ambient) Two-layer Board1 Four-layer Board2 Thermal Resistance (Junction to Top of Package) Two-layer Board3 Four-layer Board4
θja
63.5 54 0.70 0.64
°C / Watt
ψ jt
°C / Watt
1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20 % of the top & bottom layers.
2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20 % of the top & bottom layers and 0.5-oz. copper covering 90 % of the internal power plane & ground plane layers. 3. To calculate the die temperature for a given power dissipation
4. To calculate the case temperature for a given power dissipation
Tc = Tj - [ (Power Dissipation in Watts) * ψ jt ]
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Tj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ]
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CS48AU2B Data Sheet Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
5.6 Switching Characteristics— RESET
Parameter RESET minimum pulse width low All bidirectional pins high-Z after RESET low Configuration pins setup before RESET high Configuration pins hold after RESET high Symbol Trstl Trst2z Trstsu Trsthld Min 1 50 20 Max 100 Unit ms ns ns ns
RESET
HS[3:0]
All Bidirectional Pins
5.7 Switching Characteristics — XTI
Parameter External Crystal operating XTI period XTI high time XTI low time frequency1
EN D TI EL A L PH D I RA FT
Trst2z Trstl Trstsu Trsthld
Figure 1. RESET Timing
Symbol Fxtal Tclki
Min
Max 27 100
Unit MHz ns ns ns pF Ω
11.2896 33.3 13.3 13.3 10 -
Tclkih Tclkil CL
External Crystal Load Capacitance (parallel
resonant)2
18
External Crystal Equivalent Series Resistance
D
ESR
50
1. Part characterized with +/- 50 PPM Crystal with the following frequency values:11.2896, 12.288, 18.432, 24.576, and 27 MHz. 2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals that require a CL outside this range should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer’s recommendation for load capacitor selection.
O C
N
XTI
t clkih Tclki
Figure 2. XTI Timing
FI
t clkil
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CS48AU2B Data Sheet Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
5.8 Switching Characteristics — Internal Clock
Parameter Internal DCLK frequency1 CS48AU2B-CQZ Internal DCLK period1 CS48AU2B-CQZ DCLKP Symbol Fdclk Min Fxtal 6.7 Max 150 ns 1/Fxtal Unit MHz
1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until the next power-on reset.
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CS48AU2B Data Sheet Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode.
Parameter SCP_CLK frequency SCP_CLK low time SCP_CLK high time Setup time SCP_MOSI input Hold time SCP_MOSI input SCP_CLK low to SCP_MISO output valid SCP_CLK falling to SCP_IRQ rising SCP_CS rising to SCP_IRQ falling SCP_CLK low to SCP_IRQ rising
1
Symbol fspisck tspicss tspickl tspickh tspidsu tspidh tspidov tspiirql tspiirqh tspicsh
Min 24 20 20 5 5 -
Typical
Max 25 11 20 -
Units MHz ns ns ns ns ns ns ns ns ns ns ns
SCP_CS falling to SCP_CLK rising
SCP_CS rising to SCP_MISO output high-Z SCP_CLK rising to SCP_BSY falling
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is Fxtal/3.
tspicss
SCP_CS
0
SCP_CLK
fspisck
tspidsu
FI
D
SCP_MOSI
A6
A5
SCP_MISO
N
SCP_IRQ
O
SCP_BSY
C
Figure 3. Serial Control Port - SPI Slave Mode Timing
14
EN D TI EL A L PH D I RA FT
0 24 tspicsdz 20 tspicbsyl 3*DCLKP+20
tspickl 1 2 6 7 0 5 6 7 tspicsh tspickh A0 R/W MSB LSB tspidh tspidov MSB tspiirqh LSB tspicsdz tspibsyl
Copyright 2009 Cirrus Logic CONFIDENTIAL
tspiirql
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5.10 Switching Characteristics — Serial Control Port - SPI Master Mode
Parameter SCP_CLK frequency
1 3
Symbol fspisck tspicss tspickl tspickh tspidsu tspidh tspidov tspicsl tspicsh tspicsx tspidz
Min 20 20 9 5 7 -
Typical 11*DCLKP + (SCP_CLK PERIOD)/2
Max Fxtal/2 8 2
Units MHz ns ns ns ns ns ns ns ns ns ns
SCP_CS falling to SCP_CLK rising SCP_CLK low time SCP_CLK high time Setup time SCP_MISO input Hold time SCP_MISO input
SCP_CLK low to SCP_MOSI output valid SCP_CLK low to SCP_CS falling SCP_CLK low to SCP_CS rising
Bus free time between active SCP_CS
SCP_CLK falling to SCP_MOSI output high-Z
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. 2. See Section 5.7.
3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter
tspicss
EE_CS
tspicsl 0
SCP_CLK
fspisck
D
FI
SCP_MISO
A6
tspidsu
SCP_MOSI
N
C
O
Figure 4. Serial Control Port - SPI Master Mode Timing
DS876F3
EN D TI EL A L PH D I RA FT
11*DCLKP + (SCP_CLK PERIOD)/2 3*DCLKP 20
tspicsx tspickl 1 2 6 7 0 5 6 7 tspicsh tspickh A5 A0 R/W tspidov MSB LSB MSB LSB tspidz tspidh
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CS48AU2B Data Sheet Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
5.11 Switching Characteristics — Serial Control Port - I2C Slave Mode
Parameter SCP_CLK frequency SCP_CLK low time SCP_CLK high time SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition START condition to SCP_CLK falling SCP_CLK falling to STOP condition Bus free time between STOP and START conditions Hold time SCP_SDA input after SCP_CLK falling SCP_CLK low to SCP_SDA out valid SCP_CLK falling to SCP_IRQ rising NAK condition to SCP_IRQ low SCP_CLK rising to SCB_BSY low
1
Symbol fiicck tiicckl tiicckh tiicckcmd tiicstscl tiicstp tiicbft tiicsu tiich
Min 1.25 1.25 1.25 1.25 2.5 3
Typical
Max 400 -
Units kHz µs µs µs
-
µs µs µs ns ns ns ns ns ns
Setup time SCP_SDA input valid to SCP_CLK rising
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer.
tiicckcmd 0 1
SCP_CLK
tiicstscl
EN D TI EL A L PH D I RA FT
100 20 tiicdov tiicirql 18 tiicirqh 3*DCLKP + 40 3*DCLKP + 20 tiicbsyl 3*DCLKP + 20
tiicckl tiicr tiicf tiicckcmd 6 7 8 0 1 6 7 8 tiicckh tiicdov fiicck tiicstp A0 R/W ACK MSB LSB ACK tiicirqh tiicirql tiiccbsyl
tiicbft
SCP_SDA
A6
SCP_IRQ
C
SCP_BSY
O
Figure 5. Serial Control Port - I2C Slave Mode Timing
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tiicsu tiich
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CS48AU2B Data Sheet Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
5.12 Switching Characteristics — Serial Control Port - I2C Master Mode
Parameter SCP_CLK frequency1 SCP_CLK low time SCP_CLK high time SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition START condition to SCP_CLK falling SCP_CLK falling to STOP condition Bus free time between STOP and START conditions Hold time SCP_SDA input after SCP_CLK falling SCP_CLK low to SCP_SDA out valid Symbol fiicck tiicckl tiicckh tiicckcmd tiicstscl tiicstp tiicbft tiicsu tiich Min 1.25 1.25 1.25 1.25 2.5 3 Max 400 Units kHz µs µs µs µs µs µs ns ns ns
Setup time SCP_SDA input valid to SCP_CLK rising
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application.
tiicckcmd 0 1
SCP_CLK
tiicstscl
tiicckh A6
EN D TI EL A L PH D I RA FT
100 20 tiicdov 18
tiicckl tiicr tiicf tiicckcmd 6 7 8 0 1 6 7 8 tiicdov fiicck tiicstp A0 R/W ACK MSB LSB ACK
tiicbft
SCP_SDA
tiicsu
tiich
Figure 6. Serial Control Port - I2C Master Mode Timing
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CS48AU2B Data Sheet Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
5.13 Switching Characteristics — Digital Audio Slave Input Port
Parameter DAI_SCLK period DAI_SCLK duty cycle Setup time DAI_DATAn Hold time DAI_DATAn Symbol Tdaiclkp tdaidsu tdaidh Min 40 45 10 5 Max 55 Unit ns % ns ns
DAI_SCLK
DAI_DATAn
Figure 7. Digital Audio Input (DAI) Port Timing Diagram
5.14 Switching Characteristics — DSD Slave Input Port
Parameter Symbol DSD_SCLK Pulse Width Low tsclkl DSD_SCLK Pulse Width High tsclkh DSD_SCLK Frequency (64x Oversampled) DSD_A / _B valid to DSD_SCLK rising setup time tsdlrs DSD_SCLK rising to DSD_A or DSD_B hold time tsdh
EN D TI EL A L PH D I RA FT
tdaidsu tdaidh
Min 78 78 1.024 20 20 Typ Max 3.2 Copyright 2009 Cirrus Logic CONFIDENTIAL
Unit ns ns MHz ns ns
C
Figure 8. Direct Stream Digital - Serial Audio Input Timing
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CS48AU2B Data Sheet Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
5.15 Switching Characteristics — Digital Audio Output Port
Parameter DAO_MCLK period DAO_MCLK duty cycle DAO_SCLK period for Master or Slave mode Master Mode (Output A1
1
Symbol Tdaomclk Tdaosclk tdaomsck tdaomstlr tdaomlrts tdaomdv
Min 40 45 40 40 -
Max 55 60 19 8 8
Unit ns % ns % ns ns ns ns
DAO_SCLK duty cycle for Master or Slave mode1 Mode)1,2 DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an input DAO_SCLK delay from DAO_LRCLK transition, DAO1_DATA[3..0], DAO2_DATA[1..0] delay from DAO_SCLK transition3
DAO_LRCLK delay from DAO_SCLK transition, respectively3 respectively3
Slave Mode (Output A0 Mode)4 DAO1_DATA[3..0], DAO2_DATA[1..0] delay from DAO_SCLK transition3
EN D TI EL A L PH D I RA FT
10 tdaosdv 15 30 15 tdaosstlr
3
ns ns ns
DAO_LRCLK delay from DAO_SCLK transition, respectively3 DAO_SCLK delay from DAO_LRCLK transition, respectively
tdaoslrts
1. Master mode timing specifications are characterized, not production tested.
2. Master mode is defined as the CS48DVxx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_LRCLK. 3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the data is valid. 4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
tdaomlclk DAO_MCLK
tdaomclk
DAO_MCLK
D
tdaomsck
tdaomsck
tdaomdv DAOn_DATAn
N
FI
tdaomlrts
DAO_SCLK
DAO_SCLK
DAOn_DATAn tdaomstlr DAO_LRCLK
DAO_LRCLK
C
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK
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CS48AU2B Data Sheet Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
Figure 9. Digital Audio Output Port Timing, Master Mode
tdaosstlr DAO_LRCLK DAO_SCLK tdaosclk DAOn_DATAn
DAO_SCLK tdaoslrts DAO_LRCLK
tdaosclk
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK
Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)
20
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tdaosdv
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6. Ordering Information
The CS48AU2B part number is described as follows:
CS48AU2I-XYZR
where I - ROM ID Number X - Product Grade Y - Package Type Z - Lead (Pb) Free R - Tape and Reel Packaging
Part No.
CS48AU2B-CQZ
NOTE: Please contact the factory for availability of the -D (automotive grade) package.
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Table 3. Ordering Information
Grade Temp. Range Package
Commercial
0 to +70 °C
48-pin LQFP
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7. Environmental, Manufacturing, & Handling Information
Table 4. Environmental, Manufacturing, & Handling Information
Model Number Peak Reflow Temp MSL Rating* Max Floor Life
CS48AU2B-CQZ
260 °C
3
7 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
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8. Device Pinout Diagram
8.1 CS48AU2B, 48-pin LQFP Pinout Diagram
GPIO6, DAO2 _DATA0, HS3 GPIO5, DAO1_DATA3, X MTA GPIO7, DAO2_D ATA1, HS4 GPIO3, DAO1_ DATA1, HS1 GPIO4, DAO1_ DATA2, HS2 GPIO10, SCP__MISO / SDA
35
31
30
28
26
34
32
29
27
25
36
33
GPIO18, DAO_MCLK
GPIO11, SCP_CLK
GPIO9, SCP_MOSI
GNDIO3
GND4
VDD2
VDDIO3
37
24
VDDIO2
GPIO8, SCP_CS
38
GPOI12, SCP_IRQ
39
GNDIO4
40
GPIO13, SCP_BSY , EE_CS
41
VDD3
42
XTAL_OUT
43
XTI
44
XTO
45
GNDA
46
PLL_REF_RES
47
D
VDDA (3.3V)
48 1 2
GPIO16, DAI1_DATA0, TM0, DSD0
GPIO0, DAI1_DATA1, TM1, DSD1
GNDIO1
O
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Figure 11. CS48AU2B, 48-Pin LQFP Pinout
Copyright 2009 Cirrus Logic CONFIDENTIAL
DAI1_LRCLK, DAI1_DATA4, DSD5
N
DAI1_SCLK, DSD-CLK
FI
RESET
VDDIO1
GND1
DBDA
DBCK
GND2
TEST
EN D TI EL A L PH D I RA FT
23 DAO_SCLK 22 GND3 21 DAO_LRCLK 20 DAO1_DAT A0, HS0
CS48AU2B
48-Pin LQFP
19
GNDIO2
18
GPIO15, DAI2_SCLK
17
GPIO14, DAI2_LRCLK
16
VDD1
15
GPIO17, DAI2_DATA0, DSD4
14
GPIO2, DAI1_DATA3, TM3, DSD3
13
GPIO1, DAI1_DATA2, TM2, DSD2
10
12
11
3
4
5
6
7
8
9
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CS48AU2B Data Sheet Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
9. Package Mechanical Drawings
9.1 48-pin LQFP Package Drawing
48 LD LQFP (7 x 7 x 1.4 mm body)
C
24
O
A A1 A2 b D D1 e E E1 theta L L1
Number of Leads 48 MIN NOM MAX 1.60 0.05 0.15 1.35 1.40 1.45 0.17 0.22 0.27 9.00 BSC 7.00 BSC 0.50 BSC 9.00 BSC 7.00 BSC 0 7 0.45 0.60 0.75 1.00 REF
N
NOTES: 1) Reference document: JEDEC MS-026 2) All dimensions are in millimeters and controlling dimension is in millimeters. 3) D1 and E1 do not include mold flash which is 0.25 mm max. per side.A1 4) Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.
FI
D
Figure 12. 48-Pin LQFP Package Drawing
EN D TI EL A L PH D I RA FT
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10. Revision History
Revision F1 F2 F3 Date December 2, 2008 February 16, 2009 May 27, 2009 Initial Release Updated Section 5.5, adding Junction Temperature specification. Updated Note 1 in Section 5.7. Changes
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