CS4953XX

CS4953xx Data Sheet FEATURES Multi-standard 32-bit Audio Decoding plus Post Processing Framework™ Applications Library in ROM — Dolby Digital® EX, Dolby® Pro Logic® IIx, Dolby Headphone®, Dolby® Virtual Speaker® — DTS-ES Matrix 6.1, DTS:Neo6™ — AAC™ Multichannel 5.1 — SRS® CS2® and TSXT® — — — — THX® Ultra2™, THX® ReEQ™ Cirrus Original Multi-Channel Surround (COMS) Crossbar Mixer, Signal Generator Advanced Post-Processor including: 7.1Bass Manager, Tone Control, 12- Band Parametric EQ, Delay, 1:2 Upsampler 96/24™, DTS-ES™ Discrete 6.1, DTS-ES™ 32-bit Audio Decoder DSP Family with Dual DSP Engine Technology Large On-chip X, Y, and Program RAM & ROM SDRAM and Serial Flash Memory Support The CS4953xx DSP family are the enhanced versions of the CS495xx DSP family with higher overall performance and lower system cost. The CS4953xx includes all mainstream audio processing codes in on-chip ROM. This saves external memory for code storage. In addition, the intensive decoding tasks of Dolby Digital® Surround EX®, AAC multi-channel, DTS-ES 96/24, THX Ultra2 Cinema and Dolby Headphone can be accomplished without the expense of external SDRAM memory. With larger internal memories than the CS495xx, the CS49531x is designed to support up to 150 ms per channel of lip-sync delay. With 150 MHz internal clock speed, the CS4953xx supports the most demanding post-processing requirements. It is also designed for easy upgrading. Customers currently using the CS495xx can upgrade to the CS4953xx with minor hardware and software changes. — Microsoft® HDCD® Framework™ Applications for Download — Thomson MP3 Surround — Internal DSD-to-PCM Conversion Up to 12 Channels of 32-bit Serial Audio Input 6 Channel DSD Input 16 Ch x 32-bit PCM Out with either two 192 kHz S/PDIF Tx (144-pin package) or one 192 kHz S/PDIF Tx (128-pin package) PR EL IM Serial Control 1 Serial Control 2 12 Ch. Audio In / 6 Ch. SACD In 32-bit DSP A X S/PDIF S/PDIF Two SPI™/I2C®, one Parallel and one UART Port Customer Software Security Keys IN AR Y Ordering Information Parallel Control UART GPIO D M A P 32-bit DSP B X Y Y Ext. Memory Controller See page 28 for ordering information. Debug STC TMR1 TMR2 P 16 Ch PCM Audio Out PLL Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright 2008 Cirrus Logic, SEP ’08 DS705PP3 http://www.cirrus.com CS4953xx Data Sheet 32-bit Audio Decoder DSP Family Table of Contents 1. Documentation Strategy ...........................................................................................................4 2. Overview ....................................................................................................................................4 2.1 Migrating from the CS495xx(2) to the CS4953xx ..................................................................................... 4 2.2 Licensing .................................................................................................................................................. 4 3. Code Overlays ...........................................................................................................................5 4. Hardware Functional Description ...........................................................................................7 4.1 DSP Core ................................................................................................................................................. 7 4.1.1 DSP Memory ...............................................................................................................................7 4.1.2 DMA Controller ............................................................................................................................7 4.2 On-chip DSP Peripherals ......................................................................................................................... 8 4.2.1 Digital Audio Input Port (DAI) .......................................................................................................8 4.2.2 Digital Audio Output Port (DAO) ..................................................................................................8 4.2.3 Serial Control Port 1 & 2 (I2C® or SPI™) .....................................................................................8 4.2.4 Parallel Control Port ....................................................................................................................8 4.2.5 External Memory Interface ..........................................................................................................8 4.2.6 GPIO ............................................................................................................................................8 4.2.7 PLL-based Clock Generator ........................................................................................................8 4.3 DSP I/O Description ................................................................................................................................. 8 4.3.1 Multiplexed Pins ..........................................................................................................................8 4.3.2 Termination Requirements ...........................................................................................................9 4.3.3 Pads ............................................................................................................................................9 4.4 Application Code Security ........................................................................................................................ 9 5. Characteristics and Specifications .......................................................................................10 5.1 Absolute Maximum Ratings .................................................................................................................... 10 5.2 Recommended Operating Conditions .................................................................................................... 10 5.3 Digital DC Characteristics ...................................................................................................................... 10 5.4 Power Supply Characteristics ................................................................................................................ 11 5.5 Thermal Data (144 LQFP) ...................................................................................................................... 11 5.6 Thermal Data (128 LQFP) ...................................................................................................................... 11 5.7 Switching Characteristics— RESET ....................................................................................................... 11 5.8 Switching Characteristics — XTI ............................................................................................................ 12 5.9 Switching Characteristics — Internal Clock ............................................................................................ 13 5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode. .................................................... 14 5.11 Switching Characteristics — Serial Control Port - SPI Master Mode ................................................... 15 5.12 Switching Characteristics — Serial Control Port - I2C Slave Mode ...................................................... 16 5.13 Switching Characteristics — Serial Control Port - I2C Master Mode .................................................... 17 5.14 Switching Characteristics — Parallel Control Port - Intel® Slave Mode .............................................. 18 5.15 Switching Characteristics — Parallel Control Port - Motorola® Slave Mode ....................................... 20 5.16 Switching Characteristics — UART ...................................................................................................... 22 5.17 Switching Characteristics — Digital Audio Slave Input Port ................................................................. 23 5.18 Switching Characteristics — DSD Slave Input Port ............................................................................ 24 5.19 Switching Characteristics — Digital Audio Output Port ........................................................................ 24 5.20 Switching Characteristics — SDRAM Interface .................................................................................... 25 PR EL IM 2 6. Ordering Information ..............................................................................................................28 7. Environmental, Manufacturing, and Handling Information ................................................28 8. Device Pinout Diagrams .........................................................................................................29 8.1 128-Pin LQFP Pinout Diagram ............................................................................................................... 29 8.2 144-Pin LQFP Pinout Diagram ............................................................................................................... 30 Copyright 2008 Cirrus Logic DS705PP3 IN AR Y CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 9. Package Mechanical Drawings ..............................................................................................31 9.1 128-pin LQFP Package Drawing ............................................................................................................ 31 9.2 144-Pin LQFP Package Drawing ............................................................................................................ 32 10. Revision History ....................................................................................................................33 List of Figures Figure 1. RESET Timing ........................................................................................................................................12 Figure 2. XTI Timing ..............................................................................................................................................12 Figure 3. Serial Control Port - SPI Slave Mode Timing ..........................................................................................14 Figure 4. Serial Control Port - SPI Master Mode Timing ........................................................................................15 Figure 5. Serial Control Port - I2C Slave Mode Timing ..........................................................................................16 Figure 6. Serial Control Port - I2C Master Mode Timing ........................................................................................17 Figure 7. Parallel Control Port - Intel® Mode Read Cycle ......................................................................................19 Figure 8. Parallel Control Port - Intel Mode Write Cycle ........................................................................................19 Figure 9. Parallel Control Port - Motorola® Mode Read Cycle Timing ...................................................................21 Figure 10. Parallel Control Port - Motorola Mode Write Cycle Timing ...................................................................21 Figure 11. UART Timing ........................................................................................................................................22 Figure 12. Digital Audio Input (DAI) Port Timing Diagram .....................................................................................23 Figure 13. Direct Stream Digital - Serial Audio Input Timing ..................................................................................24 Figure 14. Digital Audio Port Timing, MCLK Master Mode ....................................................................................25 Figure 15. External Memory Interface - SDRAM Burst Read Cycle .......................................................................26 Figure 16. External Memory Interface - SDRAM Burst Write Cycle .......................................................................26 Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle ....................................................................27 Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle ........................................................27 Figure 19. 128-Pin LQFP Pin-Out Drawing ............................................................................................................29 Figure 20. 144-Pin LQFP Pin-Out Drawing ............................................................................................................30 Figure 21. 128-Pin LQFP Package Drawing .........................................................................................................31 Figure 22. 144-Pin LQFP Package Drawing .........................................................................................................32 PR EL IM List of Tables DS705PP3 Table 1. CS4953xx Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. CS495303 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. CS495313 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6. Environmental, Manufacturing, and Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 7. 128-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 8. 144-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 IN AR Y Copyright 2008 Cirrus Logic 3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 1. Documentation Strategy The CS4953xx Datasheet describes the CS4953xx family of multichannel audio decoders. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS4953xx family of processors. Table 1. CS4953xx Related Documentation Document Name CS4953xx Datasheet CS4953xx Hardware User’s Manual This document Includes detailed system design information including Typical Connection Diagrams, Boot-Procedures, Pin Descriptions, Etc. Includes detailed firmware design information including signal processing flow diagrams and control API information Description AN288 - CS4953xx Firmware User’s Manual The intended audience for the CS4953xx Data Sheet is the system PCB designer, mcu programmer, and the quality control engineer. 2. Overview The CS4953xx DSP Family, together with Cirrus Logic’s comprehensive library of audio processing algorithms, enables the development of next-generation audio solutions. Cirrus Logic also provides a broad array of digital interface products, audio converters, and ARM® Processors to meet your audio system-level design requirements. There are two devices in the CS4953xx DSP family. The CS495303 and CS495313 are differentiated by internal memory size and DSP Firmware. The CS495303 is available in a 128-pin QFP package and the CS495313 is available in either a 128-pin or 144-pin QFP package. The audio processing features of the CS495313 are a superset of audio features available in the CS495303. Please refer to Table 2 on page 6 for the speed and firmware features of each device. PR EL IM • • • • • • 2.1 Migrating from the CS495xx(2) to the CS4953xx The CS4953xx was designed to provide an easy upgrade path from the CS495xx(2). Although 144-pin versions of the two devices are virtually identical with respect to external system connection, there are some small differences the hardware designer should be aware of: The PLL supply voltage on the CS4953xx is 3.3V vs. 1.8V on the CS495xx(2). The PLL filter topology is simpler when using the CS4953xx rather than the CS495xx(2). The CS4953xx adds support for 6-channel DSD input. The CS4953xx adds support for TDM mode on both audio input and output ports. The CS4953xx does not support external SRAM operation. The CS4953xx external SDRAM bus speed is fixed at 150 MHz vs. the 120 MHz max bus speed for the CS495xx(2). Some firmware modules also support a 75 MHz CS4953xx SDRAM bus speed. Please refer to AN288 for details. • The CS4953xx CLKOUT pin can output XTALI or XTALI/2. The CS495xx(2) can only output XTALI. 2.2 Licensing Licenses are required for all of the 3rd party audio decoding/processing algorithms listed below, including the application notes. Please contact your local Cirrus Sales representative for more information. 4 IN AR Y Copyright 2008 Cirrus Logic The scope of the CS4953xx Datasheet is primarily the hardware specifications of the CS4953xx family of devices. This includes hardware functionality, characteristic data, pinout, and packaging information. DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 3. Code Overlays The suite of software available for the CS4953xx family consists of an operating system (OS) and a library of overlays. The overlays have been divided into three main groups called Decoders, Mid-processors, and Postprocessors. All software components are defined below: 1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-processing subroutines, error concealment, etc. 2. Decoders - Any Module that initially writes data into the audio I/O buffers, e.g. AC-3®, DTS, PCM, etc. All the decoding/processing algorithms listed below require delivery of PCM or IEC61937-packed, compressed data via I2S- or LJ-formatted digital audio to the CS4953xx. 3. Mid-processors - Any module that processes audio I/O buffer PCM data in-place before the Postprocessors. Generally speaking, these modules alter the number of valid channels in the audio I/O buffer through processes like Virtualization (n 2 channels) or Matrix Decoding (2 n channels). Examples are Dolby ProLogic IIx and DTS Neo:6. 4. Post-processors - Any module that processes audio I/O buffer PCM data in-place after the Mid-Processors. Examples are Bass Management, Audio Manager, Tone Control, EQ, Delay, Customer-specific Effects, Dolby Headphone/Virtual Speaker, etc. The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a new decoder is selected, the OS, mid-, and post-processors do not need to be reloaded — only the new decoder (the same is true for the other overlays). Table 2 below lists the firmware available based on device selection. Please refer AN288 CS4953xx Firmware User’s Manual for the latest listing of application codes and Cirrus Framework™ modules available. PR EL IM DS705PP3 Copyright 2008 Cirrus Logic IN AR Y 5 DS705PP3 Device PreProcess Table 2. Device and Firmware Selection Guide1 Decode Processor A Mid-processor A Dolby PLIIx Stereo PCM Multi-Channel PCM (2:1 Down-sampling Option) Mid-processor B Post-processor B Circle Surround® II (Stereo In) Dolby Headphone Dolby Virtual Speaker APP (Advanced Post-processing) CS495303 300 MIPS N/A Dolby Digital AAC MP3 HDCD Cirrus Original MultiChannel Surround (Effects / Reverb Processor) Down-mix (Simultaneous Process) SRSTruSurround XT THX Select CS495313 (Superset of CS495303) 300 MIPS –Tone Control –Re-EQ –PEQ (up to 11 Bands) –Delay –7.1 Bass Manager –Audio Manager 1:2 Up-sampling Copyright 2008 Cirrus Logic 6 Lip Sync Delay Same as CS495303 + DTS DTS-ES DTS 96/24 Same as CS495303 + DTS Neo:6 (Stereo In) Same as CS495303 + THX Ultra2 1.This feature list is a snapshot of features available as of the publication date of this revision of the data sheet. More features may now be available. Check with your Cirrus Logic Field Application Engineer (FAE) to obtain the latest feature list for the CS495303 and CS495313 products. CS4953xx Data Sheet 32-bit Audio Decoder DSP Family CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 4. Hardware Functional Description 4.1 DSP Core The CS4953xx is a dual-core DSP with separate X and Y data and P code memory spaces. Each core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two memory access control (MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four X- and four Ydata registers, and 12 index registers. Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between peripherals such as the digital audio input (DAI) and digital audio output (DAO), external memory, or any DSP core memory, all without the intervention of the DSP. The DMA engine offloads data move instructions from the DSP core, leaving more MIPS available for signal processing instructions. CS4953xx functionality is controlled by application codes that are stored in on-board ROM or downloaded to the CS4953xx from a host mcu or external FLASH/EEPROM. Users can choose to use standard audio decoder and post-processor modules which are available from Cirrus Logic. 4.1.1 DSP Memory Each DSP core has its own on-chip data and program RAM and ROM and does not require external memory for any of today’s popular audio algorithms including Dolby Digital Surround EX, AAC Multichannel, DTS-ES 96/24, and THX Ultra2. The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words. Table 3. CS495303 DSP Memory Sizes Memory Type X Y P DSP A 16k SRAM, 16k ROM 8k SRAM, 32k ROM PR EL IM Memory Type X P DSP A Y 16k SRAM, 32k ROM Table 4. CS495313 DSP Memory Sizes DSP B 10k SRAM, 8k ROM 16k SRAM, 16k ROM 8k SRAM, 24k ROM 16k SRAM, 16k ROM 24k SRAM, 32k ROM 8k SRAM, 32k ROM 4.1.2 DMA Controller The powerful 12-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external memory; and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment controls. The service interval for each DMA channel as well as up to 6 interrupt events, is programmable. DS705PP3 IN AR Y DSP B 10k SRAM, 8k ROM 16k SRAM, 16k ROM 8k SRAM, 24k ROM Copyright 2008 Cirrus Logic The CS4953xx is suitable for Audio Decoder, Audio Post-processor, Audio Encoder, DVD Audio/Video Player, and Digital Broadcast Decoder applications. 7 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 4.2 On-chip DSP Peripherals 4.2.1 Digital Audio Input Port (DAI) The 12-channel (6 line) DAI port supports a wide variety of data input formats. The port is capable of accepting PCM, IEC61937, or DSD. Up to 32-bit word lengths are supported. Up to 6 channels of DSD are supported and internally converted to PCM before processing. The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which off-loads the task of monitoring the S/PDIF receiver from the host. A time-stamping feature allows the input data to be sample-rate converted via software. 4.2.2 Digital Audio Output Port (DAO) There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave mode, or the ratio of the two clocks can be set to even multiples of each other in master mode. The two ports can also be ganged together into a single clock domain. Each port has one serial audio pin that can be configured as a 192 kHz S/PDIF transmitter (data with embedded clock on a single line). Note: Only one S/PDIF transmitter pin is available in the 128-pin package. 4.2.3 Serial Control Port 1 & 2 (I2C® or SPI™) There are two on-chip serial control ports that are capable of operating as master or slave in either I2C or SPI modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external clock up to 50 MHz in SPI mode. It is present in both the 144- and 128-pin packages. This high clock speed enables very fast code download, control or data delivery. SCP2 defaults to master mode and is dedicated for booting from external serial Flash memory or for audio sub-system control. SCP2 does not include the SCP2_BSY# pin in the 128-pin package. 4.2.4 Parallel Control Port PR EL IM 4.2.5 External Memory Interface 4.2.6 GPIO 4.2.7 PLL-based Clock Generator The CS4953xx parallel port supports both Motorola® and Intel® interfaces. It can be used for both control and data delivery. The parallel port pins are multiplexed with serial control port 2 and are available in the 144-pin package. The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus. Many of the CS4953xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high. The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS4953xx defaults to running from the external reference frequency and can be switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external serial FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1. 4.3 DSP I/O Description 4.3.1 Multiplexed Pins Many of the CS4953xx pins are multi-functional. For details on pin functionality please refer to the CS4953xx Hardware User’s Manual. 8 Copyright 2008 Cirrus Logic DS705PP3 IN AR Y CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 4.3.2 Termination Requirements Open-drain pins on the CS4953xx must be pulled high for proper operation. Please refer to the CS4953xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. Mode select pins on the CS4953xx are used to select the boot mode upon the rising edge of reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS4953xx Hardware User’s Manual. 4.3.3 Pads The CS4953xx I/O operates from the 3.3 V supply and is 5V tolerant. 4.4 Application Code Security The external program code may be encrypted by the programmer to protect any intellectual property it may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device. PR EL IM DS705PP3 Copyright 2008 Cirrus Logic IN AR Y 9 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5. Characteristics and Specifications Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C, CL = 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V. 5.1 Absolute Maximum Ratings (GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Parameter DC power supplies: Symbol Core supply PLL supply I/O supply |VDDA – VDDIO| VDD VDDA VDDIO Iin Vfilt Vinio Tstg Min –0.3 –0.3 –0.3 -0.3 -0.3 –65 Max 2.0 3.6 3.6 0.3 +/- 10 3.6 5.0 150 Unit V V V V mA V V °C Input pin current, any pin except supplies Input voltage on PLL_REF_RES Input voltage on I/O pins Storage temperature CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 5.2 Recommended Operating Conditions Parameter DC power supplies: (GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Core supply PLL supply I/O supply |VDDA – VDDIO| IN AR Y Symbol VDD VDDA VDDIO TA Min Typ 1.8 3.3 3.3 0 Max 1.89 3.46 3.46 Unit V V V V °C 1.71 3.13 3.13 Ambient operating temperature PR EL IM 5.3 Digital DC Characteristics Parameter (Measurements performed under static conditions.) High-level input voltage Commercial Grade (CQZ/CVZ) Automotive Grade (DQZ/DVZ) 0 - 40 +25 +25 + 70 + 85 Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply. Symbol VIH VIL VILXTI Vhys VOH VOL VOH VOL IIN IIN-PU Min 2.0 VDDIO * 0.9 VDDIO * 0.9 - Typ 0.4 - Max 0.8 0.6 VDDIO * 0.1 VDDIO * 0.1 5 50 Unit V V V V V V V V μA μA Low-level input voltage, except XTI Low-level input voltage, XTI Input Hysteresis High-level output voltage (IO = -4mA), except XTI, SDRAM pins Low-level output voltage (IO = 4mA), except XTI, SDRAM pins SDRAM High-level output voltage (IO = -8mA) SDRAM Low-level output voltage (IO = 8mA) Input leakage current (all digital pins with internal pull-up resistors disabled) Input leakage current (all digital pins with internal pull-up resistors enabled, and XTI) 10 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.4 Power Supply Characteristics (measurements performed under operating conditions) Parameter Power supply current: Core and I/O operating: VDD1 PLL operating: VDDA With external memory and most ports operating: VDDIO 1. Dependent on application firmware and DSP clock speed. Min - Typ 500 3.5 120 Max - Unit mA mA mA 5.5 Thermal Data (144 LQFP) Parameter Thermal Resistance (Junction to Ambient) Symbol Two-layer Board1 Four-layer Board2 Min - Typ 48 40 .39 .33 Max - Unit °C / Watt θja ψjt Thermal Resistance (Junction to Top of Package) °C / Watt - Two-layer Board1 Four-layer Board2 5.6 Thermal Data (128 LQFP) Parameter Thermal Resistance (Junction to Ambient) IN AR Y Symbol Min - Typ 53 44 Max - Unit °C / Watt Two-layer Board1 Four-layer Board2 Thermal Resistance (Junction to Top of Package) θja ψjt °C / Watt - Two-layer Board1 Four-layer Board2 .45 .39 PR EL IM 2. 3. 4. 5. 6. Notes: 1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20 % of the top & bottom layers. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20 % of the top & bottom layers and 0.5-oz copper covering 90 % of the internal power plane and ground plane layers. To calculate the die temperature for a given power dissipation Τj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ] To calculate the case temperature for a given power dissipation Τc = Τj - [ (Power Dissipation in Watts) * ψ jt ] 5.7 Switching Characteristics— RESET Parameter Symbol Trstl Trst2z Trstsu Trsthld Min 1 50 20 Max 100 - Unit μs ns ns ns RESET# minimum pulse width low All bidirectional pins high-Z after RESET# low Configuration pins setup before RESET# high Configuration pins hold after RESET# high DS705PP3 Copyright 2008 Cirrus Logic 11 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family RESET# HS[3:0] All Bidirectional Pins Trst2z Trstl Trstsu Trsthld Figure 1. RESET Timing 5.8 Switching Characteristics — XTI Parameter External Crystal operating XTI period XTI high time XTI low time External Crystal Equivalent Series Resistance frequency1 IN AR Y Symbol Fxtal Tclki Min Max 27 100 18 50 Unit MHz ns ns ns pF W 11.2896 33.3 13.3 13.3 10 Tclkih Tclkil CL External Crystal Load Capacitance (parallel resonant)2 ESR 1. Part characterized with the following crystal frequency values: 11.2896, 12.288, 18.432, 24.576, & 27 MH.z. 2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside this range should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer’s recommendation for load capacitor selection. PR EL IM XTI t clkih 12 t clkil Tclki Figure 2. XTI Timing Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.9 Switching Characteristics — Internal Clock Parameter Internal DCLK frequency1 Symbol Fdclk Min Fxtal Fxtal Fxtal Fxtal Fxtal Fxtal Max 150 150 150 TBD TBD TBD Unit MHz CS49530x-CVZ CS49531x-CQZ CS49531x-CVZ CS49530x-DVZ CS49531x-DQZ CS49531x-DVZ Internal DCLK period1 DCLKP CS49530x-CVZ CS49531x-CQZ CS49531x-CVZ CS49530x-DVZ CS49531x-DQZ CS49531x-DVZ 6.7 6.7 6.7 TBD TBD TBD ns 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal 1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until the next power-on reset. PR EL IM DS705PP3 Copyright 2008 Cirrus Logic IN AR Y 13 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode. Parameter SCP_CLK frequency SCP_CLK low time SCP_CLK high time Setup time SCP_MOSI input Hold time SCP_MOSI input SCP_CLK low to SCP_MISO output valid SCP_CLK falling to SCP_IRQ# rising SCP_CS# rising to SCP_IRQ# falling SCP_CLK low to SCP_CS# rising SCP_CS# rising to SCP_MISO output high-Z SCP_CLK rising to SCP_BSY# falling 1 Symbol fspisck tspicss tspickl tspickh tspidsu tspidh tspidov tspiirqh tspiirql tspicsh tspicsdz tspicbsyl Min 24 20 20 5 5 0 24 - Typical Max 25 11 20 - Units MHz ns ns ns ns ns ns ns ns ns ns ns SCP_CS# falling to SCP_CLK rising 20 3*DCLKP+20 tspicss SCP_CS# 0 1 IN AR Y tspickl 2 6 7 0 5 6 7 tspickh A0 R/W tspidov MSB tspiirqh MSB Copyright 2008 Cirrus Logic 1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is Fxtal/3. tspicsh SCP_CLK fspisck PR EL IM SCP_MOSI A6 A5 tspidsu tspidh LSB tspicsdz LSB tspiirql SCP_MISO SCP_IRQ# tspibsyl SCP_BSY# Figure 3. Serial Control Port - SPI Slave Mode Timing 14 DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.11 Switching Characteristics — Serial Control Port - SPI Master Mode Parameter SCP_CLK frequency 1 3 Symbol fspisck tspicss tspickl tspickh tspidsu tspidh tspidov tspicsl tspicsh tspicsx tspidz Min 18 18 11 5 7 - Typical 11*DCLKP + (SCP_CLK PERIOD)/2 Max Fxtal 11 - Units MHz ns ns ns ns ns ns ns ns ns ns /22 SCP_CS# falling to SCP_CLK rising SCP_CLK low time SCP_CLK high time Setup time SCP_MISO input Hold time SCP_MISO input SCP_CLK low to SCP_MOSI output valid SCP_CLK low to SCP_CS# falling SCP_CLK low to SCP_CS# rising Bus free time between active SCP_CS# SCP_CLK falling to SCP_MOSI output high-Z 11*DCLKP + (SCP_CLK PERIOD)/2 3*DCLKP 20 1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. 2. See Section 5.8. 3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter . IN AR Y - tspicsx tspicss PR EL IM tspicsl tspickl 0 1 2 EE_CS# 6 7 0 5 6 7 tspicsh SCP_CLK fspisck tspickh SCP_MISO A6 A5 A0 R/W tspidov MSB LSB tspidz tspidsu tspidh SCP_MOSI MSB LSB Figure 4. Serial Control Port - SPI Master Mode Timing DS705PP3 Copyright 2008 Cirrus Logic 15 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.12 Switching Characteristics — Serial Control Port - I2C Slave Mode Parameter SCP_CLK frequency SCP_CLK low time SCP_CLK high time SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition START condition to SCP_CLK falling SCP_CLK falling to STOP condition Bus free time between STOP and START conditions Setup time SCP_SDA input valid to SCP_CLK rising Hold time SCP_SDA input after SCP_CLK falling SCP_CLK low to SCP_SDA out valid SCP_CLK falling to SCP_IRQ# rising NAK condition to SCP_IRQ# low SCP_CLK rising to SCB_BSY# low 1 Symbol fiicck tiicckl tiicckh tiicckcmd tiicstscl tiicstp tiicbft tiicsu tiich tiicdov tiicirqh tiicirql Min 1.25 1.25 1.25 1.25 2.5 3 100 20 - Typical Max 400 - Units kHz µs µs µs 18 3*DCLKP + 40 3*DCLKP + 20 3*DCLKP + 20 µs µs µs ns ns ns ns ns ns 1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of the input data buffer. tiicckcmd 0 1 tiicckl IN AR Y tiicbsyl tiicr tiicf 7 8 0 1 6 7 tiicdov fiicck R/W ACK MSB tiicirqh LSB tiicckcmd 8 6 SCP_CLK tiicstscl tiicckh tiicstp PR EL IM tiicbft SCP_SDA A6 A0 ACK tiicirql tiicsu tiich SCP_IRQ# tiiccbsyl SCP_BSY# Figure 5. Serial Control Port - I2C Slave Mode Timing 16 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.13 Switching Characteristics — Serial Control Port - I2C Master Mode Parameter SCP_CLK frequency SCP_CLK low time SCP_CLK high time SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition START condition to SCP_CLK falling SCP_CLK falling to STOP condition Bus free time between STOP and START conditions Setup time SCP_SDA input valid to SCP_CLK rising Hold time SCP_SDA input after SCP_CLK falling SCP_CLK low to SCP_SDA out valid 1 Symbol fiicck tiicckl tiicckh tiicckcmd tiicstscl tiicstp tiicbft tiicsu tiich tiicdov Min 1.25 1.25 1.25 1.25 2.5 3 100 20 - Max 400 - Units kHz µs µs µs 18 µs µs µs ns ns ns tiicckcmd 0 1 tiicckl IN AR Y tiicr tiicf 7 8 0 1 6 7 tiicdov fiicck R/W ACK MSB LSB Copyright 2008 Cirrus Logic 1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. tiicckcmd 8 6 SCP_CLK tiicstscl tiicckh A6 tiicstp tiicbft SCP_SDA A0 ACK PR EL IM tiicsu tiich DS705PP3 Figure 6. Serial Control Port - I2C Master Mode Timing 17 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.14 Switching Characteristics — Parallel Control Port - Intel® Slave Mode Parameter Address setup before PCP_CS# and PCP_RD# low or PCP_CS# and PCP_WR# low Address hold time after PCP_CS# and PCP_RD# low or PCP_CS# and PCP_WR# high Symbol Min tias tiah 5 5 Typical Max - Unit ns ns Read Delay between PCP_RD# then PCP_CS# low or PCP_CS# then PCP_RD# low Data valid after PCP_CS# and PCP_RD# low PCP_CS# and PCP_RD# low for read Data hold time after PCP_CS# or PCP_RD# high Data high-Z after PCP_CS# or PCP_RD# high PCP_CS# or PCP_RD# high to PCP_CS# and PCP_RD# low for next read1 PCP_CS# or PCP_RD# high to PCP_CS# and PCP_WR# low for next write1 PCP_RD# rising to PCP_IRQ# rising ticdr tidd tirpw tidhr tidis tird tirdtw 0 24 8 30 30 18 18 12 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Write Delay between PCP_WR# then PCP_CS# low or PCP_CS# then PCP_WR# low Data setup before PCP_CS# or PCP_WR# high PCP_CS# and PCP_WR# low for write Data hold after PCP_CS# or PCP_WR# high PCP_CS# or PCP_WR# high to PCP_CS# and PCP_RD# low for next read1 PR EL IM PCP_WR# rising to PCP_BSY# falling 18 PCP_CS# or PCP_WR# high to PCP_CS# and PCP_WR# low for next write1 1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent overflowing the input data buffer. AN288 CS4953xx Firmware Uses’s Manual should be consulted for the firmware speed limitations. IN AR Y tirdirqhl ticdw tidsu 0 8 8 tiwpw tidhw tiwtrd tiwd 24 30 30 tiwrbsyl 2*DCLKP + 20 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family PCP_A[3:0] t iah PCP_D[7:0] PCP_CS# t icdr PCP_WR# PCP_RD# tirdirqh PCP_IRQ# Figure 7. Parallel Control Port - Intel® Mode Read Cycle t ias t idd LSP MSP t idhr t idis t irpw t ird t irdtw PCP_A[3:0] t iah PCP_D[7:0] PCP_CS# t ias t icdw PCP_RD# PCP_WR# t iwpw IN AR Y LSP MSP t idhw t idsu t iwd t iwtrd PR EL IM PCP_BSY# DS705PP3 tiwrbsyl Figure 8. Parallel Control Port - Intel Mode Write Cycle Copyright 2008 Cirrus Logic 19 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.15 Switching Characteristics — Parallel Control Port - Motorola® Slave Mode Parameter Address setup before PCP_CS# and PCP_DS# low Address hold time after PCP_CS# and PCP_DS# low Symbol tmas tmah tmcdr tmdd tmrpw tmdhr tmdis tmrd tmrdtw Min 5 5 0 24 8 30 30 - Max 19 18 12 2*DCLKP + 20 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Read Delay between PCP_DS# then PCP_CS# low or PCP_CS# then PCP_DS# low Data valid after PCP_CS# and PCP_DS# low with PCP_R/W# high PCP_CS# and PCP_DS# low for read Data hold time after PCP_CS# or PCP_DS# high after read Data high-Z after PCP_CS# or PCP_DS# high after read PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for next read1 PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for next write1 PCP_RW# rising to PCP_IRQ# falling Write Delay between PCP_DS# then PCP_CS# low or PCP_CS# then PCP_DS# low Data setup before PCP_CS# or PCP_DS# high PCP_CS# and PCP_DS# low for write PCP_R/W# setup before PCP_CS# AND PCP_DS# low PCP_R/W# hold time after PCP_CS# or PCP_DS# high Data hold after PCP_CS# or PCP_DS# high PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low with PCP_R/W# high for next read1 PR EL IM PCP_RW# rising to PCP_BSY# falling 20 PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for next write1 1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent overflowing the input data buffer. AN288 CS4953xx Firmware Uses’s Manual should be consulted for the firmware speed limitations. IN AR Y tmrwirqh tmcdw tmdsu 0 8 tmwpw 24 24 8 8 tmrwsu tmdhw tmrwhld tmwtrd tmwd tmrwbsyl 30 30 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family HADDR[3:0] t mas HDATA[7:0] HEN HR/W HDS t mah LSP MSP t mdhr t mdd t mrwsu t mcdr t mrpw t mrd t mdis t mrdtw t mrwhld tmrwirqh HREQ Figure 9. Parallel Control Port - Motorola® Mode Read Cycle Timing HADDR[3:0] t mas HDATA[7:0] HEN tmah LSP t mdsu t mcdw HR/W HDS IN AR Y MSP t mdhw t mwpw t mrwhld t mwtrd PR EL IM t mrwsu HREQ DS705PP3 t mwd tmrwirql Figure 10. Parallel Control Port - Motorola Mode Write Cycle Timing Copyright 2008 Cirrus Logic 21 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.16 Switching Characteristics — UART Parameter UART_CLK period 1 Symbol tuclki tuckrxsu tuckrxdv tucktxdv ttxen ttxhz Min 266 40 5 5 ? ? Max 60 29 ? ? Unit ns % ns ns ns ns UART_CLK duty cycle Setup time for UART_RXD Hold time for UART_RXD Delay from CLK transition to TXD transition 1. The minimum clock period is limited to DCLKP/32 or the minimum value, whichever is larger. UART_TXD UART_RXD UART_TX_EN PR EL IM 22 IN AR Y tucktxdv ttxen ttxhz tuckrxsu tuckrxdv Figure 11. UART Timing UART_CLK Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.17 Switching Characteristics — Digital Audio Slave Input Port Parameter DAI_SCLK period DAI_SCLK duty cycle Setup time DAI_DATAn Hold time DAI_DATAn Symbol Tdaiclkp tdaidsu tdaidh Min 40 45 10 5 Max 55 - Unit ns % ns ns DAI_SCLK tdaidsu DAI_DATAn tdaidh Figure 12. Digital Audio Input (DAI) Port Timing Diagram PR EL IM DS705PP3 Copyright 2008 Cirrus Logic IN AR Y 23 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.18 Switching Characteristics — DSD Slave Input Port Parameter DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency (64x Oversampled) DSD_A / _B valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_A or DSD_B hold time DSD clock to data transition (Phase Modulation mode) Symbol tsclkl tsclkh tsdlrs tsdh tdpm Min 78 78 1.024 20 20 -20 Typ - Max 3.2 20 Unit ns ns MHz ns ns ns Figure 13. Direct Stream Digital - Serial Audio Input Timing 5.19 Switching Characteristics — Digital Audio Output Port PR EL IM Parameter IN AR Y Symbol Tdaomclk Tdaosclk tdaomsck tdaomstlr tdaomdv tdaosdv Min 40 40 40 40 - Max 60 60 19 8 10 15 Unit ns % ns % ns ns ns ns DAO_MCLK period1 DAO_MCLK duty cycle 1 DAO_SCLK period for Master or Slave mode2 Master Mode (Output A1 Mode)2,3 DAO_SCLK duty cycle for Master or Slave mode2 DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an input DAO_LRCLK delay from DAO_SCLK transition, respectively4 DAO_DATA[3:0] delay from DAO_SCLK Slave Mode (Output A0 Mode)5 transition4 DAO_DATA[3..0] delay from DAO_SCLK transition4 1. CS4953xx has two Digital Audio Output modules having similar signal names ending in 1 and 2. Both DAO ports share a common MCLK but have independent SCLKs and LRCLKs. 2. Master mode timing specifications are characterized, not production tested. 3. Master mode is defined as the CS4953xx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_LRCLK. 4. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the data is valid. 5.Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source. 24 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family Tdaomclk DAO_MCLK tdaomsck DAO_SCLK tdaomdv , tdaosdv DAO_DATAn tdaomstlr DAO_LRCLK tdaomstlr Figure 14. Digital Audio Port Timing, MCLK Master Mode 5.20 Switching Characteristics — SDRAM Interface Refer to Figure 15 through Figure 18. (SD_CLKOUT = SD_CLKIN) Parameter SD_CLKIN high time SD_CLKIN low time PR EL IM IN AR Y Symbol tsdclkh tsdclkl tsdclkrf tsdcmdv tsdcmdh tsddqv tsddqh tsddsu tsddh tsdav 1.38 1.3 1.38 3.8 Min 2.3 2.3 - Typical Max 1 Unit ns ns ns MHz % ns ns ns ns ns ns ns SD_CLKOUT rise/fall time SD_CLKOUT Frequency SD_CLKOUT duty cycle 150 45 1.1 3.8 55 3.8 - SD_CLKOUT rising edge to signal valid Signal hold from SD_CLKOUT rising edge SD_CLKOUT rising edge to SD_DQMn valid SD_DQMn hold from SD_CLKOUT rising edge SD_DATA valid hold to SD_CLKIN rising edge SD_DATA valid setup to SD_CLKIN rising edge SD_CLKOUT rising edge to ADDRn valid DS705PP3 Copyright 2008 Cirrus Logic 25 DS705PP3 Copyright 2008 Cirrus Logic 26 SD_CLKOUT tsdcmdv SD_CS# tsdcmdh tsdclkrf SD_RAS# SD_CAS# SD_WE# SD_DQMn tsddqv 00 tsddqh 11 SD_An tsdav CAS=2 SD_Dn tsddsu tsddh LSP0 MSP0 LSP1 MSP1 LSP2 MSP2 LSP3 MSP3 SD_CLKIN tsdclkl tsdclkh Figure 15. External Memory Interface - SDRAM Burst Read Cycle SD_CLKOUT tsdcmdv SD_CS# tsdcmdh SD_RAS# SD_CAS# CS4953xx Data Sheet 32-bit Audio Decoder DSP Family SD_WE# SD_Dn LSP0 MSP0 LSP1 MSP1 LSP2 MSP2 LSP3 MSP3 tsdav SD_An SD_DQMn 00 11 tsddqv tsddqh Figure 16. External Memory Interface - SDRAM Burst Write Cycle CS4953xx Data Sheet 32-bit Audio Decoder DSP Family SD_CLKOUT tsdcmdv SD_CS tsdcmdv tsdcmdh SD_RAS SD_CAS SD_WE SD_DQMn SD_ADDRn SD_DATAn Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle SD_CLKOUT PR EL IM tsdcmdv SD_CS SD_RAS SD_CAS SD_WE SD_DQMn SD_ADDRn SD_DATAn DS705PP3 Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle IN AR Y tsdcmdh OPCODE Copyright 2008 Cirrus Logic 27 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 6. Ordering Information The CS4953xx family part number is described as follows: CS495NNI-XYZ where NN - Product Number Variant I - ROM ID Number X - Product Grade Y - Package Type Z - Lead (Pb) Free Table 5. Ordering Information Part No. IN AR Y Grade Temp. Range Package CS495303-CVZ CS495303-DVZ CS495313-CQZ CS495313-DQZ CS495313-CVZ CS495313-DVZ Commercial Automotive 0 to +70 °C -40 to +85 °C 0 to +70 °C 128-pin LQFP 144-pin LQFP Commercial Automotive Commercial Automotive -40 to +85 °C 0 to +70 °C -40 to +85 °C 128-pin LQFP Note: Please contact the factory for availability of the -D (automotive grade) package. PR EL IM Model Number 7. Environmental, Manufacturing, and Handling Information Table 6. Environmental, Manufacturing, and Handling Information Peak Reflow Temp MSL Rating* Max Floor Life CS495303-CVZ CS495303-DVZ CS495313-CQZ CS495313-DQZ CS495313-CVZ CS495313-DVZ 260 °C 3 7 Days * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 28 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 8. Device Pinout Diagrams 8.1 128-Pin LQFP Pinout Diagram GPIO37, SCP1_BSY#, PCP_BSY# GPIO34, SCP1__MISO / SDA GPIO33, SCP1_MOSI GPIO35, SCP1_CLK SD_BA1, EXT_A14 SD_BA0, EXT_A13 110 SD_CS# RESET# GPIO38, PCP_WR# / DS#, SCP2_CLK GPIO11, PCP_A3, AS#, SCP2_MISO / SDA GPIO10, PCP_A2 / A10, SCP2_MOSI GPOI9, SCP1_IRQ# GPIO8, PCP_IRQ#, SCP2_IRQ# GPIO7, SCP1_CS#, IOWAIT 1 105 GNDIO5 120 VDDIO6 115 GND5 125 VDD6 SD_A10, EXT_A10 EXT_CS1# SD_RAS# SD_CAS# EXT_OE# EXT_A19 EXT_A18 EXT_A17 EXT_A16 EXT_A15 SD_WE# GNDIO6 GND6 VDD5 SD_A0, EXT_A0 SD_A1, EXT_A1 100 VDDIO5 SD_A2, EXT_A2 5 GND4 SD_A3, EXT_A3 IN AR Y 128-Pin LQFP DAO_MCLK 40 GND1 45 GPIO23, DAO2_LRCLK GPIO17, DAO1_DATA3 / XMTA VDDIO1 50 VDD2 55 DAO1_DATA0, HS0 SD_D5, EXT_D5 60 VDD1 GNDIO1 GND2 SD_DQM0 SD_D7, EXT_D7 SD_D6, EXT_D6 SD_D4, EXT_D4 VDDIO2 SD_D3, EXT_D3 GPIO16, DAO1_DATA2, HS2 GPIO15, DAO1_DATA1, HS1 GPIO22, DAO2_SCLK GPIO19, DAO2_DATA1, HS4 GPIO6, PCP_CS#, SCP2_CS# VDDIO7 GNDIO7 GPIO3, DDAC 10 GPIO2, UART_TXD VDD7 GPIO1, UART_RXD GPIO0, UART_CLK GND7 15 XTAL_OUT XTI XTO GNDA PLL_REF_RES 20 VDDA (3.3V) VDD8 GPIO14, DAI1_DATA3, TM3, DSD3 SD_A4, EXT_A4 95 VDD4 EXT_CS2# SD_A5, EXT_A5 GNDIO4 SD_A6, EXT_A6 90 SD_A7, EXT_A7 VDDIO4 SD_A8, EXT_A8 SD_A9, EXT_A9 GND3 85 SD_A11, EXT_A11 SD_A12, EXT_A12 VDD3 SD_CLKEN SD_CLKIN 80 SD_CLKOUT SD_DQM1 SD_D8, EXT_D8 SD_D9, EXT_D9 GNDIO3 75 SD_D10, EXT_D10 SD_D11, EXT_D11 VDDIO3 SD_D12, EXT_D12 SD_D13, EXT_D13 70 SD_D14, EXT_D14 SD_D15, EXT_D15 SD_D0, EXT_D0 GNDIO2 EXT_WE# 65 SD_D1, EXT_D1 PR EL IM GPIO13, DAI1_DATA2, TM2, DSD2 GND8 25 GPIO12, DAI1_DATA1, TM1, DSD1 DAI1_DATA0, TM0, DSD0 VDDIO8 DAI1_SCLK, DSD-CLK DAI1_LRCLK, DSD4 30 GNDIO8 GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY# GPIO43, BDI_CLK, DAI2_SCLK BDI_DATA, DAI2_DATA, DSD5 GPIO26, DAO2_DATA3 / XMTB/UART_TX_EN 35 DBDA DBCK GPIO20, DAO2_DATA2, EE_CS# TEST Figure 19. 128-Pin LQFP Pin-Out Drawing DS705PP3 Copyright 2008 Cirrus Logic GPIO18, DAO2_DATA0, HS3 SD_D2, EXT_D2 DAO1_SCLK DAO1_LRCLK 29 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 8.2 144-Pin LQFP Pinout Diagram 105 GPIO11, PCP_A3, AS#, SCP2_MISO / SDA GPIO38, PCP_WR# / DS#, SCP2_CLK GPIO10, PCP_A2 / A10, SCP2_MOSI 108 GPIO41, PCP_IRQ#, SCP2_IRQ# GPIO37, SCP1_BSY#, PCP_BSY# GPIO39, PCP_CS#, SCP2_CS# GPIO34, SCP1__MISO / SDA GPIO40, PCP_RD# / RW# GPIO32, SCP1_CS#, IOWAIT 100 GPOI36, SCP1_IRQ# 95 GPIO33, SCP1_MOSI GPIO35, SCP1_CLK 75 SD_BA0, EXT_A13 90 EXT_CS1# 80 SD_RAS# 85 EXT_A17 SD_CAS# 94 GNDIO6 SD_WE# SD_BA1, EXT_A14 GPIO30, XMTB_IN EXT_OE# EXT_A19 EXT_A18 EXT_A16 EXT_A15 76 GNDIO5 RESET# SD_CS# SD_A10, EXT_A10 101 GND6 73 VDDIO5 72 SD_A0, EXT_A0 SD_A1, EXT_A1 70 SD_A2, EXT_A2 69 GND4 SD_A3, EXT_A3 SD_A4, EXT_A4 66 VDD4 65 EXT_CS2# SD_A5, EXT_A5 63 GNDIO4 SD_A6, EXT_A6 SD_A7, EXT_A7 60 VDDIO4 SD_A8, EXT_A8 SD_A9, EXT_A9 57 GND3 SD_A11, EXT_A11 55 SD_A12, EXT_A12 54 VDD3 SD_CLKEN SD_CLKIN SD_CLKOUT 50 SD_DQM1 SD_D8, EXT_D8 SD_D9, EXT_D9 47 GNDIO3 SD_D10, EXT_D10 45 SD_D11, EXT_D11 44 VDDIO3 SD_D12, EXT_D12 SD_D13, EXT_D13 SD_D14, EXT_D14 40 SD_D15, EXT_D15 SD_D0, EXT_D0 EXT_WE# 37 SD_D1, EXT_D1 GNDIO2 36 91 VDDIO6 86 GND5 GPIO9, PCP_A1 / A9 109 GPIO8, PCP_A0 / A8 110 GPIO7, PCP_AD7 / D7 GPIO6, PCP_AD6 / D6 VDDIO7 113 GPIO5, PCP_AD5 / D5 GPIO4, PCP_AD4 / D4 115 GNDIO7 116 GPIO3, PCP_AD3 / D3 GPIO2, PCP_AD2 / D2 VDD7 119 GPIO1, PCP_AD1 / D1 120 GPIO0, PCP_AD0 / D0 GND7 122 XTAL_OUT XTI XTO 125 GNDA 126 NC PLL_REF_RES VDDA (3.3V) 129 VDD8 130 GPIO14, DAI1_DATA3, TM3, DSD3 GPIO13, DAI1_DATA2, TM2, DSD2 GND8 133 GPIO12, DAI1_DATA1, TM1, DSD1 DAI1_DATA0, TM0, DSD0 135 VDDIO8 136 DAI1_SCLK, DSD-CLK DAI1_LRCLK, DSD4 GNDIO8 139 PR EL IM GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY# 140 GPIO43, BDI_CLK, DAI2_SCLK GPIO27 BDI_DATA, DAI2_DATA, DSD5 GPIO26 144 VDD1 10 1 5 GPIO20, DAO2_DATA2, EE_CS# GPIO28, DDAC GPIO29, XMTA_IN 9 DBDA DBCK GPIO21, DAO2_DATA3 / XMTB, UART_TX_ENABLE TEST GPIO19, DAO2_DATA1, HS4 DAO_MCLK GND1 13 GPIO17, DAO1_DATA3 / XMTA 15 VDDIO1 18 GNDIO1 21 VDD2 24 GPIO25, UART_TXD 25 GND2 27 SD_D6, EXT_D6 30 IN AR Y 144-Pin LQFP VDDIO2 33 GPIO23, DAO2_LRCLK GPIO22, DAO2_SCLK GPIO16, DAO1_DATA2, HS2 GPIO18, DAO2_DATA0, HS3 GPIO15, DAO1_DATA1, HS1 DAO1_DATA0, HS0 83 VDD5 98 VDD6 Figure 20. 144-Pin LQFP Pin-Out Drawing 30 Copyright 2008 Cirrus Logic GPIO24, UART_RXD GPIO31, UART_CLK SD_D2, EXT_D2 35 SD_DQM0 SD_D7, EXT_D7 SD_D5, EXT_D5 SD_D4, EXT_D4 SD_D3, EXT_D3 DAO1_LRCLK DAO1_SCLK DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 9. Package Mechanical Drawings 9.1 128-pin LQFP Package Drawing D D1 E E1 1 e ∝ b IN AR Y INCHES MAX MIN NOM NOM A A1 L PR EL IM DIM MIN Figure 21. 128-Pin LQFP Package Drawing Table 7. 128-Pin LQFP Package Characteristics MILLIMETERS MAX A A1 b D D1 E E1 e q L L1 --0.05 0.17 0° 0.45 ----0.22 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.50 BSC 3.5 0.60 1.00 REF 0.08 1.60 0.15 0.27 --.002” .007” 7° 0.75 0° .018” ----.009” .866” .787” .630” .551” .020” 3.5 .024” .039” REF .003” .063” .006” .011” 7° .030” TOLERANCES OF FORM AND POSITION ddd DS705PP3 Copyright 2008 Cirrus Logic 31 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 9.2 144-Pin LQFP Package Drawing E E1 D D1 Notes: 1. Controlling dimension is millimeter. 2. Dimensioning and tolerancing per ASME Y14.5M1994. IN AR Y b ddd M B e SEATING PLANE B L1 A A1 θ L PR EL IM DIM MIN NOM Figure 22. 144-Pin LQFP Package Drawing Table 8. 144-Pin LQFP Package Characteristics MILLIMETERS MAX MIN INCHES NOM MAX A A1 b D D1 E E1 e q L L1 --0.05 0.17 0° 0.45 ----0.22 22.00 BSC 20.00 BSC 22.00 BSC 20.00 BSC 0.50 BSC --0.60 1.00 REF 0.08 1.60 0.15 0.27 --.002” .007” 7° 0.75 0° .018” ----.009” .866” .787” .866” .787” .020” --.024” .039” REF .003” .063” .006” .011” 7° .030” TOLERANCES OF FORM AND POSITION ddd 32 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 10. Revision History Revision A1 A2 A3 Date FEB 2006 JUN 2006 JUL 2006 Advance release. Changes Updated part numbers for ordering (Tables 5 & 6), Updated VOH and VOL specification to include the current load used for testing Updated part numbers for ordering (Tables 5 &6). Updated text in sections 3 and 4. Updated parameter descriptions in sections 5.1 and 5.3. Updated Tspickl, Tspickh, and Tspidov timing. Corrected Figure SPI Master Timing to use EE_CS#. Added footnote to XTI table. Removed SCLK/LRCLK relative timing from DAI port timing. Removed SCLK/LRCLK slave relative timing from DAO port timing. Updated the Tspidsu, Tspickl, and Tspickh timing parameters for master mode SPI. This applies to both SPI ports. Updated product feature list in Table 2. Updated Figure 19 and Figure 20. Added typical crystal frequency values in Table Footnote 1 and Max and Min values of Fxtalin Section 5.8. Removed DSD Phase Modulation Mode from Section 5.18. Removed reference to MCLK in Section 5.18. Redefined Master mode clock speed for SCP_CLK in Section 5.11.. Redefined DC leakage characterization data in Section 5.3, correcting units of measurement. Modified Footnote 1 under Section 5.10. Removed references to External Parallel Flash / SRAM Interface. A4 PP1 PP2 OCT 2007 May 28, 2008 June 20, 2008 PP3 September 24, 2008 PR EL IM DS705PP3 Copyright 2008 Cirrus Logic IN AR Y 33 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com. IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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Microsoft and Windows Media are registered trademarks of Microsoft Corporation. The product includes technology owned by Microsoft Corporation and cannot be used or distributed without a license from Microsoft Licensing, Inc. , HDCD, High Definition Compatible Digital and Pacific Microsonics Inc. are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. HDCD technology provided under license from Microsoft Corporation. The product's design (and/or software) is covered by one or more of the following: 5,479,168; 5,638,074; 5,640,161; 5,808,574; 5,838,274; 5,854,600; 5,864,311; 5,872,531 with other patents pending. Supply of this product does not convey a license under the relevant intellectual property of Thomson multimedia and/or Fraunhofer Gesellschaft nor imply any right to use this product in any finished end user or ready-to-use final product. An independent license for such use is required. For details, please visit http://www.mp3licensing.com. 34 IN AR Y Copyright 2008 Cirrus Logic DS705PP3