CS5334-KS

CS5334 CS5335 20-Bit, Stereo A/D Converter for Digital Audio Features General Description The CS5334 and CS5335 are 2-channel, single +5V supply, pin compatable analog-to-digital converters for digital audio systems. The CS5334 and CS5335 perform sampling, analog-to-digital conversion and anti-alias filtering, generating 20-bit values for both left and right inputs in serial form. The output word rate can be up to 50 kHz per channel. The CS5334 and CS5335 use 4th-order, delta-sigma modulation with 128X oversampling followed by digital filtering and decimation, which removes the need for an external anti-alias filter. These ADCs use a differential architecture which provides excellent noise rejection. The CS5334 and CS5335 have a filter passband to 21.7kHz. The filter has linear phase, 0.0025 dB passband ripple, and >85 dB stopband rejection. An on-chip high pass filter is also included to remove DC offsets. ORDERING INFORMATION: Model Temp. Range Package Type CS5334-KS -10° to 70°C 20-pin Plastic SSOP CS5335-KS -10° to 70°C 20-pin Plastic SSOP MCLK 18 • • CS5335 Range: Dynamic CS5334 Dynamic Range: 100 dB THD+N: -90 dB 105 dB • 128X Oversampling • Fully Differential Inputs Digital Anti-Alias Filtering • Linear Phasepassband (fs = 48kHz) 21.7 kHz • High Pass Filter - DC offset removal • Peak Signal Level Detector Graph Modes High Resolution and Bar VA+ THD+N: -95 dB 85 dB stop band attenuation 0.0025 dB pass band ripple VD+ 3 6 RST OVFL 2 FRAME SCLK LRCK 10 8 12 7 CMOUT 15 Voltage Reference 9 Serial Output Interface SDATA DIF0 DIF1 20 19 AINLAINL+ 16 17 LP Filter S/H DAC Digital Decimation Filter Comparator High Pass Filter AINRAINR+ 14 13 S/H LP Filter Digital Decimation Filter High Pass Filter Comparator DAC 4 AGND 5 DGND PU 11 1 HP DEFEAT Preliminary Product Information Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com This document contains information for a new product. Crystal Semiconductor reserves the right to modify this product without notice. Copyright © Crystal Semiconductor Corporation 1996 (All Rights Reserved) NOV ’96 DS237PP2 1 CS5334 CS5335 ANALOG CHARACTERISTICS (TA = 25°C; VA+ = VD+ = 5V; -1 dBFS Input Sinewave, 997 Hz; Fs = 48 kHz; MCLK = 12.288 MHz; SCLK = 3.072 MHz; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified; Logic 0 = 0V, Logic 1 = VD+) CS5334 Parameter Resolution Symbol Min 20 A-weighted -1 dB -20 dB -60 dB THD+N TBD TBD (dc to 20 kHz) with HPF HP defeat with CAL Typ 100 97 -90 -77 -37 0.01 100 0.05 200 0 +/100 2.0 30 2.2 38 25 0.2 315 1.0 50 Max TBD TBD TBD ±5 Min 20 TBD TBD CS5335 Typ 105 102 -95 -82 -42 0.01 105 0.05 200 0 +/100 2.0 30 2.2 40 25 0.2 325 1.0 55 Max TBD TBD TBD ±5 Units Bits dB dB dB dB dB Degree dB dB % ppm/°C LSB LSB Dynamic Performance Dynamic Range Total Harmonic Distortion + Noise Interchannel Phase Deviation Interchannel Isolation dc Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Offset Error Analog Input Input Voltage Range Input Impedance Input Bias Voltage (Differential) VIN ZIN 1.9 IA ID Power Down (IA+ID) Normal Power Down 2.1 TBD TBD TBD 1.9 2.1 TBD TBD TBD Vrms kΩ V mA mA mA mW mW dB Power Supplies Power Supply Current Power Dissipation Power Supply Rejection Ratio Specifications are subject to change without notice 2 DS237PP2 CS5334 CS5335 DIGITAL FILTER CHARACTERISTICS (TA = 25 °C; VA+ = VD+ = 5V ± 5%; Fs = 48 kHz) Parameter Passband Passband Ripple Stopband Stopband Attenuation Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency (Note 1) (Note 2) tgd ∆tgd (Note 1) (Note 1) (Note 1) Symbol Min 0.02 26.3 85 Typ 32/Fs 0.9 20 2.6 Max 21.7 ±0.0025 6118 0 Units kHz dB kHz dB s µs Hz Hz Degree High Pass Filter Characteristics Frequency Response: Phase Deviation -3 dB -0.01 dB @ 20 Hz Passband Ripple 0 dB Notes: 1. Filter characteristic scales with output sample rate. 2. The analog modulator samples the input at 6.144 MHz for an output sample rate of 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency ( n x 6.144 MHz ±21.7kHz where n = 0,1,2,3...). DIGITAL CHARACTERISTICS (TA = 25 °C; VA+ = VD+ = 5V ± 5%) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at lo = -20 µA Low-Level Output Voltage at lo = 20 µA Input Leakage Current Symbol VIH VIL VOH VOL Iin Min 2.4 (VD+)-1.0 Typ Max 0.8 0.4 10 Units V V V V µA ABSOLUTE MAXIMUM RATINGS (AGND = 0V, all voltages with respect to ground.) Parameter DC Power Supply: Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage Ambient Temperature (power applied) Storage Temperature (Note 3) (Note 4) (Note 4) Symbol VA+ Iin VINA VIND TA Tstg Min -0.3 -0.7 -0.7 -55 -65 Typ Max +6.0 ±10 (VA+)+0.7 (VA+)+0.7 +125 +150 Units V mA V V °C °C Notes: 3. Any Pin except supplies. Transient currents of up to +/- 100 mA on the analog input pins will not cause SCR latch-up. 4. The maximum over/under voltage is limited by the input current. WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. DS237PP2 3 CS5334 CS5335 SWITCHING CHARACTERISTICS Parameter Output Sample Rate MCLK Period MCLK Low MCLK High MCLK Period MCLK Low MCLK High MCLK Period MCLK Low MCLK High (TA = 25 °C; VA+ = 5V ± 5%; Inputs: Logic 0 = 0V, Logic 1 = VA+ = VD+; CL = 20 pF) Symbol Fs MCLK / LRCK = 256 MCLK / LRCK = 256 MCLK / LRCK = 256 MCLK / LRCK = 384 MCLK / LRCK = 384 MCLK / LRCK = 384 MCLK / LRCK = 512 MCLK / LRCK = 512 MCLK / LRCK = 512 (Note 5) (Note 5) (Note 5) t clkw t clkl t clkh t clkw t clkl t clkh t clkw t clkl t clkh t mslr t sdo t sfo t ovfl t ovfl Min 2.0 78 31 31 52 20 20 39 15 15 -10 -10 -10 -10 -10 25 (Note 8) (Note 9) (Note 5) (Note 12) (Note 12) 1 + 30ns 6. (1024)(Fs) 10. 13. 1 + 20ns (512)(Fs) 1 + 35ns (384)(Fs) t sclkw (Note 7) t sclkl (Note 11) t sclkh t dss t lrdss t slr1 t slr2 t sfo 50 50 (Note 11) Typ 50 50 Max 50 1953 1302 976 10 35 (Note 6) 30 (Note 10) 75 (Note 11) (Note 11) (Note 13) Units kHz ns ns ns ns ns ns ns ns ns ns ns % ns ns ns % ns ns ns ns ns ns ns ns MASTER MODE SCLK falling to LRCK SCLK falling to SDATA valid SCLK Duty cycle SCLK falling to Frame Valid LRCK edge to OVFL Valid LRCK edge to OVFL edge delay SLAVE MODE LRCK duty cycle SCLK Period SCLK Pulse Width Low SCLK Pulse Width High SCLK falling to SDATA valid LRCK edge to MSB valid SCLK rising to LRCK edge delay LRCK edge to rising SCLK setup time SCLK falling to Frame delay Notes: 5. SCLK rising for Mode 1. 9. Pulse Width Low for Mode 1 12. SCLK Falling for Mode 1 1 7. (96)(Fs) 11. 8. Pulse Width High for Mode 1 1 + 50ns (512)(Fs) 4 DS237PP2 CS5334 CS5335 SCLK output* t mslr LRCK output t sdo SDATA t ovfl OVFL MSB MSB-1 SCLK output t mslr LRCK output t sdo SDATA MSB OVFL t ovfl SCLK to SDATA & LRCK - MASTER mode Format 0 and 1 t slr1 t slr2 SCLK input* (SLAVE mode) t sclkw LRCK input (SLAVE mode) t lrdss SDATA MSB t ovfl OVFL MSB-1 t dss MSB-2 t sclkl t sclkh SCLK to SDATA & LRCK - MASTER mode Format 2 t slr1 t slr2 SCLK input (SLAVE mode) t sclkw LRCK input (SLAVE mode) t dss SDATA MSB t ovfl OVFL MSB-1 t sclkl t sclkh SCLK to LRCK & SDATA - SLAVE mode Format 0 & 1 SCLK to LRCK & SDATA - SLAVE mode Format 2 SCLK* t sfo FRAME SCLK to Frame Delay *SCLK is inverted for Format 1 DS237PP2 5 CS5334 CS5335 2Ω +5V Analog + 1 µF 0.1 µF 6 VD+ 3 VA+ 0.1 µF 1 µF + Left Analog Input + Left Analog Input - 150 Ω 2.2 nF 150 Ω 17 AINL+ CS5334 OVFL CS5335 A/D Converter 2 47 kΩ 11 1 20 19 9 12 8 7 * Peak Signal Level Monitor 16 AINL- PU HP DEFEAT DIF0 15 CMOUT Mode Settings DIF1 SDATA 100 Ω 100 Ω 100 Ω 100 Ω Right Analog Input + Right Analog Input - 150 Ω 2.2 nF Audio Data Processing 13 AINR+ LRCK 150 Ω 14 AINR- SCLK MCLK Timing, Logic & Clock RST * Required for Master Mode only ** Required for Bar Graph Mode only DGND 5 FRAME 18 10 47 kΩ ** AGND 4 Figure 1. Typical Connection Diagram 6 DS237PP2 CS5334 CS5335 SYSTEM DESIGN The CS5334 and CS5335 are 20-bit, 2-channel Analog-to-Digital Converters designed for digital audio applications. These devices use two onebit delta-sigma modulators which simultaneously sample the analog input signals at 128 times the output sample rate (Fs). The resulting serial bit streams are digitally filtered, yielding a pair of 20-bit values. This technique yields nearly ideal conversion performance independent of input frequency and amplitude. The converter does not require difficult-to-design or expensive anti-alias filters and does not require external sample-andhold amplifiers or a voltage reference. Very few external components are required to support these ADCs. Normal power supply decoupling components and a resistor and capacitor on each input for anti-aliasing are all that’s required, as shown in Figure 1. An on-chip voltage reference provides for a differential input signal range of 2.0 Vrms. Output data is available in serial form, coded as 2’s complement, 20-bit numbers. Typical power consumption is 325 mW which can be reduced to 1.0 mW using the power-down feature. Master Clock The master clock (MCLK) is the clock source for the delta-sigma modulator sampling and digital filters. In Master Mode, the frequency of this clock must be 256× Fs. In Slave Mode, the master clock must be either 256×, 384× or 512× Fs. Table 1 shows some common master clock frequencies. SERIAL DATA INTERFACE The CS5334 and CS5335 support three serial data formats, including I2S, which are selected via the digital input format pins DIF0 and DIF1. The digital input format determines the relationship between the serial data, left/right clock and serial clock. Table 2 lists the three formats, along with the associated figure number. The serial data interface is accomplished via the serial data output, SDATA, serial data clock, SCLK, and the left/right clock, LRCK. DIF1 0 0 1 1 DIF0 FORMAT FIGURE 0 0 3 1 1 4 0 2 5 1 power-down Table 2. Digital Input Formats Serial Data The serial data block consists of 20 bits of audio data presented in 2’s-complement format with the MSB-first, followed by 4 bits of zero and 8 Peak Signal Level, PSL, bits as shown in Figure 2. The data is clocked from SDATA by the serial clock and the channel is determined by the Left/Right clock. 20 Audio Data Bits SDATA 19 18 FRAME 10 4 Zeros 8 PSL Bits P7 P6 P1 P0 Figure 2. Data Block and Frame LRCK (kHz) MCLK (MHz) 256 X 384 X 512 X 32 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760 Table 1. Common Clock Frequencies DS237PP2 7 CS5334 CS5335 LRCK SCLK SDATA 19 18 1 0 P7 P6 P5 P4 P3 P2 P1 P0 19 18 1 0 P7 P6 P5 P4 P3 P2 P1 P0 19 18 FRAME MASTER 20-Bit Left Justified Data Data Valid on Rising Edge of 64x SCLK MCLK equal to 256x Fs SLAVE 20-Bit Left Justified Data Data Valid on Rising Edge of SCLK MCLK equal to 256x, 384x or 512x Fs Figure 3. Serial Data Format 0 LRCK SCLK SDATA 19 18 1 0 P7 P6 P5 P4 P3 P2 P1 P0 19 18 1 0 P7 P6 P5 P4 P3 P2 P1 P0 19 18 FRAME MASTER 20-Bit Left Justified Data Data Valid on Falling Edge of 64x SCLK MCLK equal to 256x Fs SLAVE 20-Bit Left Justified Data Data Valid on Falling Edge of SCLK MCLK equal to 256x, 384x or 512x Fs Figure 4. Serial Data Format 1 LRCK SCLK SDATA 19 18 1 0 P7 P6 P5 P4 P3 P2 P1 P0 19 18 1 0 P7 P6 P5 P4 P3 P2 P1 P0 19 18 FRAME MASTER I2S 20-Bit Data Data Valid on Rising Edge of 64x SCLK MCLK equal to 256x Fs SLAVE I2S 20-Bit Data Data Valid on Rising Edge of SCLK MCLK equal to 256x, 384x or 512x Fs Figure 5. Serial Data Format 2 8 DS237PP2 CS5334 CS5335 Serial Clock The serial clock shifts the digitized audio data from the internal data registers via the SDATA pin. SCLK is an output in Master Mode. Internal dividers will divide the master clock by 4 to generate a serial clock which is 64× Fs. In Slave Mode, SCLK is an input with a serial clock typically between 48× and 128× Fs. However, the serial clock must be a minimum of 64× Fs to access the Peak Signal Level bits. Left / Right Clock The Left/Right clock determines which channel, left or right, is to be output on SDATA. Although the outputs for each channel are transmitted at different times, Left/Right pairs represent simultaneously sampled analog inputs. In Master Mode, LRCK is an output whose frequency is equal to Fs. In Slave Mode, LRCK is an input whose frequency must be equal to the output sample rate, Fs. Master Mode In Master mode, SCLK and LRCK are outputs which are internally derived from the Master Clock. Internal dividers will divide MCLK by 4 to generate a SCLK which is 64× Fs and by 256 to generate a LRCK which is equal to Fs. Master mode is only supported with a 256× master clock. The CS5334/5 is placed in the Master mode with a 47 kΩ pull-down resistor on the OVFL pin. Slave Mode LRCK and SCLK become inputs in SLAVE mode. LRCK must be externally derived from MCLK and be equal to Fs. The serial clock is typically between 64× and 128× Fs. A 48× Fs serial clock is possible though will not allow access to the Peak Signal Level bits. Master clock frequencies of 256×, 384× and 512× Fs are supported. The ratio of the applied master clock to the left/right clock is automatically detected durDS237PP2 ing power-up and internal dividers are set to generate the appropriate internal clocks. Analog Connections Figure 1 shows the analog input connections. The analog inputs are presented to the modulators via the AINR+/- and AINL+/- pins. Each analog input pin will accept a maximum of 1 Vrms centered at +2.2 Volt as shown in Figure 6. Input signals can be AC or DC coupled and the CMOUT output may be used as a reference for DC coupling. However, CMOUT is not buffered and the maximum current is 10 µA. CS5334 CS5335 AIN+ 3.6 V 2.2 V 0.78 V 3.6 V 2.2 V 0.78 V AIN- Full Scale Input level= (AIN+) - (AIN-)= 5.67 Vpp Figure 6. Full Scale Input Levels The CS5334 and CS5335 sample the analog inputs at 128×Fs, 6.144 MHz for a 48 kHz sample-rate. The digital filter rejects all noise above 26.3 kHz except for frequencies right around 6.144 MHz ± 21.7 kHz (and multiples of 6.144 MHz). Most audio signals do not have significant energy at 6.144 MHz. Nevertheless, a 150 Ω resistor in series with each analog input and a 2.2 nF capacitor across the inputs will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient must be avoided since these will degrade signal linearity. NPO and COG capacitors are acceptable. If active circuitry precedes the ADC, it is recommended that the above RC filter is placed between the active circuitry and the AINR and AINL pins. The above example frequencies scale linearly with sample rate. 9 CS5334 CS5335 High Pass Filter The operational amplifiers in the input circuitry driving the CS5334/5 may generate a small DC offset into the A/D converter. The CS5334 and CS5335 include a high pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. The high pass filter can be disabled with the HP DEFEAT pin. The high pass filter works by continuously subtracting a measure of the dc offset from the output of the decimation filter. If the HP DEFEAT pin is taken high during normal operation, the current value of the dc offset register is frozen and this dc offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system calibration by; 1. removing the signal source (or grounding the input signal) at the input to the subsystem containing the CS5334/5, 2. running the CS5334/5 with the HP DEFEAT pin low (high pass filter enabled) until the filter settles (approximately 1 second), and 3. taking the HP DEFEAT pin high, disabling the high pass filter and freezing the stored dc offset. A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS5334/5. The characteristics of the first-order high pass filter are outlined below for an output sample rate of 48 kHz. This filter response scales linearly with sample rate. Frequency response: -3 dB @ 0.9 Hz -0.01 dB @ 20 Hz Phase deviation: 2.6 degrees @ 20 Hz Passband ripple: None INPUT LEVEL MONITORING The CS5334 and CS5335 include independent Peak Input Level Monitoring for each channel. The analog-to-digital converter continually monitors the peak digital signal for both channels, prior to the digital limiter, and records these values in the Active registers. This information can be transferred to the Output registers by a high to low transition on the Peak Update pin (PU) which will also reset the Active register. The Active register contains the peak signal level since the previous peak update request. The 8-bit contents of the output registers are available in all interface modes and are present in the data block as shown in Figure 2. The monitoring function can be formatted to indicate either High Resolution Mode or Bar Graph Mode. The monitoring function is determined on power-up by the presence of a 47 kohm pulldown resistor on FRAME. The addition of a 47 kohm pull-down resistor on the FRAME pin sets the monitoring function to the Bar Graph mode. High Resolution Mode Bits P7-P0 indicate the peak input level since the previous peak update (or low transition on the Peak Update pin). If the full scale input level is exceeded (Bit P7 high), bits P5-P0 represent the peak value up to 3 dB above full-scale in 1 dB steps. If the ADC input level is less than fullscale, bits P5-P0 represent the peak value from -60 dB to 0 dB of full scale in 1 dB steps. The PSL outputs are accurate to within 0.25 dB. Bit P6 provides a coarse means of determining an ADC input idle condition. Bit P7 indicates an ADC overflow condition, if the ADC input level is greater than full-scale. 10 DS237PP2 CS5334 CS5335 P7 - Overrange 0 - Analog input less than full-scale level 1 - Analog input greater than full-scale P6 - Idle channel 0 - Analog input >-60 dB from full-scale 1 - Analog input