CS5336

CS5336 CS5338 CS5339 Semiconductor Corporation 16-Bit, Stereo A/D Converters for Digital Audio Features General Description The CS5336, CS5338 & CS5339 are complete analogto-digital converters for stereo digital audio systems. They perform sampling, analog-to-digital conversion and anti-aliasing filtering, generating 16-bit values for both left and right inputs in serial form. The output word rate can be up to 50 kHz per channel. The ADCs use delta-sigma modulation with 64X oversampling, followed by digital filtering and decimation, which removes the need for an external anti-alias filter. The CS5336 & CS5338 have an SCLK which clocks out data on rising edges. The CS5339 has an SCLK which clocks out data on falling edges. The CS5336 has a filter passband of dc to 22kHz. The CS5338 & CS5339 have a filter passband of dc to 24 kHz. The filters have linear phase, 0.01 dB passband ripple, and >80 dB stopband rejection. The ADC’s are housed in a 0.6" wide 28-pin plastic DIP, and also in a 0.3" wide 28-pin SOIC surface mount package. Extended temperature range versions of the CS5336 are also available. ORDERING INFORMATION: See Page 3-59 • Complete CMOS Stereo A/D System • Adjustable System Sampling Rates • Low Noise and Distortion >90 dB S/(N+D) Delta-Sigma A/D Converters Digital Anti-Alias Filtering S/H Circuitry and Voltage Reference including 32kHz, 44.1 kHz & 48kHz • Internal 64X Oversampling • Linear Phase Digital Anti-Alias Filtering • Low Power Dissipation: 400 mW • Evaluation Board Available IC L K A 23 VREF 28 V o ltag e R e fe re n ce 0.01dB Passband Ripple 80dB Stopband Rejection Power-Down Mode for Portable Applications APD 6 ACAL 7 O C LK D 21 IC L K D 20 FSYN C SCLK 17 15 L /R 14 16 12 13 SDATA CM ODE SMODE S e ria l O utp ut Inte rface A IN L ZER OL 2 3 S /H DAC A IN R ZERO R 27 26 S /H AGND 1 DAC 4 VA+ 5 VA25 VL+ 24 LGND L P F ilte r D ig ita l D e cim a tio n Filter L P F ilte r D ig ita l D e cim a tio n Filter C om para tor 11 TST 8 C o m p ara to r C a lib ra tio n Microcontroller 9 10 C a lib ra tio n SRAM 18 VD+ 19 DGND NC 22 NC DCAL DPD Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581 AUG ’93 DS23F1 3-39 CS5336, CS5338, CS5339 (Logic 0 = GND; Logic 1 = VD+; K grade: TA = 25°C; B and T grades: TA = TMIN to TMAX; VA+, VL+,VD+ = 5V; VA- = -5V; Full-Scale Input Sinewave, 1kHz; Output word rate = 48 kHz; SCLK = 3.072 MHz; Source Impedance = 50Ω with 10 nF to AGND; Measurement Bandwidth is 10 Hz to 20 kHz; unless otherwise specified.) Parameter Specified Temperature Range Resolution CS5336,8,9-K CS5336-B CS5336-T Symbol Min Typ Max Min Typ Max Min Typ Max Units TA 0 16 to 70 -40 16 90 85 90 to 93.5 89 95 .0001 106 .01 ±2 70 20 +85 -55 .05 ±5 35 -35 45 16 84 82 83 to +125 92 86 94 .0001 96 .01 ±3 70 20 0.1 ±6 35 -35 50 °C Bits dB dB dB % ° dB dB % ppm/°C LSB ppm/°C V kΩ mA mA mA µA µA µA mW mW dB dB ANALOG CHARACTERISTICS Dynamic Performance Dynamic Range Signal-to-(Noise + Distortion); THD+N Signal to Peak Noise Total Harmonic Distortion Interchannel Phase Deviation Interchannel Isolation dc Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Offset Drift Analog Input Input Voltage Range Input Impedance (includes Vref tolerance) (includes Vref drift, Note 1) (Note 2) (Note1) (±Full Scale) VIN ZIN (VA+)+(VL+) VAVD+ (VA+)+(VL+) VAVD+ (APD, DPD Low) (APD, DPD High) IA+ IAID+ IA+ IAID+ PDN PDS PSRR 0.01 0.05 ±1 25 ±5 15 ±5 ±15 35 -35 45 (dc to 20 kHz) THD 92.7 95.7 S/(N+D) 90.7 92.7 96 .0001 .0025 .001 100 106 .005 .001 .013 .005 Bipolar Offset Error ±10 ±30 ±16 ±65 ±3.5 ±3.68 65 25 -25 30 ±-3.5 ±3.68 65 25 -25 30 ±3.5 ±3.68 65 25 -25 30 Power Supplies Power Supply Current with APD, DPD low (Normal Operation) Power Supply Current with APD, DPD high (Power-Down Mode) Power Consumption Power Supply Rejection Ratio 10 50 -10 -50 10 400 400 575 0.15 2.5 54 100 - 10 50 -10 -50 10 400 400 575 0.15 2.5 54 100 - 10 50 -10 -50 10 400 400 600 0.15 2.5 54 100 - (dc to 26 kHz) (26 kHz to 3.046 MHz) Notes: 1. This parameter is guaranteed by design and/or characterization. 2. After calibration with DCAL connected to ACAL, and ZEROL & ZEROR terminated to AGND with an impedance matched to the AINR & AINL source impedance. Executing a calibration with ACAL tied low (See Power Down and Offset Calibration section) will yield an offset error of typically less than ± 5LSB. Specifications are subject to change without notice. 3-40 DS23F1 CS5336, CS5338, CS5339 DIGITAL FILTER CHARACTERISTICS Parameter Passband (-3 dB) (-3 dB) (-0.01 dB) (-0.01 dB) CS5336 CS5338, CS5339 CS5336 CS5338, CS5339 CS5336 CS5338, CS5339 (Note 3) t gd (TA = 25 ° C; VA+, VL+ ,VD+ = 5V ± 5%; VA- = -5V ± 5%; Output word rate of 48 kHz) Symbol Min 0 0 0 0 26 28 80 Typ to to to to to to 18/OWR Max 22 24 20 22 _ + 0.01 3046 3044 0.0 Units kHz kHz kHz kHz dB kHz kHz dB s us Passband Ripple Stopband Stopband Attenuation Group Delay (OWR = Output Word Rate) Group Delay Variation vs. Frequency t gd Notes: 3. The analog modulator samples the input at 3.072MHz for an output word rate of 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency (that is: there is no rejection for n x 3.072MHz ±22kHz for the CS5338 & CS5339, or n x 3.072MHz ±20.0kHz for the CS5336, where n = 0,1,2,3...). (TA = 25 °C; VA+, VL+ ,VD+ = 5V ± 5%; VA- = -5V ± 5%) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at Io = -20uA Low-Level Output Voltage at Io = 20uA Input Leakage Current Symbol VIH VIL VOH V OL Iin Min 70%VD+ 4.4 Typ 1.0 Max 30% VD+ 0.1 Units V V V V uA DIGITAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (AGND, LGND, DGND = 0V, all voltages with respect to GND) Parameter DC Power Supplies: Positive Analog Negative Analog Positive Logic Positive Digital Input Current, Any Pin Except Supplies Analog Input Voltage (AIN and ZERO pins) Digital Input Voltage Ambient Temperature (power applied) Storage Temperature Symbol VA+ VAVL+ VD+ I in V INA VIND TA Tstg Min -0.3 +0.3 -0.3 -0.3 (VA- )- 0.3 -0.3 -55 -65 Max +6.0 -6.0 (VA+) + 0.3 +6.0 _ + 10 (VA+ )+ 0.3 (VD+) + 0.3 +125 +150 Units V V V V mA V V C C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. DS23F1 3-41 CS5336, CS5338, CS5339 SWITCHING CHARACTERISTICS Parameter ICLKD Period (CMODE low) ICLKD Low (CMODE low) ICLKD High (CMODE low) ICLKD rising to OCLKD rising (CMODE low) ICLKD Period (CMODE high) ICLKD Low (CMODE high) ICLKD High (CMODE high) (TA = 25 °C; VA+, VL+, VD+ = 5V ± 5%; VA- = -5V ± 5%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 20 pF) Symbol (Note 6) t clkw1 t clkl1 t clkh1 t io1 t clkw2 t clkl2 t clkh2 t io2 t ilr1 t ifs1 t isclk1 t ilr2 t ifs2 t isclk2 t sdo t mslr t msfs t sclkw t sclkl t sclkh t dss t lrdss t slr1 t slr2 t sfs1 t sfs2 t pdw t pcr t pcf Min 78 31 31 5 52 20 20 5 5 5 5 5 5 5 0 40 -20 -20 155 60 60 30 30 30 30 2 x tclkw Typ 50 4096 Max 3906 40 2604 45 50 50 50 50 50 50 50 60 20 20 50 50 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns % ns ns ns ns ns ns ns ns ns ns ns ns ns 1/OWR ICLKD rising or falling to OCLKD rising (CMODE high, Note 4) ICLKD rising to L/R edge (CMODE low, MASTER mode) ICLKD rising to FSYNC edge (CMODE low, MASTER mode) ICLKD rising to SCLK edge (CMODE low, MASTER mode) ICLKD falling to L/R edge (CMODE high, MASTER mode) ICLKD falling to FSYNC edge (CMODE high, MASTER mode) ICLKD falling to SCLK edge (CMODE high, MASTER mode) SCLK rising to SDATA valid (MASTER mode, Note 5) SCLK duty cycle (MASTER mode) SCLK rising to L/R (MASTER mode, Note 5) SCLK rising to FSYNC (MASTER mode, Note 5) SCLK Period (SLAVE mode) SCLK Pulse Width Low (SLAVE mode) SCLK Pulse Width High (SLAVE mode) SCLK rising to SDATA valid (SLAVE mode, Note 5) L/R edge to MSB valid (SLAVE mode) Falling SCLK to L/R edge delay (SLAVE mode, Note 5) L/R edge to falling SCLK setup time (SLAVE mode, Note 5) Falling SCLK to rising FSYNC delay (SLAVE mode, Note 5) Rising FSYNC to falling SCLK setup time (SLAVE mode, Note 5) DPD pulse width DPD rising to DCAL rising DPD falling to DCAL falling (OWR = Output Word Rate) Notes: 4. 5. 6. ICLKD rising or falling depends on DPD to L/R timing (see Figure 2). SCLK is shown for CS5336, CS5338. SCLK is inverted for CS5339. Specifies minimum output word rate (OWR) of 1 kHz. 3-42 DS23F1 CS5336, CS5338, CS5339 t clkh t clkl t clkh2 t clkl2 ICLKD t OCLKD (CMODE low) t L/R output (MASTER mode) t FSYNC output (MASTER mode) t ifs1 SCLK output (MASTER mode) t isclk1 ilr1 io1 clkw1 ICLKD t OCLKD (CMODE high) t io2 clkw2 L/R output (MASTER mode) t FSYNC output (MASTER mode) t SCLK output (MASTER mode) t isclk2 ifs2 ilr2 ICLKD to Outputs Propagation Delays (CMODE low) SCLK output (MASTER mode) ICLKD to Outputs Propagation Delays (CMODE high) t mslr t pdw t pcf L/ R output (MASTER mode) t SDATA t FSYNC output (MASTER mode) msfs DCAL sdo DPD t pcr SCLK to SDATA, L/R & FSYNC - MASTER Mode Power Down & Calibration Timing t slr1 SCLK input (SLAVE mode) t slr2 t sclkh t sclkl t sclkw L/R input (SLAVE mode) t lrdss MSB MSB-1 t dss MSB-2 SDATA SCLK to L/R & SDATA - SLAVE mode, FSYNC high t sfs1 SCLK input (SLAVE mode) FSYNC input (SLAVE mode) MSB MSB-1 MSB-2 t sfs2 SDATA FSYNC to SCLK - SLAVE Mode, FSYNC Controlled. DS23F1 3-43 CS5336, CS5338, CS5339 RECOMMENDED OPERATING CONDITIONS (AGND, LGND, DGND = 0V; all voltages with respect to ground) Parameter DC Power Supplies: Positive Digital Positive Logic Positive Analog Negative Analog (Note 7) Symbol VD+ VL+ VA+ VAV AIN Min 4.75 4.75 4.75 _ 4.75 _ 3.68 Typ 5.0 5.0 5.0 _ 5.0 Max VA+ VA+ 5.25 _ 5.25 3.68 Units V V V V V Analog Input Voltage Notes: 7. The ADCs accept input voltages up to the analog supplies (VA+, VA-). They will produce a positive full-scale output for inputs above 3.68 V and negative full-scale output for inputs below -3.68 V. These values are subject to the gain error tolerance specification. Additional tag bits are output to indicate the amount of overdrive. +5V Analog + Ferrite Bead 0.1 µ F 1 µF 0.1 µ F 4 28 VA+ VREF VL+ 51 Ω 25 + +5V Digital 1 µF 0.1 µ F 18 VD+ APD DPD ACAL DCAL 6 10 7 Power Down & Calibrate Control + 10 µ F 0.1 µ F 9 13 12 Mode Settings Left Analog Input 51 Ω Right Analog Input 51 Ω 10 nF 10 nF 2 AINL CS5336 SMODE CS5338 27 AINR CMODE CS5339 A/D CONVERTER 16 SDATA Audio Data Processor 3 ZEROL 26 ZEROR 1 AGND 8 22 NC NC VA+ -5V Analog + L/R SCLK FSYNC ICLKD OCLKD ICLKA 14 15 17 20 21 23 Ferrite bead may be used if VD+ is derived from VA+. If used, do not drive any other logic from VD+. An example ferrite bead is Permag VK200-2.5/52 Timing Logic & Clock VA5 0.1 µ F LGND 24 DGND 19 TST 11 1 µF Figure 1. Typical Connection Diagram 3-44 DS23F1 CS5336, CS5338, CS5339 GENERAL DESCRIPTION The CS5336, CS5338, and CS5339 are 16-bit, 2channel A/D converters designed specifically for stereo digital audio applications. The devices use two one-bit delta-sigma modulators which simultaneously sample the analog input signals at a 64 X sampling rate. The resulting serial bit streams are digitally filtered, yielding pairs of 16-bit values. This technique yields nearly ideal conversion performance independent of input frequency and amplitude. The converters do not require difficultto-design or expensive anti-alias filters, and do not require external sample-and-hold amplifiers or a voltage reference. An on-chip voltage reference provides for an input signal range of ± 3.68 volts. Any zero offset is internally calibrated out during a power-up selfcalibration cycle. Output data is available in serial form, coded as 2’s complement 16-bit numbers. Typical power consumption of only 400 mW can be further reduced by use of the power-down mode. For more information on delta-sigma modulation and the particular implementation inside these ADCs, see the references at the end of this data sheet. SYSTEM DESIGN Very few external components are required to support the ADC. Normal power supply decoupling components, voltage reference bypass capacitors and a single resistor and capacitor on each input for anti-aliasing are all that’s required, as shown in Figure 1. Master Clock Input The master input clock (ICLKD) into the ADC runs the digital filter, and is used to generate the modulator sampling clock. ICLKD frequency is determined by the desired Output Word Rate (OWR) and the setting of the CMODE pin. CMODE high will set the required ICLKD frequency to 384 X OWR, while CMODE low will set the required ICLKD frequency to 256 X OWR. Table 1 shows some common clock frequencies. The digital output clock (OCLKD) is always equal to 128 X OWR, which is always 2 X the input sample rate. OCLKD should be connected to ICLKA, which controls the input sample rate. The phase alignment between ICLKD and OCLKD is determined as follows: when CMODE is 0 ICLKD Input DPD Input _ SCLK (MHz) 2.048 2.048 2.8224 2.8224 3.072 3.072 L/ R Input OCLKD Output _ L/ R Input OCLKD Output 1 1 2 2 * ** 1 2 3 4 5 6 7 OCLKD/ L/R (kHz) 32 32 44.1 44.1 48 48 CMODE low high low high low high ICLKD (MHz) 8.192 12.288 11.2896 16.9344 12.288 18.432 ICLKA (MHz) 4.096 4.096 5.6448 5.6448 6.144 6.144 *** * DPD low is recognized on the next ICLKD rising edge (#0) ** L/R rising before ICLKD rising #2 causes OCLKD -1 *** L/R rising after ICLKD rising #2 causes OCLKD - 2 Table 1. Common Clock Frequencies Figure 2. ICLKD to OCLKD Timing with CMODE high (384 X OWR) 3-45 DS23F1 CS5336, CS5338, CS5339 L/ R Output 0 * SCLK Output FSYNC Output SDATA Output * SCLK for CS5336/8. SCLK inverted for CS5339 1 2 3 16 17 18 19 20 21 31 0 1 2 3 16 17 18 19 20 21 31 0 1 15 14 1 0 T2 T1 T0 15 14 1 0 T2 T1 T0 Left Audio Data Tag Bits Left Data Tag Right Audio Data Tag Bits Right Data Tag Figure 3. Data Output Timing - MASTER mode L/ R Input 0 * SCLK Input FSYNC Input (high) 1 2 15 16 17 18 19 20 30 31 0 1 2 15 16 17 18 19 20 21 31 0 1 SDATA Output * SCLK for CS5336/8. SCLK inverted for CS5339 15 14 1 0 T2 T1 T0 15 14 1 0 T2 T1 T0 Left Audio Data Tag Bits Left Data Tag Right Audio Data Tag Bits Right Data Tag Figure 4. Data Output Timing - SLAVE Mode, FSYNC high low, ICLKD is divided by 2 to generate OCLKD. The phase relationship between ICLKD and OCLKD is always the same, and is shown in the Switching Characteristics Timing Diagrams. When CMODE is high, OCLKD is ICLKD divided by 3. There are two possible phase relationships between ICLKD and OCLKD, which depend on the start-up timing between DPD and L/R, shown in Figure 2. Serial Data Interface The serial data output interface has 3 possible modes of operation: MASTER mode, SLAVE mode with FSYNC high, and SLAVE mode with FSYNC controlled. In MASTER mode, the A/D 3-46 converter is driven from a master clock (ICLKD) and outputs all other clocks, derived from ICLKD (see Figure 3). Notice the one SCLK cycle delay between L/R edges and FSYNC rising edges. FSYNC brackets the 16 data bits for each channel. In SLAVE mode, L/R and SCLK are inputs. L/R must be externally derived from ICLKD, and should be equal to the Output Word Rate. SCLK should be equal to the input sample rate, which is equal to OCLKD/2. Other SCLK frequencies are possible, but may degrade dynamic range because of interference effects. Data bits are clocked out via the SDATA pin using the SCLK and L/R inputs. The rising edge of SCLK causes the ADC to DS23F1 CS5336, CS5338, CS5339 L/ R Input 0 * SCLK Input FSYNC Input SDATA Output *** 1 2 15 16 17 18 19 20 0 1 2 15 16 17 18 19 20 ** *** ** 15 15 14 1 0 T2 T1 T0 15 15 14 1 0 T2 T1 T0 Left Audio Data * SCLK for CS5336/8. SCLK inverted for CS5339 ** Tag Bits Left Data Tag Right Audio Data *** Tag Bits Right Data Tag Rising FSYNC enables SCLK to clock out SDATA Falling FSYNC stops SCLK from clocking out SDATA Figure 5. Data Output Timing - SLAVE Mode, FSYNC controlled output each bit, except the MSB, which is clocked out by the L/R edge. As shown in Figure 4, when FSYNC is high, serial data bits are clocked immediately following the L/R edge. In SLAVE mode with FSYNC controlled, as shown in Figure 5, when FSYNC is low, only the MSB is clocked out after the L/R edge. With FSYNC low, SCLK is ignored. When it is desired to start clocking out data, bring FSYNC high which enables SCLK to start clocking out data. Bringing FSYNC low will stop the data being clocked out. This feature is particularly useful to Input Level 1.375 x FS 1.250 x FS to 1.375 x FS 1.125 x FS to 1.250 x FS 1.000 x FS to 1.125 x FS -1.006dB to 0.000dB -3.060dB to -1.006dB -6.000dB to -3.060dB < -6.000dB T2 T1 T0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 position in time the data bits onto a common serial bus. The serial nature of the output data results in the left and right data words being read at different times. However, the words within an L/R cycle represent simultaneously sampled analog inputs. In all modes, additional bits are output after the data bits: 3 tag bits and a left/right indicator. The tag bits indicate a near-to-clipping input condition for the data word to which the tag bits are attached. Table 2 shows the relationship between input level and the tag bit values. The serial bit immediately following the tag bits is 0 for the left channel, and 1 for the right channel. The remaining bits before the next L/R edge will be 1’s for the left channel and 0’s for the right channel. Normally, the tag bits are separated from the audio data by the digital signal processor. However, if the tag bits are interpreted as audio data, their position below the LSB would result as a very small dc offset. In all modes, SCLK is shown for the CS5336 and CS5338, where data bits are clocked out on rising edges. SCLK is inverted for the CS5339. FS = Full Scale (0dB) Input Table 2. Tag Bit Definition DS23F1 3-47 CS5336, CS5338, CS5339 Certain serial modes align well with various interface requirements. A CS5339 in MASTER mode, with an inverted L/R signal, generates I2S (Philips) compatible timing. A CS5336 in MASTER mode, using FSYNC, interfaces well with a Motorola DSP56000. A CS5336 in SLAVE mode emulates a CS5326 style interface, and also links up to a DSP56000 in network mode. Analog Connections The analog inputs are presented to the modulators via the AINR and AINL pins. The analog input signal range is determined by the internal voltage reference value, which is typically -3.68 volts. The input signal range therefore is typically ± 3.68 volts. The ADC samples the analog inputs at 3.072 MHz for a 12.288 MHz ICLKD (CMODE low). For the CS5336, the digital filter rejects all noise between 26 kHz and (3.072 MHz-26 kHz). For the CS5338 and CS5339, the digital filter rejects all noise between 28 kHz and (3.072 MHz-28 kHz). However, the filter will not reject frequencies right around 3.072 MHz (and multiples of 3.072 MHz). Most audio signals do not have significant energy at 3.072 MHz. Nevertheless, a 51 Ω resistor in series with the analog input, and a 10 nF NPO or COG capacitor to ground will attenuate any noise energy at 3.072 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) should be avoided since these can degrade signal linearity. If active circuitry precedes the ADC, it is recomCal Period (4096 x L/R clocks) (85.33 ms @ 48kHz) DPD Normal Operation mended that the above RC filter is placed between the active circuitry and the AINR and AINL pins. The above example frequencies scale linearly with output word rate. The on-chip voltage reference output is brought out to the VREF pin. A 10 µF electrolytic capacitor in parallel with a 0.1 µF ceramic capacitor attached to this pin eliminates the effects of high frequency noise. Note the negative value of VREF when using polarized capacitors. No load current may be taken from the VREF output pin. The analog input level used as zero during the offset calibration period (described later) is input on the ZEROL and ZEROR pins. Typically, these pins are directly attached to AGND. For the ultimate in offset nulling, networks can be attached to ZEROR and ZEROL whose impedances match the impedances present on AINL and AINR. Power-Down and Offset Calibration The ADC has a power-down mode wherein typical consumption drops to 150 µW. In addition, exiting the power-down state initiates an offset calibration procedure. APD and DPD are the analog and digital powerdown pins. When high, they place the analog and digital sections in the power-down mode. Bringing these pins low takes the part out of power-down mode. DPD going low initiates a calibration cycle. If not using the power down feature, APD should be tied to AGND. When using the power down feature, DPD and APD may be tied together if the capacitor on VREF is not Filter Delay Time (~40 L/R periods) (~2 ms @ 48 kHz) DCAL Figure 6. Initial Calibration Cycle Timing 3-48 DS23F1 CS5336, CS5338, CS5339 greater than 10 µF, as stated in the "Power-Up Considerations" section. During the offset calibration cycle, the digital section of the part measures and stores the value of the calibration input of each channel in registers. The calibration input value is subtracted from all future outputs. The calibration input may be obtained from either the analog input pins (AINL and AINR) or the zero pins (ZEROL and ZEROR) depending on the state of the ACAL pin. With ACAL low, the analog input pin voltages are measured, and with ACAL high, the zero pin voltages are measured. As shown in Figure 6, the DCAL output is high during calibration, which takes 4096 L/R clock cycles. If DCAL is connected to the ACAL input, the calibration routine will measure the voltage on ZEROR and ZEROL. These should be connected directly to ground or through a network matched to that present on the analog input pins. Internal offsets of each channel will thus be measured and subsequently subtracted. Alternatively, ACAL may be permanently connected low and DCAL utilized to control a multiplexer which grounds the user’s front end. In this case, the calibration routine will measure and store not only the internal offsets but also any offsets present in the front end input circuitry. During calibration, the digital output of both channels is forced to a 2’s complement zero. Subtraction of the calibration input from conversions after calibration substantially reduces any power on click that might otherwise be experienced. A short delay of approximately 40 output words will occur following calibration for the digital filter to begin accurately tracking audio band signals. Power-up Considerations Upon initial application of power to the supply pins, the data in the calibration registers will be indeterminate. A calibration cycle should always be initiated after application of power to replace potentially large values of data in these registers with the correct values. The modulators settle very quickly (a matter of microseconds) after the analog section is powered on, either through the application of power, or by exiting the power-down mode. The voltage reference can take a much longer time to reach a final value due to the presence of large external capacitance on the VREF pin; allow approximately 5 ms/µF. The calibration period is long enough to allow the reference to settle for capacitor values of up to 10 µF. If a larger capacitor is used, additional time between APD going low and DPD going low should be allowed for VREF settling before a calibration cycle is initiated. Grounding and Power Supply Decoupling As with any high resolution converter, the ADC requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA+, VA- and VL+ connected to a clean ± 5 V supply. VD+, which powers the digital filter, may be run from the system +5V logic supply, provided that it is not excessively noisy (< ± 50 mV pk-to-pk). Alternatively, VD+ may be powered from VA+ via a ferrite bead. In this case, no additional devices should be powered from VD+. Analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. The printed circuit board layout should have separate analog and digital regions and ground planes, DS23F1 3-49 CS5336, CS5338, CS5339 with the ADC straddling the boundary. All signals, especially clocks, should be kept away from the VREF pin in order to avoid unwanted coupling into the modulators. The VREF decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from VREF to Pin 1 AGND and to minimize the path between VREF and the capacitors. An evaluation board is available which demonstrates the optimum layout and power supply arrangements, as well as allowing fast evaluation of the ADC. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs. Synchronization of Multiple CS5336/8/9 In systems where multiple ADC’s are required, care must be taken to insure that the ADC internal clocks are synchronized between converters to insure simultaneous sampling. In the absence of this synchronization, the sampling difference could be one ICLKD period which is typically 81.4 nsec for a 48 kHz sample rate. SLAVE MODE S ynchronous sampling in the slave mode is achieved by connecting all DPD and APD pins to a single control signal and supplying the same ICLKD and L/R to all converters. MASTER MODE The internal counters of the CS5336/8/9 are reset during DPD/APD high and will start simultaneously by insuring that the release of DPD/APD for all converters is internally latched on the same rising edge of ICLKD. This can be achieved by connecting all DPD/APD pins to the same control signal and insuring that the DPD/APD falling edge occurs outside a ±30 ns window either side of an ICLKD rising edge. PERFORMANCE FFT Tests For FFT based tests, a very pure sine wave is presented to the ADC, and an FFT analysis is performed on the output data. The resulting spectrum is a measure of the performance of the ADC. Figure 7 shows the spectral purity of the CS5336 with a 1 kHz, -10 dB input. Notice the low noise floor, the absence of any harmonic distortion, and the Dynamic Range value of 95.41 dB. Figure 8 shows the CS5336 high frequency performance. The input signal is a -10 dB, 9 kHz sine wave. Notice the small 2nd harmonic at 110 dB down. Figure 9 shows the low-level performance of the CS5336. Notice the lack of any distortion components. Traditional R-2R ladder based ADC’s can have problems with this test, since differential non-linearities around the zero point become very significant. Figure 10 shows the same very low input amplitude performance, but at 9kHz input frequency. 3-50 DS23F1 CS5336, CS5338, CS5339 0 -10 -20 -30 -40 Signal -50 Amplitude -60 Relative to -70 Full Scale -80 (dB) -90 -100 -110 -120 -130 0 -10 -20 -30 -40 Signal -50 Amplitude -60 Relative to -70 Full Scale -80 (dB) -90 -100 -110 -120 -130 Output Word Rate: 48 kHz Full Scale: 7.3 Vp-p S/(N+D): 85.03 dB Dynamic Range: 95.033 dB (dc to 20 kHz) Output Word Rate: 48 kHz Full Scale: 7.3 Vp-p S/(N+D): 85.41 dB Dynamic Range: 95.41 dB (dc to 20 kHz) 0 4 8 12 16 Input Frequency (kHz) 20 24 0 4 8 12 16 Input Frequency (kHz) 20 24 Figure 7. CS5336 FFT Plot with -10 dB, 1 kHz Input 0 -10 -20 -30 -40 Signal -50 Amplitude -60 Relative to -70 Full Scale -80 (dB) -90 -100 -110 -120 -130 Figure 8. CS5336 FFT Plot with -10 dB, 9 kHz Input 0 -10 -20 -30 -40 Signal -50 Amplitude -60 Relative to -70 Full Scale -80 (dB) -90 -100 -110 -120 -130 Output Word Rate: 48 kHz Full Scale: 7.3 Vp-p S/(N+D): 15.72 dB Dynamic Range: 95.72 dB (dc to 20 kHz) Output Word Rate: 48 kHz Full Scale: 7.3 Vp-p S/(N+D): 16.09 dB Dynamic Range: 96.09 dB (dc to 20 kHz) 0 4 8 12 16 Input Frequency (kHz) 20 24 0 4 8 12 16 Input Frequency (kHz) 20 24 Figure 9. CS5336 FFT Plot with -80 dB, 1 kHz Input Figure 10. CS5336 FFT Plot with -80 dB, 9 kHz Input DNL Tests A Differential Non-Linearity test is also shown. Here, the converter is presented with a linear ramp signal. The resulting output codes are counted to yield a number which is proportional to the codewidth. A plot of codewidth versus code graphically illustrates the uniformity of the codewidths. Figure 11 shows the excellent Differential Non-Linearity of the CS5336. This plot displays the worst case positive and negative errors in each of 512 groups of 128 codes. Codewidths typically are within ± 0.2 LSB’s of ideal. A delta-sigma modulator based ADC has no inherent mechanism for generating DNL errors. The residual small deviations shown in Figure 11 are a result of noise. Nevertheless, the performance shown is extremely good, and is superior to typical R-2R ladder based designs. DS23F1 3-51 CS5336, CS5338, CS5339 +1 +1/2 DNL (LSB) 0 -1/2 -1 0 32,768 65,535 Codes Figure 11. CS5336 Differential Non-Linearity Plot Digital Filter Figures 12 through 17 show the performance of the digital filter included in the ADC. All the plots assume an output word rate of 48 kHz. The filter frequency response will scale precisely with changes in output word rate. The passband ripple is flat to ± 0.01 dB maximum. Stopband rejection is greater than 80 dB. Figures 12,14 &16 show the CS5338 and CS5339 filter characteristics. Figure 17 is an expanded view of the transition band. Figures 13,15 & 17 show the CS5336 filter characteristics. Figure 17 is an expanded view of the transition band. 3-52 DS23F1 CS5336, CS5338, CS5339 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 8 16 24 32 Input Frequency (kHz) 40 48 Magnitude (dB) 0 8 16 24 32 Input Frequency (kHz) 40 48 Figure 12. CS5338/9 Digital Filter Stopband Rejection Figure 13. CS5336 Digital Filter Stopband Rejection Magnitude (dB) Magnitude (dB) 0.020 Magnitude (dB) 0.020 0.010 0.010 0.000 0.000 -0.010 -0.010 -0.020 -0.020 0 4 8 12 16 Input Frequency (kHz) 20 24 0 4 8 12 16 Input Frequency (kHz) 20 24 Figure 14. CS5338/9 Digital Filter Passband Ripple Figure 15. CS5336 Digital Filter Passband Ripple 0 Magnitude (dB) Magnitude (dB) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 22 23 24 25 26 27 28 Input Frequency (kHz) 29 30 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 21 22 23 24 25 26 27 28 Input Frequency (kHz) Figure 16. CS5338/9 Digital Filter Transition Band DS23F1 Figure 17. CS5336 Digital Filter Transition Band 3-53 CS5336, CS5338, CS5339 PIN DESCRIPTIONS ANALOG GROUND AGND LEFT CHANNEL ANALOG INPUT AINL LEFT CHANNEL ZERO INPUT ZEROL POSITIVE ANALOG POWER VA+ NEGATIVE ANALOG POWER VAANALOG POWER DOWN INPUT APD ANALOG CALIBRATE INPUT ACAL NO CONNECT NC DIGITAL CALIBRATE OUTPUT DCAL DIGITAL POWER DOWN INPUT DPD TEST TST SELECT CLOCK MODE CMODE SELECT SERIAL I/O MODE SMODE LEFT/RIGHT SELECT L /R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VREF AINR ZEROR VL+ LGND ICLKA NC OCLKD ICLKD DGND VD+ FSYNC SDATA SCLK VOLTAGE REFERENCE OUTPUT RIGHT CHANNEL ANALOG INPUT RIGHT CHANNEL ZERO INPUT ANALOG SECTION LOGIC POWER ANALOG SECTION LOGIC GROUND ANALOG SECTION CLOCK INPUT NO CONNECT DIGITAL SECTION OUTPUT CLOCK DIGITAL SECTION CLOCK INPUT DIGITAL GROUND DIGITAL SECTION POSITIVE POWER FRAME SYNC SIGNAL SERIAL DATA OUTPUT SERIAL DATA CLOCK Power Supply Connections VA+ - Positive Analog Power, PIN 4. Positive analog supply. Nominally +5 volts. VL+ - Positive Logic Power, PIN 25. Positive logic supply for the analog section. Nominally +5 volts. VA- - Negative Analog Power, PIN 5. Negative analog supply. Nominally -5 volts. AGND - Analog Ground, PIN 1. Analog ground reference. LGND - Logic Ground, PIN 24 Ground for the logic portions of the analog section. VD+ - Positive Digital Power, PIN 18. Positive supply for the digital section. Nominally +5 volts. DGND - Digital Ground, PIN 19. Digital ground for the digital section. Analog Inputs AINL, AINR - Left and Right Channel Analog Inputs, PINS 2, 27 Analog input connections for the left and right input channels. Nominally ±3.68 volts full scale. 3-54 DS23F1 CS5336, CS5338, CS5339 ZEROL, ZEROR - Zero Level Inputs for Left and Right Channels, PINS 3, 26. Analog zero level inputs for the left and right channels. The levels present on these pins can be used as zero during the offset calibration cycle. Normally connected to AGND, optionally through networks matched to the analog input networks. Analog Outputs VREF - Voltage Reference Output, PIN 28. Nominally -3.68 volts. Normally connected to a 0.1µF ceramic capacitor in parallel with a 10µF or larger electrolytic capacitor. Note the negative output polarity. Digital Inputs ICLKA - Analog Section Input Clock, PIN 23. This clock is internally divided by 2 to set the modulators’ sample rate. Sampling rates, output rates, and digital filter characteristics scale to ICLKA frequency. ICLKA frequency is 128 X the output word rate. For example, 6.144 MHz ICLKA corresponds to an output word rate of 48 kHz per channel. Normally connected to OCLKD. ICLKD - Digital Section Input Clock, PIN 20. This is the clock which runs the digital filter. ICLKD frequency is determined by the required output word rate and by the CMODE pin. If CMODE is low, ICLKD frequency should be 256 X the desired output word rate. If CMODE is high, ICLKD should be 384 X the desired output word rate. For example, with CMODE low, ICLKD should be 12.288 MHz for an output word rate of 48 kHz. This clock also generates OCLKD, which is always 128 X the output word rate. APD - Analog Power Down, PIN 6. Analog section power-down command. When high, the analog circuitry is in power-down mode. APD is normally connected to DPD when using the power down feature. If power down is not used, then connect APD to AGND. DPD - Digital Power Down, PIN 10 Digital section power-down command. Bringing DPD high puts the digital section into power-down mode. Upon returning low, the ADC starts an offset calibration cycle. This takes 4096 L/R periods (85.33 ms with a 12.288 MHz ICLKD). DCAL is high during the calibrate cycle and goes low upon completion. DPD is normally connected to APD when using the power down feature. A calibration cycle should always be initiated after applying power to the supply pins. ACAL - Analog Calibrate, PIN 7. Analog section calibration command. When high, causes the left and right channel modulator inputs to be internally connected to ZEROL and ZEROR inputs respectively. May be connected to DCAL. DS23F1 3-55 CS5336, CS5338, CS5339 CMODE - Clock Mode Select, PIN 12. CMODE should be tied low to select an ICLKD frequency of 256 X the output word rate. CMODE should be tied high to select an ICLKD frequency of 384 X the output word rate. SMODE - Serial Interface Mode Select, PIN 13. SMODE should be tied high to select serial interface master mode, where SCLK, FSYNC and L/R are all outputs, generated by internal dividers operating from ICLKD. SMODE should be tied low to select serial interface slave mode, where SCLK, FSYNC and L/R are all inputs. In slave mode, L/R, FSYNC and SCLK need to be derived from ICLKD using external dividers. Digital Outputs SDATA - Serial Data Output, PIN 16. Audio data bits are presented MSB first, in 2’s complement format. Additional tag bits, which indicate input overload and left/right channel data, are output immediately following each audio data word. DCAL - Digital Calibrate Output, PIN 9. DCAL rises immediately upon entering the power-down state (DPD brought high). It returns low 4096 L/R periods after leaving the power down state (DPD brought low), indicating the end of the offset calibration cycle (which = 85.33 ms with a 12.288 MHz ICLKD). May be connected to ACAL. OCLKD - Digital Section Output Clock, PIN 21. OCLKD is always 128 X the output word rate. Normally connected to ICLKA. Digital Inputs or Outputs SCLK - Serial Data Clock, PIN 15. Data is clocked out on the rising edge of SCLK for the CS5336 and CS5338. Data is clocked out on the falling edge of SCLK for the CS5339. In master mode (SMODE high), SCLK is a continuous output clock at 64 X the output word rate. In slave mode (SMODE low), SCLK is an input, which requires a continuously supplied clock at any frequency from 32 X to 128 X the output word rate (64 X is preferred). When FSYNC is high, SCLK clocks out serial data, except for the MSB which appears on SDATA when L/R changes. 3-56 DS23F1 CS5336, CS5338, CS5339 L/R - Left/Right Select, PIN 14. In master mode (SMODE high), L/R is an output whose frequency is at the output word rate. L/R edges occur 1 SCLK cycle before FSYNC rises. When L/R is high, left channel data is on SDATA, except for the first SCLK cycle. When L/R is low, right channel data is on SDATA, except for the first SCLK cycle. The MSB data bit appears on SDATA one SCLK cycle after L/R changes. In slave mode (SMODE low), L/R is an input which selects the left or right channel for output on SDATA. The rising edge of L/R starts the MSB of the left channel data. L/R frequency must be equal to the output word rate. Although the outputs of each channel are transmitted at different times, the two words in an L/R cycle represent simultaneously sampled analog inputs. FSYNC - Frame Synchronization Signal, PIN 17. In master mode (SMODE high), FSYNC is an output which goes high coincident with the start of the first SDATA bit (MSB) and falls low immediately after the last SDATA audio data bit (LSB). In slave mode (SMODE low), FSYNC is an input which controls the clocking out of the data bits on SDATA. FSYNC is normally tied high, which causes the data bits to be clocked out immediately following L/R transitions. If it is desired to delay the data bits from the L/R edge, then FSYNC must be low during the delay period. Bringing FSYNC high will then enable the clocking out of the SDATA bits. Note that the MSB will be clocked out based on the L/R edge, independent of the state of FSYNC. Miscellaneous NC - No Connection, PINS 8, 22. These two pins are bonded out to test outputs. They must not be connected to any external component or any length of PC trace. TST -Test Input, PIN 11. Allows access to the ADC test modes, which are reserved for factory use. Must be tied to DGND. DS23F1 3-57 CS5336, CS5338, CS5339 PARAMETER DEFINITIONS Resolution - The total number of possible output codes is equal to 2N, where N = the number of bits in the output word for each channel. Dynamic Range - Full scale (RMS) signal to broadband noise ratio. The broadband noise is measured over the specified bandwidth, and with an input signal 60dB below full-scale. Units in decibels. Signal-to-(Noise plus Distortion) Ratio - The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Total Harmonic Distortion - The ratio of the rms sum of all harmonics up to 20 kHz to the rms value of the signal. Units in percent. Interchannel Phase Deviation - The difference between the left and right channel sampling times. Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with the input under test grounded and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch - The decibels. gain difference between left and right channels. Units in Gain Error - The deviation of the measured full scale amplitude from the ideal full scale amplitude value. Gain Drift - The change in gain value with temperature. Units in ppm/°C. Bipolar Offset Error - The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below AGND). Units in LSBs. 3-58 DS23F1 CS5336, CS5338, CS5339 REFERENCES 1) "A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio" by D.R. Welland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention of the Audio Engineering Society, November 1988. 2) " The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC’s" by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 3) " An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Application Example" by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. Ordering Guide Model CS5336-KP CS5336-BP CS5338-KP CS5339-KP CS5336-KS CS5336-BS CS5338-KS CS5339-KS CS5336-TC CDB5336 CDB5338 CDB5339 Resolution 16-bits 16-bits 16-bits 16-bits 16-bits 16-bits 16-bits 16-bits 16-bits Passband 22 kHz 22 kHz 24 kHz 24 kHz 22 kHz 22 kHz 24 kHz 24 kHz 22 kHz SCLK ↑ active ↑ active ↑ active ↓ active ↑ active ↑ active ↑ active ↓ active ↑ active Temperature 0°C to 70 °C -40 to +85 °C 0°C to 70 °C 0°C to 70 °C 0°C to 70 °C -40 to +85 °C 0°C to 70 °C 0°C to 70 °C -55 to +125 °C Package 28-pin Plastic DIP 28-pin Plastic DIP 28-pin Plastic DIP 28-pin Plastic DIP 28-pin SOIC 28-pin SOIC 28-pin SOIC 28-pin SOIC 28-pin Sidebrazed Ceramic DIP CS5336 Evaluation Board CS5338 Evaluation Board CS5339 Evaluation Board DS23F1 3-59 Semiconductor Corporation CDB5336 CDB5338 CDB5339 General Description The CDB5336, CDB5338 & CDB5339 evaluation boards allow fast evaluation of the CS5336, CS5338 and CS5339 16-bit, stereo A/D converters. The boards generate all converter timing signals and provide both parallel and serial output interfaces. Evaluation requires a digital signal processor, a low-distortion signal source, and a power supply. Also included is a CS8402 digital audio transmitter I.C., which can generate AES/EBU, S/PDIF & EIAJ CP-340 compatible audio data. The evaluation boards may also be configured to accept external timing signals for operation in a user application during system development. Evaluation Board for CS5336, CS5338 & CS5339 Features • Demonstrates recommended layout and grounding arrangements • CS8402 Generates AES/EBU, S/PDIF & CP-340 Compatible Digital Audio • Buffered Serial Output Interface • 16-Bit Parallel Output Interface • Digital and Analog Patch Areas • On-board or externally supplied system timing -15V GND +15V GND +5V ORDERING INFORMATION: CDB5336, CDB5338, CDB5339 EXTCLKIN FSYNC DIGITAL PATCH AREA ANALOG PATCH AREA POWER SUPPLY REGULATION & CONDITIONING L/R CLOCK / TIMING AINR Input Buffer SCLK SERIAL OUTPUT DATA SDATA CS5336, CS5338, OR GENERATOR OFFSET CALIBRATION NETWORK SERIAL TO PARALLEL CONVERTER A IN L Input Buffer CS5339 A/D CONVERTER PARALLEL OUTPUT DATA CS8402 DIGITAL AUDIO LINE DRIVER DIGITAL AUDIO DATA AUG ’93 DS23DB5 3-60 Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445 7222 FAX: (512) 445 7581 CDB5336,8,9 Power Supply Circuitry The schematic diagram in Figure 1 shows the evaluation board power supply circuitry. Power is supplied to the evaluation board by five binding posts. The ±5 Volt analog power supply inputs of the converter are derived from ±15 Volts using the voltage regulators U10 and U11. The +5 Volt digital supply for the converter and the discrete logic on the board is provided by the +5V and DGND binding posts. D1, D2 and D4 are transient suppressors which also provide protection from incorrectly connected power supply leads. C25-C28, C30 and C31 provide general power supply filtering for the analog supplies. As shown in Figure 2, C10-C13 provide localized decoupling for the converter VA+ and VApins. Note that C13 is connected between VAand VA+ and not VA- and AGND. Space for a ferrite bead inductor, L1, has been provided so that the board may be modified to power the converter’s VD+ input directly from the VA+ supply. Note that the trace connecting the VD+ power to the VD+ of the converter must be bro+15V D2 AGND + D4 -15V D2 = D4 = 1N6276A 1.5KE D1 = P6KE-6V8P from Thomson +5V D1 DGND SW1 CAL 0.1uF C15 U7D + ken before L1 may be installed. R5 and C7 lowpass filter the analog logic power supply pin, VL+. The evaluation board uses both an analog and a digital ground plane which are connected at a single point by J1. This ground plane arrangement isolates the board’s digital logic from the analog circuitry. Offset Calibration & Reset Circuit Figure 1, shows the optional offset calibration circuit provided on the evaluation board. Upon power-up, this circuit provides a pulse on the Analog-to-Digital Converter’s DPD pin initiating an offset calibration cycle. Releasing SW1 also initiates an offset calibration cycle. P6 (see Figure 2) selects the signal source used during offset calibration. In the "AIN" position, the AINL and AINR inputs are selected during calibration, while in the "ZERO" position, the ZEROL and ZEROR inputs are selected. IN + C30 47 uF C31 47 uF C25 0.22 uF C26 0.22 uF IN U10 78L05 COM OUT C27 0.47 uF C28 0.47 uF J1 VA+ AGND DGND COM 79L05 OUT U11 VA9 VD+ U7E 8 RST CS8402 VD+ C8 47 uF C9 0.1 uF D3 1N4148 R26 10k 11 10 Cal (DPD CS5336) Figure 1. Power Supply and Reset Circuitry DS23DB5 3-61 CDB5336,8,9 0.1 uF C16 10 uF C17 + 28 VD+ VD+ + L1 18 1 uF C6 R5 51 VA+ + 1 uF C10 0.1 uF C12 1 + 1 uF C11 VA0.1 uF C13 VA5 24 19 R1 From Buffers Fig 3 51 R2 51 C2 10 nF NPO 3 R3* 51 C3* 10 nF C1 10 nF NPO 2 VALGND DGND AGND 0.1 uF C7 VA+ 4 VA+ 0.1 uF C5 VL+ 25 VL+ VD+ VREF 22 NC 8 NC APD DPD 6 10 Cal P6 Cal AIN ZERO 9 VD+ 12 R7 DCAL 20 k Pins 1,13 U9 ACAL DCAL 7 U1 CMODE CS5336 CS5338 CS5339 SMODE TST 13 11 L/R L/R 14 SDATA L/R SDATA 16 SCLK 15 SDATA 27 SCLK AINR FSYNC AINL ZEROL ZEROR 26 R4* 51 C4* 10 nF OCLKD 21 ICLKD ICLKA 23 ICLKA 17 20 FSYNC SCLK FSYNC ICLKD P7 EXT INT NC VD+ * Optional 7 3 U8A 0.1 uF MCK 8402 EXT CLKIN R6* 2 1 14 C14 0.1 uF 7 75 8 1 12.288 MHz Oscillator Module C15 14 U3 VD+ Figure 2 ADC Connections 3-62 DS23DB5 CDB5336,8,9 Analog Inputs As shown in Figure 2, the analog input signals are connected to the CS5336 via an RC network. R1 and C1 provide antialiasing and optimum source impedance for the right analog input channel while R2 and C2 do so for the left channel. The ZEROR and ZEROL inputs are tied to the analog ground plane on the board as shipped from the factory, but space is provided for an optional RC section on each. These RC sections may be added to model the output impedance of the analog signal source to minimize offset error during calibration. Figure 3 shows the optional input buffer circuit. This can be used as an example input buffer circuit for your application. If the ADC is driven from a 50Ω source impedance signal generator, the input buffer amplifiers may be bypassed. Place P8 and P9 jumpers in the OUT position, and short circuit R1 and R2. This ensures that the ADC is driven from a 50Ω source resistance. Also remove U13 op-amp, to remove the 1kΩ load impedance. Timing Generator P7 selects the master clock source supplied to the ICLKD pin of the converter. As shipped from the factory, P7 is set to the "INT" position to select the 12.288 MHz clock signal provided by U3. An external master clock signal may be connected to the EXTCLKIN connector and selected by placing P7 in the "EXT" position. Note that R6, tied between EXTCLKIN and GND, is available for impedance matching an external clock source. The board is shipped with SMODE high, which selects MASTER timing mode. In this mode, SCLK, L/R and FSYNC are all outputs, generated by the converter from ICLKD. Serial Output Interface The serial output interface is provided by the SDATA, SCLK, FSYNC and L/R BNC connectors on the evaluation board. These out1k VA+ R22 0.1 uF 1k AINL R21 2_ 3 8 1 C33 VA1k R24 6_ 5 U13B + MC33078P 7 OUT P9 C32 IN OUT 0.1 uF P8 U13A + 4 R1, Fig 2 1k AINR R23 IN R2, Fig 2 Figure 3. Input Buffer Circuit DS23DB5 3-63 CDB5336,8,9 VD+ 10 k SIP 142567893 OCLKD P4 DIPSW 8 SW 2 ____ PRO __ __ C7/C3 __ C1/FC0 __ __ C6/C2 __ ___ C9/C15 __ EM1/C8 __ EM0/C9 2 1 3 4 12 13 14 24 ___ RST R19 110 17 2 4 SCHOTT 67125450 FSYNC SDATA 12 13 U8D 74HC08 11 9 Q2 13 RESET2 D2 11 PULSE PE65612 12 _ L/R CS5336 R20 1 3 Digital Output FSYNC CS5336 3 2 4 5 6 8 7 1 14 15 13 12 11 9 10 16 5 VD+ 19 + C34 1 uF P3 CBL V R16 20 k C R17 20 k U R18 20 k 21 22 M0 M1 15 9 10 11 C24 0.1 uF 18 VD+ MCK 6 SCK GND CBL V C U CS8402 U2 CRE/FC1 ____ 16 RST TXP 20 23 M2 SDATA VD+ 8 FSYNC 7 TXN CS5336 74HC74 U12B CLK 8 __ Q2 SET2 10 R11 47 k +5 V Figure 4. CS8402 Digital Audio Line Driver Connections puts are buffered, as shown in Figure 5, in order to isolate the converter from the digital signal processor. If slave mode is selected by pulling SMODE low, then U9 (74HC243) will change to the opposite direction, and act as an input buffer. U9 is provided to protect against inadvertent external driving of SCLK, L/R and FSYNC while in MASTER mode. U9 is not necessary in your application circuit. 3-64 Jumper P4 allows the board to be configured for either the CS5336/38, or the CS5339, which have opposite polarities of SCLK. Parallel Output Interface Figure 6 depicts the parallel output interface on the evaluation board. 16-bit words are assembled from the serial data output of the converter. Each bit of serial data is clocked out of the converter DS23DB5 CDB5336,8,9 VD+ R8 13 SMODE 20 k 1 A-to-B Enable 13 B-to-A Enable 11 B1 10 B2 VCC U9 VD+ 14 7 GND 3 A1 A2 4 5 B4 A3 R10 20 k CS8402 Pin 6 4 5336/38 5337/39 P4 15 SCLK 17 FSYNC 14 L/R 16 SDATA 4 5 U8B SCLK FSYNC L/R SDATA SDATA VD+ 0.1 uF C20 SCLK FSYNC L/R 74HC243 9 B3 6 A4 8 6 9 U8C 10 74HC08 R9 20 k 8 SDATA U7B 3 Pin 11 U4, U5 595’s Figure 5. Serial Output Interface on the rising edge of SCLK and shifted into the 16-bit shift register formed by U4 and U5 on SCLK’s falling edge. After all data bits for the selected channel have been shifted into U4 and U5 the data is latched onto P1 by a delayed version of FSYNC. P5 selects the channel whose output data will be converted to parallel form and presented on P1. With P5 in the "B" (both) position, parallel data from one channel will be presented first with data from the other channel presented subsequently. In the "L" (left) position, only left channel conversions will be presented, while in the "R" (right) position only right channel conversions are presented. Two interface mechanisms are provided for reading the data from this port. With the first, the edges of L/R may be used to clock the parallel data into the digital signal processor. (Set jumper P2 into the L/R position.) Alternatively, a handshake protocol implemented with DACK and DRDY may be used to transfer data to the signal DS23DB5 processor. (Set jumper P2 to the DRDY position.) The fall of DRDY informs the digital signal processor that a new data word is available. The processor then reads the port and acknowledges the transfer by asserting DACK. Note that DRDY will not be asserted again unless DACK is momentarily brought high although new data will continue to be latched onto the port. Digital Audio Standard Interface Included on the evaluation board is a CS8402 Digital Audio Line Driver. This device can implement AES/EBU, S/PDIF and EIAJ CP-340 interface standards. Figure 4 shows the schematic for the CS8402. P3 allows the C, U and V bits to be driven from external logic using the CBL output for block synchronization. SW2 provides 8 DIP switches to select various modes and bits for the CS8402. Table 3 lists the settings for the professional mode which is the default setting for the evaluation board from the factory. The third switch selects between professional 3-65 CDB5336,8,9 X Y Z P1 L/R PIN14 U1 VD+ U7C C16 0.1uF 8 VD+ 5 6 R15 47 k GND U4 10 SRCLR 12 Latch CLK 11 Shift CLK VD+ 0.1 uF C29 DIN 14 9 DOUT 16 VCC QH 7 QG 6 QF 5 QE 4 Z Y RP3 DIP Resistor 68 1 16 2 3 4 5 6 7 8 15 14 13 12 11 10 9 X D15 (MSB) D14 D13 D12 D11 D10 D9 D8 VD+ P5 B L R 6 1 CLR 5 FSYNC PIN17 U1 2 D Q U12A Q 74HC595 Q D 3 QC 2 QB 1 Q A 15 OE 13 ICLKD PIN20 U1 3 CLK PRE 4 VCC GND 7 14 R11 VD+ 47 k P4 9 13 VD+ DOUT OE 16 VCC QH C17 QG 0.1uF 8 QF GND U5 QE 7 6 5 4 RP2 DIP Resistor 68 1 16 2 3 4 5 6 7 8 VD+ 0.1uF 1 C18 U7A 74HC14 13 12 11 47k R11 VD+ D 8 Q U6B 74HC74 9 CLK Q PRE 10 CLR R12 15 14 13 12 11 10 9 DACK 47k 68 R13 L/R P2 R14 68 L/R DRDY D7 D6 D5 D4 D3 D2 D1 D0 (LSB) DRDY 74HC595 Q 3 D 10 SRCLR QC 2 12 QB 1 Latch CLK 11 Shift CLK Q A 15 DIN 14 VD+ 2 14 7 VD+ 1 14 7 CLR 3 CLK 6 Q U6A 74HC74 2 5 Q D PRE 4 C19 0.1 uF SDATA Figure 6. Parallel Output Interface 3-66 DS23DB5 CDB5336,8,9 CONNECTOR +15 -15 AGND +5 DGND AINL AINR EXTCLKIN L/R SDATA SCLK FSYNC DIGITAL OUTPUT P3 P1 INPUT/OUTPUT input input input input input input input input output/input output output/input output/input output output/input output SIGNAL PRESENT +15 Volts from power supply -15 Volts from power supply analog ground connection from power supply +5V for ADC VD+ and discrete logic digital ground connection from power supply left channel analog input right channel analog input external master clock input left /right channel signal serial output data serial output clock data framing signal CS8402 digital output via transformer CS8402 C,U,V inputs; CBL output parallel output data Table 1. System Connections JUMPER P6 PURPOSE selects offset calibration input source POSITION AIN *ZERO P7 selects master clock source for CS5326 CLKIN selects channel for serial to parallel conversion *INT EXT *L R B FUNCTION SELECTED AINL and AINR selected during offset calibration ZEROL and ZEROR selected during offset calibration CLKIN provided by U3 CLKIN provided by EXTCLKIN BNC left channel data presented on P1 right channel data presented on P1 left then right channel data alternately presented on P1 DRDY selected to signal the arrival of new data for the selected channel L/R selected Buffer amplifier in circuit Buffer amplifier bypassed Correct SCLK for CS5337 & CS5339 Correct SCLK for CS5336 & CS5338 P5 P2 selects L/R or DRDY as the output status signal presented on P1 selects optional input buffers *DRDY L/R *IN OUT P8, P9 P4 selects device type 5337/39 5336/38 * Default setting from factory Table 2. Jumper Selectable Options DS23DB5 3-67 CDB5336,8,9 Switch# 3 1 default 5, 2 default 0=Closed, 1=Open PRO=0 CRE 0 1 C6, C7 1 1 0 0 C1 1 0 C9 1 0 EM1, EM0 1 1 0 0 1 0 1 0 1 0 1 0 Comment Professional Mode, C0=1 (default) Local Sample Address Counter & Reliability Flags Disabled Internally Generated (channel status bytes 14-17 and byte 22) C6,C7 - Sample Frequency 00 01 10 11 Not Indicated - Default to 48 kHz 48 kHz 44.1 kHz 32 kHz 4 default 6 default 8, 7 default C1 - Audio 0 - Normal Audio 1 - Non-Audio C8,C9,C10,C11 - Channel Mode (1 of 4 bits) 0000 - Not indicated - Default to 2-channel 0100 - Stereophonic C2,C3,C4 - Emphasis 000 100 110 111 Not Indicated - default to none No emphasis 50/15 µs CCITT J.17 Table 3. CS8402 Switch Definitions - Professional Mode and consumer modes; however, the CS8402 output to the transformer must be modified, as shown below Table 4, to be compatible with the consumer interface. Table 4 lists the switch settings for consumer mode. If the C input of connector P3 is used, the input bits are logically OR’ed with the appropriate DIP switch bits. In Tables 3 and 4, the ’C’ bits listed in the comment section are taken from the Digital Audio Interface specifications. As an example, switch 6 in the professional mode (Table 3) controls C9 which is the inverse of channel status bit 9 (also listed as byte 1, bit 1 in the CS8402 data sheet). Channel status bit 9 is one of four bits indicating channel mode. Therefore, using DIP switch 6, only two of the available channel modes may be selected. The C input port on connector P3 may be used to select other channel modes. See the 3-68 CS8401 & CS8402 part data sheet for more information on the operation of the CS8402. DS23DB5 CDB5336,8,9 Switch# 3 1, 4 0=Closed, 1=Open PRO=1 FC1, FC0 0 0 1 1 0 1 0 1 C3 1 0 Comment Consumer Mode, C0=0 (Note 1) C24,C25,C26,C27 - Sample Frequency (encoded 2 of 4 bits) 0000 0100 1100 0000 44.1 kHz 48 kHz 32 kHz 44.1 kHz, CD Mode 2 C3,C4,C5 - Emphasis (1 of 3 bits) 000 - None 100 - 50/15 µs C2 - Copy/Copyright 0 - Copy Inhibited/Copyright Asserted 1 - Copy Permitted/Copyright Not Asserted C15 - Generation Status 0 - Definition is based on category code. 1See CS8402 Data Sheet, Appendix A C8-C14 - Category Code (2 of 7 bits) 0000000 0100000 1000000 1100000 General PCM encoder/decoder Compact Disk - CD Digital Audio Tape - DAT 5 C2 1 0 6 C15 1 0 8, 7 C8, C9 1 1 0 0 1 0 1 0 Note: 1. The evaluation board is shipped from the factory in the Professional mode. Changing switch 3 to open places the CS8402 in Consumer mode; however, the hardware is not set up for consumer mode. To modify the hardware for Consumer mode, change R19 to 374Ω and add R20 at 90.9Ω. Then, as shown in the figure below, cut the trace connecting TXN to the transformer, and connect the transformer side to the ground hole provided. For a full explanation of the consumer hardware interface, see the CS8402 data sheet, Appendix B. Table 4. CS8402 Switch Definitions - Consumer Mode TXP 20 R19 374 1 3 Digital Output CS8402 U2 17 TXN 90.9 R20 2 4 SCHOTT 67125450 PULSE PE65612 DS23DB5 3-69 CDB5336,8,9 Figure 7. Top Ground Plane Layer (NOT TO SCALE) 3-70 DS23DB5 CDB5336,8,9 Figure 8. Bottom Trace Layer (NOT TO SCALE) DS23DB5 3-71 CDB5336,8,9 Figure 9. Component Layout (NOT TO SCALE) 3-72 DS23DB5