CS5345

CS5345 104 dB, 24-Bit, 192 kHz Stereo Audio ADC A/D Features Multi-Bit Delta Sigma Modulator 104 dB Dynamic Range -95 dB THD+N Stereo 6:1 Input Multiplexer Programmable Gain Amplifier (PGA) – ± 12 dB Gain, 0.5 dB Step Size – Zero Crossing, Click-Free Transitions Stereo Microphone Inputs – +32 dB Gain Stage – Low-Noise Bias Supply Up to 192 kHz Sampling Rates Selectable Serial Audio Interface Formats – Left-Justified up to 24-bit – I²S up to 24-bit High-Pass Filter or DC Offset Calibration General Description The CS5345 integrates an analog multiplexer, programmable gain amplifier, and stereo audio analog-to-digital converter. The CS5345 performs stereo analog-to-digital (A/D) conversion of up to 24-bit serial values at sample rates up to 192 kHz. A 6:1 stereo input multiplexer is included for selecting between line-level and microphone-level inputs. The microphone input path includes a +32 dB gain stage and a low-noise bias voltage supply. The PGA is available for line or microphone inputs and provides gain/attenuation of ± 12 dB in 0.5 dB steps. The output of the PGA is followed by an advanced 5thorder, multi-bit delta sigma modulator and digital filtering/decimation. Sampled data is transmitted by the serial audio interface at rates from 4 kHz to 192 kHz in either Slave or Master Mode. Integrated level translators allow easy interfacing between the CS5345 and other devices operating over a wide range of logic levels. The CS5345 is available in a 48-pin LQFP package in Commercial (-10° to +70° C) and Automotive (-40° to +105° C) grade. The CDB5345 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 41 for complete details. System Features Power-Down Mode +3.3 V to +5 V Analog Power Supply, Nominal +3.3 V to +5 V Digital Power Supply, Nominal Direct Interface with 1.8 V to 5 V Logic Levels Pin-Compatible with CS4245 1.8 V to 5 V 3.3 V to 5 V 3.3 V to 5 V Level Translator I²C/SPI Control Data Interrupt Overflow Reset Register Configuration PCM Serial Interface Internal Voltage Reference Left PGA Output Right PGA Output Stereo Input 1 Stereo Input 2 Stereo Input 3 PGA MUX PGA +32 dB High Pass Filter Low-Latency Anti-Alias Filter Multibit Oversampling ADC Multibit Oversampling ADC Serial Audio Output Level Translator High Pass Filter Low-Latency Anti-Alias Filter Stereo Input 4 / Mic Input 1 & 2 Stereo Input 5 Stereo Input 6 +32 dB http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) AUGUST '07 DS658F2 CS5345 TABLE OF CONTENTS 1. PIN DESCRIPTIONS ......................................................................................................................... 5 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7 SPECIFIED OPERATING CONDITIONS ............................................................................................. 7 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 7 ADC ANALOG CHARACTERISTICS ................................................................................................... 8 ADC ANALOG CHARACTERISTICS ................................................................................................. 10 ADC DIGITAL FILTER CHARACTERISTICS ..................................................................................... 11 PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 12 PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 13 PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 14 DC ELECTRICAL CHARACTERISTICS ............................................................................................. 15 DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 16 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 17 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................ 20 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 21 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 22 4. APPLICATIONS ................................................................................................................................... 23 4.1 Recommended Power-Up Sequence ............................................................................................. 23 4.2 System Clocking ............................................................................................................................. 23 4.2.1 Master Clock ......................................................................................................................... 23 4.2.2 Master Mode ......................................................................................................................... 24 4.2.3 Slave Mode ........................................................................................................................... 24 4.3 High-Pass Filter and DC Offset Calibration .................................................................................... 24 4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................ 25 4.5 Input Connections ........................................................................................................................... 25 4.6 PGA Auxiliary Analog Output ......................................................................................................... 25 4.7 Control Port Description and Timing ............................................................................................... 26 4.7.1 SPI Mode ............................................................................................................................... 26 4.7.2 I²C Mode ................................................................................................................................ 26 4.8 Interrupts and Overflow .................................................................................................................. 28 4.9 Reset .............................................................................................................................................. 28 4.10 Synchronization of Multiple Devices ............................................................................................. 28 4.11 Grounding and Power Supply Decoupling .................................................................................... 28 5. REGISTER QUICK REFERENCE ........................................................................................................ 30 6. REGISTER DESCRIPTION .................................................................................................................. 31 6.1 Chip ID - Register 01h .................................................................................................................... 31 6.2 Power Control - Address 02h ......................................................................................................... 31 6.2.1 Freeze (Bit 7) ......................................................................................................................... 31 6.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 31 6.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 31 6.2.4 Power-Down Device (Bit 0) ................................................................................................... 31 6.3 ADC Control - Address 04h ............................................................................................................ 32 6.3.1 Functional Mode (Bits 7:6) .................................................................................................... 32 6.3.2 Digital Interface Format (Bit 4) .............................................................................................. 32 6.3.3 Mute (Bit 2) ............................................................................................................................ 32 6.3.4 High-Pass Filter Freeze (Bit 1) .............................................................................................. 32 6.3.5 Master / Slave Mode (Bit 0) ................................................................................................... 32 6.4 MCLK Frequency - Address 05h .................................................................................................... 33 6.4.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 33 6.5 PGAOut Control - Address 06h ...................................................................................................... 33 6.5.1 PGAOut Source Select (Bit 6) ............................................................................................... 33 6.6 Channel B PGA Control - Address 07h .......................................................................................... 33 2 DS658F2 CS5345 6.6.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 33 6.7 Channel A PGA Control - Address 08h .......................................................................................... 34 6.7.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 34 6.8 ADC Input Control - Address 09h ................................................................................................... 34 6.8.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 34 6.8.2 Analog Input Selection (Bits 2:0) ........................................................................................... 35 6.9 Active Level Control - Address 0Ch ................................................................................................ 35 6.9.1 Active High/Low (Bit 0) .......................................................................................................... 35 6.10 Interrupt Status - Address 0Dh ..................................................................................................... 35 6.10.1 Clock Error (Bit 3) ................................................................................................................ 36 6.10.2 Overflow (Bit 1) .................................................................................................................... 36 6.10.3 Underflow (Bit 0) .................................................................................................................. 36 6.11 Interrupt Mask - Address 0Eh ....................................................................................................... 36 6.12 Interrupt Mode MSB - Address 0Fh .............................................................................................. 36 6.13 Interrupt Mode LSB - Address 10h ............................................................................................... 36 7. PARAMETER DEFINITIONS ................................................................................................................ 37 8. FILTER PLOTS .................................................................................................................................. 38 9. PACKAGE DIMENSIONS .................................................................................................................... 40 10. THERMAL CHARACTERISTICS AND SPECIFICATIONS ............................................................. 40 11. ORDERING INFORMATION ........................................................................................................ 41 12. REVISION HISTORY .......................................................................................................................... 41 LIST OF FIGURES Figure 1.Master Mode Serial Audio Port Timing ....................................................................................... 18 Figure 2.Slave Mode Serial Audio Port Timing ......................................................................................... 18 Figure 3.Format 0, Left-Justified up to 24-Bit Data ................................................................................... 19 Figure 4.Format 1, I²S up to 24-Bit Data ................................................................................................... 19 Figure 5.Control Port Timing - I²C Format ................................................................................................. 20 Figure 6.Control Port Timing - SPI Format ................................................................................................ 21 Figure 7.Typical Connection Diagram ....................................................................................................... 22 Figure 8.Master Mode Clocking ................................................................................................................ 24 Figure 9.Analog Input Architecture ............................................................................................................ 25 Figure 10.Control Port Timing in SPI Mode .............................................................................................. 26 Figure 11.Control Port Timing, I²C Write ................................................................................................... 27 Figure 12.Control Port Timing, I²C Read ................................................................................................... 27 Figure 13.Single-Speed Stopband Rejection ............................................................................................ 38 Figure 14.Single-Speed Stopband Rejection ............................................................................................ 38 Figure 15.Single-Speed Transition Band (Detail) ...................................................................................... 38 Figure 16.Single-Speed Passband Ripple ................................................................................................ 38 Figure 17.Double-Speed Stopband Rejection ........................................................................................... 38 Figure 18.Double-Speed Stopband Rejection ........................................................................................... 38 Figure 19.Double-Speed Transition Band (Detail) .................................................................................... 39 Figure 20.Double-Speed Passband Ripple ............................................................................................... 39 Figure 21.Quad-Speed Stopband Rejection ............................................................................................. 39 Figure 22.Quad-Speed Stopband Rejection ............................................................................................. 39 Figure 23.Quad-Speed Transition Band (Detail) ....................................................................................... 39 Figure 24.Quad-Speed Passband Ripple ................................................................................................. 39 LIST OF TABLES Table 1. Speed Modes .............................................................................................................................. 23 Table 2. Common Clock Frequencies ....................................................................................................... 23 Table 3. Slave Mode Serial Bit Clock Ratios ............................................................................................. 24 Table 4. Device Revision .......................................................................................................................... 31 DS658F2 3 CS5345 Table 5. Freeze-able Bits .......................................................................................................................... 31 Table 6. Functional Mode Selection .......................................................................................................... 32 Table 7. Digital Interface Formats ............................................................................................................. 32 Table 8. MCLK Frequency ........................................................................................................................ 33 Table 9. PGAOut Source Selection ........................................................................................................... 33 Table 10. Example Gain and Attenuation Settings ................................................................................... 34 Table 11. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 35 Table 12. Analog Input Multiplexer Selection ............................................................................................ 35 4 DS658F2 CS5345 1. PIN DESCRIPTIONS OVFL SDOUT DGND MCLK LRCK SCLK 48 47 46 45 44 43 42 41 40 39 38 37 SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN VLC RESET AIN3A AIN3B AIN2A AIN2B AIN1A AIN1B TSTI INT NC NC NC VD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TSTO FILT+ TSTO VQ AIN4A/MICIN1 AIN4B/MICIN2 AGND AFILTA AFILTB VA AIN5A AIN5B 36 35 34 33 32 31 30 29 28 27 26 25 VLS TSTO NC NC AGND AGND VA PGAOUTB PGAOUTA AIN6B AIN6A MICBIAS CS5345 Pin Name SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN VLC RESET AIN3A AIN3B AIN2A AIN2B # 1 2 3 4 5 6 7 8 9 10 Pin Description Serial Control Data (Input/Output) - SDA is a data I/O in I²C® Mode. CDOUT is the output data line for the control port interface in SPITM Mode. Serial Control Port Clock (Input) - Serial clock for the serial control port. Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS is the chip-select signal for SPI format. Address Bit 1 (I²C) / Serial Control Data Input (SPI) (Input) - AD1 is a chip address pin in I²C Mode; CDIN is the input data line for the control port interface in SPI Mode. Control Port Power (Input) - Determines the required signal level for the control port interface. Refer to the Recommended Operating Conditions for appropriate voltages. Reset (Input) - The device enters a low-power mode when this pin is driven low. Stereo Analog Input 3 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Stereo Analog Input 2 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. DS658F2 5 CS5345 AIN1A AIN1B AGND VA AFILTA AFILTB VQ TSTO FILT+ TSTO AIN4A/MICIN1 AIN4B/MICIN2 AIN5A AIN5B MICBIAS AIN6A AIN6B PGAOUTA PGAOUTB VA AGND NC TSTO VLS TSTI NC SDOUT SCLK LRCK MCLK DGND VD INT OVFL 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38, 39, 40 41 42 43 44 45 46 47 48 Stereo Analog Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Analog Ground (Input) - Ground reference for the internal analog section. Analog Power (Input) - Positive power for the internal analog section. Antialias Filter Connection (Output) - Antialias filter connection for the channel A ADC input. Antialias Filter Connection (Output) - Antialias filter connection for the channel B ADC input. Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. Test Pin (Output) - This pin must be left unconnected. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Test Pin - This pin must be left unconnected. Stereo Analog Input 4 / Microphone Input 1 & 2 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Stereo Analog Input 5 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Microphone Bias Supply (Output) - Low-noise bias supply for external microphone. Electrical characteristics are specified in the DC Electrical Characteristics specification table. Stereo Analog Input 6 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. PGA Analog Audio Output (Output) - Either an analog output from the PGA block or high impedance. See “PGAOut Source Select (Bit 6)” on page 33. Analog Power (Input) - Positive power for the internal analog section. Analog Ground (Input) - Ground reference for the internal analog section. No Connect - These pins are not connected internally and should be tied to ground to minimize any potential coupling effects. Test Pin (Output) - This pin must be left unconnected. Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages. Test Pin (Input) - This pin must be connected to ground. No Connect - These pins are not connected internally and should be tied to ground to minimize any potential coupling effects. Serial Audio Data Output (Output) - Output for two’s complement serial audio data. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the ADC’s delta-sigma modulators. Digital Ground (Input) - Ground reference for the internal digital section. Digital Power (Input) - Positive power for the internal digital section. Interrupt (Output) - Indicates an interrupt condition has occurred. Overflow (Output) - Indicates an ADC overflow condition is present. 6 DS658F2 CS5345 2. CHARACTERISTICS AND SPECIFICATIONS SPECIFIED OPERATING CONDITIONS AGND = DGND = 0 V; All voltages with respect to ground. Parameters DC Power Supplies: Analog Digital Logic - Serial Port Logic - Control Port Ambient Operating Temperature (Power Applied) Commercial Automotive Symbol VA VD VLS VLC TA TA Min 3.13 3.13 1.71 1.71 -10 -40 Nom 5.0 3.3 3.3 3.3 - Max 5.25 (Note 1) 5.25 5.25 +70 +105 Units V V V V °C °C Notes: 1. Maximum of VA+0.25 V or 5.25 V, whichever is less. ABSOLUTE MAXIMUM RATINGS AGND = DGND = 0 V All voltages with respect to ground. (Note 2) Parameter DC Power Supplies: Analog Digital Logic - Serial Port Logic - Control Port (Note 3) Logic - Serial Port Logic - Control Port Symbol VA VD VLS VLC Iin VINA VIND-S VIND-C TA Tstg Min -0.3 -0.3 -0.3 -0.3 AGND-0.3 -0.3 -0.3 -50 -65 Max +6.0 +6.0 +6.0 +6.0 ±10 VA+0.3 VLS+0.3 VLC+0.3 +125 +150 Units V V V V mA V V V °C °C Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature 2. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 3. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. DS658F2 7 CS5345 ADC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; TA = -10° to +70° C for Commercial or -40° to +85° C for Automotive; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48/96/192 kHz.; All connections as shown in Figure 7 on page 22. Line-Level Inputs Commercial Grade Parameter Symbol Dynamic Performance for VA = 4.75 V to 5.25 V Dynamic Range PGA Setting: -12 dB to +6 dB A-weighted unweighted 40 kHz bandwidth unweighted PGA Setting: +12 dB Gain A-weighted unweighted 40 kHz bandwidth unweighted 98 95 92 89 104 101 98 98 95 92 96 93 90 87 104 101 98 98 95 92 dB dB dB dB dB dB Automotive Grade Min Typ Max Unit Min Typ Max (Note 6) (Note 6) Total Harmonic Distortion + Noise (Note 5) PGA Setting: -12 dB to +6 dB -1 dB -20 dB -60 dB (Note 6) 40 kHz bandwidth -1 dB THD+N PGA Setting: +12 dB Gain -1 dB -20 dB -60 dB (Note 6) 40 kHz bandwidth -1 dB - -95 -81 -41 -92 -92 -75 -35 -89 -89 -86 - - -95 -81 -41 -92 -92 -75 -35 -89 -87 -84 - dB dB dB dB dB dB dB dB Dynamic Performance for VA = 3.13 V to 3.46 V Dynamic Range PGA Setting: -12 dB to +6 dB A-weighted unweighted 40 kHz bandwidth unweighted PGA Setting: +12 dB Gain A-weighted unweighted 40 kHz bandwidth unweighted 93 90 89 86 101 98 95 95 92 89 91 88 87 84 101 98 95 95 92 89 dB dB dB dB dB dB (Note 6) (Note 6) Total Harmonic Distortion + Noise (Note 5) PGA Setting: -12 dB to +6 dB -1 dB -20 dB -60 dB (Note 6) 40 kHz bandwidth -1 dB THD+N PGA Setting: +12 dB Gain -1 dB -20 dB -60 dB (Note 6) 40 kHz bandwidth -1 dB - -92 -78 -38 -84 -89 -72 -32 -81 -86 -83 - - -92 -78 -38 -84 -89 -72 -32 -81 -84 -81 - dB dB dB dB dB dB dB dB 8 DS658F2 CS5345 Line-Level Inputs Commercial Grade Parameter Interchannel Isolation Automotive Grade Min - Symbol Min - Typ 90 - Max ±10 - Typ 90 - Max ±10 - Unit dB % ppm/°C Vpp kΩ % DC Accuracy Gain Error Gain Drift ±100 ±100 Line-Level Input Characteristics Full-scale Input Voltage Input Impedance (Note 4) Maximum Interchannel Input Impedance Mismatch 0.51*VA 0.57*VA 0.63*VA 0.51*VA 0.57*VA 0.63*VA 6.12 6.8 7.48 5.44 6.8 8.16 5 5 - Line-Level and Microphone-Level Inputs Commercial Grade Parameter DC Accuracy Interchannel Gain Mismatch 0.1 0.5 0.4 0.1 0.5 0.4 dB dB dB Automotive Grade Min Typ Max Unit Symbol Min Typ Max Programmable Gain Characteristics Gain Step Size Absolute Gain Step Error 4. Valid for the selected input pair. DS658F2 9 CS5345 ADC ANALOG CHARACTERISTICS (Continued) Microphone-Level Inputs Commercial Grade Parameter Symbol Dynamic Performance for VA = 4.75 V to 5.25 V Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 5) PGA Setting: -12 dB to 0 dB -1 dB -20 dB THD+N -60 dB PGA Setting: +12 dB -1 dB 77 74 83 80 75 72 83 80 dB dB Automotive Grade Min Typ Max Unit Min Typ Max 65 62 71 68 - 63 60 71 68 - dB dB - -80 -60 -20 -74 - - -80 -60 -20 -72 - dB dB dB - -68 - - -68 - dB Dynamic Performance for VA = 3.13 V to 3.46 V Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 5) PGA Setting: -12 dB to 0 dB -1 dB -20 dB THD+N -60 dB PGA Setting: +12 dB -1 dB Interchannel Isolation 77 74 83 80 75 72 83 80 dB dB 65 62 71 68 - 63 60 71 68 - dB dB - -80 -60 -20 -74 - - -80 -60 -20 -72 - dB dB dB - -68 80 ±5 - - -68 80 ±5 - dB dB % ppm/°C Vpp kΩ DC Accuracy Gain Error Gain Drift ±300 ±300 Microphone-Level Input Characteristics Full-scale Input Voltage Input Impedance (Note 7) 0.013*VA 0.017*VA 0.021*VA 0.013*VA 0.017*VA 0.021*VA 60 60 - 5. Referred to the typical line-level full-scale input voltage 6. Valid for Double- and Quad-Speed Modes only. 7. Valid when the microphone-level inputs are selected. 10 DS658F2 CS5345 ADC DIGITAL FILTER CHARACTERISTICS Parameter (Notes 8, 10) Single-Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd (-0.1 dB) 0 0.5688 70 0 0.5604 69 tgd 0 0.5000 60 tgd (Note 9) (Note 9) 12/Fs 9/Fs 5/Fs 1 20 10 105/Fs 0.4896 0.035 0.4896 0.025 0.2604 0.025 0 Fs dB Fs dB s Fs dB Fs dB s Fs dB Fs dB s Hz Hz Deg dB s Symbol Min Typ Max Unit Double-Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (-0.1 dB) Quad-Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (-0.1 dB) High-Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time -3.0 dB -0.13 dB @ 20 Hz 8. Filter response is guaranteed by design. 9. Response shown is for Fs = 48 kHz. 10. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 13 to 24) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. DS658F2 11 CS5345 PGAOUT ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; TA = -10° to +70° C for Commercial or -40° to +85° C for Automotive; Input test signal: 1 kHz sine wave; Measurement bandwidth: 10 Hz to 20 kHz; Fs = 48/96/192 kHz; Synchronous mode; All connections as shown in Figure 7 on page 22. VA = 4.75 V to 5.25 V Commercial Grade Parameter Symbol Min Typ Dynamic Performance with PGA Line-Level Input Selected Dynamic Range PGA Setting: -12 dB to +6 dB A-weighted unweighted PGA Setting: +12 dB Gain A-weighted unweighted Total Harmonic Distortion + Noise (Note 11) PGA Setting: -12 dB to +6 dB -1 dB -20 dB -60 dB PGA Setting: +12 dB Gain -1 dB -20 dB -60 dB Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 11) PGA Setting: -12 dB to 0 dB -1 dB -20 dB THD+N -60 dB PGA Setting: +12 dB -1 dB 77 74 83 80 75 72 83 80 dB dB 98 95 104 101 96 93 104 101 dB dB Automotive Grade Min Typ Max Unit Max 92 89 98 95 - 90 87 98 95 - dB dB THD+N - -80 -81 -41 -74 - - -80 -81 -41 -72 - dB dB dB - -80 -75 -35 -74 - - -80 -75 -35 -72 - dB dB dB Dynamic Performance with PGA Mic-Level Input Selected 65 62 71 68 - 63 60 71 68 - dB dB - -74 -60 -20 -68 - - -74 -60 -20 -66 - dB dB dB - -68 - - -68 - dB 11. Referred to the typical Line-Level Full-Scale Input Voltage. 12 DS658F2 CS5345 PGAOUT ANALOG CHARACTERISTICS (Continued) VA = 3.13 V to 3.46 V Commercial Grade Parameter Symbol Min Typ Dynamic Performance with PGA Line-Level Input Selected Dynamic Range PGA Setting: -12 dB to +6 dB A-weighted unweighted PGA Setting: +12 dB Gain A-weighted unweighted Total Harmonic Distortion + Noise (Note 11) PGA Setting: -12 dB to +6 dB -1 dB -20 dB -60 dB PGA Setting: +12 dB Gain -1 dB -20 dB -60 dB Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 11) PGA Setting: -12 dB to 0 dB -1 dB -20 dB THD+N -60 dB PGA Setting: +12 dB -1 dB 77 74 83 80 75 72 83 80 dB dB 93 90 101 98 91 88 101 98 dB dB Automotive Grade Min Typ Max Unit Max 89 86 95 92 - 87 84 95 92 - dB dB THD+N - -80 -78 -38 -74 - - -80 -78 -38 -72 - dB dB dB - -80 -72 -32 -74 - - -80 -72 -32 -72 - dB dB dB Dynamic Performance with PGA Mic Level-Input Selected 65 62 71 68 - 63 60 71 68 - dB dB - -74 -60 -20 -68 - - -74 -60 -20 -66 - dB dB dB - -68 - - -68 - dB DS658F2 13 CS5345 PGAOUT ANALOG CHARACTERISTICS (Continued) VA = 3.13 V to 5.25 V Commercial Grade Parameter Symbol DC Accuracy with PGA Line Level Input Selected Interchannel Gain Mismatch Gain Error Gain Drift Automotive Grade Min - Min - Typ 0.1 ±5 ±100 0.3 ±5 ±300 180 - Max - Typ 0.1 ±5 ±100 0.3 ±5 ±300 180 - Max +0.1dB 1 20 Unit dB % ppm/°C dB % ppm/°C dB deg μA kΩ pF DC Accuracy with PGA Mic Level Input Selected Interchannel Gain Mismatch Gain Error Gain Drift Analog Output Frequency Response 10 Hz to 20 kHz Analog In to Analog Out Phase Shift DC Current draw from a PGAOUT pin AC-Load Resistance Load Capacitance (Note 12) IOUT RL CL -0.1dB 100 +0.1dB -0.1dB 1 100 20 - 12. Guaranteed by design. 14 DS658F2 CS5345 DC ELECTRICAL CHARACTERISTICS AGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode. Parameter Power Supply Current (Normal Operation) VA = 5 VA = 3.3 VD, VLS, VLC = 5 VD, VLS, VLC = 3.3 V V V V Symbol IA IA ID ID IA ID PSRR VQ (Note 15) IQ ZQ FILT+ MICBIAS IMB Min - Typ 41 37 39 23 0.50 0.54 400 198 4.2 55 0.5 x VA 23 VA 0.8 x VA - Max 50 45 47 28 485 241 1 2 Unit mA mA mA mA mA mA mW mW mW dB VDC μA kΩ VDC VDC mA Power Supply Current (Power-Down Mode) (Note 13) Power Consumption (Normal Operation) (Power-Down Mode) VA = 5 V VLS, VLC, VD=5 V VA, VD, VLS, VLC = 5 V VA, VD, VLS, VLC = 3.3 V VA, VD, VLS, VLC = 5 V (Note 14) Power Supply Rejection Ratio (1 kHz) VQ Characteristics Quiescent Voltage DC Current from VQ VQ Output Impedance FILT+ Nominal Voltage Microphone Bias Voltage Current from MICBIAS 13. Power-Down Mode is defines as RESET = Low with all clock and data lines held static and no analog input. 14. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram. 15. Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage through the electrolytic de-coupling capacitors. DS658F2 15 CS5345 DIGITAL INTERFACE CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 1.71 V to 5.25 V. Parameters (Note 16) High-Level Input Voltage VL = 1.71 V VL > 2.0 V Low-Level Input Voltage High-Level Output Voltage at Io = 2 mA Low-Level Output Voltage at Io = 2 mA Input Leakage Current Input Capacitance Minimum OVFL Active Time Serial Port Control Port Serial Port Control Port Serial Port Control Port Serial Port Control Port Serial Port Control Port (Note 17) VIH VIH VIH VIH VIL VIL VOH VOH VOL VOL Iin 0.8xVLS 0.8xVLC 0.7xVLS 0.7xVLC VLS-1.0 VLC-1.0 10 ---------------LRCK 6 Symbol Min Typ - Max 0.2xVLS 0.2xVLC 0.4 0.4 ±10 1 - Units V V V V V V V V V V μA pF μs 16. Serial Port signals include: MCLK, SCLK, LRCK, SDOUT. Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, RESET, INT, OVFL. 17. Guaranteed by design. 16 DS658F2 CS5345 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT Logic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VL, CL = 20 pF. (Note 18) Parameter Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode Symbol Fs Fs Fs fmclk tclkhl Min 4 50 100 1.024 8 -10 0 40 Typ 50 50 50 - Max 50 100 200 51.200 10 36 60 - Unit kHz kHz kHz MHz ns % % ns ns % ns MCLK Specifications MCLK Frequency MCLK Input Pulse Width High/Low Master Mode LRCK Duty Cycle SCLK Duty Cycle SCLK falling to LRCK edge SCLK falling to SDOUT valid tslr tsdo Slave Mode LRCK Duty Cycle SCLK Period Single-Speed Mode tsclkw tsclkw tsclkw tsclkh tsclkl tslr tsdo 10 -------------------( 128 ) Fs 10 ----------------( 64 ) Fs 10 ----------------( 64 ) Fs 30 48 -10 0 9 9 9 Double-Speed Mode - - ns Quad-Speed Mode SCLK Pulse Width High SCLK Pulse Width Low SCLK falling to LRCK edge SCLK falling to SDOUT valid - 10 36 ns ns ns ns ns 18. See Figure 1 and Figure 2 on page 18. DS658F2 17 CS5345 LRCK Output t SCLK Output t SDOUT sdo slr Figure 1. Master Mode Serial Audio Port Timing LRCK Input t SCLK Input t SDOUT sdo t sclkw t sclkh t slr sclkl Figure 2. Slave Mode Serial Audio Port Timing 18 DS658F2 CS5345 LRCK SCLK SDATA Channel A - Left Channel B - Right MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 3. Format 0, Left-Justified up to 24-Bit Data LRCK SCLK SDATA Channel A - Left Channel B - Right MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 4. Format 1, I²S up to 24-Bit Data DS658F2 19 CS5345 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL = 30 pF. Parameter SCL Clock Frequency RESET Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 20) (Note 20) (Note 19) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc, trd tfc, tfd tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 Max 100 1 300 1000 Unit kHz ns µs µs µs µs µs µs ns µs ns µs ns 19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 20. Guaranteed by design. RST t Stop irs Sta rt R e p e ate d Sta rt t rd t fd Stop SDA t buf t hdst t high t hdst t fc t susp SCL t t t sud t ack t sust t rc lo w hdd Figure 5. Control Port Timing - I²C Format 20 DS658F2 CS5345 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL = 30 pF. Parameter CCLK Clock Frequency RESET Rising Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 22) (Note 22) (Note 21) Symbol fsck tsrs tcsh tcss tscl tsch tdsu tdh tpd tr1 tf1 tr2 tf2 Min 500 1.0 20 66 66 40 15 - Max 6.0 50 25 25 100 100 Units MHz ns μs ns ns ns ns ns ns ns ns ns ns 21. Data must be held for sufficient time to bridge the transition time of CCLK. 22. For fsck