CS5346-DQZR

CS5346 103 dB, 192 kHz, Stereo Audio ADC with 6:1 Input Mux ADC Features Multi-bit Delta Sigma Modulator 103 dB Dynamic Range -95 dB THD+N Stereo 6:1 Input Multiplexer Programmable Gain Amplifier (PGA) – ± 12 dB Gain, 0.5 dB Step Size – Zero-crossing, Click-free Transitions Stereo Microphone Inputs – +32 dB Gain Stage – Low-noise Bias Supply Up to 192 kHz Sampling Rates Selectable 24-bit, Left-justified or I²S Serial Audio Interface Formats General Description The CS5346 integrates an analog multiplexer, programmable gain amplifier, and stereo audio analog-to-digital converter. The CS5346 performs stereo analog-to-digital (A/D) conversion of 24-bit serial values at sample rates up to 192 kHz. A 6:1 stereo input multiplexer is included for selecting between line-level and microphone-level inputs. The microphone input path includes a +32 dB gain stage and a low-noise bias voltage supply. The PGA is available for line or microphone inputs and provides gain/attenuation of ±12 dB in 0.5 dB steps. The output of the PGA is followed by an advanced 5thorder, multi-bit delta sigma modulator and digital filtering/decimation. Sampled data is transmitted by the serial audio interface at rates from 8 kHz to 192 kHz in either Slave or Master Mode. Integrated level translators allow easy interfacing between the CS5346 and other devices operating over a wide range of logic levels. The CS5346 is available in a 48-pin LQFP package in Commercial (-40° to +85° C) and Automotive (-40° to +105° C) grades. The CDB5346 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 40 for complete details. System Features Power-down Mode +5 V Analog Power Supply, Nominal +3.3 V Digital Power Supply, Nominal Direct Interface with 3.3 V to 5 V Logic Levels Pin Compatible with CS5345* *See Section 2. on page 7 for more details. 3.3 V to 5 V 3.3 V 5V Level Translator I²C /SPI™ Control Data Interrupt Overflow Reset ® Left PGA Output Register Configuration PCM Serial Interface Internal Voltage Reference Right PGA Output Stereo Input 1 Stereo Input 2 Stereo Input 3 PGA MUX PGA +32 dB High Pass Filter Low-Latency Anti-Alias Filter Multibit Oversampling ADC Multibit Oversampling ADC Serial Audio Output Level Translator Stereo Input 4 / Mic Input 1 & 2 +32 dB High Pass Filter Low-Latency Anti-Alias Filter Stereo Input 5 Stereo Input 6 Preliminary Product Information http://www.cirrus.com This document contains information for a product under development. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved) NOVEMBER ‘08 DS861PP1 CS5346 TABLE OF CONTENTS 1. PIN DESCRIPTIONS - CS5346 ............................................................................................................. 5 2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES ..................................................................... 7 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8 RECOMMENDED OPERATING CONDITIONS ................................................................................... 8 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 8 ANALOG CHARACTERISTICS (COMMERCIAL) ................................................................................ 9 ANALOG CHARACTERISTICS (COMMERCIAL) CONT. .................................................................. 10 ANALOG CHARACTERISTICS (AUTOMOTIVE) ............................................................................... 11 ANALOG CHARACTERISTICS (AUTOMOTIVE) CONT. ................................................................... 12 DIGITAL FILTER CHARACTERISTICS .............................................................................................. 13 DC ELECTRICAL CHARACTERISTICS ............................................................................................. 14 DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 15 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 16 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................ 18 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 19 4. TYPICAL CONNECTION DIAGRAM ................................................................................................... 20 5. APPLICATIONS ................................................................................................................................... 21 5.1 Recommended Power-Up Sequence ............................................................................................. 21 5.2 System Clocking ............................................................................................................................. 21 5.2.1 Master Clock ......................................................................................................................... 21 5.2.2 Master Mode ......................................................................................................................... 22 5.2.3 Slave Mode ........................................................................................................................... 22 5.3 High-Pass Filter and DC Offset Calibration .................................................................................... 22 5.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................ 23 5.5 Input Connections ........................................................................................................................... 23 5.5.1 Analog Input Configuration for 1 VRMS Input Levels ............................................................ 23 5.5.2 Analog Input Configuration for 2 VRMS Input Levels ............................................................ 24 5.6 PGA Auxiliary Analog Output ......................................................................................................... 25 5.7 Control Port Description and Timing ............................................................................................... 25 5.7.1 SPI Mode ............................................................................................................................... 25 5.7.2 I²C Mode ................................................................................................................................ 26 5.8 Interrupts and Overflow .................................................................................................................. 27 5.9 Reset .............................................................................................................................................. 28 5.10 Synchronization of Multiple Devices ............................................................................................. 28 5.11 Grounding and Power Supply Decoupling .................................................................................... 28 6. REGISTER QUICK REFERENCE ........................................................................................................ 29 7. REGISTER DESCRIPTION .................................................................................................................. 30 7.1 Chip ID - Register 01h .................................................................................................................... 30 7.2 Power Control - Address 02h ......................................................................................................... 30 7.2.1 Freeze (Bit 7) ......................................................................................................................... 30 7.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 30 7.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 30 7.2.4 Power-Down Device (Bit 0) ................................................................................................... 30 7.3 ADC Control - Address 04h ............................................................................................................ 31 7.3.1 Functional Mode (Bits 7:6) .................................................................................................... 31 7.3.2 Digital Interface Format (Bit 4) .............................................................................................. 31 7.3.3 Mute (Bit 2) ............................................................................................................................ 31 7.3.4 High-Pass Filter Freeze (Bit 1) .............................................................................................. 31 7.3.5 Master / Slave Mode (Bit 0) ................................................................................................... 31 7.4 MCLK Frequency - Address 05h .................................................................................................... 32 7.4.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 32 7.5 PGAOut Control - Address 06h ...................................................................................................... 32 2 DS861PP1 CS5346 7.5.1 PGAOut Source Select (Bit 6) ............................................................................................... 32 7.6 Channel B PGA Control - Address 07h .......................................................................................... 32 7.6.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 32 7.7 Channel A PGA Control - Address 08h .......................................................................................... 33 7.7.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 33 7.8 ADC Input Control - Address 09h ................................................................................................... 33 7.8.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 33 7.8.2 Analog Input Selection (Bits 2:0) ........................................................................................... 34 7.9 Active Level Control - Address 0Ch ................................................................................................ 34 7.9.1 Active High/ Low (Bit 0) ......................................................................................................... 34 7.10 Status - Address 0Dh ................................................................................................................... 34 7.10.1 Clock Error (Bit 3) ................................................................................................................ 35 7.10.2 Overflow (Bit 1) .................................................................................................................... 35 7.10.3 Underflow (Bit 0) .................................................................................................................. 35 7.11 Status Mask - Address 0Eh .......................................................................................................... 35 7.12 Status Mode MSB - Address 0Fh ................................................................................................. 35 7.13 Status Mode LSB - Address 10h .................................................................................................. 35 8. PARAMETER DEFINITIONS ................................................................................................................ 36 9. FILTER PLOTS ..................................................................................................................................... 37 10. PACKAGE DIMENSIONS .................................................................................................................. 39 11. THERMAL CHARACTERISTICS AND SPECIFICATIONS .............................................................. 39 12. ORDERING INFORMATION .............................................................................................................. 40 13. REVISION HISTORY .......................................................................................................................... 40 LIST OF FIGURES Figure 1.Master Mode Serial Audio Port Timing ....................................................................................... 17 Figure 2.Slave Mode Serial Audio Port Timing ......................................................................................... 17 Figure 3.Format 0, 24-Bit Data Left-Justified ............................................................................................ 17 Figure 4.Format 1, 24-Bit Data I²S ............................................................................................................ 17 Figure 5.Control Port Timing - I²C Format ................................................................................................. 18 Figure 6.Control Port Timing - SPI Format ................................................................................................ 19 Figure 7.Typical Connection Diagram ....................................................................................................... 20 Figure 8.Master Mode Clocking ................................................................................................................ 22 Figure 9.Analog Input Architecture ............................................................................................................ 23 Figure 10.CS5346 PGA ............................................................................................................................ 24 Figure 11.1 VRMS Input Circuit .................................................................................................................. 24 Figure 12.1 VRMS Input Circuit with RF Filtering ....................................................................................... 24 Figure 13.2 VRMS Input Circuit .................................................................................................................. 24 Figure 14.Control Port Timing in SPI Mode .............................................................................................. 26 Figure 15.Control Port Timing, I²C Write ................................................................................................... 26 Figure 16.Control Port Timing, I²C Read ................................................................................................... 27 Figure 17.Single-Speed Stopband Rejection ............................................................................................ 37 Figure 18.Single-Speed Stopband Rejection ............................................................................................ 37 Figure 19.Single-Speed Transition Band (Detail) ...................................................................................... 37 Figure 20.Single-Speed Passband Ripple ................................................................................................ 37 Figure 21.Double-Speed Stopband Rejection ........................................................................................... 37 Figure 22.Double-Speed Stopband Rejection ........................................................................................... 37 Figure 23.Double-Speed Transition Band (Detail) .................................................................................... 38 Figure 24.Double-Speed Passband Ripple ............................................................................................... 38 Figure 25.Quad-Speed Stopband Rejection ............................................................................................. 38 Figure 26.Quad-Speed Stopband Rejection ............................................................................................. 38 Figure 27.Quad-Speed Transition Band (Detail) ....................................................................................... 38 Figure 28.Quad-Speed Passband Ripple ................................................................................................. 38 DS861PP1 3 CS5346 LIST OF TABLES Table 1. Speed Modes .............................................................................................................................. 21 Table 2. Common Clock Frequencies ....................................................................................................... 21 Table 3. Slave Mode Serial Bit Clock Ratios ............................................................................................. 22 Table 4. Device Revision .......................................................................................................................... 30 Table 5. Freeze-able Bits .......................................................................................................................... 30 Table 6. Functional Mode Selection .......................................................................................................... 31 Table 7. Digital Interface Formats ............................................................................................................. 31 Table 8. MCLK Frequency ........................................................................................................................ 32 Table 9. PGAOut Source Selection ........................................................................................................... 32 Table 10. Example Gain and Attenuation Settings ................................................................................... 33 Table 11. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 34 Table 12. Analog Input Multiplexer Selection ............................................................................................ 34 4 DS861PP1 CS5346 1. PIN DESCRIPTIONS - CS5346 OVFL SDOUT DGND MCLK LRCK SCLK INT NC NC NC 48 47 46 45 44 43 42 41 40 39 38 37 SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN VLC RST AIN3A AIN3B AIN2A AIN2B AIN1A AIN1B NC VD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FILT+ VQ VQ NC AIN4A/MICIN1 AIN4B/MICIN2 AGND AFILTA AFILTB VA AIN5A AIN5B 36 35 34 33 32 VLS NC NC NC AGND NC NC PGAOUTB PGAOUTA AIN6B AIN6A MICBIAS CS5346 31 30 29 28 27 26 25 Pin Name SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN VLC RST AIN3A AIN3B AIN2A AIN2B # 1 2 3 4 5 6 7 8 9 10 Pin Description Serial Control Data (Input/Output) - SDA is a data I/O in I²C® Mode. CDOUT is the output data line for the control port interface in SPITM Mode. Serial Control Port Clock (Input) - Serial clock for the serial control port. Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS is the chip-select signal for SPI format. Address Bit 1 (I²C) / Serial Control Data Input (SPI) (Input) - AD1 is a chip address pin in I²C Mode; CDIN is the input data line for the control port interface in SPI Mode. Control Port Power (Input) - Determines the required signal level for the control port interface. Refer to the Recommended Operating Conditions for appropriate voltages. Reset (Input) - The device enters a low-power mode when this pin is driven low. Stereo Analog Input 3 (Input) - The full-scale level is specified in the Analog Characteristics specification table. Stereo Analog Input 2 (Input) - The full-scale level is specified in the Analog Characteristics specification table. DS861PP1 5 CS5346 AIN1A AIN1B AGND VA AFILTA AFILTB VQ FILT+ NC AIN4A/MICIN1 AIN4B/MICIN2 AIN5A AIN5B MICBIAS AIN6A AIN6B PGAOUTA PGAOUTB NC AGND NC 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Stereo Analog Input 1 (Input) - The full-scale level is specified in the Analog Characteristics specification table. Analog Ground (Input) - Ground reference for the internal analog section. Analog Power (Input) - Positive power for the internal analog section. Anti-alias Filter Connection (Output) - Antialias filter connection for the channel A ADC input. Anti-alias Filter Connection (Output) - Antialias filter connection for the channel B ADC input. Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. No Connect - This pin is not connected internally and should be tied to ground to minimize any potential coupling effects. Stereo Analog Input 4 / Microphone Input 1 & 2 (Input) - The full-scale level is specified in the Analog Characteristics specification table. Stereo Analog Input 5 (Input) - The full-scale level is specified in the Analog Characteristics specification table. Microphone Bias Supply (Output) - Low-noise bias supply for external microphone. Electrical characteristics are specified in the DC Electrical Characteristics specification table. Stereo Analog Input 6 (Input) - The full-scale level is specified in the Analog Characteristics specification table. PGA Analog Audio Output (Output) - Either an analog output from the PGA block or high impedance. See “PGAOut Source Select (Bit 6)” on page 32. No Connect - These pins are not connected internally and should be tied to ground to minimize any potential coupling effects. Analog Ground (Input) - Ground reference for the internal analog section. No Connect - These pins are not connected internally and should be tied to ground to minimize any potential coupling effects. Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages. No Connect - These pins are not connected internally and should be tied to ground to minimize any potential coupling effects. Serial Audio Data Output (Output) - Output for two’s complement serial audio data. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the ADC’s delta-sigma modulators. Digital Ground (Input) - Ground reference for the internal digital section. Digital Power (Input) - Positive power for the internal digital section. Interrupt (Output) - Indicates an interrupt condition has occurred. Overflow (Output) - Indicates an ADC overflow condition is present. VLS NC SDOUT SCLK LRCK MCLK DGND VD INT OVFL 6 DS861PP1 CS5346 2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES The CS5346 is pin compatible with the CS5345 and is a drop in replacement for CS5345 applications where VA = 5 V, VD = 3.3 V, VLS ≥ 3.3 V, and VLC ≥ 3.3 V. The pinout diagram and table below show the requirements for the remaining pins when replacing the CS5345 in these designs with a CS5346. OVFL SDOUT DGND MCLK LRCK SCLK TSTI INT NC NC 48 47 46 45 44 43 42 41 40 39 38 37 SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN VLC RST AIN3A AIN3B AIN2A AIN2B AIN1A AIN1B NC VD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AIN4A/MICIN1 AIN4B/MICIN2 AFILTA AFILTB AGND FILT+ TSTI VA AIN5A AIN5B TSTO VQ 36 35 34 33 VLS TSTO NC NC AGND AGND VA PGAOUTB PGAOUTA AIN6B AIN6A MICBIAS CS5345 Compatibility 32 31 30 29 28 27 26 25 # 5 14 18 20 30 31 35 36 37 46 CS5345 Pin Name VLC VA TSTO TSTI VA AGND TSTO VLS TSTI VD CS5346 Pin Name VLC VA VQ NC NC NC NC VLS NC VD CS5346 Connection for Compatibility Control Port Power (Input) -Limited to nominal 5 or 3.3 V. Analog Power (Input) - Limited to nominal 5 V. This pin must be left unconnected. This pin should be tied to ground. This pin may be connected to the analog supply voltage. The decoupling capacitor for the CS5345 is not required. This pin should be connected to ground. This pin may be left unconnected. Serial Audio Interface Power (Input) - Limited to nominal 5 or 3.3 V. This pin should be tied to ground. Digital Power (Input) - Limited to nominal 3.3 V DS861PP1 7 CS5346 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS AGND = DGND = 0 V; All voltages with respect to ground. Parameters Analog Digital Logic - Serial Port Logic - Control Port Ambient Operating Temperature (Power Applied) Commercial Automotive DC Power Supplies: Symbol VA VD VLS VLC TA TA Min 4.75 3.13 3.13 3.13 -40 -40 Nom 5.0 3.3 3.3 3.3 - Max 5.25 3.47 5.25 5.25 +85 +105 Units V V V V °C °C ABSOLUTE MAXIMUM RATINGS AGND = DGND = 0 V All voltages with respect to ground. (Note 1) Parameter DC Power Supplies: Analog Digital Logic - Serial Port Logic - Control Port (Note 2) Logic - Serial Port Logic - Control Port Symbol VA VD VLS VLC Iin VINA VIND-S VIND-C TA Tstg Min -0.3 -0.3 -0.3 -0.3 AGND-0.3 -0.3 -0.3 -50 -65 Max +6.0 +3.63 +6.0 +6.0 ±10 VA+0.3 VLS+0.3 VLC+0.3 +125 +150 Units V V V V mA V V V °C °C Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 8 DS861PP1 CS5346 ANALOG CHARACTERISTICS (COMMERCIAL) Test conditions (unless otherwise specified): VA = 5 V; VD = VLS = VLC = 3.3 V; AGND = DGND = 0 V; TA = +25° C; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48/96/192 kHz; PGA gain = 0 dB; All connections as shown in Figure 7 on page 20. Parameter Analog-to-Digital Converter Characteristics Dynamic Range (Line Level Inputs) Symbol Min Typ Max Unit A-weighted 97 103 unweighted 94 100 (Note 3) 40 kHz bandwidth unweighted 98 Total Harmonic Distortion + Noise (Line Level Inputs) (Note 4) -1 dB -95 -89 -20 dB THD+N -80 -40 -60 dB (Note 3) 40 kHz bandwidth -1 dB -92 Dynamic Range (Mic Level Inputs) A-weighted 77 83 (Note 3) unweighted 74 80 Total Harmonic Distortion + Noise (Mic Level Inputs) (Note 4) -80 -74 -1 dB THD+N -20 dB -60 -20 (Note 3) -60 dB Interchannel Isolation (Line Level Inputs) 90 (Mic Level Inputs) 80 A/D Full-scale Input Voltage 0.51*VA 0.57*VA 0.63*VA Gain Error ±10 Interchannel Gain Mismatch 0.1 - dB dB dB dB dB dB dB dB dB dB dB dB dB dB Vpp % dB dB V/V dB kΩ Microphone - Level Input Characteristics Preamplifier Gain Interchannel Gain Mismatch Input Impedance 31 35.5 32 40 0.1 60 33 44.7 - (Note 5) 3. Valid for Double- and Quad-Speed Modes only. 4. Referred to the typical A/D full-scale input voltage 5. Valid when the microphone-level inputs are selected. DS861PP1 9 CS5346 ANALOG CHARACTERISTICS (COMMERCIAL) CONT. Parameter Line-Level Input and Programmable Gain Amplifier Gain Range Gain Step Size Absolute Gain Step Error Maximum Input Level Input Impedance Selected inputs Un-selected inputs Selected Interchannel Input Impedance Mismatch Symbol Min - 12 -4 28.8 - Typ 0.5 36 5 Max + 12 +4 0.4 0.85*VA 43.2 38 - Unit dB V/V dB dB Vpp kΩ kΩ % Analog Outputs Dynamic Range (Line Level Inputs) A-weighted unweighted (Note 6) -1 dB THD+N -20 dB -60 dB A-weighted unweighted (Note 6) -1 dB THD+N -20 dB -60 dB 98 95 77 74 -0.1dB 100 104 101 -80 -81 -41 83 80 -74 -60 -20 180 -74 -68 +0.1dB 1 20 dB dB dB dB dB dB dB dB dB dB dB deg µA kΩ pF Total Harmonic Distortion + Noise (Line Level Inputs) Dynamic Range (Mic Level Inputs) Total Harmonic Distortion + Noise (Mic Level Inputs) Frequency Response 10 Hz to 20 kHz Analog In to Analog Out Phase Shift DC Current draw from a PGAOUT pin AC-Load Resistance Load Capacitance IOUT RL CL 6. Referred to the typical A/D Full-Scale Input Voltage. 10 DS861PP1 CS5346 ANALOG CHARACTERISTICS (AUTOMOTIVE) Test conditions (unless otherwise specified): VA = 5.0 V +/- 5%; VD = VLS = VLC = 3.3 V +/- 5%; AGND = DGND = 0 V; TA = -40° to +85° C; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48/96/192 kHz; PGA gain = 0 dB; All connections as shown in Figure 7 on page 20. Parameter Analog-to-Digital Converter Characteristics Dynamic Range (Line Level Inputs) Symbol Min Typ Max Unit A-weighted 95 103 unweighted 92 100 (Note 3) 40 kHz bandwidth unweighted 98 Total Harmonic Distortion + Noise (Line Level Inputs) (Note 4) -1 dB -95 -87 -20 dB THD+N -80 -40 -60 dB (Note 3) 40 kHz bandwidth -1 dB -92 Dynamic Range (Mic Level Inputs) A-weighted 75 83 (Note 3) unweighted 72 80 Total Harmonic Distortion + Noise (Mic Level Inputs) (Note 4) -80 -72 -1 dB THD+N -20 dB -60 -20 (Note 3) -60 dB Interchannel Isolation (Line Level Inputs) 90 (Mic Level Inputs) 80 A/D Full-scale Input Voltage 0.51*VA 0.57*VA 0.63*VA Gain Error ±10 Interchannel Gain Mismatch 0.1 - dB dB dB dB dB dB dB dB dB dB dB dB dB dB Vpp % dB dB V/V dB kΩ Microphone - Level Input Characteristics Preamplifier Gain Interchannel Gain Mismatch Input Impedance 31 35.48 32 40 0.1 60 33 44.67 - (Note 5) 7. Valid for Double- and Quad-Speed Modes only. 8. Referred to the typical A/D full-scale input voltage 9. Valid when the microphone-level inputs are selected. DS861PP1 11 CS5346 ANALOG CHARACTERISTICS (AUTOMOTIVE) CONT. Parameter Line-Level Input and Programmable Gain Amplifier Gain Range Gain Step Size Absolute Gain Step Error Maximum Input Level Input Impedance Selected inputs Un-selected inputs Selected Interchannel Input Impedance Mismatch Symbol Min - 12 -4 28.8 - Typ 0.5 36 5 Max + 12 +4 0.4 0.85*VA 43.2 38 - Unit dB V/V dB dB Vpp kΩ kΩ % Analog Outputs Dynamic Range (Line Level Inputs) A-weighted unweighted (Note 6) -1 dB THD+N -20 dB -60 dB A-weighted unweighted (Note 6) -1 dB THD+N -20 dB -60 dB 96 93 77 74 -0.1dB 100 104 101 -80 -81 -41 83 80 -74 -60 -20 180 -74 -68 +0.1dB 1 20 dB dB dB dB dB dB dB dB dB dB dB deg µA kΩ pF Total Harmonic Distortion + Noise (Line Level Inputs) Dynamic Range (Mic Level Inputs) Total Harmonic Distortion + Noise (Mic Level Inputs) Frequency Response 10 Hz to 20 kHz Analog In to Analog Out Phase Shift DC Current draw from a PGAOUT pin AC-Load Resistance Load Capacitance IOUT RL CL 10. Referred to the typical A/D Full-Scale Input Voltage. 12 DS861PP1 CS5346 DIGITAL FILTER CHARACTERISTICS Parameter (Note 11) Single-Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd (-0.1 dB) 0 0.5688 70 0 0.5604 69 tgd 0 0.5000 60 tgd (Note 12) (Note 12) 12/Fs 9/Fs 5/Fs 1 20 10 105/Fs 0.4896 0.035 0.4896 0.025 0.2604 0.025 0 Fs dB Fs dB s Fs dB Fs dB s Fs dB Fs dB s Hz Hz Deg dB s Symbol Min Typ Max Unit Double-Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (-0.1 dB) Quad-Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (-0.1 dB) High-Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time -3.0 dB -0.13 dB @ 20 Hz 11. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 17 to 28) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 12. Response shown is for Fs = 48 kHz. DS861PP1 13 CS5346 DC ELECTRICAL CHARACTERISTICS AGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode. Parameter Power Supply Current (Normal Operation) Power Supply Current (Power-Down Mode) (Note 13) Power Consumption (Normal Operation) (Power-Down Mode) VA = 5 V VD, VLS, VLC = 3.3 V VA = 5 V VLS, VLC, VD = 3.3 V VA = 5 V VD, VLS, VLC = 3.3 V VA = 5V; VD, VLS, VLC = 3.3 V (Note 14) Symbol IA ID IA ID PSRR VQ IQ ZQ FILT+ MICBIAS IMB Min - Typ 41 23 0.50 0.54 205 76 4.2 55 0.5 x VA 1 23 VA 0.8 x VA - Max 50 28 250 93 2 Unit mA mA mA mA mW mW mW dB VDC µA kΩ VDC VDC mA Power Supply Rejection Ratio (1 kHz) VQ Characteristics Quiescent Voltage Maximum DC Current from VQ VQ Output Impedance FILT+ Nominal Voltage Microphone Bias Voltage Current from MICBIAS 13. Power-Down Mode is defines as RST = Low with all clock and data lines held static and no analog input. 14. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram. 14 DS861PP1 CS5346 DIGITAL INTERFACE CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 3.3 V. Parameters (Note 15) High-Level Input Voltage Serial Port Control Port Serial Port Control Port Serial Port Control Port Serial Port Control Port VIH VIH VIL VIL VOH VOH VOL VOL Iin 0.7xVLS 0.7xVLC VLS-1.0 VLC-1.0 10 ---------------LRCK 6 Symbol Min Typ 1 - Max 0.3xVLS 0.3xVLC 0.4 0.4 ±10 - Units V V V V V V V V µA pF µs Low-Level Input Voltage High-Level Output Voltage at Io = 2 mA Low-Level Output Voltage at Io = 2 mA Input Leakage Current Input Capacitance Minimum OVFL Active Time 15. Serial Port signals include: MCLK, SCLK, LRCK, SDOUT. Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, RST, INT, OVFL. DS861PP1 15 CS5346 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT Logic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VLS, CL = 20 pF. (Note 16) Parameter Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode Symbol Fs Fs Fs fmclk tclkhl Min 8 50 100 2.048 8 -10 0 40 Typ 50 50 50 - Max 50 100 200 51.200 10 36 60 - Unit kHz kHz kHz MHz ns % % ns ns % ns MCLK Specifications MCLK Frequency MCLK Input Pulse Width High/Low Master Mode LRCK Duty Cycle SCLK Duty Cycle SCLK falling to LRCK edge SCLK falling to SDOUT valid tslr tsdo Slave Mode LRCK Duty Cycle SCLK Period Single-Speed Mode tsclkw 10 -------------------( 128 ) Fs 10 ----------------( 64 ) Fs 10 ----------------( 64 ) Fs 30 48 -10 0 9 9 9 Double-Speed Mode tsclkw - - ns Quad-Speed Mode SCLK Pulse Width High SCLK Pulse Width Low SCLK falling to LRCK edge SCLK falling to SDOUT valid tsclkw tsclkh tsclkl tslr tsdo - 10 36 ns ns ns ns ns 16. See Figure 1 and Figure 2 on page 17. 16 DS861PP1 CS5346 LRCK Input t sclkh t t SCLK Input t SDOUT slr sclkl sdo t sclkw Figure 1. Master Mode Serial Audio Port Timing LRCK Output t SCLK Output t SDOUT slr sdo Figure 2. Slave Mode Serial Audio Port Timing LRCK SCLK Channel A - Left Channel B - Right SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 3. Format 0, 24-Bit Data Left-Justified LRCK SCLK Channel A - Left Channel B - Right SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 4. Format 1, 24-Bit Data I²S DS861PP1 17 CS5346 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL = 30 pF. Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 17) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc, trd tfc, tfd tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 Max 100 1 300 1000 Unit kHz ns µs µs µs µs µs µs ns µs ns µs ns 17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. RST t S to p irs S t a rt R e p e a te d S t a rt t rd t fd S to p SDA t buf t h d st t h igh t h d st t fc t su sp SCL t t t su d t a ck t su st t rc lo w hdd Figure 5. Control Port Timing - I²C Format 18 DS861PP1 CS5346 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL = 30 pF. Parameter CCLK Clock Frequency RST Rising Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 19) (Note 19) (Note 18) Symbol fsck tsrs tcsh tcss tscl tsch tdsu tdh tpd tr1 tf1 tr2 tf2 Min 500 1.0 20 66 66 40 15 - Max 6.0 50 25 25 100 100 Units MHz ns µs ns ns ns ns ns ns ns ns ns ns 18. Data must be held for sufficient time to bridge the transition time of CCLK. 19. For fsck