CS5373A-ISZ

CS5373A Low-power, High-performance ∆Σ Modulator and Test DAC Modulator Features Fourth-order ∆Σ Architecture • • • • Clock-jitter-tolerant architecture Input signal bandwidth: DC to 2 kHz Max AC amplitude: 5 Vpp differential Max DC amplitude: ± 2.5 Vdc differential Description The CS5373A is a high-performance, fourth-order ∆Σ modulator integrated with a ∆Σ digital-to-analog converter (DAC). When combined with a CS3301A / CS3302A differential amplifier and the CS5378 digital filter, a small, low-power, self-testing, high-accuracy, singlechannel measurement system results. The modulator has high dynamic range and low total harmonic distortion with very low power consumption. It converts differential analog input signals from the CS3301A / CS3302A amplifier to an oversampled serial bit stream at 512 kbits per second. This oversampled bit stream is then decimated by the CS5378 digital filter to a 24-bit output at the selected output word rate. The test DAC operates in either AC or DC test modes. AC test modes measure system dynamic performance through THD and CMRR tests while DC test modes are for gain calibration and pulse tests. It has two sets of differential analog outputs, OUT and BUF, as dedicated outputs for testing the electronics channel and for incircuit sensor tests. Output attenuation settings are binary weighted and match the gain settings of the CS3301A / CS3302A differential amplifiers for full-scale testing at all gain ranges. ORDERING INFORMATION See page 39. VA+ VREF+ VREFVD High Dynamic Range • 127 dB SNR @ 215 Hz BW (2 ms sampling) • 124 dB SNR @ 430 Hz BW (1 ms sampling) Low Total Harmonic Distortion • -118 dB THD typical (0.000126%) • -112 dB THD maximum (0.000251%) Low Power Consumption: 25 mW, 10 µW Test DAC Features Digital ∆Σ Input from CS5378 Digital Filter Selectable Differential Analog Outputs • Precision output (OUT±) for electronics tests • Buffered output (BUF±) for sensor tests Multiple AC and DC Operational Modes • Output signal bandwidth: DC to 100 Hz • Max AC amplitude: 5 Vpp differential • Max DC amplitude: + 2.5 Vdc differential Selectable Attenuation for CS3301A / CS3302A • 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 Outstanding Performance • AC (OUT): -116 dB THD typical, -112 dB max • AC (BUF): -108 dB THD typical, -90 dB max • DC absolute accuracy: 0.4% typical, 1% max INR+ INF+ INFINROUT+ MDATA 24-Bit ∆Σ Modulator MFLAG Clock Generator MCLK MSYNC Low Power Consumption • AC modes / DC modes: 40 mW / 20 mW • Sleep mode / Power down: 1 mW / 10 µW Common Features Extremely Small Footprint • 28-pin SSOP package, 8 mm x 10 mm TDATA OUTBUF+ BUFAttenuator 1/1 to 1/64 24-Bit ∆Σ Test DAC CAP+ CAP- Bipolar Power Supply Configuration • VA+ = +2.5 V; VA- = -2.5 V; VD = +3.3 V VAATT(0, 1, 2) MODE(0, 1, 2) GND http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) DEC ‘06 DS703F1 CS5373A TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 SPECIFIED OPERATING CONDITIONS ................................................................................. 4 TEMPERATURE CONDITIONS ............................................................................................... 5 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5 ANALOG INPUT CHARACTERISTICS ................................................................................... 6 ANALOG OUTPUT CHARACTERISTICS ............................................................................... 7 MODULATOR CHARACTERISTICS ........................................................................................ 8 PERFORMANCE PLOTS ......................................................................................................... 9 DAC AC DIFFERENTIAL MODES 1, 2, 3............................................................................... 10 DIGITAL CHARACTERISTICS .............................................................................................. 15 POWER SUPPLY CHARACTERISTICS ................................................................................ 18 2. GENERAL DESCRIPTION ..................................................................................................... 19 2.1 Delta-Sigma Modulator .................................................................................................... 19 2.2 Digital-to-Analog Converter .............................................................................................. 19 3. SYSTEM DIAGRAM ............................................................................................................ 20 4. POWER MODES ..................................................................................................................... 21 4.1 Power Down ..................................................................................................................... 21 4.2 Sleep Mode ...................................................................................................................... 21 4.3 Modulator Mode ............................................................................................................... 21 4.4 AC Test Modes ................................................................................................................ 21 4.5 DC Test Modes ................................................................................................................ 21 5. OPERATIONAL MODES ........................................................................................................ 22 5.1 Modulator Mode ............................................................................................................... 22 5.1.1 Modulator One’s Density ..................................................................................... 22 5.1.2 Modulator Decimated Output .............................................................................. 22 5.1.3 Modulator Synchronization .................................................................................. 22 5.1.4 Modulator Idle Tones .......................................................................................... 23 5.1.5 Modulator Stability ............................................................................................... 23 5.2 AC Test Modes ................................................................................................................ 23 5.2.1 AC Differential ..................................................................................................... 23 5.2.2 AC Common Mode .............................................................................................. 24 5.2.3 DAC Stability ....................................................................................................... 24 5.3 DC Test Modes ................................................................................................................ 24 5.3.1 DC Common Mode ............................................................................................. 24 5.3.2 DC Differential ..................................................................................................... 25 5.4 Sleep Mode ...................................................................................................................... 25 6. DIGITAL SIGNALS ................................................................................................................. 26 6.1 MCLK Connection ............................................................................................................ 26 6.2 MSYNC Connection ......................................................................................................... 26 6.3 MDATA Connection ......................................................................................................... 27 6.4 MFLAG Connection ......................................................................................................... 27 6.5 TDATA Connection .......................................................................................................... 27 6.6 GPIO Connections ........................................................................................................... 27 7. ANALOG SIGNALS ................................................................................................................ 28 7.1 INR±, INF± Modulator Inputs ........................................................................................... 28 7.1.1 Modulator Input Impedance ................................................................................ 28 7.1.2 Modulator Anti-alias Filter ................................................................................... 28 7.2 DAC Output Attenuation .................................................................................................. 29 7.3 DAC OUT± Precision Output ........................................................................................... 29 7.4 DAC BUF± Buffered Output ............................................................................................. 30 7.5 DAC CAP± Connection .................................................................................................... 30 7.6 Analog Differential Signals ............................................................................................... 30 8. VOLTAGE REFERENCE ........................................................................................................ 31 2 DS703F1 CS5373A 8.1 VREF Power Supply ........................................................................................................ 31 8.2 VREF RC Filter ................................................................................................................ 31 8.3 VREF PCB Routing ......................................................................................................... 31 8.4 VREF Input Impedance ................................................................................................... 31 8.5 VREF Accuracy ............................................................................................................... 32 8.6 VREF Independence ....................................................................................................... 32 9. POWER SUPPLIES ................................................................................................................ 33 9.1 Power Supply Bypassing ................................................................................................. 33 9.2 PCB Layers and Routing ................................................................................................. 33 9.3 Power Supply Rejection .................................................................................................. 33 9.4 SCR Latch-up .................................................................................................................. 34 9.5 DC-DC Converters .......................................................................................................... 34 10. TERMINOLOGY ................................................................................................................... 35 11. PIN DESCRIPTION ............................................................................................................... 36 12. PACKAGE DIMENSIONS .................................................................................................... 38 13. ORDERING INFORMATION ............................................................................................... 39 14. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .......................... 39 15. REVISION HISTORY ........................................................................................................... 40 LIST OF FIGURES Figure 1. Modulator Noise Performance ......................................................................................... 9 Figure 2. Modulator + Test DAC Dynamic Performance................................................................. 9 Figure 3. Digital Input Rise and Fall Times ................................................................................... 15 Figure 4. System Timing Diagram................................................................................................. 17 Figure 5. MCLK / MSYNC Timing Detail ....................................................................................... 17 Figure 6. CS5373A Block Diagram ............................................................................................... 19 Figure 8. Connection Diagram ...................................................................................................... 20 Figure 7. System Diagram ............................................................................................................ 20 Figure 9. Power Mode Diagram .................................................................................................... 21 Figure 10. AC Differential Modes .................................................................................................. 23 Figure 11. AC Common Mode ...................................................................................................... 24 Figure 12. DC Test Modes ............................................................................................................ 25 Figure 13. Digital Signals .............................................................................................................. 26 Figure 14. Analog Signals ............................................................................................................. 28 Figure 15. DAC Output Attenuation Settings ................................................................................ 29 Figure 16. Voltage Reference Circuit ............................................................................................ 31 Figure 17. Power Supply Diagram ................................................................................................ 33 LIST OF TABLES Table 1. Selections for Operational Mode and DAC Attenuation .................................................... 4 Table 2. Operational Modes.......................................................................................................... 22 Table 3. Output Coding for the CS5373A Modulator and CS5378 Digital Filter Combination ...... 22 DS703F1 3 CS5373A 1. • • • • CHARACTERISTICS AND SPECIFICATIONS Min / Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are measured at nominal supply voltages and TA = 25°C. GND = 0 V. Single-ended voltages with respect to GND, differential voltages with respect to opposite half. Device is connected as shown in Figure 8 on page 20 unless otherwise noted. SPECIFIED OPERATING CONDITIONS Parameter Bipolar Power Supplies Positive Analog Negative Analog Positive Digital Voltage Reference {VREF+} - {VREF-} VREFThermal Ambient Operating Temperature Industrial (-ISZ) TA -40 25 85 °C (Note 2, 3) (Note 4) VREF VREF2.500 VA V V Symbol Min 2.45 -2.45 3.20 Nom 2.50 -2.50 3.30 Max 2.55 -2.55 3.40 Unit V V V ± 2% (Note 1) ± 2% ± 3% VA+ VAVD Notes: 1. VA- must always be the most-negative input voltage to avoid potential SCR latch-up conditions. 2. By design, a 2.500 V voltage reference input results in the best signal-to-noise performance. 3. Full-scale accuracy is directly proportional to the voltage reference absolute accuracy. 4. VREF inputs must satisfy: VA- < VREF- < VREF+ < VA+. Modes of Operation MODE Selection [2:0] 0 1 2 3 4 5 6 7 000 001 010 0 11 100 101 11 0 111 Selection Mode Description DAC Attenuation ATT[2:0] 000 001 010 0 11 100 101 11 0 111 Attenuation 1/1 1/2 1/4 1/8 1/16 1/32 1/64 reserved dB 0 dB -6.02 dB -12.04 dB -18.06 dB -24.08 dB -30.10 dB -36.12 dB reserved Modulator: enabled. DAC: sleep. Modulator: enabled. DAC: AC OUT and BUF outputs. Modulator: enabled. DAC: AC OUT only, BUF high-z. Modulator: enabled. DAC: AC BUF only, OUT high-z. Modulator: enabled. DAC: DC common mode output. Modulator: enabled. DAC: DC differential output. Modulator: enabled. DAC: AC common mode output. Modulator: sleep. DAC: sleep. 0 1 2 3 4 5 6 7 Table 1. Selections for Operational Mode and DAC Attenuation 4 DS703F1 CS5373A TEMPERATURE CONDITIONS Parameter Ambient Operating Temperature Storage Temperature Range Allowable Junction Temperature Junction to Ambient Thermal Impedance (4-layer PCB) Symbol TA TSTR TJCT ΘJA Min -40 -65 Typ 65 Max 85 150 125 Unit ºC ºC ºC ºC / W ABSOLUTE MAXIMUM RATINGS Parameter DC Power Supplies Positive Analog Negative Analog Digital (VA+) - (VA-) (VD) - (VA-) (Note 5) (Note 5, 6) (Note 5) Symbol VA+ VAVD VADIFF VDDIFF IPWR IIN IOUT PDN VINA VIND Min -0.5 -6.8 -0.5 (VA-) - 0.5 -0.5 Max 6.8 0.5 6.8 6.8 7.6 Parameter V V V V V mA mA mA mW V V Analog Supply Differential Digital Supply Differential Input Current, Power Supplies Input Current, Any Pin Except Supplies Output Current Power Dissipation Analog Input Voltages Digital Input Voltages ±50 ±10 ±25 500 (VA+) + 0.5 (VD) + 0.5 WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 5. Transient currents up to ±100 mA will not cause SCR latch-up. 6. Includes continuous over-voltage conditions at the modulator analog input pins. DS703F1 5 CS5373A ANALOG INPUT CHARACTERISTICS Parameter VREF Input {VREF+} - {VREF-} VREFVREF Input Current, Modulator Only VREF Input Current, Modulator + DAC AC Mode VREF Input Current, Modulator + DAC DC Mode VREF Input Noise Modulator INR±, INF± Inputs External Anti-alias Filter (Note 8) Differential Input Impedance Single-ended Input Impedance DAC CAP± Input External Anti-alias Filter (Note 8) Differential Capacitance CAA 10 nF Series Resistance Differential Capacitance INR± INF± INR± INF± RAA CAA ZDIFINR ZDIFINF ZSEINR ZSEINF 680 20 20 1 40 2 Ω nF kΩ MΩ kΩ MΩ (Note 7) (Note 2, 3) (Note 4) VREF VREFVREFIMOD VREFIMAC VREFIMDC VREFIN 2.500 VA 120 200 160 1 V V µA µA µA µVrms Symbol Min Typ Max Unit Notes: 7. Maximum integrated noise over the measurement bandwidth for the voltage reference device attached to the VREF± inputs. 8. Differential anti-alias capacitors are discrete external components and must be of good quality (C0G, NPO, poly). Poor quality capacitors will degrade total harmonic distortion (THD) performance. 6 DS703F1 CS5373A ANALOG OUTPUT CHARACTERISTICS Parameter DAC Analog OUT± Output Analog External Load at OUT± (Note 9, 10) Differential Output Impedance Load Resistance Load Capacitance 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1 1/2 1/4 1/8 1/16 1/32 1/64 (Note 9) (Note 9) Load Resistance Load Capacitance 1/1 - 1/64 1/1 - 1/32 (Note 11) (BUF-) 1/64 (Note 11) (BUF+) 1/64 (Note 9) (Note 9) RLOUT CLOUT ZDIFOUT 50 1 1.4 10.1 7.9 5.1 3.3 2.3 1.7 0.8 7.4 9.0 9.4 9.5 9.5 9.2 3 -120 6 3 3 50 4.5 -120 50 2 MΩ pF kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ MΩ dB kΩ nF Ω Ω Symbol Min Typ Max Unit Single-ended Output Impedance ZSEOUT High-Z Impedance Crosstalk to BUF± High-Z Output DAC Analog BUF± Output Analog External Load at BUF± (Note 9) Differential Output Impedance Single-ended Output Impedance HZOUT XTOUT RLBUF CLBUF ZDIFBUF ZSEBUF High-Z Impedance Crosstalk to OUT± High-Z Output HZBUF XTBUF MΩ dB Notes: 9. Guaranteed by design and/or characterization. 10. Load on the precision OUT± outputs is normally from a CS3301A / CS3302A amplifier, which has 1 GΩ/1 TΩ typical input impedance and 18 pF typical input capacitance. 11. Single-ended output impedance at 1/64 is different for BUF+ and BUF- due to the output attenuator architecture. DS703F1 7 CS5373A MODULATOR CHARACTERISTICS Parameter Input Characteristics Input Signal Frequencies Full Scale Differential AC Input Full Scale Differential DC Input Input Common Mode Voltage Input Voltage Range (Signal ± Vcm) Dynamic Performance Dynamic Range (Note 12, 14) (1/4 ms) DC to 1720 Hz (1/2 ms) DC to 860 Hz (1 ms) DC to 430 Hz (2 ms) DC to 215 Hz (4 ms) DC to 108 Hz (8 ms) DC to 54 Hz (16 ms) DC to 27 Hz (1 ms) DC to 430 Hz (Note 16) (Note 16) SNR 121 100 109 121 124 127 130 133 136 110 -118 0.000126 Symbol (Note 9, 12) (Note 9) (Note 9) (Note 13) (Note 9) VBW VAC VDC VCM VRNG Min DC -2.5 (VA-)+0.7 Typ (VA-)+2.5 Max 2000 5 2.5 (VA+)-1.25 Unit Hz Vpp Vdc V V dB dB dB dB dB dB dB dB dB % dB % ppm/°C mV µV %FS nV/°C - -112 0.000251 Signal Dependent Noise (Note 15, 16) Total Harmonic Distortion Linearity Common Mode Rejection Ratio Gain Accuracy SDN THD LIN CMRR 110 - Channel to Channel Gain Accuracy Channel Gain Drift Offset Offset Voltage, Differential Offset after Calibration Offset Calibration Range Offset Voltage Drift (Note 3) (Note 17) GA GATC OFST ±1 22 +100 ±2 - (Note 18) OFSTCAL (Note 19) OFSTRNG (Note 17) OFSTTC ±1 100 300 Notes: 12. The upper bandwidth limit is determined by the CS5378 digital filter cut-off frequency. 13. Common mode voltage is defined as the mid-point of the differential signal. 14. Dynamic Range defined as 20 log [ (RMS full scale) / (RMS idle noise) ] where idle noise is measured from a CS3301A / CS3302A amplifier terminated input at 1x gain. 15. Signal-dependent Noise defined as 20 log [ (RMS full scale) / (RMS signal noise) ] where signal noise is measured by subtracting out the signal power at the fundamental and harmonic frequencies. 16. Tested with a 31.25 Hz sine wave at -1 dB amplitude. 17. Specification is for the parameter over the specified temperature range and is for the device only. It does not include the effects of external components. 18. Specification applies to the effective offset voltage calculated from the output codes of the CS5378 digital filter following offset calibration and correction. 19. Offset calibration is performed in the CS5378 digital filter and includes the full-scale signal range. 8 DS703F1 CS5373A PERFORMANCE PLOTS Figure 1. Modulator Noise Performance Figure 2. Modulator + Test DAC Dynamic Performance DS703F1 9 CS5373A DAC AC DIFFERENTIAL MODES 1, 2, 3 Parameter AC Differential Characteristics Full-scale Differential AC Output 1/1 1/2 1/4 1/8 1/16 1/32 1/64 (Note 9) (Note 9, 20) 1/1 1/2 1/4 1/8 1/16 1/32 1/64 Symbol VACFS Min - 0.5 - 0.2 - Typ 5 2.5 1.25 625 312.5 156.25 78.125 - 0.2 ± 0.1 ± 0.1 ± 0.1 -0.1 ± 0.2 -0.2 ± 0.3 -0.5 ± 0.5 Max 100 -20 0.2 0.2 - Unit Vpp Vpp Vpp mVpp mVpp mVpp mVpp Hz dBfs %FS % % % % % % Full-scale Bandwidth Impulse Amplitude AC Differential Accuracy Full-scale Accuracy (Note 3, 21) Relative Accuracy (Note 22) VACBW VACIMP VACABS VACREL Full-scale Drift DC Common Mode Characteristics Common Mode Common Mode Drift (Note 17) (Note 13) VACTC VACCM - 25 (VA-)+2.35 - µV/°C V µV/°C (Note 13, 17) VACCMTC 300 Notes: 20. Maximum amplitude for DAC operation above 100 Hz. A reduced amplitude for higher frequencies is required to guarantee stability of the low-power ∆Σ DAC architecture. 21. Full-scale accuracy compares the defined full-scale 1/1 amplitude to the measured 1/1 amplitude. Specification is for unloaded outputs. Applying a differential load lowers the output amplitude ratiometric to the differential output impedance. 22. Relative accuracy compares the measured 1/2,1/4,1/8,1/16,1/32,1/64 amplitude to the measured 1/1 amplitude. 10 DS703F1 CS5373A DAC AC DIFFERENTIAL MODES 1, 2, 3 (CONT.) Parameter Signal to Noise Signal to Noise (OUT± Unloaded) (Note 23) 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1 1/2 1/4 1/8 1/16 1/32 1/64 -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x SNROUT 114 114 114 113 111 108 103 110 106 101 95 89 83 77 -116 -115 -114 -112 -111 -110 -106 -108 -105 -100 -94 -88 -82 -76 -102 -101 -97 -92 -87 -82 -76 -112 -90 -80 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Symbol Min Typ Max Unit Signal to Noise (BUF± Unloaded, 1 kΩ load) (Note 23, 24) SNRBUF Total Harmonic Distortion Total Harmonic Distortion (OUT± Unloaded) (Note 16, 25) THDOUT Total Harmonic Distortion (BUF± Unloaded) (Note 16, 24, 25) THDBUF Total Harmonic Distortion (BUF± 1 kΩ load) (Note 16, 24, 25) THDBUFL Notes: 23. Specification measured using CS3301A amplifier at corresponding gain with the modulator measuring a 430 Hz bandwidth. Amplified noise dominates for x16, x32, x64 amplifier gains. 24. Buffered outputs (BUF±) include 1/f noise not present on the precision outputs (OUT±). 25. Specification measured using CS3301A amplifier at corresponding gain with the modulator measuring a 430 Hz bandwidth. Amplified noise in the harmonic bins dominates THD measurements for x16, x32, x64 amplifier gains. DS703F1 11 CS5373A DAC DC COMMON MODE 4 Parameter DC Common Mode Characteristics Common Mode Output Common Mode Drift DC Common Mode Accuracy Common Mode Match Noise Noise (OUT± Unloaded) (Note 23) 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1 1/2 1/4 1/8 1/16 1/32 1/64 -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x NOUT 6 7 7 7 7 9 14 7 10 17 33 64 130 257 µVrms µVrms µVrms µVrms µVrms µVrms µVrms µVrms µVrms µVrms µVrms µVrms µVrms µVrms 1/1 VDCCMM -5 ±1 5 mV VDCCM (Note 17) VDCCMTC (VA-)+2.35 Symbol Min Typ Max - Unit V µV/°C 300 Noise (BUF± Unloaded, 1 kΩ load) (Note 23, 24) NBUF 12 DS703F1 CS5373A DAC DC DIFFERENTIAL MODE 5 Parameter DC Differential Mode Characteristics Full-scale Differential DC Output (Note 26) 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1 1/2 1/4 1/8 1/16 1/32 1/64 Symbol VDCFS Min - 1.0 - 0.2 - Typ 2.5 1.25 625 312.5 156.25 78.125 39.0625 - 0.4 ± 0.1 ± 0.1 -0.1 ± 0.4 -0.2 ± 0.9 -0.5 ± 1.7 -1.0 ± 3.6 Max 0.2 0.2 - Unit V V mV mV mV mV mV %FS % % % % % % DC Differential Accuracy Full-scale Accuracy (Note 3, 21) Relative Accuracy (Note 22) VDCABS VDCREL Full-scale Drift DC Common Mode Characteristics Common Mode Common Mode Drift Noise Noise (OUT± Unloaded) (Note 23, 26) (Note 17) (Note 13) VDCTC VDCCM - 25 (VA-)+2.35 - µV/°C V µV/°C µVrms µVrms µVrms µVrms µVrms µVrms µVrms µVrms µVrms µVrms µVrms µVrms µVrms µVrms (Note 13, 17) VDCCMTC 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1 1/2 1/4 1/8 1/16 1/32 1/64 -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x NOUT 300 9 9 9 9 10 11 15 10 12 18 32 67 122 265 Noise (BUF± Unloaded, 1 kΩ load) (Note 23, 24, 26) NBUF Notes: 26. DC differential output is chopper stabilized and includes low-level 32 kHz out-of-band noise which is rejected by the digital filter during acquisition. DS703F1 13 CS5373A DAC AC COMMON MODE 6 Parameter AC Common Mode Characteristics Full-scale Common Mode AC Output (Note 27) 1/1 1/2 1/4 1/8 1/16 1/32 (Note 9) (Note 9, 20) VCMFS 2.5 1.25 625 312.5 156.25 78.125 -115 -95 -0.3 -0.1 -0.5 -1.0 -2.0 -5.0 25 (VA-)+2.35 Symbol Min Typ Max 100 -20 -105 -85 - Unit Vpp Vpp mVpp mVpp mVpp mVpp Hz dBfs dB dB %FS % % % % % µV/°C V µV/°C Full-scale Bandwidth Impulse Amplitude AC Common Mode Accuracy Common Mode Match (OUT± Unloaded) (Note 16, 27) VCMBW VCMIMP VCMCMM VCMCMM Common Mode Match (BUF± Unloaded, 1 kΩ load) (Note 16, 24, 27) Full-scale Accuracy (Note 3, 21) Relative Accuracy (Note 22) 1/1 1/2 1/4 1/8 1/16 1/32 (Note 17) (Note 28) VCMABS VCMREL Full-scale Drift DC Common Mode Characteristics Common Mode Mean Common Mode Mean Drift VCMTC VCMCM (Note 17, 28) VCMCMTC 300 Notes: 27. No AC common mode signal is output at 1/64 attenuation due to the attenuator architecture. 28. Common mode mean is defined as [(SIGmax) + (SIGmin)] / 2. 14 DS703F1 CS5373A DIGITAL CHARACTERISTICS Parameter Digital Inputs High-level Input Voltage Low-level Input Voltage Input Leakage Current Digital Input Capacitance Input Rise Times Except MCLK Input Fall Times Except MCLK Digital Outputs High-level Output Voltage, Iout = -40 µA Low-level Output Voltage, Iout = 40 µA High-Z Leakage Current Digital Output Capacitance Output Rise Times Output Fall Times (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) VOH VOL IOZ COUT tRISE tFALL VD-0.3 9 0.3 V V µA pF ns ns (Note 9) (Note 9) (Note 9) (Note 9, 29) (Note 9, 29) VIH VIL IIN CIN tRISE tFALL 0.6*VD 0.0 VD 0.8 V V µA pF ns ns Symbol Min Typ Max Unit ±1 9 - ±10 100 100 ±10 100 100 Notes: 29. Device is intended to be driven with CMOS logic levels. t rise t fall 0.9 * VD 0.1 * VD Figure 3. Digital Input Rise and Fall Times DS703F1 15 CS5373A DIGITAL CHARACTERISTICS (CONT.) Parameter Master Clock Input MCLK Frequency MCLK Period MCLK Duty Cycle MCLK Rise Time MCLK Fall Time MCLK Jitter (In-band or aliased in-band) MCLK Jitter (Out-of-band) Master Sync Input MSYNC Setup Time to MCLK Rising MSYNC Period MSYNC Hold Time after MCLK Falling MSYNC Instant to TDATA Start MDATA Output MDATA Output Bit Rate MDATA Output Bit Period MDATA Output One’s Density Range Full-scale Output Code TDATA Input TDATA Input Bit Rate TDATA Input One’s Density Range TBSGAIN Full-scale Code TBSGAIN -20 dB Code (Note 34) (Note 9) (Note 35) (Note 35) ftdata TBSOD TBSFS TBS-20dB 25 256 0x04B8F2 0x0078E5 Symbol (Note 30) (Note 30) (Note 9) (Note 9) (Note 9) (Note 9) fCLK tmclk MCLKDC tRISE tFALL MCLKIBJ Min 40 20 40 20 14 0xA2EBE0 Typ 2.048 488 122 976 122 1220 512 1953 - Max 60 50 50 300 1 86 0x5D1420 Unit MHz ns % ns ns ps ns ns ns ns ns kbits/s ns % (Note 9) MCLKOBJ (Note 9, 31) (Note 9, 31) (Note 9, 31) (Note 9, 32) tmss tmsync tmsh ttdata fmdata tmdata (Note 9) (Note 33) MDATOD MDATFS 75 - kbits/s % Notes: 30. MCLK is generated by the CS5378 digital filter. If MCLK is disabled, the device automatically enters a power-down state. 31. MSYNC is generated by the CS5378 digital filter and is latched on MCLK rising edge, synchronization instant (t0) on next MCLK rising edge. 32. TDATA can be delayed from 0 to 63 full bit periods by the test bit stream generator in the CS5378 digital filter. The timing diagrams show no TBSDATA delay. 33. Decimated, filtered, and offset-corrected 24-bit output word from the CS5378 digital filter. 34. TDATA is generated by the test bit stream generator in the CS5378 digital filter. 35. TBSGAIN register value in the CS5378 digital filter. 16 DS703F1 CS5373A DIGITAL CHARACTERISTICS (CONT.) SYNC MCLK (2.048 MHz) MSYNC t0 MDATA (512 kHz) MFLAG TDATA (256 kHz) Figure 4. System Timing Diagram MCLK (2.048 MHz) tmss tmsh tmclk MSYNC t0 tmsync MDATA (2.048 MHz) tmdata MFLAG ttdata TDATA (256 kHz) Figure 5. MCLK / MSYNC Timing Detail DS703F1 17 CS5373A POWER SUPPLY CHARACTERISTICS Parameter Modulator Supply Current (MODE = 0, 1, 2, 3, 4, 5, 6) Analog Power Supply Current Digital Power Supply Current Modulator Sleep Current (MODE = 7) Analog Power Supply Current Digital Power Supply Current Analog Power Supply Current Digital Power Supply Current DAC DC Mode Supply Current (MODE = 4) Analog Power Supply Current Digital Power Supply Current DAC DC Mode Supply Current (MODE = 5) Analog Power Supply Current Digital Power Supply Current DAC Sleep Current (MODE = 0, 7) Analog Power Supply Current Digital Power Supply Current Chip Power Down Current (MCLK = OFF) Analog Power Supply Current Digital Power Supply Current Time to Enter Power Down (MCLK disabled) Power Supply Rejection Power Supply Rejection Ratio (Note 37) PSRR 90 dB (Note 36) (Note 36) (Note 9) IA ID PDTC 1 20 40 µA µA µS (Note 36) (Note 36) IA ID 0.2 20 mA µA (Note 36) (Note 36) IA ID 4.2 20 mA µA (Note 36) (Note 36) IA ID 2.7 20 mA µA (Note 36) (Note 36) (Note 36) (Note 36) IA ID IA ID 0.5 75 8 20 10 mA µA mA µA (Note 36) (Note 36) IA ID 5 75 6 mA µA Symbol Min Typ Max Unit DAC AC Mode Supply Current (MODE = 1, 2, 3, 6) Notes: 36. All outputs unloaded. Digital inputs forced to VD or GND respectively. 37. Power supply rejection is characterized by applying a 100 mVp-p 50-Hz sine wave to each supply. 18 DS703F1 CS5373A VA+ VREF+ VREFVD INR+ INF+ INFINROUT+ 24-Bit ∆Σ Modulator MDATA MFLAG Clock Generator MCLK MSYNC TDATA OUTBUF+ BUFAttenuator 1/1 to 1/64 24-Bit ∆Σ Test DAC CAP+ CAP- VA- ATT(0, 1, 2) MODE(0, 1, 2) GND Figure 6. CS5373A Block Diagram 2. GENERAL DESCRIPTION The CS5373A is a high-performance, fourthorder ∆Σ modulator integrated with a digital-toanalog converter (DAC). When combined with a CS3301A / CS3302A differential amplifier and a CS5378 digital filter, a small low-power self-testing high-accuracy single-channel measurement system results. 2.1 Delta-Sigma Modulator The CS5373A modulator has high dynamic range and low total harmonic distortion with very low power consumption, and is optimized for extremely high-resolution measurement of 5 Vpp or smaller differential signals. It converts analog input signals between DC and 2000 Hz to an oversampled serial bit stream at 512 kbits per second. The CS5378 digital filter generates the clock and synchronization inputs for the modulator while receiving the modulator one-bit data and over-range flag outputs. The digital filter then decimates the modulator’s oversampled output bit stream to a 24-bit output at the selected output word rate. 2.2 Digital-to-Analog Converter The CS5373A test DAC is driven by a digital ∆Σ bit stream from the CS5378 digital filter’s test bit stream (TBS) generator and operates in either AC or DC test modes. AC test modes (MODE 1, 2, 3, 6) are used to measure system THD and CMRR performance. DC test modes (MODE 4, 5) are for gain calibration and pulse tests. The digital filter also provides clock and syncronization signals as well as GPIO control signals to set the operational mode and analog output attenuation. Two sets of differential analog outputs, OUT and BUF, simplify system design as dedicated outputs for testing the electronics channel and for in-circuit sensor tests. Output attenuator settings are binary weighted (1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64) and match the CS3301A / CS3302A amplifier input levels for full-scale testing at all gain ranges. For maximum performance, the precision outputs (OUT±) must drive only high-impedance loads such as the CS3301A / CS3302A amplifier inputs. The buffered outputs (BUF±) can drive lower-impedance loads, down to 1 kΩ, but with reduced performance compared to the precision outputs. The test DAC is optimized for low-power operation and has a restricted operational bandwidth in the AC modes. For stable operation, full-scale AC test signals must not contain frequencies above 100 Hz. AC test signals above 100 Hz (TBS impulse mode, for example) must have a -20 dB reduced amplitude to ensure stability of the low-power ∆Σ architecture. DS703F1 19 CS5373A 3. SYSTEM DIAGRAM System Telemetry Geophone or Hydrophone Sensor M U X CS3301A CS3302A AMP CS5373A CS5378 ∆Σ Modulator and Test DAC Digital Filter w/ PLL µController or Configuration EEPROM Communication Interface Figure 7. System Diagram VA+ 0.1µF VA+ 10nF C0G SENSOR TEST OUTPUT VA+ ELECTRONICS TEST OUTPUT Route BUF as diff pair CAP+ CAPBUF+ BUFRoute OUT as diff pair OUT+ OUTRoute VREF as diff pair VD 0.1µF VD CS5378 SIGNALS MODE0 MODE1 MODE2 ATT0 ATT1 ATT2 TDATA MCLK MSYNC MDATA GPIO GPIO GPIO GPIO GPIO GPIO TBSDATA MCLK MSYNC MDATA MFLAG 2.5 V VREF VA- 10 Ω 100µF + CS5373A VREF+ VREF- 680 Ω INPUT FROM CS3301A CS3302A AMPLIFIER 680 Ω 680 Ω 680 Ω *Populate with 2 x 10nF or 1 x 22nF C0G or better. INR+ 20nF* C0G 20nF* C0G INF+ INFINRVAVA0.1µF MFLAG GND Figure 8. Connection Diagram 20 DS703F1 CS5373A POWER DOWN MCLK = OFF MODE = XXX SLEEP MODE MCLK = ON MODE = 7 MODULATOR MODE MCLK = ON MODE = 0 AC TEST MODES MCLK = ON MODE = 1, 2, 3, 6 DC TEST MODES MCLK = ON MODE = 4, 5 Figure 9. Power Mode Diagram 4. POWER MODES The CS5373A has five power modes. Modulator mode, AC test modes, and DC test modes are operational modes, while power down and sleep mode are non-operational standby modes. 4.1 Power Down If MCLK is stopped, an internal loss-of-clock detection circuit automatically places the CS5373A into power down. Power down is independent of the MODE and ATT pin settings, and is automatically invoked after approximately 40 µs without an incoming MCLK edge. In power down the modulator, AC test circuitry and DC test circuitry are inactive and all outputs are high impedance. When used with the CS5378 digital filter, the CS5373A is in power down immediately after reset since MCLK is disabled by default. 4.2 Sleep Mode With MCLK active, selecting sleep mode (MODE 7) places the CS5373A into a micropower sleep state. In sleep mode the modulator, AC test circuitry and DC test circuitry are inactive and all outputs are high impedance. 4.3 Modulator Mode With MCLK active, selecting modulator mode (MODE 0) enables the CS5373A modulator and places the AC and DC test circuitry into a micro-power sleep state with the analog test outputs high impedance. Following completion of AC and DC system self-tests, the CS5373A is typically set into modulator mode for normal data acquisition. 4.4 AC Test Modes With MCLK and TDATA active, selecting an AC test mode (MODE 1, 2, 3, 6) enables the modulator and causes the DAC to output AC waveforms on the analog test outputs. AC test modes use the low-power ∆Σ DAC circuitry in the CS5373A to create precision differential or common mode analog AC output signals from the encoded digital test bit stream (TBS) input. 4.5 DC Test Modes With MCLK active, selecting a DC test mode (MODE 4, 5) enables the modulator and causes the DAC to generate precision DC voltages on the analog test outputs. DC test modes use switch-capacitor level-shifting buffer circuitry in the CS5373A to create differential or common mode DC analog output voltages from the voltage reference input. DS703F1 21 CS5373A 5. OPERATIONAL MODES The CS5373A has seven operational modes and one sleep mode selected by the MODE2, MODE1, and MODE0 pins. Modes of Operation Selection 0 1 2 3 4 5 6 7 MODE [2:0] 000 001 010 0 11 100 101 11 0 111 bit stream output, i.e. an 86% one’s density has, on average, a ‘1’ value in 86 of every 100 output data bits. The MDATA output has a nominal 50% one’s density for a mid-scale differential input, approximately 86% one’s density for a positive full-scale input, and approximately 14% one’s density for a negative full-scale input. 5.1.2 Modulator Decimated Output When the CS5373A modulator operates with the CS5378 digital filter, the final decimated, 24-bit, full-scale output code range depends if digital offset correction is enabled. With digital offset correction enabled, amplifier offset and the modulator internal offset are removed from the final conversion result. CS5378 Digital Filter Output Code Offset Corrected 5D1420 000000 A2EBE0 +100 mV Offset 60CD40 03B920 A6A500 Mode Description Modulator: enabled. DAC: sleep. Modulator: enabled. DAC: AC OUT and BUF outputs. Modulator: enabled. DAC: AC OUT only, BUF high-z. Modulator: enabled. DAC: AC BUF only, OUT high-z. Modulator: enabled. DAC: DC common mode output. Modulator: enabled. DAC: DC differential output. Modulator: enabled. DAC: AC common mode output. Modulator: sleep. DAC: sleep. Modulator Differential Analog Input Signal > + (VREF + 5%) + VREF 0V - VREF > - (VREF + 5%) Error Flag Possible Table 2. Operational Modes Error Flag Possible 5.1 Modulator Mode Modulator mode (MODE 0) enables the ∆Σ modulator and disables the DAC AC and DC test circuitry to save power. This mode is used for normal sensor measurements after selftests are completed. 5.1.1 Modulator One’s Density In modulator mode (and whenever the modulator is enabled) the differential analog input signal is converted to an oversampled ∆Σ serial bit stream on the MDATA output, with a one’s density proportional to the differential amplitude of the analog input signal. One’s density of the MDATA output is defined as the ratio of ‘1’ bits to total bits in the serial Table 3. Output Coding for the CS5373A Modulator and CS5378 Digital Filter Combination 5.1.3 Modulator Synchronization The modulator is designed to operate synchronously with other modulators in a measurement network, so a rising edge on the MSYNC input resets the internal conversion state machine to synchronize analog sample timing. MSYNC is automatically generated by the CS5378 digital filter after receiving a synchronization signal from the external system, and is chip-to-chip accurate within ± 1 MCLK period. 22 DS703F1 CS5373A 5.1.4 Modulator Idle Tones The CS5373A modulator is ∆Σ type and so can produce ‘idle tones’ in the measurement bandwidth when the differential input signal is a steady-state DC signal near mid-scale. Idle tones result from low-frequency patterns in the output bit stream and appear in the measurement spectrum as small tones about -135 dB down from full scale. Idle tones are eliminated within the CS5373A modulator by automatically adding +100 mV of internal differential offset during conversion to push idle tones out of the measurement bandwidth. Care should be taken to ensure external offset voltages do not negate the internally added differential offset. 5.1.5 Modulator Stability The CS5373A’s ∆Σ modulator has a 4th order architecture which is conditionally stable and may go into an oscillatory condition if the analog inputs are over-ranged more than 5% past either positive or negative full scale. If an unstable condition is detected, the modulator collapses to a 1st order system and transitions the MFLAG output low-to-high to signal an error condition to the CS5378 digital filter. The analog input signal must be reduced to within the full-scale range for at least 32 MCLK cycles for the modulator to recover from an oscillatory condition. If the analog input remains over-ranged for an extended period, the modulator will cycle between 4th order and 1st order operation and the MFLAG output will be seen to pulse. 5.2 AC Test Modes AC test modes (MODE 1, 2, 3, 6) enable the modulator and use the digital test bit stream (TBS) input from the CS5378 digital filter to construct analog AC waveforms. The digital bit stream input to the TDATA pin encodes the analog waveform as over-sampled one-bit ∆Σ data, which is then converted into precision differential or common mode analog AC sigDS703F1 nals by the CS5373A’s test DAC. 5.2.1 AC Differential The first three AC test modes (MODE 1, 2, 3) enable the modulator and AC test circuitry to create precision differential analog signals for THD and impulse testing of the measurement channel. In mode 1, both sets of differential analog outputs (OUT and BUF) are enabled. In mode 2 only the OUT analog output is enabled, and the BUF output is high impedance. In mode 3 only the BUF analog output is enabled, and the OUT output is high impedance. OUT+ OUT- Maximum 5 Vpp Differential CS5373A MODE 1 BUF+ BUFMaximum 5 Vpp Differential OUT+ OUT- Maximum 5 Vpp Differential CS5373A MODE 2 BUF+ BUFHigh Impedance OUT+ OUT- High Impedance CS5373A MODE 3 BUF+ BUFMaximum 5 Vpp Differential Figure 10. AC Differential Modes 23 CS5373A Differential AC test signals out of the CS5373A consist of two halves with equal but opposite magnitude, varying about a common mode voltage. A full-scale 5 VPP differential AC signal centered on a -0.15 V common mode voltage will have: SIG+ = -0.15 V + 1.25 V = +1.1 V SIG- = -0.15 V - 1.25 V = -1.4 V SIG+ is +2.5 V relative to SIGFor the opposite case: SIG+ = -0.15 V - 1.25 V = -1.4 V SIG- = -0.15 V + 1.25 V = +1.1 V SIG+ is -2.5 V relative to SIGSo the total swing for SIG+ relative to SIG- is (+2.5 V) - (-2.5 V) = 5 Vpp differential. A similar calculation can be done for SIG- relative to SIG+. It’s important to note that a 5 Vpp differential signal centered on a -0.15 V common mode voltage never exceeds +1.1 V with respect to ground and never drops below -1.4 V with respect to ground on either half. By definition, differential voltages are measured with respect to the opposite half, not relative to ground. A voltmeter differentially measuring between SIG+ and SIG- in the above example would correctly read 1.767 Vrms, or 5 Vpp. 5.2.2 AC Common Mode The final AC test mode (MODE 6) enables the modulator and AC test circuitry to create a matched AC common mode analog signal for CMRR testing of the measurement channel. In mode 6, both sets of analog outputs (OUT and BUF) are enabled. There is no AC common mode output for an attenuator setting of 1/64. Gross leakage in the sensor channel can be detected by applying a full-scale AC common mode signal. If there is a significant differential mismatch in the channel due to sensor leakage, the AC common mode signal will be converted to a measurable differential signal at the fundamental frequency. 5.2.3 DAC Stability For the CS5373A’s low-power ∆Σ DAC architecture to remain stable, the TDATA input bit stream should only encode 100 Hz or lower bandwidth analog signals. For TDATA bit stream frequencies above 100 Hz (for example, TBS impulse mode), the encoded amplitude must be reduced -20 dB below full scale to guarantee stability. If the CS5373A’s low-power ∆Σ DAC architecture becomes unstable, persistent elevated noise will be present on the analog outputs and AC linearity will be poor. To recover stability, place the CS5373A into power down or sleep mode and restart the CS5378 test bit stream generator before placing the CS5373A back into an AC test mode. 5.3 DC Test Modes DC test modes enable the modulator and DC test circuitry to create precision level-shifted and buffered versions of the voltage reference input as precision DC common mode and DC differential analog outputs. The absolute accuracy of the DC test modes is highly dependent on the absolute accuracy of the voltage reference input voltage. 5.3.1 DC Common Mode The first DC test mode (MODE 4) enables the modulator and DC test circuitry to create a matched DC common mode analog output voltage as a baseline measurement for gain DS703F1 OUT+ OUT- Maximum 2.5 Vpp Common Mode CS5373A MODE 6 BUF+ BUFMaximum 2.5 Vpp Common Mode Figure 11. AC Common Mode 24 CS5373A calibration and differential pulse tests. In mode 4, both sets of analog outputs (OUT and BUF) are enabled. 5.3.2 DC Differential The second DC test mode (MODE 5) enables the modulator and DC test circuitry to create a precision differential DC analog output voltage as the final measurement for gain calibration and as the step/pulse output for differential pulse tests. In mode 5, both sets of analog outputs (OUT and BUF) are enabled. In DC differential mode (MODE 5), level-shifting buffer circuitry adds low-level 32 kHz switched-capacitor noise to the DC output. This noise is out of the measurement bandwidth for systems designed with a CS3301A / CS3302A amplifier and CS5373A modulator and is rejected by the CS5378 digital filter. This 32 kHz noise does not affect DC system tests, though it may be visible on an oscilloscope at high gain levels. By measuring both DC test modes (MODE 4, 5), precision gain-calibration coeffiApprox -0.15 VDC Common Mode cients can be calculated for the measurement channel. By first measuring the differential offset of the DC common mode output (MODE 4) and then measuring the DC differential mode amplitude (MODE 5), a precise offset-corrected, volts-to-codes conversion ratio can be calculated. This known ratio is then used along with the CS5378 digital filter GAIN register to normalize the full-scale amplitude to match other channels in the measurement network. By switching between DC common mode (MODE 4) and DC differential mode (MODE 5), pulse waveforms can be created to characterize the step response of the measurement channel. If a pulse test requires precise timing control, an external controller should directly toggle the MODE pins of the CS5373A to avoid delays associated with writing to the CS5378 digital filter GPIO register. Sensor impedance can be measured using DC differential mode (MODE 5), provided matched series resistors are installed between the BUF analog outputs and the sensor. Applying the known DC differential voltage to the resistor-sensor-resistor string permits a ratiometric sensor impedance calculation from the measured voltage drop across the sensor. Switching between DC differential mode (MODE 5) and modulator mode (MODE 0) can, in the case of a moving-coil geophone, test basic parameters of the electro-mechanical transfer function. The voltage relaxation characteristic of the sensor when switching the analog outputs from a differential DC voltage to high impedance depends primarily on the geophone resonant frequency and damping factor. 5.4 Sleep Mode Sleep mode (MODE 7) saves system power when measurements are not required by turning off the modulator, AC test circuitry, and DC test circuitry. In sleep mode the modulator digital outputs and the BUF and OUT analog outputs are high impedance. 25 OUT+ OUT- CS5373A MODE 4 BUF+ BUFApprox -0.15 VDC Common Mode OUT+ OUT- Maximum 2.5 VDC Differential CS5373A MODE 5 BUF+ BUFMaximum 2.5 VDC Differential Figure 12. DC Test Modes DS703F1 CS5373A VA+ 0.1µF VA+ CAP+ CAPBUF+ BUFRoute OUT as diff pair OUT+ OUTRoute VREF as diff pair MODE0 MODE1 MODE2 ATT0 ATT1 VD VD 0.1µF 10nF C0G SENSOR TEST OUTPUT VA+ ELECTRONICS TEST OUTPUT Route BUF as diff pair CS5378 SIGNALS GPIO GPIO GPIO GPIO GPIO GPIO TBSDATA MCLK MSYNC MDATA MFLAG 2.5 V VREF VA- 10 Ω 100µF + CS5373A VREF+ VREF- ATT2 TDATA MCLK 680 Ω INPUT FROM CS3301A CS3302A AMPLIFIER 680 Ω 680 Ω 680 Ω *Populate with 2 x 10nF or 1 x 22nF C0G or better. INR+ 20nF* C0G 20nF* C0G INF+ MSYNC MDATA INFINRVAVA0.1µF MFLAG GND Figure 13. Digital Signals 6. DIGITAL SIGNALS The CS5373A is designed to operate with the CS5378 digital filter. The digital filter generates the master clock and synchronization signals (MCLK and MSYNC) while receiving back the modulator one-bit ∆Σ conversion data (MDATA) and over-range flag (MFLAG). It also generates digital one-bit ∆Σ test bit stream data for the test DAC (TDATA) and controls GPIO pins to set the operational mode (MODE) and attenuation (ATT). 6.1 MCLK Connection The CS5378 digital filter generates the master clock for CS5373A, typically 2.048 MHz, from a synchronous CLK input from the external system. By default, MCLK is disabled at reset and is enabled by writing the digital filter CONFIG register. If MCLK is disabled during operation, the CS5373A will enter power down after approximately 40 µS. MCLK must have low in-band jitter to guarantee full analog performance, requiring a crystal- or VCXO-based system clock into the digital filter. Clock jitter on the digital filter external CLK input directly translates to jitter on MCLK. 6.2 MSYNC Connection The CS5378 digital filter also provides a synchronization signal to the CS5373A. The MSYNC signal is generated following a rising edge received on the digital filter SYNC input. By default MSYNC generation is disabled at reset and is enabled by writing to the digital filter CONFIG register. The input SYNC signal to the CS5378 digital filter sets a common reference time t0 for measurement events, thereby synchronizing analog sampling across a measurement network. The timing accuracy of the received SYNC signal from node to node must be +/- 1 MCLK to maximize the MSYNC analog sample synchronization accuracy. The CS5373A MSYNC input is rising-edge triggered and resets the internal MCLK counter/divider to guarantee synchronous operation with other system devices. While the MSYNC signal synchronizes the internal operation of the CS5373A, by default, it does not synchronize the phase of the incoming encoded digital test bit stream (TBS) sine wave unless enabled in the digital filter TBSCFG register. 26 DS703F1 CS5373A 6.3 MDATA Connection The CS5373A modulator outputs a ∆Σ serial bit stream to the MDATA pin, with a one’s density proportional to the differential amplitude of the analog input signal. The output bit rate from the MDATA output is a divide-by-four of the input master clock, and so is nominally 512 kHz. The MDATA output has a nominal 50% one’s density for mid-scale input, approximately 86% one’s density for a positive full-scale input, and approximately 14% one’s density for a negative full-scale input. One’s density of the MDATA output is defined as the ratio of ‘1’ bits to total bits in the serial bit stream output, i.e. an 86% one’s density has, on average, a ‘1’ value in 86 of every 100 output data bits. 6.4 MFLAG Connection The CS5373A ∆Σ modulator has a 4th order architecture which is conditionally stable and may go into an oscillatory condition if the analog inputs are over-ranged more than 5% past either positive or negative full-scale. If an unstable condition is detected, the modulator collapses to a 1st order system and transitions the MFLAG output low-to-high to signal an error condition to the CS5378 digital filter. The analog signal must be reduced to within the full-scale input range for at least 32 MCLK cycles for the modulator to recover from an oscillatory condition. If the analog input remains over-ranged for an extended period, the modulator will cycle between 4th order and 1st order operation and the MFLAG output will be seen to pulse. The MFLAG output connects to a dedicated input on the CS5378 digital filter, causing an error flag to be set in the status portion of the next conversion output data word. 6.5 TDATA Connection The TDATA digital input to the test DAC expects encoded one-bit ∆Σ data nominally at a 256 kHz rate. The one’s density input range is DS703F1 approximately 25% minimum to 75% maximum, with differential mid-scale at 50% one’s density. The CS5378 digital filter test bit stream (TBS) generator can encode two types of AC signals as over-sampled, one-bit ∆Σ data – a pure sine wave for THD and CMRR testing or a triggerable impulse waveform for synchronization testing and impulse response characterization. In the AC test modes, the test DAC converts the over-sampled test bit stream digital data into precision differential or common mode analog AC signals. The CS5378 TBS sine mode encodes an approximately 5 Vpp full-scale sine wave signal with a digital filter TBSGAIN register setting of 0x04B8F2. Because TBS impulse mode encodes frequencies above 100 Hz, a maximum 0x0078E5 TBSGAIN impulse mode register setting is specified to guarantee stability of the DAC low-power ∆Σ circuitry. Details on the setup and operation of the digital filter test bitstream (TBS) generator can be found in the CS5378 data sheet. 6.6 GPIO Connections The CS5378 controls 8 general-purpose input output (GPIO) pins through the digital filter GPCFG register. These GPIO pins are typically assigned to operate the CS5373A mode and attenuator pins, along with the CS3301A / CS3302A amplifier input mux and gain pins. The gain and attenuation settings of the CS3301A / CS3302A amplifiers and the CS5373A test DAC are identically decoded to allow full-scale performance testing at all system gain ranges with shared GAIN and ATT control signals. If precise timing control of operational modes is required (for example, switching between DC modes for pulse generation), an external controller should directly toggle the MODE pins of the CS5373A to avoid the delay associated with writing to the CS5378 digital filter GPCFG register. 27 CS5373A VA+ 0.1µF VA+ CAP+ CAPBUF+ BUFRoute OUT as diff pair OUT+ OUTRoute VREF as diff pair MODE0 MODE1 MODE2 ATT0 ATT1 VD VD 0.1µF 10nF C0G SENSOR TEST OUTPUT VA+ ELECTRONICS TEST OUTPUT Route BUF as diff pair CS5378 SIGNALS GPIO GPIO GPIO GPIO GPIO GPIO TBSDATA MCLK MSYNC MDATA MFLAG 2.5 V VREF VA- 10 Ω 100µF + CS5373A VREF+ VREF- ATT2 TDATA MCLK 680 Ω INPUT FROM CS3301A CS3302A AMPLIFIER 680 Ω 680 Ω 680 Ω *Populate with 2 x 10nF or 1 x 22nF C0G or better. INR+ 20nF* C0G 20nF* C0G INF+ MSYNC MDATA INFINRVAVA0.1µF MFLAG GND Figure 14. Analog Signals 7. ANALOG SIGNALS The CS5373A has multiple differential analog inputs and outputs. The modulator analog inputs are separated into rough and fine charge differential pairs (INR±, INF±) for maximum sampling accuracy. Both sets of modulator inputs require a simple differential anti-alias RC filter to ensure high-frequency signals do not alias into the measurement bandwidth. The test DAC has a precision differential output (OUT±) that provides the best analog performance, but with only minimal drive capability. A buffered output (BUF±) can drive an external load, but with reduced analog performance. Finally, the test DAC internal antialias filter requires a dedicated capacitor connection (CAP±) to eliminate undesired highfrequency signals. 7.1 INR±, INF± Modulator Inputs The modulator analog inputs are separated into differential rough and fine signals (INR±, INF±). The positive half of the differential input signal is connected to INR+ and INF+, while the negative half is attached to INF- and INR-. The INR± pins are switched-capacitor ‘rough charge’ inputs that pre-charge the internal analog sampling capacitor before it is connected to the INF± fine input pins. 28 7.1.1 Modulator Input Impedance The modulator input has a dynamic switchedcapacitor architecture and so has a rough charge input impedance that is inversely proportional to the input master clock frequency and the input capacitor size, [1 / (f * C)]. • • • MCLK = 2.048 MHz INR± Input Cap = 20 pF Impedance = [1 / (2.048 MHz * 20 pF)] = 24 kΩ. Internal to the modulator, the rough inputs (INR±) pre-charge the sampling capacitor used by the fine inputs (INF±), therefore the input current to the fine inputs is very low and the effective input impedance is orders of magnitude above the impedance of the rough inputs. 7.1.2 Modulator Anti-alias Filter The modulator inputs are required to be bandwidth limited to ensure modulator loop stability and prevent high-frequency signals from aliasing into the measurement band. The use of simple single-pole differential low-pass RC filters across the INR± and INF± inputs ensures high-frequency signals are rejected before they can alias into the measurement band. DS703F1 CS5373A The -3 dB corner of the input anti-alias filter is nominally set to the internal analog sampling rate divided by 64, which itself is a division by 4 of the MCLK input rate. • • • • MCLK Frequency = 2.048 MHz Sampling Frequency = MCLK / 4 = 512 kHz -3 dB Filter Corner = Sample Freq / 64 = 8 kHz RC filter = 8 kHz = 1 / [ 2π * (2 * Rseries) * Cdiff)] Selection ATT[2:0] 0 1 2 3 4 5 6 7 000 001 010 0 11 100 101 11 0 111 Attenuation 1/1 1/2 1/4 1/8 1/16 1/32 1/64 reserved dB 0 dB -6.02 dB -12.04 dB -18.06 dB -24.08 dB -30.10 dB -36.12 dB reserved Figure 14 illustrates the CS5373A modulator analog connections with input anti-alias filter components. Filter components on the rough and fine pins should be identical values for optimum performance, with the capacitor values a minimum of 0.02 µF. The rough input can use either X7R or C0G type capacitors, while the fine input requires C0G type capacitors for optimal linearity. Using X7R type capacitors on the fine analog inputs will degrade total harmonic distortion significantly. The CS3301A / CS3302A differential amplifiers are designed with separate rough and fine analog outputs (OUTR±, OUTF±) that match the rough and fine inputs to the modulator (INR±, INF±). External anti-alias series resistors and differential capacitors create the required anti-alias RC filters. 7.2 DAC Output Attenuation The CS5373A test DAC has seven analog output attenuation settings from 1/1 to 1/64 selected with the ATT2, ATT1, and ATT0 pins. When enabled, attenuation is applied to both the OUT± and BUF± differential analog outputs. At 1/64 attenuation in AC Common Mode (MODE 6) there is no output signal amplitude Figure 15. DAC Output Attenuation Settings due to the attenuator architecture. The OUT± pins connect directly into the internal attenuator resistors and so attenuation accuracy is highly sensitive to load impedance on the OUT± pins. Loading on the BUF± pins does not affect attenuator accuracy. The attenuation settings of CS5373A match the gain ranges of the CS3301A / CS3302A differential amplifiers to enable full-scale testing at all gain ranges. The CS3301A / CS3302A amplifier gain settings (GAIN) are decoded identical to the CS5373A attenuator settings (ATT) and so can share GPIO control signals from the CS5378 digital filter. 7.3 DAC OUT± Precision Output The test DAC OUT± pins are precision differential analog outputs for testing the high-performance electronics measurement channel. These precision outputs have higher perfor- DS703F1 29 CS5373A mance specifications than the BUF± outputs, but with a much higher sensitivity to external loading. Excessive resistive or capacitive loading on the OUT± pins will degrade the analog performance characteristics of the test DAC in all operational modes. The OUT± precision output is optimized for direct connection to the CS3301A / CS3302A amplifier differential inputs, which have very high input impedance. These amplifiers include a pin-controlled input multiplexer to switch between an internal differential termination for noise tests and two external differential inputs. One external input is typically dedicated to sensor measurements and the other to testing the electronics channel. The OUT± outputs are enabled in all operational modes except modulator mode (MODE 0), “AC BUF Only” mode (MODE 3) and sleep mode (MODE 7). In these modes the OUT± pins are high impedance. 7.4 DAC BUF± Buffered Output The test DAC BUF± pins are buffered differential analog outputs for testing external sensors such as geophones or hydrophones. The buffered outputs have reduced performance specifications compared with the OUT± outputs, but are less sensitive to external loading. The BUF± outputs are enabled in all operational modes except modulator mode (MODE 0), “AC OUT Only” mode (MODE 2) and sleep mode (MODE 7). In these modes the BUF± pins are high impedance to ensure they do not interfere with sensor operation during normal data acquisition. For sensor impedance testing, it is required to place matched series resistors in between the BUF± outputs and the differential sensor. With known series resistors and a known DC differential source voltage, sensor resistance can be calculated ratiometrically from the measured voltage drop across the sensor. 7.5 DAC CAP± Connection The CS5373A test DAC requires a 10 nF C0G type capacitor to be connected differentially across the CAP± pins. This capacitor creates an internal anti-alias filter to eliminate high-frequency signals from the OUT± and BUF± analog outputs and helps to maintain the stability of the low-power ∆Σ DAC circuitry. A COG, NPO or similar high-quality capacitor is required for CAP± since other capacitor types, such as X7R, do not have the required linearity. Using a poor-quality capacitor on CAP± will significantly degrade THD performance of the test DAC AC operational modes. 7.6 Analog Differential Signals Differential AC test signals into and out of the CS5373A consist of two halves with equal but opposite magnitude varying about a common mode voltage. A full-scale 5 VPP differential AC signal centered on a -0.15 V common mode voltage will have: SIG+ = -0.15 V + 1.25 V = +1.1 V SIG- = -0.15 V - 1.25 V = -1.4 V SIG+ is +2.5 V relative to SIGFor the opposite case: SIG+ = -0.15 V - 1.25 V = -1.4 V SIG- = -0.15 V + 1.25 V = +1.1 V SIG+ is -2.5 V relative to SIGSo the total swing for SIG+ relative to SIG- is (+2.5 V) - (-2.5 V) = 5 Vpp differential. A similar calculation can be done for SIG- relative to SIG+. It’s important to note that a 5 Vpp differential signal centered on a -0.15 V common mode voltage never exceeds +1.1 V with respect to ground and never drops below -1.4 V with respect to ground on either half. By definition, differential voltages are measured with respect to the opposite half, not relative to ground. A voltmeter differentially measuring between SIG+ and SIG- in the above example would correctly read 1.767 Vrms, or 5 Vpp. 30 DS703F1 CS5373A From VA+ Regulator 100 µF 0.1 µF 10 Ω 2.500 V VREF 0.1 µF Route VREF± as a differential pair from the 100uF RC filter capacitor + 100 µF 0.1 µF To VREF+ From VARegulator 100 µF 0.1 µF 0.1 µF To VREF- Figure 16. Voltage Reference Circuit 8. VOLTAGE REFERENCE The CS5373A requires a 2.500 V precision voltage reference to be supplied to the VREF± pins. 8.1 VREF Power Supply To guarantee proper regulation headroom for the voltage reference device, the voltage reference GND pin should be connected to VA- instead of system ground, as shown in Figure 16. This connection results in a VREFvoltage equal to VA- and a VREF+ voltage very near ground [(VA-) + 2.500 VREF]. Power supply inputs to the voltage reference device should be bypassed to system ground with 0.1 µF capacitors placed as close as possible to the power and ground pins. In addition to 0.1 µF local bypass capacitors, at least 100 µF of bulk capacitance to system ground should be placed on each power supply near the voltage regulator outputs. Bypass capacitors should be X7R, C0G, tantalum, or other high-quality dielectric type. 8.2 VREF RC Filter A primary concern in selecting a precision voltage reference device is noise performance in the measurement bandwidth. The Linear Technology LT1019AIS8-2.5 voltage reference yields acceptable noise levels if the output is filtered with a low-pass RC filter. A separate RC filter is required for each system device connected to a given voltage referDS703F1 ence. By sharing a common RC filter, signaldependent sampling of the voltage reference by one system device could cause unwanted tones to appear in the measurement bandwidth of another system device via common impedance coupling. 8.3 VREF PCB Routing To minimize the possibility of outside noise coupling into the CS5373A voltage reference input, the VREF± traces should be routed as a differential pair from the large capacitor of the voltage reference RC filter. Careful control of the voltage reference source and return currents by routing VREF± as a differential pair will improve immunity from external noise. To further improve noise rejection of the VREF± routing, include 0.1 µF bypass capacitors to system ground as close as possible to the VREF+ and VREF- pins of the CS5373A. 8.4 VREF Input Impedance The switched-capacitor input architecture of the VREF± inputs results in an input impedance that depends on the internal capacitor size and the clock frequency. With a 15 pF internal capacitor and a 2.048 MHz MCLK the VREF input impedance is approximately [1 / [(2.048 MHz) * (15 pF)]] = 32 kΩ. While the size of the internal capacitor is fixed, the voltage reference input impedance will vary 31 CS5373A with MCLK. The voltage reference external RC filter series resistor creates a voltage divider with the VREF input impedance to reduce the effective applied input voltage. To minimize gain error resulting from this voltage divider effect, the RC filter series resistor should be the minimum size recommended in the voltage reference device data sheet. 8.5 VREF Accuracy The nominal voltage reference input is specified as 2.500 V across the VREF± pins, and all CS5373A gain accuracy specifications are measured with a nominal voltage reference input. Any variation from a nominal VREF input will proportionally vary the analog full-scale gain accuracy. Since temperature drift of the voltage reference results in gain drift of the analog full-scale amplitude, care should be taken to minimize temperature drift effects through careful selection of passive components and the voltage reference device itself. Gain drift specifications of the CS5373A do not include the temperature drift effects of external passive components or of the voltage reference device itself. 8.6 VREF Independence If the test signal source is required to be fully independent of the measurement channel, the CS5373A device cannot be used. Instead, a CS5371A modulator and a CS4373A test DAC should be used and connected to two independent voltage reference devices. This will eliminate the possibility for undetected ratiometric errors when the same voltage reference device is used by both the test signal source and the measurement channel. Because modern precision voltage references are highly reliable, requirements for separate modulator and test DAC voltage references should be considered carefully. In the unlikely event of voltage reference failure independent of other system components, the CS5373A volts-to-codes ratio will be out of spec and measurement channel performance will be poor during system self-tests. 32 DS703F1 CS5373A To VA+ Regulator 100 uF 0.1 uF VA+ VD 0.1 uF 100 uF To VD Regulator CS5373A VATo VARegulator 100 uF 0.1 uF GND Figure 17. Power Supply Diagram 9. POWER SUPPLIES The CS5373A has a positive analog power supply pin (VA+), a negative analog power supply pin (VA-), a digital power supply pin (VD), and a ground pin (GND). For proper operation, power must be supplied to all power supply pins, and the ground pin must be connected to system ground. The CS5373A digital power supply (VD) and the CS5378 digital power supply (VDDPAD) must share a common power supply voltage. 9.1 Power Supply Bypassing The VA+, VA-, and VD power supplies should be bypassed to system ground with 0.1 µF capacitors placed as close as possible to the power pins of the device. In addition to the 0.1 µF local bypass capacitors, at least 100 µF bulk capacitance to system ground should be placed on each power supply near the voltage regulator output, with additional power supply bulk capacitance placed among the analog component route if space permits. Bypass capacitors should be X7R, C0G, tantalum, or other high-quality dielectric type. 9.2 PCB Layers and Routing The CS5373A is a high-performance device, and special care must be taken to ensure power and ground routing is correct. Power can be supplied either through dedicated power planes or routed traces. When routing power traces, it is recommended to use a “star” routDS703F1 ing scheme with the star point either at the voltage regulator output or at a local power supply bulk capacitor. It is also recommended to dedicate a full PCB layer to a solid ground plane, without splits or routing. All bypass capacitors should connect between the power supply circuit and the solid ground plane as near as possible to the device power supply pins. The CS5373A analog signals are differentially routed and do not normally require connection to a separate analog ground. However, if a separate analog ground is required, it should be routed using a “star” routing scheme on a separate layer from the solid ground plane and connected to the ground plane only at the star point. Be sure all active devices and passive components connected to the analog ground are included in the “star” route to ensure sensitive analog currents do not return through the ground plane. 9.3 Power Supply Rejection Power supply rejection of the CS5373A is frequency dependent. The CS5378 digital filter rejects power supply noise for frequencies above the selected digital filter corner frequency. Power supply noise frequencies between DC and the digital filter corner frequency are rejected as specified in the Power Supply Characteristics table. 33 CS5373A 9.4 SCR Latch-up The VA- pin is tied to the CS5373A CMOS substrate and must always be the most-negative voltage applied to the device to ensure SCR latch-up does not occur. In general, latch-up may occur when any pin voltage exceeds the limits specified in the Absolute Maximum Ratings table. It is recommended to connect the VA- power supply to system ground (GND) with a reverse-biased Schottky diode. At power up, if the VA+ power supply ramps before the VAsupply is established, the VA- pin voltage could be pulled above ground potential through the CS5373A device. If the VA- supply is pulled 0.7 V or more above GND, SCR latch-up can occur. A reverse-biased Schottky diode will clamp the VA- voltage a maximum of 0.3 V above ground to ensure SCR latch-up does not occur at power up. 9.5 DC-DC Converters Many low-frequency measurement systems are battery powered and utilize DC-DC con- verters to efficiently generate power supply voltages. To minimize interference effects, operate the DC-DC converter at a frequency which is rejected by the digital filter, or operate it synchronous to the MCLK rate. A synchronous DC-DC converter whose operating frequency is derived from MCLK will theoretically minimize the potential for “beat frequencies” to appear in the measurement bandwidth. However this requires the source clock to remain jitter-free within the DC-DC converter circuitry. If clock jitter can occur within the DC-DC converter (as in a PLL-based architecture), it’s better to use a nonsynchronous DC-DC converter whose switching frequency is rejected by the digital filter. During PCB layout, do not place high-current DC-DC converters near sensitive analog components. Carefully routing a separate DC-DC “star” ground will help isolate noisy switching currents away from the sensitive analog components. 34 DS703F1 CS5373A 10. TERMINOLOGY • Signal-to-Noise Ratio (Dynamic Range) - Ratio of the rms magnitude of the full-scale signal to the integrated rms noise from DC to 430 Hz. The following formula is used to calculate SNR: SNR = 20log • Total Harmonic Distortion - Ratio of the power of the fundamental frequency to the sum of the powers of all harmonic frequencies from DC to 430 Hz. The following formula is used to calculate THD: THD = 10log • Full-scale Bandwidth - The bandwidth in which the converter can generate a full-scale signal while maintaining performance specifications. • Impulse Amplitude - The maximum amplitude of the output signal beyond the full-scale bandwidth. • Differential Output Level - The voltage between the analog output pins of the device. • Full-scale Accuracy - Variation in the measured output voltage from the theoretical full-scale output voltage at 1x attenuation. The following formula is used to calculate full-scale accuracy: full scale accuracy = • •100% Relative Accuracy - Variation in the measured output voltage from the theoretical attenuated output voltage at each of the attenuation ranges. The following formula is used to calculate relative accuracy: measured attenuated voltage - theoretical attenuated voltage relative accuracy = theoretical attenuated voltage (relative to the measured full scale voltage) •100% • Full Scale Drift - The variation of the measured full-scale voltage across the specified temperature range. • Common Mode Drift - The variation in the measured common mode voltage across the specified temperature range. DS703F1 35 | ( ( | ( ( measured full scale voltage - theoretical full scale voltage theoretical full scale voltage ( of the harmonic frequencies ( sum of the powers fundamental frequency power of the ( full scale signal ( rms magnitude of of noise floor rms magnitude | | CS5373A 11. PIN DESCRIPTION Positive Capacitor Output Negative Capacitor Output Positive Buffered Output Negative Buffered Output Positive High Precision Output Negative High Precision Output Positive Analog Power Supply Negative Analog Power Supply Negative Voltage Reference Positive Voltage Reference Positive Analog Rough Input Positive Analog Fine Input Negative Analog Fine Input Negative Analog Rough Input CAP+ CAPBUF+ BUFOUT+ OUTVA+ VAVREFVREF+ INR+ INF+ INFINRGND MODE0 MODE1 MODE2 ATT0 ATT1 ATT2 TDATA VD GND MCLK MSYNC MDATA MFLAG System Ground Mode Select Mode Select Mode Select Attenuation Range Select Attenuation Range Select Attenuation Range Select Test Bit Stream Input Positive Digital Power Supply System Ground Master Clock Input Master Sync Input Modulator Data Output Modulator Over-range Indicator 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Pin Name Pin # I/O Pin Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CAP+, CAPBUF+, BUFOUT+, OUTVA+, VAVREF-, VREF+ INR+, INF+ INF-, INR-, MFLAG MDATA MSYNC MCLK GND VD TDATA O Capacitor connection for internal anti-alias filter. O Buffered differential analog output. O Precision differential analog output. Analog power supply. Refer to the Specified Operating Conditions. I I I Voltage reference input. Refer to the Specified Operating Conditions. Analog differential rough and fine + inputs. From the + half of the differential anti-alias filter. Analog differential rough and fine - inputs. From the - half of the differential anti-alias filter. O Amplitude overload indicator flag. O Oversampled ∆Σ bit stream conversion output. I Master sync input. Low to high transition resets the internal clock phasing. Master clock input. CMOS compatible clock input. System ground. Digital power supply. Refer to the Specified Operating Conditions. I I Test Bit Stream input from digital filter TBS generator. 36 DS703F1 CS5373A Pin Name Pin # I/O Pin Description 22, 23, 24 ATT2, ATT1, ATT0 I Attenuation Range. Selects the output attenuation range. Attenuation Selection 0 1 2 3 4 5 6 7 ATT[2:0] 000 001 010 0 11 100 101 11 0 111 Attenuation 1/1 1/2 1/4 1/8 1/16 1/32 1/64 reserved dB 0 dB -6.02 dB -12.04 dB -18.06 dB -24.08 dB -30.10 dB -36.12 dB reserved MODE2, MODE1, MODE0 25, 26, 27 I Mode Selection. Determines the operational mode of the device. Modes of Operation Selection MODE[2:0] 0 1 2 3 4 5 6 7 000 001 010 0 11 100 101 11 0 111 Mode Description Modulator: enabled. DAC: sleep. Modulator: enabled. DAC: AC OUT and BUF outputs. Modulator: enabled. DAC: AC OUT only, BUF high-z. Modulator: enabled. DAC: AC BUF only, OUT high-z. Modulator: enabled. DAC: DC common mode output. Modulator: enabled. DAC: DC differential output. Modulator: enabled. DAC: AC common mode output. Modulator: sleep. DAC: sleep. GND 28 System ground. DS703F1 37 CS5373A 12. PACKAGE DIMENSIONS 28L SSOP PACKAGE DRAWING N D E11 A2 A1 A E ∝ L e b2 SIDE VIEW END VIEW SEATING PLANE 123 TOP VIEW DIM A A1 A2 b D E E1 e L ∝ MIN -0.002 0.064 0.009 0.390 0.291 0.197 0.022 0.025 0° INCHES NOM -0.006 0.069 -0.4015 0.307 0.209 0.026 0.0354 4° MAX 0.084 0.010 0.074 0.015 0.413 0.323 0.220 0.030 0.041 8° MIN -0.05 1.62 0.22 9.90 7.40 5.00 0.55 0.63 0° MILLIMETERS NOM -0.15 1.75 -10.20 7.80 5.30 0.65 0.90 4° NOTE MAX 2.13 0.25 1.88 0.38 10.50 8.20 5.60 0.75 1.03 8° 2,3 1 1 JEDEC #: MO-150 Controlling Dimension is Millimeters Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. 38 DS703F1 CS5373A 13.ORDERING INFORMATION Model Temperature Package CS5373A-ISZ (lead free) -40 to +85 °C 28-pin SSOP 14.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS5373A-ISZ (lead free) 260 °C 3 7 Days * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS703F1 39 CS5373A 15.REVISION HISTORY Revision PP1 PP2 Date NOV 2005 NOV 2005 Preliminary release for CS5373A. Correct voltage units of full-scale DC differential output and common mode AC output at 1/4 attenuation. Add Ttdata timing to Figure 5. Correct bypass capacitor sizes in Figure 8. Correct definition of pin 28 in Pin Description table. Updated to final status with most-recent characterization data for Cirrus QPL process. Changes F1 DEC 2006 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. 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IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 40 DS703F1