CS5376A

CS5376A Low-power, Multi-channel Decimation Filter Features 1- to 4-channel Digital Decimation Filter Multiple On-chip FIR and IIR Coefficient Sets Programmable Coefficients for Custom Filters Synchronous Operation Description The CS5376A is a multi-function digital filter utilizing a low-power signal processing architecture to achieve efficient filtering for up to four ∆Σ modulators. By combining the CS5376A with CS3301A/02A differential amplifiers, CS5371A/72A ∆Σ modulators, and the CS4373A ∆Σ test DAC a synchronous, high-resolution, self-testing, multi-channel measurement system can be designed quickly and easily. Digital filter coefficients for the CS5376A FIR and IIR filters are included on-chip for a simple setup, or they can be programmed for custom applications. Selectable digital filter decimation ratios produce output word rates from 4000 SPS to 1 SPS, resulting in measurement bandwidths ranging from 1600 Hz down to 400 mHz when using the on-chip coefficient sets. Selectable Output Word Rate 4000, 2000, 1000, 500, 333, 250 SPS 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS Digital Gain and Offset Corrections Test DAC Bit-stream Generator Digital Sine Wave Output Time Break Controller, General Purpose I/O Secondary SPI™ Port, Boundary Scan JTAG Microcontroller or EEPROM Configuration The CS5376A includes integrated peripherals to simplify Small-footprint, 64-pin TQFP Package system design: offset and gain corrections, a test DAC bit stream generator, a time-break controller, 12 generLow Power Consumption 9 mW per Channel at 500 SPS Flexible Power Supplies I/O Interface: 3.3 V or 5.0 V Digital Logic Core: 3.0 V, 3.3 V or 5.0 V I al-purpose I/O pins, a secondary SPI port, and a boundary scan JTAG port. ORDERING INFORMATION See page 106. VDD2 (x2) SDRDY SDCLK VD (x2) SDDAT RESET SDTKI BOOT VDD1 S e ria l D a ta O u tp u t P o rt C lo c k a n d S yn c h ro n iz a tio n CLK SYNC M CLK M SYNC SSI SCK1 M IS O M OSI S IN T T IM E B TBSCLK T B SD AT A G P IO 1 1 :E E C S G P IO 1 0 G P IO 9 G P IO 8 G P IO 7 G P IO 6 G P IO 5 G P IO 4 :C S 4 G P IO 3 :C S 3 G P IO 2 :C S 2 G P IO 1 :C S 1 G P IO 0 :C S 0 SCK2 SO S I1 S I2 S I3 S I4 SPI 1 S e ria l P e rip h e ra l In te rfa c e 1 T im e B re a k C o n tro lle r T e s t B it S tre a m C o n tro lle r D e c im a tio n a n d F ilte rin g E n g in e G P IO G e n e ra l P u rp o s e I/O JTAG In te rfa c e M o d u la to r D a ta In te rfa c e SPI 2 S e ria l P e rip h e ra l In te rfa c e 2 MDATA [4:1] MFLAG [4:1] GND (x2) GND1 TMS http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved) GND2 (x2) TRST TDO TCK TDI SEP ‘08 DS612F4 CS5376A TABLE OF CONTENTS 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1. 1.2. 1.3. 1.4. Digital Filter Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Integrated Peripheral Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 System Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Configuration Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2. Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 13 Specified Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3. System Design with CS5376A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.7. 3.8. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Digital Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Data Collection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Integrated peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.2. Bypass Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.3. Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 5. Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.2. Reset Self-Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.3. Boot Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 6. Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 6.2. Synchronous Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 6.3. Master Clock Jitter and Skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 7. Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1. 7.2. 7.3. 7.4. 7.5. 8.1. 8.2. 8.3. 8.4. 8.5. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 MSYNC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Digital Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Modulator Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Test Bit Stream Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 EEPROM Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 EEPROM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 EEPROM Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Example EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 8. Configuration By EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9. Configuration By Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DS612F4 2 CS5376A 9.1. 9.2. 9.3. 9.4. 9.5. 10.1. 10.2. 10.3. 10.4. 10.5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Microcontroller Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Microcontroller Serial Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Microcontroller Configuration Commands . . . . . . . . . . . . . . . . . . . . . . .35 Example Microcontroller Configuration . . . . . . . . . . . . . . . . . . . . . . . . .37 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Modulator Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Modulator Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Modulator Data Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Modulator Flag Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 10. Modulator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11. Digital Filter Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.1. Filter Coefficient Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 11.2. Filter Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 12. SINC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.1. 12.2. 12.3. 12.4. 13.1. 13.2. 13.3. 13.4. 13.5. 14.1. 14.2. 14.3. 14.4. 14.5. 14.6. 14.7. SINC1 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 SINC2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 SINC3 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 SINC Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 FIR1 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 FIR2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 On-Chip FIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Programmable FIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 FIR Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 IIR Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 IIR1 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 IIR2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 IIR3 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 On-Chip IIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Programmable IIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 IIR Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 13. FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 14. IIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 15. Gain and Offset Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.1. Gain Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 15.2. Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 15.3. Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 16. Serial Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 16.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 16.2. SD Port Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 16.3. SD Port Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 17. Test Bit Stream Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 17.1. 17.2. 17.3. 17.4. 17.5. 17.6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 TBS Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 TBS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 TBS Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 TBS Sine Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 TBS Loopback Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 DS612F4 3 CS5376A 17.7. TBS Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 18. Time Break Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 18.1. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 18.2. Time Break Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 18.3. Time Break Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 19. General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 19.1. 19.2. 19.3. 19.4. 19.5. 20.1. 20.2. 20.3. 20.4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 GPIO Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 GPIO Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 GPIO Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 SPI 2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 SPI 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 SPI 2 Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 20. Serial Peripheral Interface 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 21. Boundary Scan JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 21.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 21.2. JTAG Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 22. Device Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 22.1. Changes from CS5376 rev A to CS5376 rev B . . . . . . . . . . . . . . . . . .78 22.2. Changes from CS5376 rev B to CS5376A rev A . . . . . . . . . . . . . . . . .78 23. Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 23.1. SPI 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 23.2. Digital Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 24. 25. 26. 27. 28. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Environmental, Manufacturing, & Handling Information . . . . . . 106 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 LIST OF FIGURES Figure 1. CS5376A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 2. Digital Filtering Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 3. FIR and IIR Coefficient Set Selection Word. . . . . . . . . . . . . . . . . . . . .11 Figure 4. MOSI Write Timing in SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 5. MISO Read Timing in SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 6. SD Port Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 7. SYNC, MCLK, MSYNC, MDATA Interface Timing . . . . . . . . . . . . . . .17 Figure 8. TBS Output Clock and Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .18 Figure 9. Multi-Channel System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .19 Figure 10. Power Supply Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Figure 11. Reset Control Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Figure 12. Clock Generation Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Figure 13. Synchronization Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 DS612F4 4 CS5376A Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. EEPROM Configuration Block Diagram . . . . . . . . . . . . . . . . . . . . . .26 SPI 1 EEPROM Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . .27 8 Kbyte EEPROM Memory Organization. . . . . . . . . . . . . . . . . . . . . .28 Serial Peripheral Interface 1 (SPI 1) Block Diagram . . . . . . . . . . . . .32 Microcontroller Serial Transactions . . . . . . . . . . . . . . . . . . . . . . . . . .33 SPI 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Modulator Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Digital Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 FIR and IIR Coefficient Set Selection Word. . . . . . . . . . . . . . . . . . . .42 SINC Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 SINC Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 FIR Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 FIR Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Minimum Phase Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 IIR Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 IIR Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Gain and Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Serial Data Port Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 SD Port Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 SD Port Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Test Bit Stream Generator Block Diagram . . . . . . . . . . . . . . . . . . . .64 Time Break Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 GPIO Bi-directional Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Serial Peripheral Interface 2 (SPI 2) Block Diagram . . . . . . . . . . . . .70 SPI 2 Master Mode Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . .73 SPI 2 Transaction Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 JTAG Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 SPI 1 Control Register SPI1CTRL. . . . . . . . . . . . . . . . . . . . . . . . . . .82 SPI 1 Command Register SPI1CMD . . . . . . . . . . . . . . . . . . . . . . . . .83 SPI 1 Data Register SPI1DAT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 SPI 1 Data Register SPI1DAT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Hardware Configuration Register CONFIG . . . . . . . . . . . . . . . . . . . .87 GPIO Configuration Register GPCFG0 . . . . . . . . . . . . . . . . . . . . . . .88 GPIO Configuration Register GPCFG1 . . . . . . . . . . . . . . . . . . . . . . .89 SPI 2 Control Register SPI2CTRL. . . . . . . . . . . . . . . . . . . . . . . . . . .90 SPI 2 Command Register SPI2CMD . . . . . . . . . . . . . . . . . . . . . . . . .91 SPI 2 Data Register SPI2DAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Filter Configuration Register FILTCFG . . . . . . . . . . . . . . . . . . . . . . .93 Gain Correction Register GAIN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Offset Correction Register OFFSET1 . . . . . . . . . . . . . . . . . . . . . . . .95 Time Break Counter Register TIMEBRK . . . . . . . . . . . . . . . . . . . . . .96 Test Bit Stream Configuration Register TBSCFG . . . . . . . . . . . . . . .97 Test Bit Stream Gain Register TBSGAIN . . . . . . . . . . . . . . . . . . . . .98 User Defined System Register SYSTEM1. . . . . . . . . . . . . . . . . . . . .99 Hardware Version ID Register VERSION . . . . . . . . . . . . . . . . . . . .100 Self Test Result Register SELFTEST . . . . . . . . . . . . . . . . . . . . . . .101 DS612F4 5 CS5376A LIST OF TABLES Table 1. Microcontroller and EEPROM Configuration Commands . . . . . . . . . . .10 Table 2. TBS Configurations Using On-Chip Data . . . . . . . . . . . . . . . . . . . . . . .11 Table 3. SPI 1 and Digital Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Table 4. Maximum EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 5. EEPROM Boot Configuration Commands . . . . . . . . . . . . . . . . . . . . . .29 Table 6. Example EEPROM File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Table 7. Microcontroller Boot Configuration Commands . . . . . . . . . . . . . . . . . .35 Table 8. Example Microcontroller Configuration . . . . . . . . . . . . . . . . . . . . . . . . .38 Table 9. SINC Filter Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 10. SINC1 and SINC2 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . .45 Table 11. SINC3 Filter Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Table 12. FIR Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 13. SINC + FIR Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 14. FIR1 Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Table 15. FIR2 Linear Phase Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 16. FIR2 Minimum Phase Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Table 17. IIR Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Table 18. IIR Filter Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Table 19. TBS Configurations Using On-chip Data . . . . . . . . . . . . . . . . . . . . . .65 Table 20. JTAG Instructions and IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Table 21. JTAG Scan Cell Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 DS612F4 6 CS5376A VDD2 (x2) SDRDY SDCLK SDDAT VD (x2) RESET SDTKI BOOT VDD1 Serial Data Output Port Clock and Synchronization CLK SYNC MCLK MSYNC SSI SCK1 MISO MOSI SINT TIMEB TBSCLK TBSDATA GPIO11:EECS GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4:CS4 GPIO3:CS3 GPIO2:CS2 GPIO1:CS1 GPIO0:CS0 SCK2 SO SI1 SI2 SI3 SI4 SPI 1 Serial Peripheral Interface 1 Time Break Controller Test Bit Stream Controller Decimation and Filtering Engine GPIO General Purpose I/O JTAG Interface Modulator Data Interface SPI 2 Serial Peripheral Interface 2 MDATA [4:1] MFLAG [4:1] GND (x2) GND1 Figure 1. CS5376A Block Diagram 1. GENERAL DESCRIPTION The CS5376A is a multi-channel digital filter with integrated system peripherals. Figure 1 illustrates a simplified block diagram of the CS5376A. • Low bandwidth rates: 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS. 1.1 Digital Filter Features • Multi-channel decimation CS5371A/72A ∆Σ modulators. • filter for Flexible digital filter configuration. (See Figure 2) Cascaded SINC, FIR, and IIR filters with selectable output stage. Linear and minimum phase FIR low-pass filter coefficients included. 3 Hz Butterworth IIR high-pass filter coefficients included. FIR and IIR coefficients are programmable to create a custom filter response. Individual channel gain correction to normalize signal amplitudes. 1, 2, 3, or 4 channel concurrent operation. Synchronous operation for simultaneous sampling in multi-sensor systems. Internal synchronization of digital filter phase to an external SYNC signal. • • Multiple output word rates, including low bandwidth rates. Standard output rates: 4000, 2000, 1000, 500, 333, 250 SPS. Digital gain correction. - DS612F4 GND2 (x2) TMS TDI TRST TDO TCK 7 CS5376A Modulator Input 512 kHz Sinc Filter 2 - 64000 FIR1 4 FIR2 2 IIR1 1 Order st IIR2 2 nd Order Gain & DC Offset Corrections Output to High Speed Serial Data Port Output Word Rate from 4000 SPS ~ 1 SPS Figure 2. Digital Filtering Stages • Digital offset correction and calibration. Individual channel offset correction to remove measurement offsets. Calibration engine for automatic calculation of offset correction factors. • Time break controller to record system timing information. Dedicated TB status bit in the output data stream. Programmable output delay to match system group delay. 1.2 Integrated Peripheral Features • Synchronous operation for simultaneous sampling in multi-sensor systems. • MCLK / MSYNC output signals to synchronize external components. Asynchronous operation to 4 MHz for direct connection to system telemetry. Internal 8-deep data FIFO for flexible output timing. • Additional hardware peripherals simplify system design. 12 General Purpose I/O (GPIO) pins for local hardware control. Secondary SPI 2 serial port to control local serial peripherals. JTAG port for boundary scan (IEEE 1149.1 compliant). High speed serial data output port (SD port). - 1.3 System Level Features • Flexible configuration options. • Configuration 'on-the-fly' via microcontroller or system telemetry. Fixed configuration via stand-alone boot EEPROM. • Digital test bit stream signal generator suitable for CS4373A ∆Σ test DAC. Sine wave output mode for testing total harmonic distortion. Programmable waveform data for custom test signal generation. Low power consumption. 8 DS612F4 CS5376A • • 37 mW for 4-channel operation at 500 SPS (9.25 mW/channel). 40 µW standby mode. • Separate digital logic core, telemetry I/O, and modulator I/O power supplies. Telemetry I/O and modulator I/O interfaces operate from 3.3 V or 5 V. Digital logic core operates from 3.0 V, 3.3 V or 5 V. Total footprint 12 mm x 12 mm plus five bypass capacitors. alone boot EEPROM. Microcontroller boot permits reconfiguration during operation. EEPROM boot sets a fixed operational configuration. Flexible power supply configurations. Configuration commands written through Serial Peripheral Interface 1. (See Table 1) Standardized microcontroller interface using SPI 1 registers. (See Table 3) Commands write digital filter registers, filter coefficients, and test bit stream data. Digital filter registers set hardware configuration options. Small 64-pin TQFP package. - 1.4 Configuration Interface • Configuration from microcontroller or stand- DS612F4 9 CS5376A Microcontroller Boot Configuration Commands Name NOP WRITE DF REGISTER READ DF REGISTER WRITE FIR COEFFICIENTS WRITE IIR COEFFICIENTS CMD 24-bit 000000 000001 000002 000003 000004 DAT1 24-bit REG REG [DATA] NUM FIR1 (FIR COEF) a11 b11 a22 b21 COEF SEL NUM TBS (TBS DATA) DAT2 24-bit DATA NUM FIR2 (FIR COEF) b10 a21 b20 b22 (TBS DATA) Description No Operation Write Digital Filter Register Read Digital Filter Register Write Custom FIR Coefficients Write Custom IIR Coefficients WRITE ROM COEFFICIENTS WRITE TBS DATA WRITE ROM TBS FILTER START FILTER STOP 000005 000006 000007 000008 000009 Use On-Chip Coefficients Write Custom Test Bit Stream Data Use On-Chip TBS Data Start Digital Filter Operation Stop Digital Filter Operation EEPROM Boot Configuration Commands Name NOP WRITE DF REGISTER WRITE FIR COEFFICIENTS CMD 8-bit 00 01 02 DATA 24-bit REG DATA NUM FIR1 NUM FIR2 (FIR COEF) a11 b10 b11 a21 a22 b20 b21 b22 COEF SEL NUM TBS (TBS DATA) No Operation Write Digital Filter Register Write Custom FIR Coefficients Description WRITE IIR COEFFICIENTS 03 Write Custom IIR Coefficients WRITE ROM COEFFICIENTS WRITE TBS DATA WRITE ROM TBS FILTER START 04 05 06 07 Use On-Chip Coefficients Write Custom Test Bit Stream Data Use On-Chip TBS Data Start Digital Filter Operation [DATA] indicates data word returned from digital filter. (DATA) indicates multiple words of this type are to be written. Table 1. Microcontroller and EEPROM Configuration Commands DS612F4 10 CS5376A Bits Selection 23:20 0000 19:16 0000 15:12 IIR2 11:8 IIR1 7:4 FIR2 3:0 FIR1 Bits 15:12 0000 0001 0010 0011 0100 IIR2 Coefficients 3 Hz @ 2000 SPS 3 Hz @ 1000 SPS 3 Hz @ 500 SPS 3 Hz @ 333 SPS 3 Hz @ 250 SPS Bits 11:8 0000 0001 0010 0011 0100 IIR1 Coefficients 3 Hz @ 2000 SPS 3 Hz @ 1000 SPS 3 Hz @ 500 SPS 3 Hz @ 333 SPS 3 Hz @ 250 SPS Bits 3:0 0000 0001 FIR1 Coefficients Linear Phase Minimum Phase Bits 7:4 0000 0001 FIR2 Coefficients Linear Phase Minimum Phase Figure 3. FIR and IIR Coefficient Set Selection Word Test Bit Stream Characteristic Equation: (Signal Freq) * (# TBS Data) * (Interpolation + 1) = Output Rate Example: (31.25 Hz) * (1024) * (0x07 + 1) = 256 kHz Signal Frequency (TBSDATA) 10.00 Hz 10.00 Hz 25.00 Hz 25.00 Hz 31.25 Hz 31.25 Hz 50.00 Hz 50.00 Hz 125.00 Hz 125.00 Hz Output Rate (TBSCLK) 256 kHz 512 kHz 256 kHz 512 kHz 256 kHz 512 kHz 256 kHz 512 kHz 256 kHz 512 kHz Output Rate Selection (RATE) 0x4 0x5 0x4 0x5 0x4 0x5 0x4 0x5 0x4 0x5 Interpolation Selection (INTP) 0x18 0x31 0x09 0x13 0x07 0x0F 0x04 0x09 0x01 0x03 Table 2. TBS Configurations Using On-Chip Data DS612F4 11 CS5376A SPI 1 Registers Name SPI1CTRL SPI1CMD SPI1DAT1 SPI1DAT2 Addr. 00 - 02 03 - 05 06 - 08 09 - 0B Type R/W R/W R/W R/W # Bits 8, 8, 8 8, 8, 8 8, 8, 8 8, 8, 8 SPI 1 Control SPI 1 Command SPI 1 Data 1 SPI 1 Data 2 Description Digital Filter Registers Name CONFIG RESERVED GPCFG0 GPCFG1 SPI2CTRL SPI2CMD SPI2DAT RESERVED FILTCFG GAIN1 GAIN2 GAIN3 GAIN4 OFFSET1 OFFSET2 OFFSET3 OFFSET4 TIMEBRK TBSCFG TBSGAIN SYSTEM1 SYSTEM2 VERSION SELFTEST Addr. 00 01-0D 0E 0F 10 11 12 13-1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W # Bits 24 24 24 24 24 16 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 Description Hardware Configuration Reserved GPIO[7:0] Direction, Pull-up Enable, and Data GPIO[11:8] Direction, Pull-up Enable, and Data SPI 2 Control SPI 2 Command SPI 2 Data Reserved Digital Filter Configuration Gain Correction Channel 1 Gain Correction Channel 2 Gain Correction Channel 3 Gain Correction Channel 4 Offset Correction Channel 1 Offset Correction Channel 2 Offset Correction Channel 3 Offset Correction Channel 4 Time Break Delay Test Bit Stream Configuration Test Bit Stream Gain User Defined System Register 1 User Defined System Register 2 Hardware Version ID Self-Test Result Code Table 3. SPI 1 and Digital Filter Registers DS612F4 12 CS5376A 2. CHARACTERISTICS AND SPECIFICATIONS • • • Min / Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C. GND, GND1, GND2 = 0 V, all voltages with respect to 0 V. SPECIFIED OPERATING CONDITIONS Parameter Logic Core Power Supply Microcontroller Interface Power Supply Modulator Interface Power Supply Ambient Operating Temperature Industrial (-IQ) Symbol VD VDD1 VDD2 TA Min 2.85 3.135 3.135 -40 Nom 3.0 3.3 3.3 Max 5.25 5.25 5.25 85 Unit V V V °C ABSOLUTE MAXIMUM RATINGS Parameter DC Power Supplies Logic Core Microcontroller Interface Modulator Interface (Note 1) (Note 1) (Note 1) Symbol VD VDD1 VDD2 IIN IIN IOUT PDN VIND TA TSTG Min -0.3 -0.3 -0.3 -0.5 -40 -65 Max 6.0 6.0 6.0 ±10 ±50 ±25 500 VDD+0.5 85 150 Units V V V mA mA mA mW V °C °C Input Current, Any Pin Except Supplies Input Current, Power Supplies Output Current Power Dissipation Digital Input Voltages Ambient Operating Temperature (Power Applied) Storage Temperature Range 1. Transient currents up to 100 mA will not cause SCR latch-up. DS612F4 13 CS5376A THERMAL CHARACTERISTICS Parameter Allowable Junction Temperature Junction to Ambient Thermal Impedance Ambient Operating Temperature (Power Applied) Symbol TJ ΘJA TA Min -40 Typ 65 +85 Max 135 Unit °C °C / W °C DIGITAL CHARACTERISTICS Parameter High-Level Input Drive Voltage Low-Level Input Drive Voltage High-Level Output Drive Voltage Low-Level Output Drive Voltage Rise Times, Digital Inputs Fall Times, Digital Inputs Rise Times, Digital Outputs Fall Times, Digital Outputs Input Leakage Current 3-State Leakage Current Digital Input Capacitance Digital Output Pin Capacitance (Note 2) Iout = -40 µA Iout = +40 µA Symbol VIH VIL VOH VOL tRISE tFALL tRISE tFALL IIN IOZ CIN COUT Min 0.6 * VDD 0.0 VDD - 0.3 0.0 Typ ±1 9 9 Max VDD 0.8 VDD 0.3 100 100 100 100 ± 10 ± 10 Unit V V V V ns ns ns ns µA µA pF pF Notes: 2. Max leakage for pins with pull-up resistors (TRST, TMS, TDI, SSI, GPIO, MOSI, SCK1) is ±250 µA. t rise out t fallo ut t ris e in t fa llin 0.9 2.6 V * VDD 0.1 0.7 V * VDD 0.9 * VDD V 4 .6 0.1 * VDDV 0 .4 POWER CONSUMPTION Parameter Operational Power Consumption 1.024 MHz Digital Filter Clock 2.048 MHz Digital Filter Clock 4.096 MHz Digital Filter Clock 8.192 MHz Digital Filter Clock 16.384 MHz Digital Filter Clock Standby Power Consumption 32 kHz Digital Filter Clock, Filter Stopped PWRS 40 µW PWR1 PWR2 PWR4 PWR8 PWR16 21 26 37 57 85 mW mW mW mW mW Symbol Min Typ Max Unit DS612F4 14 CS5376A SWITCHING CHARACTERISTICS SPI 1 Interface Timing (External Master) SSI MOSI MSB t1 MSB - 1 t2 t3 t4 t5 LSB t6 SCK1 SCLK Figure 4. MOSI Write Timing in SPI Slave Mode SS I t 10 MISO MSB t7 MSB - 1 t8 t9 LSB SCK1 SCLK Figure 5. MISO Read Timing in SPI Slave Mode Parameter MOSI Write Timing SSI Enable to Valid Latch Clock Data Set-up Time Prior to SCK1 Rising Data Hold Time After SCK1 Rising SCK1 High Time SCK1 Low Time SCK1 Falling Prior to SSI Disable MISO Read Timing SCK1 Falling to New Data Bit SCK1 High Time SCK1 Low Time SSI Rising to MISO Hi-Z Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Min 60 60 120 120 120 60 120 120 - Typ - Max 60 150 Unit ns ns ns ns ns ns ns ns ns ns DS612F4 15 CS5376A SWITCHING CHARACTERISTICS Serial Data Port (SD Port) SDRDY SDCLK t3 t6 t7 SDDAT SDTKI SDTKO t1 t2 t10 Figure 6. SD Port Read Timing t4 t5 t8 t9 t11 Parameter SDTKI to SDRDY Falling Edge SDTKI High Time Width SDRDY Falling Edge to SDCLK Falling Edge Data Setup Time Prior to SDCLK Rising Data Hold Time After SDCLK Rising SDCLK High Time SDCLK Low Time SDCLK Rising to SDRDY Rising Data Hold Time After SDRDY Rising SDRDY High to SDTKO Rising Edge SDTKO High Time Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Min 60 60 50 60 60 120 120 60 90 Typ - Max 1000 150 60 - Unit ns ns ns ns ns ns ns ns ns ns ns DS612F4 16 CS5376A SWITCHING CHARACTERISTICS CLK, SYNC, MCLK, MSYNC, and MDATAx SYNC MCLK MSYNC tmsd MDATAx tmsh tmsd Data1 Data2 Note: SYNC input latched on MCLK rising edge. MSYNC output triggered by MCLK falling edge. fMCLK 2.048 MHz 1.024 MHz tmsd = TMCLK / 4 tmsh = TMCLK tmsd = 122 ns tmsh = 488 ns tmsd = 244 ns tmsh = 976 ns Figure 7. SYNC, MCLK, MSYNC, MDATA Interface Timing Parameter Master Clock Frequency Master Clock Duty Cycle Master Clock Rise Time Master Clock Fall Time Master Clock Jitter Synchronization after SYNC rising MSYNC Setup Time to MCLK rising MCLK rising to Valid MDATA MSYNC falling to MCLK rising (Note 4) (Note 3) Symbol CLK DTY tRISE tFALL JTR SYNC tmsr tmdv tmsf Min 32 40 -2 20 20 Typ 32.768 - Max 33 60 20 20 300 2 75 - Unit MHz % ns ns ps µs ns ns ns Notes: 3. Master clock frequencies above or below 32.768 MHz will affect generated clock frequencies. 4. Sampling synchronization between multiple CS5376A devices receiving identical SYNC signals. DS612F4 17 CS5376A SWITCHING CHARACTERISTICS Test Bit Stream (TBS) t1 t2 t3 TBSCLK TBSDATA t4 t5 MCLK Note: Example timing shown for a 256 kHz output rate and no programmable delays. Figure 8. TBS Output Clock and Data Timing Parameter TBS Clock Timing TBS Clock Period TBS Clock High Time TBS Clock Low Time TBS Data Output Timing TBS Data Bit Rate TBS Data Rising to TBS Clock Rising Setup Time TBS Clock Rising to TBS Data Falling Hold Time (Note 6) (Note 5) Symbol t1 t2 t3 Min 40 40 - Typ 3.906 256 - Max 60 60 - Unit µs % % kbps ns ns t4 t5 60 60 5. TBSCLK phase can be delayed in 1/8 increments. The timing diagram shows no TBSCLK delay. 6. TBSDATA can be delayed from 0 to 63 full bit periods. The timing diagram shows no TBSDATA delay. DS612F4 18 CS5376A Geophone or Hydrophone Sensor M U X CS3301A CS3302A AMP CS5371A CS5372A System Telemetry ∆Σ Modulator Geophone or Hydrophone Sensor M U X CS3301A CS3302A AMP CS5376A µ Controller or Configuration EEPROM Digital Filter Geophone or Hydrophone Sensor M U X CS3301A CS3302A AMP CS5371A CS5372A ∆Σ Modulator Communication Interface Geophone or Hydrophone Sensor M U X CS3301A CS3302A AMP CS4373A Switch Switch MUX MUX Test DAC Figure 9. Multi-Channel System Block Diagram 3. SYSTEM DESIGN WITH CS5376A Figure 9 illustrates a simplified block diagram of the CS5376A in a multi-channel measurement system. Up to four differential sensors are connected through CS3301A/02A differential amplifiers to the CS5371A/72A ∆Σ modulators, where analog to digital conversion occurs. Each modulators 1-bit output connects to a CS5376A MDATA input, where the oversampled ∆Σ data is decimated and filtered to 24-bit output samples at a programmed output rate. These output samples are buffered in an 8-deep data FIFO and passed to the system telemetry on command. System self tests are performed by connecting the CS5376A test bit stream (TBS) generator to the CS4373A test DAC. Analog tests drive differential signals from the CS4373A test DAC into the multiplexed inputs of the CS3301A/02A amplifiers or DS612F4 directly to the sensors through external analog switches. Digital loopback tests internally connect the TBS digital output directly to the CS5376A modulator inputs. 3.1 Power Supplies The multi-channel system shown in Figure 9 typically operates from a ±2.5 V analog power supply and a 3.3 V digital power supply. The CS5376A logic core can be powered from 3 V to minimize power consumption, if required. 3.2 Reset Control System reset is required only for the CS5376A device, and is a standard active low signal that can be generated by a power supply monitor or microcontroller. Other system devices default to a powerdown state when the CS5376A is reset. 19 CS5376A 3.3 Clock Generation A single 32.768 MHz low-jitter clock input, which can be generated from a VCXO based PLL, is required to drive the CS5376A device. Clock inputs for other system devices are driven by clock outputs from the CS5376A. 3.7 Data Collection Data is collected from the CS5376A through the Serial Data port (SD port). Automatically or upon request, depending how the SDTKI pin is connected, the SD port initiates serial transactions to transfer 32-bit data from the output FIFO to the system telemetry. The output FIFO has eight data locations to permit latency in data collection. 3.4 Synchronization Digital filter phase and analog sample timing of the four ∆Σ modulators connected to the CS5376A are synchronized by a rising edge on the SYNC pin. If a synchronization signal is received identically by all CS5376A devices in a measurement network, synchronous sampling across the network is guaranteed. 3.8 Integrated peripherals Test Bit Stream (TBS) A digital signal generator built into the CS5376A produces a 1-bit ∆Σ sine wave. This digital test bit stream can be connected to the CS4373A test DAC to create high quality analog test signals or it can be internally looped back to the CS5376A MDATA inputs to test the digital filter and data collection circuitry. Time Break Timing information is recorded during data collection by strobing the TIMEB pin. A dedicated flag in the sample status bits, TB, is set high to indicate over which measurement the timing event occurred. General Purpose I/O (GPIO) Twelve general purpose pins are available on the CS5376A for system control. Each pin can be set as input or output, high or low, with an internal pullup enabled or disabled. The CS3301A/02A, CS5371A/72A and CS4373A devices in Figure 9 are configured by simple pin settings controlled through the CS5376A GPIO pins. Serial Peripheral Interface 2 (SPI 2) A secondary master mode serial port to communicate with external serial peripherals. JTAG Port Boundary scan JTAG is IEEE 1149.1 compliant. 3.5 System Configuration Through the SPI 1 serial port, filter coefficients and digital filter register settings can either be programmed by a microcontroller or automatically loaded from an external EEPROM after reset. System configuration is only required for the CS5376A device, as other devices are configured via the CS5376A General Purpose I/O pins. Two registers in the digital filter, SYSTEM1 and SYSTEM2 (0x2C, 0x2D), are provided for user defined system information. These are general purpose registers that will hold any 24-bit data values written to them. 3.6 Digital Filter Operation After analog to digital conversion occurs in the modulators, the oversampled 1-bit ∆Σ data is read into the CS5376A through the MDATA pins. The digital filter then processes data through the enabled filter stages, decimating it to 24-bit words at a programmed output word rate. The final 24-bit samples are concatenated with 8-bit status words and placed into an output FIFO. 20 DS612F4 CS5376A TRST TMS TCK TDI TDO GND VD TBSCLK TBSDATA DNC VDD2 MCLK/2 MCLK MSYNC MDATA4 MFLAG4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 VDD1 Pad Ring 2 3 4 5 6 VD 7 Pad Ring 8 9 VD Pad Ring 10 11 12 13 14 15 VDD2 Pad Ring 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SDTKI SDTKO SDCLK SDRDY SDDAT SYNC CLK TIMEB BOOT RESET VDD1 GND1 SINT MOSI MISO SSI CS5376A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCK1 SSO GPIO11:EECS GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 VD GND GND2 GPIO5 GPIO4:CS4 GPIO3:CS3 GPIO2:CS2 GPIO1:CS1 Figure 10. Power Supply Block Diagram 4. POWER SUPPLIES The CS5376A has three sets of power supply inputs. Two sets supply power to the I/O pins of the device (VDD1, VDD2), and the third supplies power to the logic core (VD). The I/O pin power supplies determine the maximum input and output voltages when interfacing to peripherals, and the logic core power supply largely determines the power consumption of the CS5376A. GPIO6 - GPIO11:EECS SSO, SCK1, SSI, MISO, MOSI, SINT, RESET, BOOT, TIMEB, CLK, SYNC SDDAT, SDRDY, SDCLK, SDTKO, SDTKI 4.1 Pin Descriptions VDD1, GND1 - Pins 54,53 Sets the interface voltage to a microcontroller and system telemetry. Can be driven with voltages from 3.3 V to 5 V. VDD1 powers pins 1-5 and 41-64: TRST, TMS, TCK, TDI, TDO DS612F4 MDATA3 MFLAG3 MDATA2 MFLAG2 MDATA1 MFLAG1 GND GND2 VDD2 SI4 SI3 SI2 SI1 SO SCK2 GPIO0:CS0 VDD2, GND2 - Pins 11, 25, 24, 38 Sets the interface voltage to the modulators, test DAC, and serial peripherals. Can be driven with voltages from 3.3 V to 5 V. VDD2 powers pins 8-37: TBSCLK, TBSDATA MCLK/2, MCLK, MSYNC MDATA1 - MDATA4 MFLAG1 - MFLAG4 SI1 - SI4, SO, SCK2 GPIO0:CS0 - GPIO5 21 CS5376A VD, GND - Pins 7, 40, 6, 23, 39 Sets the operational voltage of the CS5376A logic core. Can be driven with voltages from 3 V to 5 V. A 3 V supply minimizes total power consumption. (X7R, C0G), tantalum, or other good quality dielectric type. 4.3 Power Consumption Power consumption of the CS5376A depends primarily on the power supply voltage of the logic core (VD) and the programmed digital filter clock rate. Digital filter clock rates are selected based on the required output word rate as explained in “Digital Filter Initialization” on page 41. 4.2 Bypass Capacitors Each power supply pin should be bypassed with parallel 1 µF and 0.01 µF caps, or by a single 0.1 µF cap, placed as close as possible to the CS5376A. Bypass capacitors should be ceramic 22 DS612F4 CS5376A RESET Self-Tests BOOT Pin 1 0 SELFTEST Register EEPROM Boot µController Boot Figure 11. Reset Control Block Diagram 5. RESET CONTROL The CS5376A reset signal is active low. When released, a series of self-tests are performed and the device either actively boots from an external EEPROM or enters an idle state waiting for microcontroller configuration. combined into the SELFTEST register (0x2F), with 0x0AAAAA indicating all passed. Self-tests require 60 ms to complete, after which configuration commands are serviced. 5.3 Boot Configurations 5.1 Pin Descriptions RESET - Pin 55 Reset input, active low. BOOT - Pin 56 Boot mode select, latched following a RESET rising edge. BOOT = 1 = EEPROM boot BOOT = 0 = Microcontroller boot The logic state of the BOOT pin after reset determines if the CS5376A actively reads configuration information from EEPROM or enters an idle state waiting for a microcontroller to write configuration commands. EEPROM Boot When the BOOT pin is high after reset, the CS5376A actively reads data from an external serial EEPROM and then begins operation in the specified configuration. Configuration commands and data are encoded in the EEPROM as specified in the ‘Configuration By EEPROM’ section of this data sheet, starting on page 26. Microcontroller Boot When the BOOT pin is low after reset, the CS5376A enters an idle state waiting for a microcontroller to write configuration commands and initialize filter operation. Configuration commands and data are written as specified in the ‘Configuration By Microcontroller’ section of this data sheet, starting on page 32. 5.2 Reset Self-Tests After RESET is released but before booting, a series of digital filter self-tests are run. Results are Self-Test Type Program ROM Data ROM Program RAM Data RAM Execution Unit Pass Code 0x00000A 0x0000A0 0x000A00 0x00A000 0x0A0000 Fail Code 0x00000F 0x0000F0 0x000F00 0x00F000 0x0F0000 DS612F4 23 CS5376A CLK Clock Divider and MCLK Generator Internal Clocks MCLK Output DSPCFG Register Figure 12. Clock Generation Block Diagram 6. CLOCK GENERATION The CS5376A requires a 32.768 MHz master clock input, which is used to generate internal digital filter clocks and external modulator clocks. ensure recovered clocks have identical phase, system PLL designs should use a phase/frequency detector architecture. 6.1 Pin Description CLK - Pin 58 Clock input, nominal frequency 32.768 MHz. 6.3 Master Clock Jitter and Skew Care must be taken to minimize jitter and skew in the received master clock as both parameters affect measurement performance. Jitter in the master clock causes jitter in the generated modulator clocks, resulting in sample timing errors and increased noise. Skew in the master clock from node to node creates a sample timing offset, resulting in systematic measurement errors in the reconstructed signal. 6.2 Synchronous Clocking To guarantee synchronous measurements throughout a sensor network, the CS5376A master clock should be distributed to arrive at all nodes in phase. The 32.768 MHz master clock can either be directly distributed through the system telemetry, or reconstructed locally using a VCXO based PLL. To 24 DS612F4 CS5376A 0 SYNC 1 MSYNC Generator Digital Filter 0 1 Test Bit Stream MSEN MSYNC Output TSYNC Figure 13. Synchronization Block Diagram 7. SYNCHRONIZATION The CS5376A has a dedicated SYNC input that aligns the internal digital filter phase and generates an external signal for synchronizing modulator analog sampling. By providing simultaneous rising edges to the SYNC pins of multiple CS5376A devices, synchronous sampling across a network can be guaranteed. phase. Filter convolutions restart, and the next output word is available one full sample period later. Repetitive synchronization is supported when SYNC events occur at exactly the selected output word rate. In this case, re-synchronization occurs at the start of a convolution cycle when the digital filter state machine is already reset. 7.1 Pin Description SYNC - Pin 59 Synchronization input, rising edge triggered. 7.4 Modulator Synchronization The external MSYNC signal phase aligns modulator analog sampling when connected to the CS5371A/72A MSYNC input. This ensures synchronous analog sampling relative to MCLK. Repetitive synchronization of the modulators is supported when SYNC events occur at exactly the selected output word rate. In this case, synchronization will occur at the start of analog sampling. 7.2 MSYNC Generation The SYNC signal rising edge is used to generate a retimed synchronization signal, MSYNC. The MSYNC signal reinitializes internal digital filter phase and is driven onto the MSYNC output pin to phase align modulator analog sampling. The MSEN bit in the digital filter CONFIG register (0x00) enables MSYNC generation. See “Modulator Interface” on page 39 for more information about MSYNC. 7.5 Test Bit Stream Synchronization When the test bit stream generator is enabled, an MSYNC signal can reset the internal data pointer. This restarts the test bit stream from the first data point to establish a known output signal phase. The TSYNC bit in the digital filter TBSCFG register (0x2A) enables synchronization of the test bit stream by MSYNC. When TSYNC is disabled, the test bit stream phase is not affected by MSYNC. 7.3 Digital Filter Synchronization The internal MSYNC signal resets the digital filter state machine to establish a known digital filter DS612F4 25 CS5376A VD 3 WP 8 7 VCC HOLD GPIO11:EECS SCK1 46 48 50 51 1 6 2 5 CS SCK CS5376A MISO MOSI AT25640 SO SI 4 GND Figure 14. EEPROM Configuration Block Diagram 8. CONFIGURATION BY EEPROM After reset, the CS5376A reads the state of the BOOT pin to determine a source for configuration commands. If BOOT is high, the CS5376A initiates serial transactions through the SPI 1 port to read configuration information from an external EEPROM. in Figure 15, to read configuration commands and data. 8-bit SPI opcodes and 16-bit addresses are combined to read back 8-bit configuration commands and 24-bit configuration data. System design should include a connection to the configuration EEPROM for in-circuit reprogramming. The CS5376A SPI 1 pins go high impedance when inactive to support external connections to the serial bus. 8.1 Pin Descriptions Pins required for EEPROM boot are listed here, other SPI 1 pins are inactive. GPIO11:EECS - Pin 46 EEPROM chip select output, active low. SCK1 - Pin 48 Serial clock output, nominally 1.024 MHz. MOSI - Pin 51 Serial data output pin. Valid on rising edge of SCK1, transition on falling edge. MISO - Pin 50 Serial data input pin. Valid on rising edge of SCK1, transition on falling edge. 8.3 EEPROM Organization The boot EEPROM holds the 8-bit commands and 24-bit data required to initialize the CS5376A into an operational state. Configuration information starts at memory location 0x10, with addresses 0x00 to 0x0F free for use as manufacturing header information. The first serial transaction reads a 1-byte command from memory location 0x10 and then, depending on the command type, reads multiple 3-byte data words to complete the command. Command and data reads continue until the ‘Filter Start’ command is recognized. The maximum number of bytes that can be written for a single configuration is approximately 8.2 EEPROM Hardware Interface When booting from EEPROM the CS5376A SPI 1 port actively performs serial transactions, as shown 26 DS612F4 CS5376A Instruction Read 0x03 Opcode Address ADDR[15:0] Definition Read data beginning at the address given in ADDR. SPI 1 Read from EEPROM SSI READ CMD 0x03 2 BYTE ADDR ADDR ADDR MOSI MISO DATA1 DATA2 DATA3 1 BYTE / 3 BYTE DATA EECS Cycle 1 2 3 4 5 6 7 8 SCK1 MOSI MSB 6 5 4 3 2 1 LSB MISO MSB 6 5 4 3 2 1 LSB X EECS Figure 15. SPI 1 EEPROM Read Transactions DS612F4 27 CS5376A Write DF Register - 0x01 This EEPROM command writes a data value to the specified digital filter register. Digital filter registers control hardware peripherals and filtering functions. See “Digital Filter Registers” on page 86 for the bit definitions of the digital filter registers. 0000h 0010h Mfg Header 8-bit Command N x 24-bit Data 8-bit Command N x 24-bit Data EEPROM Manufacturing Information EEPROM Command and Data Values Sample Command: Write digital filter register 0x00 with data value 0x070431. Then write 0x20 with data 0x000240. 01 00 00 00 07 04 31 01 00 00 20 00 02 40 Write FIR Coefficients - 0x02 This EEPROM command writes custom coefficients for the FIR1 and FIR2 filters. The first two data words set the number of FIR1 and FIR2 coefficients to be written. The remaining data words are the concatenated FIR1 and FIR2 coefficients. A maximum of 255 coefficients can be written for each FIR filter, though the available digital filter computation cycles will limit their practical size. See “FIR Filter” on page 47 for more information about FIR filter coefficients. 1FFFh ... Figure 16. 8 Kbyte EEPROM Memory Organization 5 KByte (40 Kbit), which includes command overhead: Memory Requirement Bytes Digital Filter Registers (22) FIR Coefficients (255+255) IIR Coefficients (3+5) Test Bit Stream Data (1024) ‘Filter Start’ Command Total Bytes 154 1537 25 3076 1 4793 Sample Command: Write FIR1 coefficients 0x00022E, 0x000771 then FIR2 coefficients 0xFFFFB9, 0xFFFE8D. 02 00 00 02 00 00 02 00 02 2E 00 07 71 FF FF B9 FF FE 8D Table 4. Maximum EEPROM Configuration Supported serial configuration EEPROMs are SPI mode 0 (0,0) compatible, 16-bit addresses, 8bit data, larger than 5 KByte (40 KBit). ATMEL AT25640, AT25128, or similar serial EEPROMs are recommended. 8.4 EEPROM Configuration Commands A summary of available EEPROM commands is shown in Table 5. Write IIR Coefficients - 0x03 This EEPROM command writes custom coefficients for the two stage IIR filter. The IIR architecture and number of coefficients is fixed, so eight data words containing coefficient values always immediately follow the command byte. The IIR coefficient write order is: a11, b10, b11, a21, a22, b20, b21, and b22. See “IIR Filter” on page 55 for more information about IIR filter coefficients. 28 DS612F4 CS5376A Sample Command: Write IIR1 coefficients 0x84BC9D, 0x7DA1B1, 0x825E4F, and IIR2 coefficients 0x83694F, 0x3CAD5F, 0x3E5104, 0x835DF8, 0x3E5104. 03 84 BC 9D 7D A1 B1 82 5E 4F 83 69 4F 3C AD 5F 3E 51 04 83 5D F8 3E 51 04 Write ROM Coefficients - 0x04 This EEPROM command selects the on-chip coefficients for the FIR1, FIR2, IIR 1st order, and IIR 2nd order filters for use by the digital filter. One data word is required to select which internal coefficient sets to use. See “Filter Coefficient Selection” on page 41 for information about selecting on-chip FIR and IIR coefficient sets. Sample Command: Select IIR1 and IIR2 3 Hz @ 500 SPS low-cut coefficients, with FIR1 and FIR2 linear phase highcut coefficients. Data word 0x002200. 04 00 22 00 Write TBS Data - 0x05 This EEPROM command writes a custom data set for the test bit stream (TBS) generator. This command, along with the ability to program the test bit stream generator interpolation and clock rate, can create custom frequency test signals. The first data word sets the number of TBS data to be written and the remaining data words are the TBS data values. See “Test Bit Stream Generator” on page 64 for information about using custom test bit stream data sets. Name NOP WRITE DF REGISTER WRITE FIR COEFFICIENTS CMD 8-bit 00 01 02 DATA 24-bit REG DATA NUM FIR1 NUM FIR2 (FIR COEF) a11 b10 b11 a21 a22 b20 b21 b22 COEF SEL NUM TBS (TBS DATA) No Operation Description Write Digital Filter Register Write Custom FIR Coefficients WRITE IIR COEFFICIENTS 03 Write Custom IIR Coefficients WRITE ROM COEFFICIENTS WRITE TBS DATA WRITE ROM TBS FILTER START 04 05 06 07 Use On-Chip Coefficients Write Custom Test Bit Stream Data Use On-Chip TBS Data Start Digital Filter Operation (DATA) indicates multiple words of this type are to be written. Table 5. EEPROM Boot Configuration Commands DS612F4 29 CS5376A Sample Command: Write test bit stream data 0x000000, 0x0007DA, 0x000FB5, 0x00178F. 05 00 00 04 00 00 00 00 07 DA 00 0F B5 00 17 8F Write TBS ROM Data - 0x06 This EEPROM command selects the on-chip test bit stream (TBS) data for use by the TBS generator. No data words are required for this EEPROM command. See “Test Bit Stream Generator” on page 64 for more information about the on-chip test bit stream data set. Sample Command: 06 Filter Start - 0x07 This EEPROM command initializes and starts the digital filter. Measurement data becomes available one full sample period after this command is received. No data words are required for this EEPROM command. Sample Command: 07 8.5 Example EEPROM Configuration Table 6 shows an example EEPROM file for a minimal CS5376A configuration. 30 DS612F4 CS5376A Addr 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Data 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 22 00 06 01 00 00 00 07 04 31 01 00 00 20 Description Mfg header Addr 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Data 00 02 40 01 00 00 2A 07 40 40 01 00 00 2B 04 B0 00 07 Description Write TBSCFG Register Write TBSGAIN Register Write ROM Coefficients 30 31 Filter Start Write TBS ROM Data Write CONFIG Register Write FILTCFG Register Table 6. Example EEPROM File DS612F4 31 CS5376A Digital Filter Command Interpreter SPI 1 Registers SPI 1 Pin Logic SSI SCK1 MOSI MISO SINT Figure 17. Serial Peripheral Interface 1 (SPI 1) Block Diagram 9. CONFIGURATION BY MICROCONTROLLER After reset, the CS5376A reads the state of the BOOT pin to determine a source for configuration commands. If BOOT is low, the CS5376A receives configuration commands from a microcontroller. 9.2 Microcontroller Hardware Interface When booting from a microcontroller the CS5376A SPI 1 port receives configuration commands and configuration data through serial transactions, as shown in Figure 18. 8-bit SPI opcodes and 8-bit addresses are combined to read and write 24-bit configuration commands and data. Microcontroller serial transactions require toggling the SSI pin as the CS5376A chip select and writing a serial clock to the SCK1 input. Serial data is input to the CS5376A on the MOSI pin, and output from the CS5376A on the MISO pin. 9.1 Pin Descriptions Pins required for microcontroller boot are listed here, other SPI 1 pins are inactive. SSI - Pin 49 Slave select input pin, active low. Serial chip select input from a microcontroller. SCK1 - Pin 48 Serial clock input pin. Serial clock input from microcontroller, maximum 4.096 MHz. MOSI - Pin 51 Serial data input pin. Valid on rising edge of SCK1, transition on falling edge. MISO - Pin 50 Serial data output pin. Valid on rising edge of SCK1, transition on falling edge. Open drain output requiring a 10 kΩ pull-up resistor. SINT - Pin 52 Serial interrupt output pin, active low. 1 uS active low pulse output when ready for next serial transaction. 9.3 Microcontroller Serial Transactions Microcontroller configuration commands are written to the digital filter through the SPI 1 registers. A 24-bit command and two 24-bit data words can be written to the SPI 1 registers in any single serial transaction. Some commands require additional data words through additional serial transactions to complete. 9.3.1 SPI opcodes A microcontroller communicates with the CS5376A SPI 1 port using standard 8-bit SPI opcodes and an 8-bit SPI address. The standard SPI ‘Read’ and ‘Write’ opcodes are listed in Figure 18. 32 DS612F4 CS5376A Instruction Write Read Opcode 0x02 0x03 Address ADDR[7:0] ADDR[7:0] Definition Write SPI 1 registers beginning at the address in ADDR. Read SPI 1 registers beginning at the address in ADDR. Microcontroller Write to SPI 1 SSI MOSI 0x02 ADDR Data1 Data2 DataN MISO Microcontroller Read from SPI 1 SSI MOSI 0x03 ADDR MISO Data1 Data2 DataN Cycle 1 2 3 4 5 6 7 8 SCK1 MOSI MSB 6 5 4 3 2 1 LSB MISO MSB 6 5 4 3 2 1 LSB X SSI Figure 18. Microcontroller Serial Transactions DS612F4 33 CS5376A 9.3.2 SPI 1 registers The SPI 1 registers are shown in Figure 19 and are 24-bit registers mapped into an 8-bit register space as high, mid, and low bytes. See “SPI 1 Registers” on page 81 for the bit definitions of the SPI 1 registers. 9.3.3 SPI 1 transactions A serial transaction to the SPI 1 registers starts with an SPI opcode, followed by an address, and then some number of data bytes written or read starting at that address. Typical serial write transactions require sending groups of 5, 8, or 11 total bytes to the SPI1CMD or SPI1DAT1 registers. Example 5-byte write transaction to SPI1CMD 02 03 12 34 56 Example 5-byte write transaction to SPI1DAT1 02 06 12 34 56 Example 8-byte write transaction to SPI1CMD 02 03 12 34 56 AB CD EF Example 8-byte write transaction to SPI1DAT1 02 06 12 34 56 AB CD EF Example 11-byte write transaction to SPI1CMD 02 03 12 34 56 AB CD EF 65 43 21 Typical serial read transactions require groups of 3 or 5 bytes, split between writing into MOSI and reading from MISO. 3-byte read transaction of mid-byte of SPI1CTRL MOSI: 03 01 00 MISO: xx xx 12 5-byte read transaction of SPI1DAT1 MOSI: 03 06 00 00 00 MISO: xx xx 12 34 56 9.3.4 Multiple serial transactions Some configuration commands require multiple serial transactions to complete. There must be a small delay between transactions for the CS5376A to process the incoming data. Three methods can be used to ensure the CS5376A is ready to receive the next configuration command. 1) Delay a fixed 1 ms period to guarantee enough time for the command to be completed. 2) Monitor the SINT pin for a 1 us active low pulse. This pulse output occurs once the CS5376A completes processing the current command. 3) Verify the status of the E2DREQ bit by reading the SPI1CTRL register. When low, the CS5376A is ready for the next command. 9.3.5 Polling E2DREQ One transaction type that can always be performed no matter the delay from the previous configuration command is reading E2DREQ in the mid-byte of the SPI1CTRL register. A 3-byte read transaction. MOSI: 03 01 00 MISO: xx xx 01 EXP] YSUM(n) = Y(n) + YSUM(n-1) Offset Correction = YSUM >> EXP Once the EXP bits are written, the ORCAL bit in the FILTCFG register is set to enable offset calibration. When enabled, updated offset correction values are automatically written to the OFFSETx registers. When the offset calibration algorithm is fully settled, the ORCAL bit is cleared to maintain the final values in the OFFSETx registers. 15.3 Offset Calibration An offset calibration algorithm in the CS5376A can automatically calculate offset correction values. When using the offset calibration algorithm, background noise data should be used as the basis for calculating the offset value of each measurement channel. The offset calibration algorithm is an exponential averaging function that places increased weight on 60 DS612F4 CS5376A System Telemetry Token Out Data Ready Clock Out Data In Token In CS5376A SDTKI SDRDY SDCLK SDDAT SDTKO Figure 31. Serial Data Port Block Diagram 16.SERIAL DATA PORT Once digital filtering is complete, each 24-bit output sample is combined with an 8-bit status byte. These 32-bit data words are written to an 8-deep FIFO buffer and then transmitted to the communications channel through a high speed serial data port (SD port). 16.2 SD Port Data Format Serial data transactions transfer 32-bit words. Each word consists of an 8-bit status byte followed by a 24-bit output sample. The status byte, shown in Figure 32, has an MFLAG bit, channel bits, a time break bit, and a FIFO overflow bit. MFLAG Bit - MFLAG The MFLAG bit is set when an MFLAG signal is received on the MFLAG1-MFLAG4 pins. When received, that channel MFLAG bit is set in the next output word. See “Modulator Interface” on page 39 for more information about MFLAG. Channel Bits - CH[1:0] Channel bits indicate from which conversion channel the data word is from. The channel number, CH[1:0], is zero based. 16.1 Pin Descriptions SDTKI - Pin 64 Token input, requests an SD port transaction. SDRDY - Pin 61 Data ready output signal, active low. Open drain output requiring a 10 kΩ pull-up resistor. SDCLK - Pin 62 Serial clock input. SDDAT - Pin 60 Serial data output. Data valid on rising edge of SDCLK, transition on falling edge. SDTKO - Pin 63 Token output, ends an SD port transaction. Passes through the SDTKI signal when no data is available in the SD port output FIFO. CH[1:0] = 00 = Channel 1 CH[1:0] = 01 = Channel 2 CH[1:0] = 10 = Channel 3 CH[1:0] = 11 = Channel 4 Time Break Bit - TB The time break bit marks a timing reference based on a rising edge into the TIMEB pin. After a programmed delay, the TB bit in the status byte is set for one output sample in all channels. The TIME61 DS612F4 CS5376A Status Word 1 Data Word 2 128 bits Word 3 Word 4 31 Status 23 Data 0 MFLAG 31 -30 CH[1] 29 CH[0] 28 -27 TB 26 -25 W 24 0 - Modulator Ok 1 - Modulator Error 00 - Channel 1 01 - Channel 2 10 - Channel 3 11 - Channel 4 0 - No Time Break 1 - Time Break 0 - FIFO Ok 1 - FIFO Overflow Figure 32. SD Port Data Format BRK digital filter register (0x29) programs the sample delay for the TB bit output. See “Time Break Controller” on page 67 for more information about time break. FIFO Overflow Bit - W The FIFO overflow bit indicates an error condition in the SD port data FIFO, and is set if new digital filter data overwrites a FIFO location containing data which has not yet been sent. 16.3 SD Port Transactions The SD port can operate in two modes depending how the SDTKI pin is connected: request mode where data is output when requested by the communications channel, or continuous mode where data is output immediately when ready. 16.3.1 Request Mode To initiate SD port transactions on request, SDTKI is connected to an active high polling signal from the communications channel. A rising edge into SDTKI when new data is available in the SD port FIFO causes the CS5376A to initiate an SD port transaction by driving SDRDY low. If data is not yet available in the SD port FIFO, the SDTKI signal is passed through to the SDTKO output. The W bit is sticky, meaning it persists indefinitely once set. Clearing the W bit requires sending the ‘Filter Stop’ and ‘Filter Start’ configuration commands to reinitialize the data FIFO. Conversion Data Word The lower 24-bits of the SD port output data word is the conversion sample for the specified channel. Conversion data is 24-bit two’s complement format. Once an SD port transaction is initiated, serial clocks into SDCLK cause data to be output to SDDAT, as shown in Figure 33. When all available 62 DS612F4 CS5376A SDTKI SDTKO SDRDY SDCLK SDDAT MSB LSB Figure 33. SD Port Transaction data is read from the SD port data FIFO, SDRDY is released and SDTKO is pulsed high for 100 nS. 16.3.2 Continuous Mode To have the CS5376A automatically initiate SD port transactions whenever data becomes available, connect SDTKI to a 4 MHz or slower clock source such as MCLK/2. The first rising edge into SDTKI after data becomes available in the SD port FIFO causes the CS5376A to initiate an SD port transaction by driving SDRDY low. If data is not available in the SD port FIFO, the SDTKI signal is passed through to the SDTKO output. Once an SD port transaction is initiated, serial clocks into SDCLK cause data to be output to SDDAT, as shown in Figure 33. When all available data is read from the SD port data FIFO, SDRDY is released and SDTKO is pulsed high for 100 nS. DS612F4 63 CS5376A Digital Filter Data Bus 24-bit TBSGAIN Register 24-bit Digital ∆Σ Modulator 1-bit TBSDATA TBSCLK Clock Generation TBSCFG Register Figure 34. Test Bit Stream Generator Block Diagram 17.TEST BIT STREAM GENERATOR The CS5376A test bit stream (TBS) generator creates sine wave ∆Σ bit stream data to drive an external test DAC. The TBS digital output can also be internally connected to the MDATA inputs for loopback testing of the digital filter. full scale 1-bit ∆Σ output from the TBS generator is defined as 25% minimum and 75% maximum one’s density. 17.3 TBS Configuration Configuration options for the TBS generator are set through the TBSCFG register (0x2A). Gain scaling of the TBS generator output is set by the TBSGAIN register (0x2B). Interpolation Factor - INTP[7:0] Selects how many times the interpolator uses a data point when generating the output bit stream. Interpolation is zero based and represents one greater than the programmed register value. Clock Rate - RATE[2:0] Selects the TBSDATA and TBSCLK output rate. Synchronization - TSYNC Enables synchronization of the TBS output phase to the MSYNC signal. Clock Delay - CDLY[2:0] Programs a fractional delay for TBSCLK with a 1/8 clock period resolution. 17.1 Pin Descriptions TBSDATA - Pin 9 Test bit stream 1-bit ∆Σ data output. TBSCLK - Pin 8 Test bit stream clock output. Not used by the CS4373A test DAC. 17.2 TBS Architecture The test bit stream generator consists of a data interpolator and a digital ∆Σ modulator. It receives periodic 24-bit data from the digital filter to create a 1-bit ∆Σ data output on the TBSDATA pin. It also creates a clock signal at the data rate, output to the TBSCLK pin. The TBS input data from the digital filter is scaled by the TBSGAIN register (0x2B). Maximum stable amplitude is 0x04FFFF, with 0x04B8F2 approximately full scale for the CS4373A test DAC. The 64 DS612F4 CS5376A Test Bit Stream Characteristic Equation: (Signal Freq) * (# TBS Data) * (Interpolation + 1) = Output Rate Example: (31.25 Hz) * (1024) * (0x07 + 1) = 256 kHz Signal Frequency (TBSDATA) Output Rate (TBSCLK) Output Rate Selection (RATE) Interpolation Selection (INTP) 10.00 Hz 10.00 Hz 25.00 Hz 25.00 Hz 31.25 Hz 31.25 Hz 50.00 Hz 50.00 Hz 125.00 Hz 125.00 Hz 256 kHz 512 kHz 256 kHz 512 kHz 256 kHz 512 kHz 256 kHz 512 kHz 256 kHz 512 kHz 0x4 0x5 0x4 0x5 0x4 0x5 0x4 0x5 0x4 0x5 0x18 0x31 0x09 0x13 0x07 0x0F 0x04 0x09 0x01 0x03 Table 19. TBS Configurations Using On-chip Data Loopback - LOOP Enables digital loopback from the TBS output to the MDATA inputs. Run - RUN Enables the test bit stream generator. Data Delay - DDLY[5:0] Programs full period delays for TBSDATA, up to a maximum of 63 bits. Gain - TBSGAIN[23:0] Scales the amplitude of the sine wave output. Maximum 0x04FFFF, nominal 0x04B8F2. though custom data is required to support custom signal frequencies. See “EEPROM Configuration Commands” on page 28 or “Microcontroller Configuration Commands” on page 35 for information about programming TBS data. TBS ROM Data 17.4 TBS Data Source Data to create test signals is loaded into digital filter memory by configuration commands. The onchip sine wave data is suitable for most tests, An on-chip 24-bit 1024 point digital sine wave is stored on the CS5376A. When selected by the ‘Write TBS ROM Data’ configuration command, the TBS generator can produce the test signal frequencies listed in Table 19. Additional discrete test frequencies and output rates can be programmed with the on-chip data by varying the interpolation factor and output rate. Custom TBS Data If a required test frequency cannot be generated using the on-chip test bit stream data, a custom data DS612F4 65 CS5376A set can be written into the CS5376A. The number of data points to write, up to a maximum of 1024, depends on the required test signal frequency, output rate, and available interpolation factors. Custom data sets must be continuous on the ends; i.e. when copied end-to-end the data set must produce a smooth curve. MDATA inputs. This loopback mode provides a fully digital signal path to test the TBS generator, digital filter, and data collection interface. Digital loopback testing expects 512 kHz ∆Σ data for the MDATA inputs. A mismatch of the TBS generator full scale output and the MDATA full scale input results in an amplitude mismatch when testing in loopback mode. The TBS generator outputs a 75% maximum one’s density, while the MDATA inputs expect an 86% maximum one’s density from a ∆Σ modulator, resulting in a measured full scale error of -3.6 dB. 17.5 TBS Sine Wave Output The TBS generator uses data from digital filter memory to create a sine wave test signal that can drive a test DAC. Sine wave frequency and output data rate are calculated as shown by the characteristic equation of Table 19. The sine wave maximum ∆Σ one’s density output from the TBS generator is set by the TBSGAIN register. TBSGAIN can be programmed up to a maximum of 0x04FFFF, with the TBS generator unstable for higher amplitudes. For the CS4373A test DAC, a gain value of 0x04B8F2 produces an approximately full scale sine wave output (5 Vpp differential). 17.7 TBS Synchronization When the TSYNC bit is set in the TBSCFG register, the MSYNC signal resets the sine wave data pointer and phase aligns the TBS signal output. Once the digital filter is settled, all CS5376A devices receiving the SYNC signal will have identical TBS signal phase. See “Synchronization” on page 25 for more information about the SYNC and MSYNC signals. If TSYNC is clear, MSYNC has no effect on the TBS data pointer and no change in the TBS output phase will occur during synchronization. 17.6 TBS Loopback Testing Included as part of the CS5376A test bit stream generator is a feedback path to the digital filter 66 DS612F4 CS5376A TIMEB TIMEBRK Delay Counter TB Flag in SD Port Status Byte Figure 35. Time Break Block Diagram 18.TIME BREAK CONTROLLER A time break signal is used to mark timing events that occur during measurement. An external signal sets a flag in the status byte of an output sample to mark when the external event occurred. A rising edge input to the TIMEB pin causes the TB timing reference flag to be set in the SD port status byte. When set, the TB flag appears for only one output sample in the status byte of all enabled channels. The TB flag output can be delayed by programming a sample delay value into the TIMEBRK digital filter register. 18.3 Time Break Delay The TIMEBRK register (0x29) sets a sample delay between a received rising edge on the TIMEB pin and writing the TB flag into the SD port status byte. The programmable sample counter can compensate for group delay through the digital filters. When the proper group delay value is programmed into the TIMEBRK register, the TB flag will be set in the status byte of the measurement sample taken when the timing reference signal was received. 18.3.1 Step Input and Group Delay A simple method to empirically measure the step response and group delay of a CS5376A measurement channel is to use the time break signal as both a timing reference input and an analog step input. 18.1 Pin Description TIMEB - Pin 57 Time break input pin, rising edge triggered. 18.2 Time Break Operation An externally generated timing reference signal applied to the TIMEB pin initiates an internal sample counter. After a number of output samples have passed, programmed in the TIMEBRK digital filter register (0x29), the TB flag is set in the status byte of the SD port output word for all enabled channels. The TB flag is automatically cleared for subsequent data words, and appears for only one output sample in each channel. When a rising edge is received on the TIMEB pin with no delay programmed into the TIMEBRK register, the TB flag is set in the next SD port status byte. The same rising edge can act as a step input to the analog channel, propagating through the digital filter to appear as a rising edge in the measurement data. By comparing the timing of the TB status flag output and the rising edge in the measurement data, the measurement channel group delay can be determined. DS612F4 67 CS5376A GP_PULL CS output from SPI Data bit GP_DATA Pull Up Logic R GPIO/CS GP_DIR Figure 36. GPIO Bi-directional Structure 19.GENERAL PURPOSE I/O The General Purpose I/O (GPIO) block provides 12 general purpose pins to interface with external hardware. sponding GPIO pin should be initialized as output mode and logical 1 to produce the chip select falling edge. 19.1 Pin Descriptions GPIO[4:0]:CS[4:0] - Pins 32 - 36 Standard GPIO pins also used as SPI 2 chip selects. 19.3 GPIO Registers When used as standard GPIO pins, settings are programmed in the GPCFG0 and GPCFG1 registers. GP_DIR bits set the input/output mode, GP_PULL bits enable/disable the internal pull-up resistor, and GP_DATA bits set the output data value. After reset, GPIO pins default as inputs with pull-up resistors enabled. GPIO[5:10] - Pins 37, 41 - 45 Standard GPIO pins. GPIO11:EECS - Pin 46 Standard GPIO pin also used as an SPI 1 chip select when booting from an external EEPROM. 19.4 GPIO Input Mode When reading a value from the GP_DATA bits, the returned data reports the current state of the pins. If a pin is externally driven high it reads a logical 1, if externally driven low it reads a logical 0. When a GPIO pin is used as an input, the pull-up resistor should be disabled to save power if it isn’t required. 19.2 GPIO Architecture Each GPIO pin can be configured as input or output, high or low, with a weak (~200 kΩ) internal pull-up resistor enabled or disabled. Several GPIO pins also double as chip selects for the SPI 1 and SPI 2 serial ports. Figure 36 shows the structure of a bi-directional GPIO pin with SPI chip select functionality. When the CS5376A is used as an SPI master, either when booting from EEPROM using SPI 1 or performing master mode transactions using SPI 2, the chip select signals from SPI 1 and SPI 2 are logically AND-ed with the GPIO data bit. The corre68 19.5 GPIO Output Mode When a GPIO pin is programmed as an output with a data value of 0, the pin is driven low and the internal pull-up resistor is automatically disabled. When programmed as an output with a data value of 1, the pin is driven high and the pull-up resistor is inconsequential. DS612F4 CS5376A Any GPIO pin can be used as an open-drain output by setting the data value to 0, enabling the pull-up, and using the GP_DIR direction bits to control the pin value. This open-drain output configuration uses the internal pull-up resistor to hold the pin high when GP_DIR is set as an input, and drives the pin low when GP_DIR is set as an output. 19.5.1 GPIO Reads in Output Mode When reading GPIO pins the GP_DATA register value always reports the current state of the pins, so a value written in output mode does not necessarily read back the same value. If a pin in output mode is written as a logical 1, the CS5376A attempts to drive the pin high. If an external device forces the pin low, the read value reflects the pin state and returns a logical 0. Similarly, if an output pin is written as a logical 0 but forced high externally, the read value reflects the pin state and returns a logical 1. In both cases the CS5376A is in contention with the external device resulting in increased power consumption. DS612F4 69 CS5376A SCKFS[2:0] / SCKPO / SCKPH Digital Filter SPI2EN[4:1] / RCH[1:0] Pin logic 4:1 SCK2 SO SI1 SI2 SI3 SI4 CS0 CS1 CS2 CS3 CS4 To GPIO Block CS[4:0] Select logic Figure 37. Serial Peripheral Interface 2 (SPI 2) Block Diagram 20.SERIAL PERIPHERAL INTERFACE 2 The Serial Peripheral Interface 2 (SPI 2) port is a master mode SPI port designed to interface with serial peripherals. By writing the SPI2 digital filter registers, multiple serial slave devices can be controlled through the CS5376A. is selected by bits in the SPI2CTRL digital filter register. SPI 2 chip select outputs are multiplexed with GPIO pins, which cannot perform both functions simultaneously. When used as a chip select, the GPIO output must be programmed high to permit the chip select to operate as an active low signal. See “General Purpose I/O” on page 68 for information about programming the GPIO pins. The SPI 2 interface transfers data from the SPI 2 registers to a slave serial device and back through a bi-directional 8-bit shift register. Serial transactions are automatic once control, command, and data values are written into the SPI 2 digital filter registers. 20.1 Pin Descriptions CS[4:0] - Pins 32 - 36 Serial chip selects. Multiplexed with GPIO pins. SCK2 - Pin 31 Serial clock output, common to all channels. SO - Pin 30 Serial data output, common to all channels. SI[4:1] - Pins 26 - 29 Serial data inputs. 20.3 SPI 2 Registers SPI 2 transactions are initiated by first writing command, address, and data values to the SPI2CMD and SPI2DAT digital filter registers, and then writing the SPI2CTRL register to set the D2SREQ bit. The D2SREQ bit initiates a serial transaction using the programmed SPI2CTRL configuration. DS612F4 20.2 SPI 2 Architecture The SPI 2 pin interface has multiple chip selects and serial data inputs, but a common serial clock and serial data output. Which chip select and serial input to use for a particular slave serial transaction 70 CS5376A 20.3.1 SPI 2 Control Register The SPI 2 hardware is configured by the SPI2CTRL digital filter register (0x10). ports all four SPI modes, with mode 0 and mode 3 the most commonly used. Supported modes are: SPI Mode 0 (0,0): SCKPO = 0, SCKPH = 0 SPI Mode 1 (0,1): SCKPO = 0, SCKPH = 1 SPI Mode 2 (1,0): SCKPO = 1, SCKPH = 0 SPI Mode 3 (1,1): SCKPO = 1, SCKPH = 1 Wired-Or Mode - WOM The SPI 2 pins can operate in two modes depending on the WOM bit. A default push-pull configuration drives output signals both high and low. Wired-Or mode only drives low, relying on a weak internal pull-up resistor to pull the output high. Wired-Or mode permits multiple serial controllers to access the same bus without contention. Initiating Serial Transactions - D2SREQ Writing the D2SREQ bit starts an SPI 2 serial transaction. When complete, the D2SREQ bit is automatically cleared by the SPI 2 hardware. Status and Error Bits - D2SOP, SWEF, TM Three bits in the SPI2CTRL register report status and error information. Bits in this register select the serial input pin and chip select pin used for a transaction, set the total number of bytes in a transaction, initiate a serial transaction, and report status information about a transaction. Other bits in SPI2CTRL set hardware configuration options such as the serial clock rate, the SPI mode, and the state of internal pull-up resistors. Chip Select Enable - CS[4:0] The chip select pin to use during a transaction is selected by the CS0, CS1, CS2, CS3, and CS4 bits. Multiple chip selects can be enabled to send a transaction to more than one serial peripheral. Serial Input Select - SPI2EN[4:1], RCH[1:0] Which serial input pin will receive data is selected using the SPI2EN bits and the RCH bits. The SPI2EN bits enable the serial input, while the RCH bits select it for the SPI 2 transaction. A channel’s SPI2EN bit should always be enabled, even when transactions do not expect to receive data from the slave device. Transaction Bytes - DNUM[2:0] DNUM bits specify the total number of bytes to transfer during a serial transaction, including command and address bytes. DNUM is zero based and represents one greater than the number programmed. Serial Clock Rate - SCKFS[2:0] The serial clock rate output from the SCK2 pin is selected by the SCKFS bits. Serial clock rates range from 32 kHz to 4.096 MHz. SPI Mode - SCKPO, SCKPH The serial mode used for a transaction depends on the SCKPO and SCKPH bits. The SPI 2 port sup- D2SOP is set when the SPI 2 port is busy performing a transaction. It is automatically cleared when the transaction is completed. SWEF is set if a request to initiate a new transaction occurs during the current transaction. This flag is latched and must be cleared manually. TM is set to indicate the SPI 2 port timed out on the requested transaction. This flag is latched and must be cleared manually. 20.3.2 SPI 2 Command Register The SPI2CMD register (0x11) is a 16-bit digital filter register with the high byte designated as an SPI command and the low byte designated as an address. The high byte holds an 8-bit SPI ‘write’ or ‘read’ opcode, as shown in Figure 38, and the low byte holds an 8-bit serial address. 71 DS612F4 CS5376A During a transaction, bits in SPI2CMD are output MSB first, with data in SPI2DAT written or read following. 20.3.3 SPI 2 Data Register The SPI2DAT register (0x12) is a 24-bit digital filter register containing three SPI data bytes. Data in SPI2DAT is always LSB aligned, with 1-byte data written or received using the low byte, 2-byte data written or received using the middle and low bytes, and 3-byte data written or received using all three bytes. dard write commands they can be written into SPI2CMD and SPI2DAT as required. Read Transactions Read transactions start by writing an SPI ‘read’ (0x03) opcode and an 8-bit source address to the SPI2CMD register. Writing the D2SREQ bit in the SPI2CTRL register initiates the SPI 2 transaction based on the SPI2CTRL configuration, with the data value automatically received into the SPI2DAT register. Data in SPI2DAT is written or read after writing the command and address bytes from the SPI2CMD register. 20.4 SPI 2 Transactions The SPI 2 port operates as an SPI master to perform write and read transactions with serial slave peripherals. The exact format of the SPI transactions depends on the SPI mode, selected using the SCKPO and SCKPH bits in the SPI2CTRL register. Write Transactions Write transactions start by writing an SPI ‘write’ (0x02) opcode and an 8-bit destination address into the SPI2CMD register and the output data value to the SPI2DAT register. Writing the D2SREQ bit in the SPI2CTRL register initiates the SPI 2 transaction based on the SPI2CTRL configuration. A read transaction outputs 2 bytes from the SPI2CMD register and can receive 1, 2, or 3 bytes into the SPI2DAT register. Read transactions are a minimum of 3 bytes (DNUM = 2) and a maximum of 5 bytes (DNUM = 4). The SPI 2 port uses the DNUM bits in the SPI2CTRL register to determine the total number of bytes to send and receive during a read transaction. Read transactions are not required to use standard SPI commands. If serial peripherals use non-standard read commands they can be written to the SPI2CMD register, as long as they conform to the format of 2 bytes out with 1, 2, or 3 bytes in. SPI Modes The SPI mode for the SPI 2 port is selected in the SPI2CTRL register using the SCKPO and SCKPH bits. The most commonly used SPI modes are mode 0 and mode 3, both of which define the serial clock with data valid on rising edges and transitioning on falling edges. A write transaction outputs 1 or 2 bytes from the SPI2CMD register followed by 1, 2, or 3 bytes from the SPI2DAT register. Write transactions are therefore a minimum of 1 byte (DNUM = 0) and a maximum of 5 bytes (DNUM = 4). The SPI 2 port uses the DNUM bits in the SPI2CTRL register to determine the total number of bytes to send during a write transaction. Write transactions are not required to use standard SPI commands. If serial peripherals use non-stan- In SPI mode 0, the SCK2 serial clock is defined initially in a low state. Output data on the SO pin is valid immediately after the chip select pin goes low, and the first rising edge of SCK2 latches valid data. In SPI mode 3, the SCK2 serial clock is defined initially in a high state. Output data on the SO pin is invalid until the initial falling edge of SCK2, and the first rising edge of SCK2 latches valid data. 72 DS612F4 CS5376A Instruction Write Read 0x02 0x03 Opcode Address SPI2CMD[7:0] SPI2CMD[7:0] Definition Write serial peripheral beginning at the address given in SPI2CMD[7:0]. Read serial peripheral beginning at the address given in SPI2CMD[7:0]. SPI 2 Write to External Slave SPI2CMD[15:8] SPI2CMD[7:0] SPI2DAT SO 0x02 ADDR Data1 Data2 Data3 SI CS SPI 2 Read from External Slave SPI2CMD[15:8] SPI2CMD[7:0] SO 0x03 ADDR SI Data1 Data2 Data3 CS SPI2DAT Figure 38. SPI 2 Master Mode Transactions SPI modes 1 and 4 work similarly to modes 0 and 3, with the serial clock defined to have data valid on falling edges and transitioning on rising edges. DS612F4 73 CS5376A SPI 2 Transaction with SCKPH=0 Cycle SCK2 SCK2 SO SI CS SCKPO = 0 1 2 3 4 5 6 7 8 SCKPO = 1 MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB X Slave devices only drive SI after being selected and responding to a read command. SPI 2 Transaction with SCKPH=1 Cycle SCK2 SCK2 SO SI CS X SCKPO = 0 1 2 3 4 5 6 7 8 SCKPO = 1 MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB Slave devices only drive SI after being selected and responding to a read command. Figure 39. SPI 2 Transaction Details DS612F4 74 CS5376A TRST TMS TCK TDI TAP Controller TDO Boundary Scan Cells Figure 40. JTAG Block Diagram 21.BOUNDARY SCAN JTAG The CS5376A includes an IEEE 1149.1 boundary scan JTAG port to test PCB interconnections. Refer to the IEEE 1149.1 specification for more information about boundary scan testing. 21.1 Pin Descriptions TRST - Pin 1 Reset input for the test access port (TAP) controller and all boundary scan cells, active low. Connect to GND to disable the JTAG port. TMS - Pin 2 Serial input to select the JTAG test mode. TCK - Pin 3 Clock input to the TAP controller. TDI - Pin 4 Serial input to the scan chain or TAP controller. TDO - Pin 5 Serial output from the scan chain or TAP controller. 21.2 JTAG Architecture The JTAG test circuitry consists of a test access port (TAP) controller and boundary scan cells connected to each pin. The boundary scan cells are linked together to create a scan chain around the CS5376A. DS612F4 75 CS5376A 21.2.1 JTAG Reset As required by the IEEE 1149.1 specification, the JTAG TRST signal is independent of the CS5376A RESET signal. In systems not using the JTAG port, TRST should be connected to ground. In systems using the JTAG port, TRST and RESET should be independently driven to provide reset capability during boundry scan. 21.2.2 TAP Controller The test access port (TAP) controller manages commands and data through the boundary scan chain. It supports the four JTAG instructions and contains the IDCODE listed in Table 20. JTAG Instructions BYPASS EXTEST IDCODE SAMPLE / PRELOAD Encoding 11 00 01 10 JTAG IDCODE Components Revision Device ID Manufacturer ID CS5376A IDCODE Encoding 0x10000000 0x05376000 0x000000C9 0x153760C9 Table 20. JTAG Instructions and IDCODE The TAP controller also implements the 16 JTAG state assignments from the IEEE 1149.1 specification, which are sequenced using TMS and TCK. 21.2.3 Boundary Scan Cells The CS5376A JTAG test port provides access to all device pins via internal boundary scan cells. When the JTAG port is disabled, boundary scan cells are transparent and do not affect CS5376A operation. When the JTAG port is enabled, boundary scan cells can write and read each pin independent of CS5376A operation. Boundary scan cells are serially linked to create a scan chain around the CS5376A controlled by the TAP controller. Table 21 lists the scan cell mapping of the CS5376A. 76 DS612F4 CS5376A BRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Pin TBSCLK TBSDATA DNC MCLK/2 MCLK MSYNC MDATA4 MFLAG4 MDATA3 MFLAG3 MDATA2 MFLAG2 MDATA1 MFLAG1 GND SI4 SI3 SI2 SI1 SO SCK2 GPIO0 Function data out data out data out data out data out data out data in data in data in data in data in data in data in data in data in data in data in data in data in data out WOM data out WOM data in data out output enable pullup BRC 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Pin GPIO3 Function data in data out output enable pullup BRC 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 SSI SSO Pin GPIO11 Function data in data out output enable pullup data out output enable WOM GPIO4 data in data out output enable pullup SCK1 data in data out output enable WOM pullup data in data in data out output enable WOM pullup GPIO5 data in data out output enable pullup GPIO6 data in data out output enable pullup MISO GPIO7 data in data out output enable pullup MOSI data in data out output enable WOM pullup GPIO8 data in data out output enable pullup SINT RESET BOOT TIMEB CLK SYNC SDDAT SDRDY SDCLK SDTKO SDTKI data out data in data in data in data in data in data out output enable data out data in data out data in GPIO9 data in data out output enable pullup GPIO1 data in data out output enable pullup GPIO10 data in data out output enable pullup GPIO2 data in data out output enable pullup Table 21. JTAG Scan Cell Mapping DS612F4 77 CS5376A 22.DEVICE REVISION HISTORY The CS5376A is a pin compatible upgrade to the CS5376. The part family has had three revisions: CS5376 rev A CS5376 rev B CS5376A rev A Modified ROM Coefficient Selection Method Changed the ROM coefficient selection routines (SPI and EEPROM) to require a 24 bit data word. Previously no data word was required, only the command byte. The data word is parsed to select the FIR1, FIR2, IIR1, and IIR2 coefficient sets. Modified ROM TBS Data Selection Method Changed the ROM test bit stream selection routine (SPI and EEPROM) to require a 24 bit data word. Previously no data word was required, only the command byte. The data word scales the ROM test bit stream data to a user selected amplitude. Modified SPI port to strobe SINT pin The SPI port now pulses the SINT pin whenever data is received. Can be used by a microcontroller to trigger additional data writes. Eliminates the need to poll the e2dreq bit. Fixed continuous synchronization operation The synchronization operation was modified to permit continuous re-sync. The SD port FIFO is no longer reset by the SYNC interrupt. Corrected EEPROM loader bug The EEPROM loader bug is fixed. A preamble to write required constants into memory is no longer required. The part number change for CS5376A reflects additional functionality built into the device. 22.1 Changes from CS5376 rev A to CS5376 rev B New Sinc Filter, SINC3 Added a new sinc filter, SINC3, between the previous sinc filters and FIR1. Will permit higher decimation rates for seismology applications. Not used for 0.25 ms, 0.5 ms, 1 ms, or 2 ms output rates to maintain backward compatibility. Added FIR1 Coefficients Included an improved FIR1 filter to compensate for sinc filter droop. Previous filter had stop band frequency components up to -100 dB not removed by the FIR2 brick wall filter. Required stop band attenuation is 130 dB minimum. Previous FIR1 filter coefficients still included to maintain backwards compatibility. Added IIR Coefficients Included 3 Hz IIR1 and IIR2 filter coefficients for the 0.5 ms, 1 ms, 2 ms, 3 ms, and 4 ms configurations (5 sets IIR1, 5 sets IIR2). Previous 2 Hz @ 1 ms coefficient set was removed. Modified Output Word Rate Selection Changed the DEC bit settings in the FILTCFG register used to select an output word rate. Re-numbered to include the new 120 Hz, 60 Hz, 30 Hz, 15 Hz, and 7.5 Hz output rates. Other settings the same for backward compatibility. 22.2 Changes from CS5376 rev B to CS5376A rev A Fixed synchronization repeatability bug Identical synchronization signals previously caused different impulse responses from multiple devices. Synchronization is now repeatable. DS612F4 78 CS5376A Modified SINC2 filter to correct gain and timing errors Corrected SINC2 decimate by 2 gain error which affected 4000 SPS operation. Also modified SINC2 decimate by 16 output timing to match output of other SINC2 rates. Previous SINC2 decimate by 16 output was one sample later than expected. Corrected gain error of 333 SPS output rate SINC architecture was modified to correct gain error in SINC2 decimate by 12 by moving decimate by 3 stage into SINC3. Modified SINC3 filter for new low bandwidth rates. Newly supported output word rates are 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS. Older low bandwidth rates of 120, 60, 30, 15, 7.5 SPS were removed. No changes to 4000, 2000, 1000, 500, 333, 250 SPS rates for backwards compatibility to CS5376 revision A/B. Added minimum phase FIR coefficients Minimum phase FIR1 coefficient set 1 and FIR2 coefficient set 1 are newly available as selections for the SPI and EEPROM 'Write ROM Coefficients' command. Corrected IIR2/IIR3 channels 2, 3, 4 bug When selecting IIR2 or IIR3 output, data from channels 2, 3, and 4 were corrupted. IIR2 and IIR3 now operate correctly for these channels. Corrected IIR2 coefficient DC offset IIR2 coefficient sets 0, 1, and 3 did not perfectly cancel DC due to coefficient b20, b21, b22 mismatch. New b21 IIR2 coefficients correct this offset error. Removed gain scale factor from 'Write TBS ROM' command TBS data was previously scaled during configuration by a data word following the 'Write TBS ROM' command. Added a new TBSGAIN register (0x2B, replacing WD_CFG) that scales the TBS amplitude and can be modified during normal operation. Removed watchdog timer The watchdog timer was removed. Replaced WD_CFG register (0x2B) with TBSGAIN register. Set GPIO11 as tri-state when EEPROM boot completed After stand-alone boot from EEPROM, GPIO11 (acting as EEPROM chip select) was previously driven high. This pin now tri-states with an internal pull-up to hold it high. Modified Test Bit Stream (TBS) to disable loopback when TBS disabled. If TBS loopback mode was enabled, the external MDATA inputs were disconnected from the SINC filter even if the TBS was disabled. Now when the TBS is disabled, loopback mode is automatically disabled also. DS612F4 79 CS5376A Added Test Bit Stream (TBS) synchronization in sine wave mode. The TBS sine wave phase will reset if bit 11 of the TBSCFG register is set (TBSCFG bit 11 = 1) and a rising edge is received on the SYNC pin. When TBSCFG bit 11 is set low (TBSCFG bit 11 = 0), TBS phase is unaffected by the SYNC input similar to CS5376 revision A/B. Modified Time Break delay function. The timing delay between receiving a rising edge on the TIMEB pin and asserting the TIMEB flag in the output word status bits is corrected. In CS5376 revision A/B a '0' value in the TIMEBREAK register (0x29) disabled the TIMEB status bit write, and a '1' value set the status bit in the current output word. Now, a '0' value sets the TIMEB status bit in the current output word, and a '1' value delays until the following word. 80 DS612F4 CS5376A 23.REGISTER SUMMARY 23.1 SPI 1 Registers The CS5376A SPI 1 registers interface the serial port to the digital filter. Name Addr. Type # Bits Description SPI1CTRLH SPI1CTRLM SPI1CTRLL SPI1CMDH SPI1CMDM SPI1CMDL SPI1DAT1H SPI1DAT1M SPI1DAT1L SPI1DAT2H SPI1DAT2M SPI1DAT2L 00 01 02 03 04 05 06 07 08 09 0A 0B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 SPI 1 Control Register, High Byte SPI 1 Control Register, Middle Byte SPI 1 Control Register, Low Byte SPI 1 Command, High Byte SPI 1 Command, Middle Byte SPI 1 Command, Low Byte SPI 1 Data 1, High Byte SPI 1 Data 1, Middle Byte SPI 1 Data 1, Low Byte SPI 1 Data 2, High Byte SPI 1 Data 2, Middle Byte SPI 1 Data 2, Low Byte DS612F4 81 CS5376A 23.1.1 SPI1CTRL : 0x00, 0x01, 0x02 Figure 41. SPI 1 Control Register SPI1CTRL (MSB) 23 22 21 20 19 18 17 16 -R/W 0 -R/W1 0 -R/W 0 -R/W 0 -R/W 1 -R/W 0 -R/W 1 -R/W 1 SPI 1 Address: 0x00 0x01 0x02 -15 14 13 12 11 10 9 8 SMODF R 0 -R/W 0 -R 0 EMOP R 0 SWEF R 0 -R/W 0 -R/W 1 E2DREQ R/W 0 R W R/W Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 -R/W 0 -R/W 0 -R/W 1 -R/W 0 -R/W 0 -R/W 0 -R/W 0 -R/W 0 Bits in bottom rows are reset condition Bit definitions: 23:16 -reserved 15 SMODF SPI 1 mode fault flag reserved External master to SPI 1 operation in progress flag SPI 1 write collision error flag reserved 7:0 -reserved 14:13 -12 EMOP 11 SWEF 10:9 8 -- E2DREQ External master to digital filter request flag 82 DS612F4 CS5376A 23.1.2 SPI1CMD : 0x03, 0x04, 0x05 Figure 42. SPI 1 Command Register SPI1CMD (MSB) 23 22 21 20 19 18 17 16 S1CMD23 R/W 0 S1CMD22 R/W 0 S1CMD21 R/W 0 S1CMD20 R/W 0 S1CMD19 R/W 0 S1CMD18 R/W 0 S1CMD17 R/W 0 S1CMD16 R/W 0 SPI 1 Address: 0x03 0x04 0x05 -15 14 13 12 11 10 9 8 S1CMD15 R/W 0 S1CMD14 R/W 0 S1CMD13 R/W 0 S1CMD12 R/W 0 S1CMD11 R/W 0 S1CMD10 R/W 0 S1CMD9 R/W 0 S1CMD8 R/W 0 R W R/W Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 S1CMD7 R/W 0 S1CMD6 R/W 0 S1CMD5 R/W 0 S1CMD4 R/W 0 S1CMD3 R/W 0 S1CMD2 R/W 0 S1CMD1 R/W 0 S1CMD0 R/W 0 Bits in bottom rows are reset condition Bit definitions: 23:16 S1CMD[23:16] SPI 1 Command High Byte 15:8 S1CMD[15:8] SPI 1 Command Middle Byte 15:8 S1CMD[7:0] SPI 1 Command Low Byte DS612F4 83 CS5376A 23.1.3 SPI1DAT1 : 0x06, 0x07, 0x08 Figure 43. SPI 1 Data Register SPI1DAT1 (MSB) 23 22 21 20 19 18 17 16 S1DAT23 R/W 0 S1DAT22 R/W 0 S1DAT21 R/W 0 S1DAT20 R/W 0 S1DAT19 R/W 0 S1DAT18 R/W 0 S1DAT17 R/W 0 S1DAT16 R/W 0 SPI 1 Address: 0x06 0x07 0x08 -15 14 13 12 11 10 9 8 S1DAT15 R/W 0 S1DAT14 R/W 0 S1DAT13 R/W 0 S1DAT12 R/W 0 S1DAT11 R/W 0 S1DAT10 R/W 0 S1DAT9 R/W 0 S1DAT8 R/W 0 R W R/W Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 S1DAT7 R/W 0 S1DAT6 R/W 0 S1DAT5 R/W 0 S1DAT4 R/W 0 S1DAT3 R/W 0 S1DAT2 R/W 0 S1DAT1 R/W 0 S1DAT0 R/W 0 Bits in bottom rows are reset condition Bit definitions: 23:16 S1DAT[23:16] SPI 1 Data High Byte 15:8 S1DAT[15:8] SPI 1 Data Middle Byte 15:8 S1DAT[7:0] SPI 1 Data Low Byte 84 DS612F4 CS5376A 23.1.4 SPI1DAT2 : 0x09, 0x0A, 0x0B Figure 44. SPI 1 Data Register SPI1DAT2 (MSB) 23 22 21 20 19 18 17 16 S1DAT23 R/W 0 S1DAT22 R/W 0 S1DAT21 R/W 0 S1DAT20 R/W 0 S1DAT19 R/W 0 S1DAT18 R/W 0 S1DAT17 R/W 0 S1DAT16 R/W 0 SPI 1 Address: 0x09 0x0A 0x0B -15 14 13 12 11 10 9 8 S1DAT15 R/W 0 S1DAT14 R/W 0 S1DAT13 R/W 0 S1DAT12 R/W 0 S1DAT11 R/W 0 S1DAT10 R/W 0 S1DAT9 R/W 0 S1DAT8 R/W 0 R W R/W Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 S1DAT7 R/W 0 S1DAT6 R/W 0 S1DAT5 R/W 0 S1DAT4 R/W 0 S1DAT3 R/W 0 S1DAT2 R/W 0 S1DAT1 R/W 0 S1DAT0 R/W 0 Bits in bottom rows are reset condition Bit definitions: 23:16 S1DAT[23:16] SPI 1 Data High Byte 15:8 S1DAT[15:8] SPI 1 Data Middle Byte 15:8 S1DAT[7:0] SPI 1 Data Low Byte DS612F4 85 CS5376A 23.2 Digital Filter Registers The CS5376A digital filter registers control hardware peripherals and filtering functions. Name Addr. Type # Bits Description CONFIG RESERVED GPCFG0 GPCFG1 SPI2CTRL SPI2CMD SPI2DAT RESERVED FILTCFG GAIN1 GAIN2 GAIN3 GAIN4 OFFSET1 OFFSET2 OFFSET3 OFFSET4 TIMEBRK TBSCFG TBSGAIN SYSTEM1 SYSTEM2 VERSION SELFTEST 00 01-0D 0E 0F 10 11 12 13-1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 24 24 24 24 24 16 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 Hardware Configuration Reserved GPIO[7:0] Direction, Pull-Up Enable, and Data GPIO[11:8] Direction, Pull-Up Enable, and Data SPI2 Control SPI2 Command SPI2 Data Reserved Digital Filter Configuration Gain Correction Channel 1 Gain Correction Channel 2 Gain Correction Channel 3 Gain Correction Channel 4 Offset Correction Channel 1 Offset Correction Channel 2 Offset Correction Channel 3 Offset Correction Channel 4 Time Break Delay Test Bit Stream Configuration Test Bit Stream Gain User Defined System Register 1 User Defined System Register 2 Hardware Version ID Self-Test Result Code 86 DS612F4 CS5376A 23.2.1 CONFIG : 0x00 Figure 45. Hardware Configuration Register CONFIG (MSB)23 22 21 20 19 18 17 16 -R/W 0 -R/W 0 -R/W 0 -R/W 0 -R/W 0 DFS2 R/W 1 DFS1 R/W 0 DFS0 R/W 1 DF Address: 0x00 -R W R/W 15 14 13 12 11 10 9 8 -R/W 0 -R/W 0 -R/W 0 -R/W 0 -R/W 0 MCKFS2 R/W 1 MCKFS1 R/W 0 MCKFS0 R/W 0 Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB)0 Bits in bottom rows are reset condition -R/W 0 -R/W 0 MCKEN2 R/W 0 MCKEN R/W 0 MDIFS R/W 0 -R/W 0 BOOT R 0 MSEN R/W 1 Bit definitions: 23:19 -18:16 DFS [2:0] reserved Digital filter frequency select 111: 16.384 MHz 110: 8.192 MHz 101: 4.096 MHz 100: 2.048 MHz 011: 1.024 MHz 010: 512 kHz 001: 256 kHz 000: 32 kHz 15:11 -10:8 MCKFS [2:0] reserved 7:6 -MCKEN2 reserved MCLK/2 output enable 1: Enabled 0: Disabled MCLK output enable 1: Enabled 0: Disabled MDATA input frequency select 1: 256 kHz 0: 512 kHz reserved Boot source indicator 1: Booted from EEPROM 0: Booted from Micro MSYNC enable 1: MSYNC generated 0: MSYNC remains low MCLK frequency select 5 111: reserved 110: reserved 101: 4.096 MHz 100: 2.048 MHz 4 011: 1.024 MHz 010: 512 kHz 001: reserved 000: reserved 3 MCKEN MDIFS 2 1 -BOOT 0 MSEN DS612F4 87 CS5376A 23.2.2 GPCFG0 : 0x0E Figure 46. GPIO Configuration Register GPCFG0 (MSB) 23 GP_DIR7 22 GP_DIR6 21 GP_DIR5 20 GP_DIR4 19 GP_DIR3 18 GP_DIR2 17 GP_DIR1 16 GP_DIR0 DF Address: 0x0E R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 -R W R/W 15 GP_PULL7 14 GP_PULL6 13 GP_PULL5 12 GP_PULL4 11 GP_PULL3 10 GP_PULL2 9 GP_PULL1 8 GP_PULL0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Not defined; read as 0 Readable Writable Readable and Writable 7 GP_DATA7 6 GP_DATA6 5 GP_DATA5 4 GP_DATA4 3 GP_DATA3 2 GP_DATA2 1 GP_DATA1 (LSB) 0 GP_DATA0 Bits in bottom rows are reset condition R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit definitions: 23:16 GP_DIR [7:0] GPIO pin direction 1: Output 0: Input 15:8 GP_PULL GPIO pullup resistor [7:0] 1: Enabled 0: Disabled 7:0 GP_DATA GPIO data value [7:0] 1: VDD 0: GND Note: GPIO[4:0] also used as SPI 2 chip selects CS[4:0]. 88 DS612F4 CS5376A 23.2.3 GPCFG1 : 0x0F Figure 47. GPIO Configuration Register GPCFG1 (MSB) 23 22 21 20 19 GP_DIR11 18 GP_DIR10 17 GP_DIR9 16 GP_DIR8 -R/W 0 -R/W 0 -R/W 0 -R/W 0 DF Address: 0x0F R/W 0 R/W 0 R/W 0 R/W 0 -R W R/W 15 14 13 12 11 GP_PULL11 10 GP_PULL10 9 GP_PULL9 8 GP_PULL8 -R/W 0 -R/W 0 -R/W 0 -R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 GP_DATA11 2 GP_DATA10 1 GP_DATA9 (LSB) 0 GP_DATA8 Bits in bottom rows are reset condition -R/W 0 -R/W 0 -R/W 0 -R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 Bit definitions: 23:20 -19:16 GP_DIR [11:8] reserved GPIO pin direction 1: Output 0: Input 15:12 -11:8 reserved 7:4 3:0 -reserved GP_PULL GPIO pullup resistor [11:8] 1: Enabled 0: Disabled GP_DATA GPIO data value [11:8] 1: VDD 0: GND Note: GPIO11 also used as boot EEPROM chip select EECS. DS612F4 89 CS5376A 23.2.4 SPI2CTRL : 0x10 Figure 48. SPI 2 Control Register SPI2CTRL (MSB) 23 22 21 20 19 18 17 16 WOM R/W 0 SCKFS2 R/W 0 SCKFS1 R/W 1 SCKFS0 R/W 1 SPI2EN3 R/W 1 SPI2EN2 R/W 1 SPI2EN1 R/W 1 SPI2EN0 R/W 1 DF Address: 0x10 -R W R/W 15 14 13 12 11 10 9 8 RCH1 R/W 0 RCH0 R/W 0 D2SOP R 0 SCKPH R/W 0 SWEF R/W 0 SCKPO R/W 0 TM R/W 0 D2SREQ R/W 0 Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 Bits in bottom rows are reset condition. DNUM2 R/W 1 DNUM1 R/W 1 DNUM0 R/W 1 CS4 R/W 0 CS3 R/W 0 CS2 R/W 0 CS1 R/W 0 CS0 R/W 0 Bit definitions: 23 WOM 15:14 RCH Wired-or mode [1:0] 1: Enabled (open drain) 0: Disabled (push-pull) Read channel 11: SI4 10: SI3 01: SI2 00: SI1 Digital filter to SPI2 operation in progress flag SO output timing 1: Data becomes valid on first SCK2 edge 0: Data becomes valid before first SCK2 edge 7:5 DNUM [2:0] Number of bytes in serial transaction 22:20 SCKFS [2:0] SCK2 frequency select 111: reserved 110: reserved 101: 4.096 MHz 100: 2.048 MHz 011: 1.024 MHz 010: 512 kHz 001: 128 kHz 000: 32 kHz 13 D2SOP 4 CS4 Chip Select 4 Enable 12 SCKPH 3 2 CS3 CS2 Chip Select 3 Enable Chip Select 2 Enable 11 19:16 SPI2EN [3:0] SI[4:1] input enable 1111: All enabled 0000: All disabled 10 SWEF SCKPO SPI2 write collision flag 1 0 SCK2 data polarity 1: Valid on falling edge, transition on rising edge 0: Valid on rising edge, transition on falling edge SPI2 timeout flag 1: SPI2 timed out 0: not timed out CS1 CS0 Chip Select 1 Enable Chip Select 0 Enable 9 TM 8 D2SREQ Digital filter to SPI2 serial transaction request 1: Request operation 0: Operation complete (cleared by hardware) 90 DS612F4 CS5376A 23.2.5 SPI2CMD : 0x11 Figure 49. SPI 2 Command Register SPI2CMD (MSB) 23 22 21 20 19 18 17 16 DF Address: 0x11 -R/W 0 -R/W 0 -R/W 0 -R/W 0 -R/W 0 -R/W 0 -R/W 0 -R/W 0 -R W R/W 15 14 13 12 11 10 9 8 SCMD15 R/W 0 SCMD14 R/W 0 SCMD13 R/W 0 SCMD12 R/W 0 SCMD11 R/W 0 SCMD10 R/W 0 SCMD9 R/W 0 SCMD8 R/W 0 Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 Bits in bottom rows are reset condition SCMD7 R/W 0 SCMD6 R/W 0 SCMD5 R/W 0 SCMD4 R/W 0 SCMD3 R/W 0 SCMD2 R/W 0 SCMD1 R/W 0 SCMD0 R/W 0 Bit definitions: 23:16 -reserved 15:8 SCMD[15:8] SPI2 Upper Command 15:8 Byte SCMD[7:0] SPI2 Lower Command Byte DS612F4 91 CS5376A 23.2.6 SPI2DAT : 0x12 Figure 50. SPI 2 Data Register SPI2DAT (MSB) 23 22 21 20 19 18 17 16 DF Address: 0x12 SDAT23 R/W 0 SDAT22 R/W 0 SDAT21 R/W 0 SDAT20 R/W 0 SDAT19 R/W 0 SDAT18 R/W 0 SDAT17 R/W 0 SDAT16 R/W 0 -R W R/W 15 14 13 12 11 10 9 8 SDAT15 R/W 0 SDAT14 R/W 0 SDAT13 R/W 0 SDAT12 R/W 0 SDAT11 R/W 0 SDAT10 R/W 0 SDAT9 R/W 0 SDAT8 R/W 0 Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 Bits in bottom rows are reset condition SDAT7 R/W 0 SDAT6 R/W 0 SDAT5 R/W 0 SDAT4 R/W 0 SDAT3 R/W 0 SDAT2 R/W 0 SDAT1 R/W 0 SDAT0 R/W 0 Bit definitions: 23:16 SDAT[23:16] SPI2 Upper Data Byte 15:8 SDAT[15:8] SPI2 Middle Data Byte 15:8 SDAT[7:0] SPI2 Lower Data Byte 92 DS612F4 CS5376A 23.2.7 FILTCFG : 0x20 Figure 51. Filter Configuration Register FILTCFG (MSB) 23 22 21 20 19 18 17 16 DF Address: 0x20 -R/W 0 -R/W 0 -R/W 0 EXP4 R/W 0 EXP3 R/W 0 EXP2 R/W 0 EXP1 R/W 0 EXP0 R/W 0 -R W R/W 15 14 13 12 11 10 9 8 -R/W 0 ORCAL R/W 0 USEOR R/W 0 USEGR R/W 0 -R/W 0 FSEL2 R/W 0 FSEL1 R/W 0 FSEL0 R/W 0 Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 Bits in bottom rows are reset condition DEC3 R/W 0 DEC2 R/W 0 DEC1 R/W 0 DEC0 R/W 0 -R/W 0 -R/W 0 CH1 R/W 0 CH0 R/W 0 Bit definitions: 23:21 -reserved 15 14 -ORCAL reserved Run OFFSET calibration 1: Enable 0: Disable 7:4 DEC[3:0] Decimation selection (Output word rate) 0111: 0110: 0101: 0100: 0011: 0010: 0001: 0000: 1111: 1110: 1101: 1100: 1011: 1010: 1001: 1000: 3:2 -CH[1:0] 4000 SPS 2000 SPS 1000 SPS 500 SPS 333 SPS 250 SPS 200 SPS 125 SPS 100 SPS 50 SPS 40 SPS 25 SPS 20 SPS 10 SPS 5 SPS 1 SPS 20:16 EXP[4:0] OFFSET calibration exponent 13 USEOR Use OFFSET correction 1: Enable 0: Disable 12 USEGR Use GAIN correction 1: Enable 0: Disable 11 10:8 -- reserved reserved Channel Enable 11: 3 Channel (1, 2, 3) 10: 2 Channel (1, 2) 01: 1 Channel (1 only) 00: 4 Channel (1, 2, 3, 4) FSEL[2:0] Output filter stage select 1:0 111: reserved 110: reserved 101: IIR 3rd Order 100: IIR 2nd Order 011: IIR 1st Order 010: FIR2 Output 001: FIR1 Output 000: SINC Output DS612F4 93 CS5376A 23.2.8 GAIN1 - GAIN4 : 0x21 - 0x24 Figure 52. Gain Correction Register GAIN1 (MSB) 23 22 21 20 19 18 17 16 DF Address: 0x21 GAIN23 R/W 0 GAIN22 R/W 0 GAIN21 R/W 0 GAIN20 R/W 0 GAIN19 R/W 0 GAIN18 R/W 0 GAIN17 R/W 0 GAIN16 R/W 0 -R W R/W 15 14 13 12 11 10 9 8 GAIN15 R/W 0 GAIN14 R/W 0 GAIN13 R/W 0 GAIN12 R/W 0 GAIN11 R/W 0 GAIN10 R/W 0 GAIN9 R/W 0 GAIN8 R/W 0 Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 Bits in bottom rows are reset condition GAIN7 R/W 0 GAIN6 R/W 0 GAIN5 R/W 0 GAIN4 R/W 0 GAIN3 R/W 0 GAIN2 R/W 0 GAIN1 R/W 0 GAIN0 R/W 0 Bit definitions: 23:16 GAIN[23:16] Gain Correction Upper Byte 15:8 GAIN[15:8] Gain Correction Middle Byte 15:8 GAIN[7:0] Gain Correction Lower Byte 94 DS612F4 CS5376A 23.2.9 OFFSET1 - OFFSET4 : 0x25 - 0x28 Figure 53. Offset Correction Register OFFSET1 (MSB) 23 22 21 20 19 18 17 16 DF Address: 0x25 OFST23 R/W 0 OFST22 R/W 0 OFST21 R/W 0 OFST20 R/W 0 OFST19 R/W 0 OFST18 R/W 0 OFST17 R/W 0 OFST16 R/W 0 -R W R/W 15 14 13 12 11 10 9 8 OFST15 R/W 0 OFST14 R/W 0 OFST13 R/W 0 OFST12 R/W 0 OFST11 R/W 0 OFST10 R/W 0 OFST9 R/W 0 OFST8 R/W 0 Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 Bits in bottom rows are reset condition OFST7 R/W 0 OFST6 R/W 0 OFST5 R/W 0 OFST4 R/W 0 OFST3 R/W 0 OFST2 R/W 0 OFST1 R/W 0 OFST0 R/W 0 Bit definitions: 23:16 OFST[23:16] Offset Correction Upper Byte 15:8 OFST[15:8] Offset Correction Middle Byte 15:8 OFST[7:0] Offset Correction Lower Byte DS612F4 95 CS5376A 23.2.10 TIMEBRK : 0x29 Figure 54. Time Break Counter Register TIMEBRK (MSB) 23 22 21 20 19 18 17 16 DF Address: 0x29 TBRK23 R/W 0 TBRK22 R/W 0 TBRK21 R/W 0 TBRK20 R/W 0 TBRK19 R/W 0 TBRK18 R/W 0 TBRK17 R/W 0 TBRK16 R/W 0 -R W R/W 15 14 13 12 11 10 9 8 TBRK15 R/W 0 TBRK14 R/W 0 TBRK13 R/W 0 TBRK12 R/W 0 TBRK11 R/W 0 TBRK10 R/W 0 TBRK9 R/W 0 TBRK8 R/W 0 Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 Bits in bottom rows are reset condition TBRK7 R/W 0 TBRK6 R/W 0 TBRK5 R/W 0 TBRK4 R/W 0 TBRK3 R/W 0 TBRK2 R/W 0 TBRK1 R/W 0 TBRK0 R/W 0 Bit definitions: 23:16 TBRK[23:16] Time Break Counter 15:8 Upper Byte TBRK[15:8] Time Break Counter 15:8 Middle Byte TBRK[7:0] Time Break Counter Lower Byte 96 DS612F4 CS5376A 23.2.11 TBSCFG : 0x2A Figure 55. Test Bit Stream Configuration Register TBSCFG (MSB) 23 22 21 20 19 18 17 16 DF Address: 0x2A INTP7 R/W 0 INTP6 R/W 0 INTP5 R/W 0 INTP4 R/W 0 INTP3 R/W 0 INTP2 R/W 0 INTP1 R/W 0 INTP0 R/W 0 -R W R/W 15 14 13 12 11 10 9 8 -R/W 0 RATE2 R/W 0 RATE1 R/W 0 RATE0 R/W 0 TSYNC R/W 0 CDLY2 R/W 0 CDLY1 R/W 0 CDLY0 R/W 0 Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 Bits in bottom rows are reset condition LOOP R/W 0 RUN R/W 0 DDLY5 R/W 0 DDLY4 R/W 0 DDLY3 R/W 0 DDLY2 R/W 0 DDLY1 R/W 0 DDLY0 R/W 0 Bit definitions: 23:16 INTP[7:0] Interpolation factor 0xFF: 256 0xFE: 255 ... 0x01: 2 0x00: 1 (use once) 15 -Reserved 7 LOOP Loopback TBSDATA output to MDATA inputs 1: Enabled 0: Disabled Run Test Bit Stream 1: Enabled 0: Disabled 14:12 RATE[2:0] TBSDATA and TBSCLK output rate. 111: 2.048 MHz 110: 1.024 MHz 101: 512 kHz 100: 256 kHz 011: 128 kHz 010: 64 kHz 001: 32 kHz 000: 4 kHz Synchronization 1: Sync enabled 0: No sync TBSCLK output phase delay 111: 7/8 period 110: 3/4 period 101: 5/8 period 100: 1/2 period 011: 3/8 period 010: 1/4 period 001: 1/8 period 000: none 6 RUN 11 TSYNC 10:8 CDLY[2:0] 5:0 DDLY[5:0] TBSDATA output delay 0x3F: 63 bits 0x3E: 62 bits ... 0x01: 1 bit 0x00: 0 bits ( no delay) DS612F4 97 CS5376A 23.2.12 TBSGAIN : 0x2B Figure 56. Test Bit Stream Gain Register TBSGAIN (MSB) 23 22 21 20 19 18 17 16 DF Address: 0x2B TGAIN23 R/W 0 TGAIN22 R/W 0 TGAIN21 R/W 0 TGAIN20 R/W 0 TGAIN19 R/W 0 TGAIN18 R/W 0 TGAIN17 R/W 0 TGAIN16 R/W 0 -R W R/W 15 14 13 12 11 10 9 8 TGAIN15 R/W 0 TGAIN14 R/W 0 TGAIN13 R/W 0 TGAIN12 R/W 0 TGAIN11 R/W 0 TGAIN10 R/W 0 TGAIN9 R/W 0 TGAIN8 R/W 0 Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 Bits in bottom rows are reset condition TGAIN7 R/W 0 TGAIN6 R/W 0 TGAIN5 R/W 0 TGAIN4 R/W 0 TGAIN3 R/W 0 TGAIN2 R/W 0 TGAIN1 R/W 0 TGAIN0 R/W 0 Bit definitions: 23:16 TGAIN[23:16] Test Bit Stream Gain 15:8 Upper Byte TGAIN[15:8] Test Bit Stream Gain Middle Byte 15:8 TGAIN[7:0] Test Bit Stream Gain Lower Byte 98 DS612F4 CS5376A 23.2.13 SYSTEM1, SYSTEM2 : 0x2C, 0x2D Figure 57. User Defined System Register SYSTEM1 (MSB) 23 22 21 20 19 18 17 16 DF Address: 0x2C SYS23 R/W 0 SYS22 R/W 0 SYS21 R/W 0 SYS20 R/W 0 SYS19 R/W 0 SYS18 R/W 0 SYS17 R/W 0 SYS16 R/W 0 -R W R/W 15 14 13 12 11 10 9 8 SYS15 R/W 0 SYS14 R/W 0 SYS13 R/W 0 SYS12 R/W 0 SYS11 R/W 0 SYS10 R/W 0 SYS9 R/W 0 SYS8 R/W 0 Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 Bits in bottom rows are reset condition SYS7 R/W 0 SYS6 R/W 0 SYS5 R/W 0 SYS4 R/W 0 SYS3 R/W 0 SYS2 R/W 0 SYS1 R/W 0 SYS0 R/W 0 Bit definitions: 23:16 SYS[23:16] System Register Upper Byte 15:8 SYS[15:8] System Register Middle Byte 15:8 SYS[7:0] System Register Lower Byte DS612F4 99 CS5376A 23.2.14 VERSION : 0x2E Figure 58. Hardware Version ID Register VERSION (MSB) 23 22 21 20 19 18 17 16 DF Address: 0x2E TYPE7 R/W 0 TYPE6 R/W 1 TYPE5 R/W 1 TYPE4 R/W 1 TYPE3 R/W 0 TYPE2 R/W 1 TYPE1 R/W 1 TYPE0 R/W 0 -R W R/W 15 14 13 12 11 10 9 8 HW7 R/W 0 HW6 R/W 0 HW5 R/W 0 HW4 R/W 0 HW3 R/W 0 HW2 R/W 0 HW1 R/W 1 HW0 R/W 1 Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 Bits in bottom rows are reset condition ROM7 R/W 0 ROM6 R/W 0 ROM5 R/W 0 ROM4 R/W 0 ROM3 R/W 0 ROM2 R/W 0 ROM1 R/W 1 ROM0 R/W 1 Bit definitions: 23:16 TYPE [7:0] Chip Type 15:8 76 - CS5376, CS5376A HW [7:0] Hardware Revision 01 - CS5376 Rev A 02 - CS5376 Rev B 03 - CS5376A Rev A 7:4 ROM [7:0] ROM Version 01 - Ver 1.0 02 - Ver 2.0 03 - Ver 3.0 100 DS612F4 CS5376A 23.2.15 SELFTEST : 0x2F Figure 59. Self Test Result Register SELFTEST (MSB) 23 22 21 20 19 18 17 16 DF Address: 0x2F -R/W 0 -R/W 0 -R/W 0 -R/W 0 EU3 R/W 1 EU2 R/W 0 EU1 R/W 1 EU0 R/W 0 -R W R/W 15 14 13 12 11 10 9 8 DRAM3 R/W 1 DRAM2 R/W 0 DRAM1 R/W 1 DRAM0 R/W 0 PRAM3 R/W 1 PRAM2 R/W 0 PRAM1 R/W 1 PRAM0 R/W 0 Not defined; read as 0 Readable Writable Readable and Writable 7 6 5 4 3 2 1 (LSB) 0 Bits in bottom rows are reset condition DROM3 R/W 1 DROM2 R/W 0 DROM1 R/W 1 DROM0 R/W 0 PROM3 R/W 1 PROM2 R/W 0 PROM1 R/W 1 PROM0 R/W 0 Bit definitions: 23:20 -reserved 15:12 DRAM [3:0] Data RAM Test ‘A’: Pass ‘F’: Fail Program RAM Test ‘A’: Pass ‘F’: Fail 7:4 DROM [3:0] Data ROM Test ‘A’: Pass ‘F’: Fail Program ROM Test ‘A’: Pass ‘F’: Fail 19:16 EU [3:0] Execution Unit Test ‘A’: Pass ‘F’: Fail 11:8 PRAM [3:0] 3:0 PROM [3:0] DS612F4 101 CS5376A 24.PIN DESCRIPTIONS TIMEB CLK SYNC SDDAT SDRDY SDCLK SDTKO SDTKI TRST TMS TCK TDI TDO GND VD TBSCLK TBSDATA DNC VDD2 MCLK/2 MCLK MSYNC MDATA4 MFLAG4 MDATA3 MFLAG3 MDATA2 MFLAG2 MDATA1 MFLAG1 GND GND2 BOOT RESET VDD1 GND1 SINT MOSI MISO SSI SCK1 SSO GPIO11:EECS GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 VD GND GND2 GPIO5 GPIO4:CS4 GPIO3:CS3 GPIO2:CS2 GPIO1:CS1 GPIO0:CS0 SCK2 SO SI1 SI2 SI3 SI4 VDD2 64 63 62 61 60 59 58 5756 55 54 53 52 51 50 49 1 48 47 2 3 46 45 4 5 44 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 2425 26 2728 29 30 3132 64-PIN TQFP CS5376A DS612F4 102 CS5376A Pin Name Pin Number 1 2 3 4 5 8 9 10 12 13 14 15, 17, 19, 21 16, 18, 20, 22 26, 27, 28, 29 30 31 32, 33, 34, 35, 36 37, 41, 42, 43, 44, 45 46 47 48 49 50 51 52 Pin Type JTAG port Input Input Input Input Output Test Bit Stream Output Output No Connect N/A Modulator Interface Output Output Output Input Input Serial Peripheral Interface 2 Input Output Output General Purpose Input / Output Input / Output Input / Output Input / Output Output Input / Output Input Input / Output Input / Output Output Reset Control Pin Description JTAG reset, active low. Connect to GND if JTAG is not used. JTAG test mode select. JTAG clock input. JTAG data input. JTAG data output. Test bit stream clock output. Test bit stream data output. Do not connect. Modulator clock output, half rate. Modulator clock output, full rate. Modulator sync output. Modulator data inputs. Modulator flag inputs. SPI 2 data inputs. SPI 2 data output. SPI 2 clock output. General Purpose I/O with SPI 2 chip selects. General Purpose I/O. General Purpose I/O with boot EEPROM chip select. SPI 1 slave select output, active low. SPI 1 serial clock input / output. SPI 1 slave select input, active low. SPI 1 data, master in / slave out. Open drain output requiring a 10 kΩ pull-up. SPI 1 data, master out / slave in. SPI 1 serial interrupt output, active low. TRST TMS TCK TDI TDO TBSCLK TBSDATA DNC MCLK/2 MCLK MSYNC MDATA[4:1] MFLAG[4:1] SI[4:1] SO SCK2 GPIO[0:4]:CS[0:4] GPIO[5:10] GPIO11:EECS Serial Peripheral Interface 1 SSO SCK1 SSI MISO MOSI SINT RESET BOOT TIMEB 55 56 57 Input Input Time Break Input Reset, active low. Boot mode select. Time break input. DS612F4 103 CS5376A Pin Name Pin Number Pin Type Clock and Synchronization CLK SYNC SDDAT SDRDY SDCLK SDTKO SDTKI VDD1 VDD2 VD GND1, GND2, GND 58 59 60 61 62 63 64 54 11, 25 7, 40 6, 23, 24, 38, 39, 53 Input Input Serial Data Port Output Output Input Output Input Power Supplies Supply Supply Supply Supply Pin power supply for pins 1 - 5 and 41 - 64. Pin power supplies for pins 8 - 37. Logic core power supplies. Digital grounds. SD port data output. SD port data ready, active low. Open drain output requiring a 10 kΩ pull-up. SD port clock input. SD port token output. SD port token input. Clock input, nominal 32.768 MHz. Sync input. Pin Description 104 DS612F4 CS5376A 25.PACKAGE DIMENSIONS 64L TQFP PACKAGE DRAWING E E1 D D1 1 e ∝ B A A1 L DIM A A1 B D D1 E E1 e* L µ INCHES MILLIMETERS MIN MAX MIN MAX --0.063 --1.60 0.002 0.006 0.05 0.15 0.007 0.011 0.17 0.27 0.461 0.484 11.70 12.30 0.390 0.398 9.90 10.10 0.461 0.484 11.70 12.30 0.390 0.398 9.90 10.10 0.016 0.024 0.40 0.60 0.018 0.030 0.45 0.75 0.000° 7.000° 0.00° 7.00° * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026 DS612F4 105 CS5376A 26.ORDERING INFORMATION Model Temperature Package CS5376A-IQ -40 to +85 °C CS5376A-IQZ Lead Free 64-pin TQFP 27.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp 240 °C 250 °C 3 7 Days MSL Rating* Max Floor Life CS5376A-IQ CS5376A-IQZ Lead Free * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 28.REVISION HISTORY Revision Date Changes PP1 F1 F2 F3 F4 SEP 2003 FEB 2004 AUG 2005 SEP 2005 SEP 2008 Initial “Preliminary Product” release. Update group delay, power consumption and MISO read timing. Add TBS impulse data and MISO pull-up. Updated ordering information. Added MSL data. Added lead-free device ordering information. Update Total-S part numbers. Remove TBS impulse mode. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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