CS53L21

CS53L21 Low Power, Stereo Analog to Digital Converter FEATURES 98 dB Dynamic Range (A-wtd) -88 dB THD+N Analog Gain Controls – +32 dB or +16 dB MIC Pre-Amplifiers – Analog Programmable Gain Amplifier (PGA) SYSTEM FEATURES 24-bit Conversion 4 kHz to 96 kHz Sample Rate Multi-bit Delta Sigma Architecture Low Power Operation – Stereo Record (ADC): 8.72 mW @ 1.8 V – Stereo Record (MIC to PGA and ADC): 13.73 mW @ 1.8 V +20 dB Digital Boost Programmable Automatic Level Control (ALC) – Noise Gate for Noise Suppression – Programmable Threshold and Attack/Release Rates Variable Power Supplies – 1.8 V to 2.5 V Digital & Analog – 1.8 V to 3.3 V Interface Logic Independent Left/Right Channel Control Digital Volume Control High-Pass Filter Disable for DC Measurements Stereo 3:1 Analog Input MUX Dual MIC Inputs – Programmable, Low Noise MIC Bias Levels – Differential MIC Mix for Common Mode Noise Rejection Power Down Management – ADC, MIC Pre-Amplifier, PGA Software Mode (I²C® & SPI™ Control) Hardware Mode (Stand-Alone Control) Flexible Clocking Options – Master or Slave Operation Digital Routing Mixes – Mono Mixes Very Low 64 Fs Oversampling Clock Reduces Power Consumption 1.8 V to 3.3 V 1.8 V to 2.5 V PCM Serial Interface Hardware Mode or I2C & SPI Software Mode Control Data Level Translator Digital Signal Processing Engine ALC Multibit Oversampling ADC Multibit Oversampling ADC MUX PGA MUX +32 dB Stereo Input 1 Stereo Input 2 Stereo Input 3 / Mic Input 1 & 2 Reset Volume Controls High Pass Filters Register Configuration MUX PGA +32 dB Serial Audio Output ALC MIC Bias Preliminary Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) MAY ‘06 DS700PP1 CS53L21 APPLICATIONS Portable Audio Players Digital Microphones Digital Voice Recorders Voice Recognition Systems Audio/Video Capture Cards GENERAL DESCRIPTION The CS53L21 is a highly integrated, 24-bit, 96 kHz, low power stereo A/D. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment between 4 kHz and 96 kHz. The ADC offers many features suitable for low power, portable system applications. The ADC input path allows independent channel control of a number of features. An input multiplexer selects between line-level or microphone-level inputs for each channel. The microphone input path includes a selectable programmable-gain pre-amplifier stage and a low noise MIC bias voltage supply. A PGA is available for line or microphone inputs and provides analog gain with soft ramp and zero cross transitions. The ADC also features a digital volume attenuator with soft ramp transitions. A programmable ALC and Noise Gate monitor the input signals and adjust the volume levels appropriately. The Signal Processing Engine (SPE) controls left/right channel volume mixing, channel swap and channel mute functions. All volume-level changes may be configured to occur on soft ramp and zero cross transitions. The CS53L21 is available in a 32-pin QFN package in both Commercial (-10 to +70° C) and Automotive grades (-40 to +85° C). The CDB53L21 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 63 for complete details. In addition to its many features, the CS53L21 operates from a low-voltage analog and digital core, making this A/D ideal for portable systems that require extremely low power consumption in a minimal amount of space. 2 DS700PP1 CS53L21 TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6 1.1 Digital I/O Pin Characteristics ........................................................................................................... 8 2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9 3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 11 SPECIFIED OPERATING CONDITIONS ............................................................................................. 11 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 11 ANALOG CHARACTERISTICS (COMMERCIAL - CNZ) .................................................................... 12 ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ) ..................................................................... 13 ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 14 SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 14 SWITCHING SPECIFICATIONS - I²C CONTROL PORT ..................................................................... 16 SWITCHING CHARACTERISTICS - SPI CONTROL PORT ................................................................ 17 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 18 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 18 POWER CONSUMPTION .................................................................................................................... 19 4. APPLICATIONS ................................................................................................................................... 20 4.1 Overview ......................................................................................................................................... 20 4.1.1 Architecture ........................................................................................................................... 20 4.1.2 Line & MIC Inputs .................................................................................................................. 20 4.1.3 Signal Processing Engine ..................................................................................................... 20 4.1.4 Device Control (Hardware or Software Mode) ...................................................................... 20 4.1.5 Power Management .............................................................................................................. 20 4.2 Hardware Mode .............................................................................................................................. 21 4.3 Analog Inputs ................................................................................................................................. 22 4.3.1 Digital Code, Offset & DC Measurement ............................................................................... 22 4.3.2 High-Pass Filter and DC Offset Calibration ........................................................................... 23 4.3.3 Digital Routing ....................................................................................................................... 23 4.3.4 Differential Inputs .................................................................................................................. 23 4.3.4.1 External Passive Components ................................................................................... 23 4.3.5 Analog Input Multiplexer ........................................................................................................ 25 4.3.6 MIC & PGA Gain ................................................................................................................... 25 4.3.7 Automatic Level Control (ALC) .............................................................................................. 26 4.3.8 Noise Gate ............................................................................................................................ 27 4.4 Signal Processing Engine ............................................................................................................... 28 4.4.1 Volume Controls .................................................................................................................... 28 4.4.2 Mono Channel Mixer ............................................................................................................. 28 4.5 Serial Port Clocking ........................................................................................................................ 29 4.5.1 Slave ..................................................................................................................................... 30 4.5.2 Master ................................................................................................................................... 30 4.5.3 High-Impedance Digital Output ............................................................................................. 31 4.5.4 Quarter- and Half-Speed Mode ............................................................................................. 31 4.6 Digital Interface Formats ................................................................................................................ 31 4.7 Initialization ..................................................................................................................................... 32 4.8 Recommended Power-Up Sequence ............................................................................................. 32 4.9 Recommended Power-Down Sequence ........................................................................................ 33 4.10 Software Mode ............................................................................................................................. 34 4.10.1 SPI Control .......................................................................................................................... 34 4.10.2 I²C Control ........................................................................................................................... 34 4.10.3 Memory Address Pointer (MAP) .......................................................................................... 36 4.10.3.1 Map Increment (INCR) ............................................................................................. 36 5. REGISTER QUICK REFERENCE ........................................................................................................ 37 6. REGISTER DESCRIPTION .................................................................................................................. 40 DS700PP1 3 CS53L21 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 40 6.2 Power Control 1 (Address 02h) ...................................................................................................... 40 6.3 MIC Power Control & Speed Control (Address 03h) ...................................................................... 41 6.4 Interface Control (Address 04h) ..................................................................................................... 43 6.5 MIC Control (Address 05h) ............................................................................................................. 44 6.6 ADC Control (Address 06h) ............................................................................................................ 45 6.7 ADCx Input Select, Invert & Mute (Address 07h) ........................................................................... 47 6.8 SPE Control (Address 09h) ............................................................................................................ 48 6.9 ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) ................. 49 6.10 ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh) ................................................ 50 6.11 ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh) .............................. 51 6.12 Channel Mixer (Address 18h) ....................................................................................................... 51 6.13 ALC Enable & Attack Rate (Address 1Ch) ................................................................................... 52 6.14 ALC Release Rate (Address 1Dh) ................................................................................................ 52 6.15 ALC Threshold (Address 1Eh) ...................................................................................................... 53 6.16 Noise Gate Configuration & Misc. (Address 1Fh) ......................................................................... 54 6.17 Status (Address 20h) (Read Only) ............................................................................................... 55 7. ANALOG PERFORMANCE PLOTS .................................................................................................... 56 7.1 ADC_FILT+ Capacitor Effects on THD+N ...................................................................................... 56 8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 57 8.1 Auto Detect Enabled ....................................................................................................................... 57 8.2 Auto Detect Disabled ...................................................................................................................... 58 9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 59 9.1 Power Supply, Grounding ............................................................................................................... 59 9.2 QFN Thermal Pad .......................................................................................................................... 59 10. DIGITAL FILTERS .............................................................................................................................. 60 11. PARAMETER DEFINITIONS .............................................................................................................. 61 12. PACKAGE DIMENSIONS ................................................................................................................. 62 THERMAL CHARACTERISTICS .......................................................................................................... 62 13. ORDERING INFORMATION ............................................................................................................. 63 14. REFERENCES .................................................................................................................................... 63 15. REVISION HISTORY ......................................................................................................................... 64 LIST OF FIGURES Figure 1.Typical Connection Diagram (Software Mode) ............................................................................. 9 Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 10 Figure 3.Serial Audio Interface Slave Mode Timing .................................................................................. 15 Figure 4.Serial Audio Interface Master Mode Timing ................................................................................ 15 Figure 5.Control Port Timing - I²C ............................................................................................................. 16 Figure 6.Control Port Timing - SPI Format ................................................................................................ 17 Figure 7.Analog Input Architecture ............................................................................................................ 22 Figure 8.MIC Input Mix w/Common Mode Rejection ................................................................................. 24 Figure 9.Differential Input .......................................................................................................................... 24 Figure 10.ALC ........................................................................................................................................... 26 Figure 11.Noise Gate Attenuation ............................................................................................................. 27 Figure 12.Signal Processing Engine ......................................................................................................... 28 Figure 13.Master Mode Timing ................................................................................................................. 30 Figure 14.Tri-State Serial Port .................................................................................................................. 31 Figure 15.I²S Format ................................................................................................................................. 31 Figure 16.Left-Justified Format ................................................................................................................. 32 Figure 17.Initialization Flow Chart ............................................................................................................. 33 Figure 18.Control Port Timing in SPI Mode .............................................................................................. 34 Figure 19.Control Port Timing, I²C Write ................................................................................................... 35 Figure 20.Control Port Timing, I²C Read ................................................................................................... 35 4 DS700PP1 CS53L21 Figure 21.AIN & PGA Selection ................................................................................................................ 47 Figure 22.ADC THD+N vs. Frequency w/Capacitor Effects ...................................................................... 56 Figure 23.ADC Passband Ripple .............................................................................................................. 60 Figure 24.ADC Stopband Rejection .......................................................................................................... 60 Figure 25.ADC Transition Band ................................................................................................................ 60 Figure 26.ADC Transition Band Detail ...................................................................................................... 60 LIST OF TABLES Table 1. I/O Power Rails ............................................................................................................................. 8 Table 2. Hardware Mode Feature Summary ............................................................................................. 21 Table 3. MCLK/LRCK Ratios .................................................................................................................... 30 DS700PP1 5 CS53L21 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE SDOUT (M/S) DGND MCLK TSTN SCLK VD 32 31 30 29 28 27 VL 26 LRCK SDA/CDIN (MCLKDIV2) SCL/CCLK (I²S/LJ) AD0/CS (TSTN) VA_PULLUP TSTO AGND TSTO RESET 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 AIN1B AIN1A AFILTB AFILTA AIN2B/BIAS AIN2A MICIN2/BIAS/AIN3B MICIN1/AIN3A CS53L21 21 20 19 18 17 AGND TSTO Pin Name LRCK SDA/CDIN (MCLKDIV2) SCL/CCLK (I²S/LJ) # 1 Pin Description Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the control port interface in SPI Mode. MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry. Serial Control Port Clock (Input) - Serial clock for the serial control port. 2 3 Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interface formats for the ADC. Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS is the chip-select signal for SPI format. Test In (Input) - Hardware Mode: This pin is an input used for test purposes only and should be tied to DGND for normal operation. Reference Pull-up (Input) - This pin is an input used for test purposes only and must be pulled-up to VA using a 47 kΩ resistor. Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no connection external to the pin). Analog Ground (Input) - Ground reference for the internal analog section. Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no connection external to the pin). AD0/CS (TSTN) 4 VA_PULLUP TSTO AGND TSTO 5 6 7 8 6 TSTO FILT+ NIC NIC VA VQ DS700PP1 CS53L21 TSTO NIC NIC VA AGND TSTO VQ FILT+ MICIN1/ AIN3A MICIN2/ BIAS/AIN3B AIN2A AIN2B/BIAS AFILTA AFILTB AIN1A AIN1B RESET VL VD DGND SDOUT (M/S) MCLK SCLK TSTN Thermal Pad 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no connection external to the pin). .Not Internally Connected - This pin is not connected internal to the device and may be connected to ground or left “floating”. No other external connection should be made to this pin. Analog Power (Input) - Positive power for the internal analog section. Analog Ground (Input) - Ground reference for the internal analog section. Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no connection external to the pin). Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Microphone Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Microphone Input 2 (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specification table. This pin can also be configured as an output to provide a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table. Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Analog Input (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specification table. This pin can also be configured as an output to provide a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table. Filter Connection (Output) - Filter connection for the ADC inputs. Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Reset (Input) - The device enters a low power mode when this pin is driven low. Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and host control port. Refer to the Recommended Operating Conditions for appropriate voltages. Digital Power (Input) - Positive power for the internal digital section. Digital Ground (Input) - Ground reference for the internal digital section. Serial Audio Data Output (Output) - Output for two’s complement serial audio data. Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between Master and Slave Mode for the serial port. Master Clock (Input) - Clock source for the delta-sigma modulators. Serial Clock (Input/Output) -- Serial clock for the serial audio interface. Test In (Input) - This pin is an input used for test purposes only and should be tied to DGND for normal operation. Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page 59. DS700PP1 7 CS53L21 1.1 Digital I/O Pin Characteristics The logic level for each input should not exceed the maximum ratings for the VL power supply. Pin Name SW/(HW) RESET SCL/CCLK (I²S/LJ) SDA/CDIN (MCLKDIV2) AD0/CS (DEM) MCLK LRCK SCLK SDOUT (M/S) I/O Input Input Input/Output Input Input Input/Output Input/Output Input/Output Driver 1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V, CMOS Table 1. I/O Power Rails Receiver 1.8 V - 3.3 V 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 8 DS700PP1 CS53L21 2. TYPICAL CONNECTION DIAGRAMS +1.8 V or +2.5 V 1 µF 0.1 µF See Note 4 0.1 µF 47 kΩ +1.8 V or +2.5 V 1 µF Note 4: Series resistance in the path of the power supplies must be avoided. VD VA VA_ PULLUP CS53L21 AIN1A TSTN 1800 pF 1800 pF * * 1 µF 100 Ω Left Analog Input 1 100 kΩ 100 kΩ MCLK SCLK LRCK Digital Audio Processor SDOUT RESET SCL/CCLK SDA/CDIN AD0/CS AIN1B 1 µF 100 Ω Right Analog Input 1 Left Analog Input 2 100 kΩ 100 kΩ AIN2A 1800 pF 1800 pF * 1 µF * 1 µF 100 Ω AIN2B BIAS1 MICIN1 AIN3A BIAS2 AIN3B/MICIN2 100 Ω Right Analog Input 2 Microphone Input 1 µF 100 kΩ Microphone Bias 0.1 µF RL See Note 3 2k Ω 2k Ω +1.8 V, +2.5 V or +3.3 V See Note 1 0.1 µF Note 3: The value of R L is dictated by the microphone cartridge. VL FILT+ Note 1: Resistors are required for I²C control port operation AGND * * 150 pF 150 pF 10 µF AFILTA AFILTB VQ DGND 1 µF * Capacitors must be C0G or equivalent Figure 1. Typical Connection Diagram (Software Mode) DS700PP1 9 CS53L21 +1.8V or +2.5V 1 µF 0.1 µF See Note 4 0.1 µF 47 kΩ +1.8V or +2.5V VD VA VA_ PULLUP Note 4: Series resistance in the path of the power supplies (typically used for added filtering) must be avoided. CS53L21 TSTN MCLK SCLK LRCK VL or DGND (1) AIN1A SDOUT/ M/S RESET I²S/LJ MCLKDIV2 FILT+ 1800 pF * 1 µF 100 Ω 1800 pF * 100 Ω 1 µF Left Analog Input 1 100 kΩ 100 kΩ Digital Audio Processor AIN1B Right Analog Input 1 AGND * * 150 pF 150 pF 10 µF +1.8V, 2.5 V or +3.3V VL 0.1 µF AFILTA AFILTB VQ DGND 1 µF * Capacitors must be C0G or equivalent (1) Pull-up to VL (47 kΩ ≤ Master Mode. for Pull-down to DGND for Slave Mode. Figure 2. Typical Connection Diagram (Hardware Mode) 10 DS700PP1 CS53L21 3. CHARACTERISTIC AND SPECIFICATION TABLES (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0 V, all voltages with respect to ground.) Parameters DC Power Supply (Note 1) Analog Core Digital Core Serial/Control Port Interface Ambient Temperature Commercial - CNZ Automotive - DNZ VA VD VL TA 1.65 2.37 1.65 2.37 1.65 2.37 3.14 -10 -40 1.8 2.5 1.8 2.5 1.8 2.5 3.3 1.89 2.63 1.89 2.63 1.89 2.63 3.47 +70 +85 V V V V V V V °C °C Symbol Min Nom Max Units ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Analog Digital Serial/Control Port Interface (Note 2) (Note 3) Symbol VA VD VL Iin Min -0.3 -0.3 -0.3 AGND-0.7 -0.3 -50 -65 Max 3.0 3.0 4.0 ±10 VA+0.7 VL+ 0.4 +115 +150 Units V V V mA Input Current Analog Input Voltage Digital Input Voltage (Note 3) Ambient Operating Temperature (power applied) Storage Temperature VIN VIND TA Tstg V V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. The device will operate properly over the full range of the analog, digital core and serial/control port interface supplies. 2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current. DS700PP1 11 CS53L21 ANALOG CHARACTERISTICS (COMMERCIAL - CNZ) (Test Conditions (unless otherwise specified): Input sine wave (relative to digital full scale): 1 kHz through passive input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz) VA = 2.5 V (nominal) Min Typ Max A-weighted unweighted -1 dBFS -20 dBFS -60 dBFS 93 90 99 96 -86 -76 -36 -80 - Parameter (Note 4) VA = 1.8 V (nominal) Min Typ Max 90 87 96 93 -84 -73 -33 -78 - Unit dB dB dB dB dB Analog In to ADC (PGA bypassed) Dynamic Range Total Harmonic Distortion + Noise Analog In to PGA to ADC Dynamic Range PGA Setting: 0 dB PGA Setting: +12 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB PGA Setting: +12 dB -1 dBFS -60 dBFS -1 dBFS -88 -35 -85 -81 -79 -86 -32 -83 -80 -77 dB dB dB A-weighted unweighted A-weighted unweighted 92 89 85 82 98 95 91 88 89 86 82 79 95 92 88 85 dB dB dB dB Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC Dynamic Range PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -76 -74 dB A-weighted unweighted 86 83 83 80 dB dB Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC Dynamic Range PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -74 -71 dB A-weighted unweighted 78 74 75 71 dB dB Other Characteristics DC Accuracy Interchannel Gain Mismatch Gain Drift Offset Error Input Interchannel Isolation Full-scale Input Voltage ADC 0.74•VA PGA (0 dB) 0.75•VA MIC (+16 dB) MIC (+32 dB) ADC PGA MIC 90 0.78•VA 0.82•VA 0.794•VA 0.83•VA 0.129•VA 0.022•VA 20 39 50 0.74•VA 0.75•VA 90 0.78•VA 0.794•VA 0.129•VA 0.022•VA 20 39 50 0.82•VA 0.83•VA dB Vpp Vpp Vpp Vpp kΩ kΩ kΩ SDOUT Code with HPF On 0.2 ±100 352 0.2 ±100 352 dB ppm/°C LSB Input Impedance (Note 5) - - 12 DS700PP1 CS53L21 ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ) (Test Conditions (unless otherwise specified): Input sine wave (relative to full scale): 1 kHz through passive input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz) Parameter (Note 4) VA = 2.5 V (nominal) Min Typ Max A-weighted unweighted -1 dBFS -20 dBFS -60 dBFS 91 78 99 96 -86 -76 -36 -78 - VA = 1.8 V (nominal) Min Typ Max 88 85 96 93 -84 -73 -33 -76 - Unit dB dB dB dB dB Analog In to ADC Dynamic Range Total Harmonic Distortion + Noise Analog In to PGA to ADC Dynamic Range PGA Setting: 0 dB PGA Setting: +12 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB PGA Setting: +12 dB -1 dBFS -60 dBFS -1 dBFS -88 -35 -85 -80 -77 -86 -32 -83 -78 -75 dB dB dB A-weighted unweighted A-weighted unweighted 90 87 83 80 98 95 91 88 87 84 80 77 95 92 88 85 dB dB dB dB Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC Dynamic Range PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -76 -74 dB A-weighted unweighted 86 83 83 80 dB dB Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC Dynamic Range PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -74 -71 dB A-weighted unweighted 78 74 75 71 dB dB Other Characteristics DC Accuracy Interchannel Gain Mismatch Gain Drift Offset Error Input Interchannel Isolation Full-scale Input Voltage 0.74•VA ADC PGA (0 dB) 0.75•VA MIC (+16 dB) MIC (+32 dB) 18 ADC 40 PGA 50 MIC 90 0.78•VA 0.794•VA 0.129•VA 0.022•VA 0.82•VA 0.83•VA 0.74•VA 0.75•VA 90 0.78•VA 0.794•VA 0.129•VA 0.022•VA 0.82•VA 0.83•VA dB Vpp Vpp Vpp Vpp kΩ kΩ kΩ SDOUT Code with HPF On 0.1 ±100 352 0.1 ±100 352 dB ppm/°C LSB Input Impedance (Note 5) - 18 40 50 - 4. Referred to the typical full-scale voltage. Applies to all THD+N and Dynamic Range values in the table. 5. Measured between AINxx and AGND. DS700PP1 13 CS53L21 ADC DIGITAL FILTER CHARACTERISTICS Parameter (Note 6) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay to -0.1 dB corner Min 0 -0.09 0.6 33 - Typ 7.6/Fs 3.7 24.2 10 10 /Fs 5 Max 0.4948 0.17 0.17 0 Unit Fs dB Fs dB s Hz Hz Deg dB s High-Pass Filter Characteristics (48 kHz Fs) Frequency Response Phase Deviation Passband Ripple Filter Settling Time -3.0 dB -0.13 dB @ 20 Hz - 6. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 23 to 26) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. HPF parameters are for Fs = 48 kHz. SWITCHING SPECIFICATIONS - SERIAL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.) Parameters RESET pin Low Pulse Width MCLK Frequency MCLK Duty Cycle (Note 8) (Note 7) Symbol Min 1 1.024 45 Max 38.4 55 Units ms MHz % Slave Mode Input Sample Rate (LRCK) Quarter-Speed Mode Half-Speed Mode Single-Speed Mode Double-Speed Mode Fs Fs Fs Fs 1/tP ts(LK-SK) td(MSB) ts(SDO-SK) th(SK-SDO) 4 8 4 50 45 45 40 20 30 12.5 25 50 100 55 64•Fs 55 52 kHz kHz kHz kHz % Hz % ns ns ns ns LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Setup Time Before SCLK Rising Edge LRCK Edge to SDOUT MSB Output Delay SDOUT Setup Time Before SCLK Rising Edge SDOUT Hold Time After SCLK Rising Edge 14 DS700PP1 CS53L21 Parameters Master Mode (Note 9) Output Sample Rate (LRCK) LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Edge to SDOUT MSB Output Delay SDOUT Setup Time Before SCLK Rising Edge SDOUT Hold Time After SCLK Rising Edge td(MSB) ts(SDO-SK) th(SK-SDO) 1/tP All Speed Modes (Note 10) Fs 45 45 20 30 MCLK ---------------128 55 64•Fs 55 52 Hz % Hz % ns ns ns Symbol Min Max Units 7. After powering up the CS53L21, RESET should be held low after the power supplies and clocks are settled. 8. See “Example System Clock Frequencies” on page 57 for typical MCLK frequencies. 9. See“Master” on page 30. 10. “MCLK” refers to the external master clock applied. LRCK ts(LK-SK) // // // // td(MSB) th(SK-SDO) // MSB // ts(SDO-SK) MSB-1 tP SCLK SDOUT Figure 3. Serial Audio Interface Slave Mode Timing LRCK SCLK td(MSB) // // // // th(SK-SDO) // MSB // ts(SDO-SK) MSB-1 tP SDOUT Figure 4. Serial Audio Interface Master Mode Timing DS700PP1 15 CS53L21 SWITCHING SPECIFICATIONS - I²C CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL = 30 pF) Parameter SCL Clock Frequency Symbol fscl tirs tbuf thdst tlow thigh tsust (Note 11) thdd tsud trc tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 Max 100 1 300 3450 Unit kHz ns µs µs µs µs µs µs ns µs ns µs ns RESET Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling 11. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. RST t irs Stop SDA t buf SCL Repeated Start Start Stop t hdst t high t hdst tf t susp t low t hdd t sud t sust tr Figure 5. Control Port Timing - I²C 16 DS700PP1 CS53L21 SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL) Parameter CCLK Clock Frequency Symbol fsck tsrs tcss tcsh tscl tsch tdsu (Note 12) (Note 13) (Note 13) tdh tr2 tf2 Min 0 20 20 1.0 66 66 40 15 - Max 6.0 100 100 Units MHz ns ns μs ns ns ns ns ns ns RESET Rising Edge to CS Falling CS Falling to CCLK Edge CS High Time Between Transmissions CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN 12. Data must be held for sufficient time to bridge the transition time of CCLK. 13. For fsck PGAx AIN2x-->PGAx AIN3x/MICINx-->PGAx AIN3x/MICINx-->Pre-Amp(+16/+32 dB Gain)-->PGAx AIN1x AIN2x AIN3x/MICINx Reserved Function: Selects the specified analog input signal into ADCx. The microphone pre-amplifier is only available when PDN_PGAx is disabled. See Figure 21. AIN1x AIN2x AIN1x AIN2x AIN3x MUX ADC MUX +16/ 32 dB PGA AIN3x / MICINx Decoder AINx_MUX[1:0] PDN_PGAx Figure 21. AIN & PGA Selection ADCX Invert Signal Polarity (INV_ADCX) Default: 0 0 - Disabled 1 - Enabled Function: When enabled, this bit will invert the signal polarity of the ADC x channel. ADCX Channel Mute (ADCX_MUTE) Default: 0 0 - Disabled 1 - Enabled Function: The output of channel x ADC will mute when enabled. The muting function is affected by the ADCx Soft bit (SOFT). DS700PP1 47 CS53L21 6.8 SPE Control (Address 09h) 6 SPE_ENABLE 5 FREEZE 4 Reserved 3 Reserved 2 Reserved 1 SPE_SZC1 0 SPE_SZC0 7 Reserved SPE_ENABLE Default: 0 0 - Reserved 1 - ADC Serial Port to SPE Function: Selects the digital signal source for the SPE. Note: If DIGMIX = 1, SPE_ENABLE must be 1 for the SPE to be functional. Freeze Controls (FREEZE) Default: 0 Function: This function will freeze the previous settings of, and allow modifications to be made to all control port registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in the control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. 48 DS700PP1 CS53L21 SPE Soft Ramp and Zero Cross Control (SPE_SZC[1:0]) Default = 10 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Note: The SPE_ENABLE bits in reg09h must be set to 1 to enable function control Immediate Change When Immediate Change is selected all volume-level changes will take effect immediately in one step. Zero Cross This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Note: The LIM_SRDIS bit is ignored. Soft Ramp Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 0.5 dB per 4 left/right clock periods. Soft Ramp on Zero Crossing This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Note: The LIM_SRDIS bit is ignored. 6.9 ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) 5 Reserved 4 PGAX_VOL4 3 PGAX_VOL3 2 PGAX_VOL2 1 PGAX_VOL1 0 PGAX_VOL0 7 6 ALCX_SRDIS ALCX_ZCDIS ALCX Soft Ramp Disable (ALCX_SRDIS) Default: 0 0 - Off 1 - On Function: Overrides the SOFTx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be dictated by the soft ramp setting. ALC volume-level changes will take effect in one step. DS700PP1 49 CS53L21 ALCX Zero Cross Disable (ALCX_ZCDIS) Default: 0 0 - Off 1 - On Function: Overrides the ZCROSSx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be dictated by the zero cross setting. ALC volume-level changes will take effect immediately in one step. PGA X Gain Control (PGAX_VOL[4:0]) Default: 00000 Binary Code 11000 ··· 01010 ··· 00000 11111 11110 ··· 11001 11010 Volume Setting +12 dB ··· +5 dB ··· 0 dB -0.5 dB -1 dB ··· -3 dB -3 dB Function: The PGAx Gain Control register allows independent setting of the signal levels in 0.5 dB increments as dictated by the ADCx Soft and Zero Cross bits (SOFTx & ZCROSSx) from +12 dB to -3 dB. Gain settings are decoded as shown in the table above. The gain changes are implemented as dictated by the ALCX Soft & Zero Cross bits (ALCX_SRDIS & ALCX_ZCDIS). Note: When the ALC is enabled, the PGA is automatically controlled and should not be adjusted manually. 6.10 ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh) 6 ADCx_ATT6 5 ADCx_ATT5 4 ADCx_ATT4 3 ADCx_ATT3 2 ADCx_ATT2 1 ADCx_ATT1 0 ADCx_ATT0 7 ADCx_ATT7 ADCX Attenuation Control (ADCX_ATT[7:0]) Default: 00h Binary Code 0111 1111 ··· 0000 0000 1111 1111 1111 1110 ··· 1010 0000 ··· 1000 0000 Volume Setting 0 dB ··· 0 dB -1 dB -2 dB ··· -96 dB ··· -96 dB 50 DS700PP1 CS53L21 Function: The level of ADCX can be adjusted in 1.0 dB increments as dictated by the ADCx Soft and Zero Cross bits (SOFTx & ZCROSSx) from 0 to -96 dB. Levels are decoded in two’s complement, as shown in the table above. Note: When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should not be adjusted manually. 6.11 7 ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh) 6 5 4 3 2 1 0 MUTE_ADCMIXx ADCMIXx_VOL6 ADCMIXx_VOL5 ADCMIXx_VOL4 ADCMIXx_VOL3 ADCMIXx_VOL2 ADCMIXx_VOL1 ADCMIXx_VOL0 Note: The SPE_ENABLE bit in reg09h must be set to 1 to enable function control in this register. ADCX Mixer Channel Mute (MUTE_ADCMIXX) Default: 1 0 - Disabled 1 - Enabled Function: The ADC channel X input to the output mixer will mute when enabled. The muting function is affected by the SPEX Soft and Zero Cross bits (SPEX_SZC[1:0]). ADCX Mixer Volume Control (ADCMIXX_VOL[6:0]) Default = 000 0000 Binary Code 001 1000 ··· 000 0000 111 1111 111 1110 ··· 001 1001 Volume Setting +12.0 dB ··· 0 dB -0.5 dB -1.0 dB ··· -51.5 dB Function: The level of the ADCX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the SPEX Soft and Zero Cross bits (SPE_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as shown in the table above. 6.12 Channel Mixer (Address 18h) 6 Reserved 5 Reserved 4 Reserved 3 ADCA1 2 ADCA0 1 ADCB1 0 ADCB0 7 Reserved Note: The SPE_ENABLE bits in reg09h must be set to 1 to enable function control in this register. Channel Mixer (ADCx[1:0]) Default: 00 ADCA[1:0] 00 SDOUT L ADCB[1:0] 00 SDOUT R DS700PP1 51 CS53L21 ADCA[1:0] 01 10 11 SDOUT L+R ----------2 R ADCB[1:0] 01 10 11 SDOUT L+R ----------2 L Function: Implements mono mixes of the left and right channels as well as a left/right channel swap. 6.13 ALC Enable & Attack Rate (Address 1Ch) 6 ALC_ENA 5 4 3 2 1 0 ALC_ARATE5 ALC_ARATE4 ALC_ARATE3 ALC_ARATE2 ALC_ARATE1 ALC_ARATE0 7 ALC_ENB ALC Enable (ALC_ENX) Default: 0 0 - Disabled 1 - Enabled Function: Enables automatic level control for ADC channel x. Note: When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should not be adjusted manually. ALC Attack Rate (ARATE[5:0]) Default: 000000 Binary Code 000000 ··· 111111 Attack Time Fastest Attack ··· Slowest Attack Function: Sets the rate at which the ALC attenuates the analog input from levels above the maximum setting in the ALC threshold register. The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the SOFTx & ZCROSSx bit settings unless the disable bit for each function is enabled. 6.14 ALC Release Rate (Address 1Dh) 6 Reserved 5 4 3 2 1 0 ALC_RRATE5 ALC_RRATE4 ALC_RRATE3 ALC_RRATE2 ALC_RRATE1 ALC_RRATE0 7 Reserved ALC Release Rate (RRATE[5:0]) Default: 111111 Binary Code 000000 ··· 111111 Release Time Fastest Release ··· Slowest Release 52 DS700PP1 CS53L21 Function: Sets the rate at which the ALC releases the PGA & digital attenuation from levels below the minimum setting in the ALC threshold register, and returns the input level to the PGA_VOL[4:0] & ADCx_ATT[7:0] setting. The ALC release rate is user selectable, but is also a function of the sampling frequency, Fs, and the SOFTx & ZCROSS bit settings unless the disable bit for each function is enabled. 6.15 ALC Threshold (Address 1Eh) 6 MAX1 5 MAX0 4 MIN2 3 MIN1 2 MIN0 1 Reserved 0 Reserved 7 MAX2 Maximum Threshold (MAX[2:0]) Default: 000 MAX[2:0] Threshold Setting (dB) 0 -3 -6 -9 -12 -18 -24 -30 000 001 010 011 100 101 110 111 Function: Sets the maximum level, relative to full scale, at which to limit and attenuate the input signal at the attack rate. Minimum Threshold (MIN[2:0]) Default: 000 MIN[2:0] 000 001 010 011 100 101 110 111 Threshold Setting (dB) 0 -3 -6 -9 -12 -18 -24 -30 Function: Sets the minimum level at which to disengage the ALC’s attenuation or amplify the input signal at a rate set in the release rate register until levels again reach this minimum threshold. The ALC uses this minimum as a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the minimum setting. This provides a more natural sound as the ALC attacks and releases. DS700PP1 53 CS53L21 6.16 Noise Gate Configuration & Misc. (Address 1Fh) 6 NG_EN 5 NG_BOOST 4 THRESH2 3 THRESH1 2 THRESH0 1 NGDELAY1 0 NGDELAY0 7 NG_ALL Noise Gate Channel Gang (NG_ALL) Default: 0 0 - Disabled 1 - Enabled Function: Gangs the noise gate function for channel A and B. When enabled, both channels must fall below the threshold setting for the noise gate attenuation to take effect. Noise Gate Enable (NG_EN) Default: 0 0 - Disabled 1 - Enabled Function: Enables the noise gate. Maximum attenuation is relative to all gain settings applied. Noise Gate Boost (NG_BOOST) and Threshold (THRESH[3:0]) Default: 000 THRESH[2:0] 000 001 010 011 100 101 110 111 Minimum Setting (NG_BOOST = ‘0’b) -64 dB -67 dB -70 dB -73 dB -76 dB -82 dB Reserved Reserved Minimum Setting (NG_BOOST = ‘1’b) -34 dB -37 dB -40 dB -43 dB -46 dB -52 dB -58 dB -64 dB Function: Sets the threshold level of the noise gate. Input signals below the threshold level will be attenuated to -96 dB. NG_BOOST = ‘1’b adds 30 dB to the threshold settings. Noise Gate Delay Timing (NGDELAY[1:0]) Default: 00 00 - 50 ms 01 - 100 ms 10 - 150 ms 11 - 200 ms Function: Sets the delay time before the noise gate attacks. Noise gate attenuation is dictated by the SOFTx & ZCROSS bit settings unless the disable bit for each function is enabled. 54 DS700PP1 CS53L21 6.17 Status (Address 20h) (Read Only) 6 SP_CLKERR 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 ADCA_OVFL 0 ADCB_OVFL 7 Reserved For all bits in this register, a “1” means the associated error condition has occurred at least once since the register was last read. A ”0” means the associated error condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0. Serial Port Clock Error (SP_CLK Error) Default: 0 Function: Indicates an invalid MCLK to LRCK ratio. See “Serial Port Clocking” on page 29“Serial Port Clocking” on page 29 for valid clock ratios. Note: On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes. ADC Overflow (ADCX_OVFL) Default = 0 Function: Indicates that there is an over-range condition anywhere in the CS53L21 ADC signal path of each of the associated ADC’s. DS700PP1 55 CS53L21 7. ANALOG PERFORMANCE PLOTS 7.1 ADC_FILT+ Capacitor Effects on THD+N The value of the capacitor on the ADC_FILT+ pin, 16, affects the low frequency total harmonic distortion + noise (THD+N) performance of the ADC. Larger capacitor values yield significant improvement in THD+N at low frequencies. Figure 22 shows the THD+N versus frequency for the ADC analog input. Plots were taken from the CDB53L21 using an Audio Precision analyzer. -60 -64 1 µF 10 µF 22 µF Legend – Capacitor Value on ADC_FILT+ -68 -72 -76 d B F S -80 -84 -88 -92 -96 -100 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 22. ADC THD+N vs. Frequency w/Capacitor Effects 56 DS700PP1 CS53L21 8. EXAMPLE SYSTEM CLOCK FREQUENCIES 8.1 Auto Detect Enabled Sample Rate LRCK (kHz) 8 11.025 12 1024x 8.1920 11.2896 12.2880 MCLK (MHz) 1536x 2048x* 12.2880 16.9344 18.4320 16.3840 22.5792 24.5760 3072x* 24.5760 33.8688 36.8640 Sample Rate LRCK (kHz) 16 22.05 24 512x 8.1920 11.2896 12.2880 768x 12.2880 16.9344 18.4320 MCLK (MHz) 1024x* 16.3840 22.5792 24.5760 1536x* 24.5760 33.8688 36.8640 Sample Rate LRCK (kHz) 32 44.1 48 256x 8.1920 11.2896 12.2880 384x 12.2880 16.9344 18.4320 MCLK (MHz) 512x* 16.3840 22.5792 24.5760 768x* 24.5760 33.8688 36.8640 Sample Rate LRCK (kHz) 64 88.2 96 128x 8.1920 11.2896 12.2880 192x MCLK (MHz) 256x* 16.3840 22.5792 24.5760 384x* 24.5760 33.8688 36.8640 12.2880 16.9344 18.4320 *The”MCLKDIV2” pin 4 must be set HI. DS700PP1 57 CS53L21 8.2 Auto Detect Disabled Sample Rate LRCK (kHz) 8 11.025 12 512x 6.1440 768x 6.1440 8.4672 9.2160 MCLK (MHz) 1024x 1536x 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 2048x 16.3840 22.5792 24.5760 3072x 24.5760 33.8688 36.8640 Sample Rate LRCK (kHz) 16 22.05 24 256x 6.1440 384x 6.1440 8.4672 9.2160 512x 8.1920 11.2896 12.2880 MCLK (MHz) 768x 12.2880 16.9344 18.4320 1024x 16.3840 22.5792 24.5760 1536x 24.5760 33.8688 36.8640 Sample Rate LRCK (kHz) 32 44.1 48 256x 8.1920 11.2896 12.2880 MCLK (MHz) 384x 512x 12.2880 16.9344 18.4320 16.3840 22.5792 24.5760 768x 24.5760 33.8688 36.8640 Sample Rate LRCK (kHz) 64 88.2 96 128x 8.1920 11.2896 12.2880 MCLK (MHz) 192x 256x 12.2880 16.9344 18.4320 16.3840 22.5792 24.5760 384x 24.5760 33.8688 36.8640 58 DS700PP1 CS53L21 9. PCB LAYOUT CONSIDERATIONS 9.1 Power Supply, Grounding As with any high-resolution converter, the CS53L21 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 on page 9 shows the recommended power arrangements, with VA connected to a clean supply. VD, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this case, no additional devices should be powered from VD. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS53L21 as possible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the CS53L21 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and AGND. The CS53L21 evaluation board demonstrates the optimum layout and power supply arrangements. 9.2 QFN Thermal Pad The CS53L21 is available in a compact QFN package. The under side of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers. In split ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The CS53L21 evaluation board demonstrates the optimum thermal pad and via configuration. DS700PP1 59 CS53L21 10.DIGITAL FILTERS Figure 23. ADC Passband Ripple Figure 24. ADC Stopband Rejection Figure 25. ADC Transition Band Figure 26. ADC Transition Band Detail 60 DS700PP1 CS53L21 11.PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channel pairs. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. DS700PP1 61 CS53L21 12.PACKAGE DIMENSIONS 32L QFN (5 X 5 mm BODY) PACKAGE DRAWING D b e Pin #1 Corner Pin #1 Corner E E2 A1 A Top View Side View L D2 Bottom View DIM A A1 b D D2 E E2 e L MIN -0.0000 0.0071 0.1280 0.1280 0.0118 INCHES NOM --0.0091 0.1969 BSC 0.1299 0.1969 BSC 0.1299 0.0197 BSC 0.0157 MAX 0.0394 0.0020 0.0110 0.1319 0.1319 0.0197 MIN -0.00 0.18 3.25 3.25 0.30 MILLIMETERS NOM --0.23 5.00 BSC 3.30 5.00 BSC 3.30 0.50 BSC 0.40 NOTE MAX 1.00 0.05 0.28 3.35 3.35 0.50 1 1 1,2 1 1 1 1 1 1 JEDEC #: MO-220 Controlling Dimension is Millimeters. 1. Dimensioning and tolerance per ASME Y 14.5M-1995. 2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. THERMAL CHARACTERISTICS Parameter Junction to Ambient Thermal Impedance 2 Layer Board 4 Layer Board Symbol θJA Min - Typ 52 38 Max - Units °C/Watt 62 DS700PP1 CS53L21 13.ORDERING INFORMATION Product CS53L21 Description Low-Power Stereo A/D CS53L21 Evaluation Board Package Pb-Free 32L-QFN Yes Grade Temp Range Container Order # Commercial -10 to +70° C Automotive CDB53L21 No -40 to +85° C - Rail CS53L21-CNZ Tape & Reel CS53L21-CNZR Rail CS53L21-DNZ Tape & Reel CS53L21-DNZR CDB53L21 14.REFERENCES 1. Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998. 2. Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the Audio Engineering Society, September 1997. 3. Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention of the Audio Engineering Society, November 1988. 4. Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 5. Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Application Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 6. Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters, by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992. 7. Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 8. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com DS700PP1 63 CS53L21 15.REVISION HISTORY Revision A1 Initial Release Adjusted the minimum voltage specification in “Specified Operating Conditions” section on page 11. Adjusted maximum “Analog In to PGA to ADC” THD+N performance specification in “Analog Characteristics (Commercial - CNZ)” on page 12. Corrected Interchannel Gain Mismatch specification in “Analog Characteristics (Commercial - CNZ)” on page 12 and “Analog Characteristics (Automotive - DNZ)” on page 13. Adjusted ADC full scale input voltage specification in “Analog Characteristics (Commercial - CNZ)” on page 12 and “Analog Characteristics (Automotive - DNZ)” on page 13. Removed td timing specification from table in section “Switching Specifications - Serial Port” on page 14. Corrected Group Delay characteristic in table in section “ADC Digital Filter Characteristics” on page 14. Adjusted timing specifications td(MSB) from 40 ns to 52 ns and ts(SDO-SK) from 30 ns to 20 ns in table in section “Switching Specifications - Serial Port” on page 14. Adjusted I²C timing specifications tack from 1000 ns to 3450 ns in table in section “” on page 15. Modified the Typ. Conn. HW and SW figures by adding a pull-up to the VA_HP pin and changed AFILTA, B cap values from 1000 pF to 150 pF. Modified the Pin Descriptions table description for pin 5 to add a pull-up. Adjusted High-Level Input Voltage specifications VIH from 0.65VL to 0.68VL and VIL from 0.35VL to 0.32VL in table in section “Digital Interface Specifications & Characteristics” on page 18. Adjusted the +20 dB Digital Boost block before the ALC feedback path in Figure 7 on page 22. Modified ALC Recommended Settings in section “Automatic Level Control (ALC)” on page 26. Modified step 2 of the “Recommended Power-Down Sequence” on page 33. Corrected default values for ALC and Limiter Release Rates shown in “Register Quick Reference” on page 37. Corrected default value for the SPE_SZC bits in “SPE Control (Address 09h)” on page 48. Corrected ADC Filter Response shown in Figures 23, 24, 25, and 26 on page 60. Corrected ADC_SNGVOL description in “MIC Control (Address 05h)” on page 44. Changes PP1 64 DS700PP1 CS53L21 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com. IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. DS700PP1 65 CS53L21 66 DS700PP1