CS5460-BS

CS5460 Single Phase Bi-Directional Power/Energy IC Features Description l Energy The CS5460 is a highly integrated ∆Σ Analog-to-Digital Converter (ADC) which combines two ∆Σ ADCs, high speed power calculation functions, and a serial interface on a single chip. It is designed to accurately measure and calculate: Energy, Instantaneous Power, I RMS, and VRMS for single phase 2 or 3-wire power meter applications. The CS5460 interfaces to a low cost shunt or transformer to measure current, and resistive divider or transformer to measure voltage. The CS5460 features a bi-directional serial interface for communication with a micro-controller and a fixed-width programmable frequency output that is proportional to energy. The product is initialized and fully functional upon power-up, and includes facilities for system-level calibration under control of the user program. Data Linearity: 0.1% of Reading over 1000:1 Dynamic Range l On-Chip Functions: Energy, I ∗ V, IRMS and VRMS, Energy to Pulse-Rate Conversion l Complies with IEC 687/1036, JIS l Power Consumption register address bits in the Register Read/Write Command word ** “default” => bit status after reset 4.1 Configuration Register Address: RA[4:0]* = 0x00 23 PC3 22 PC2 21 PC1 20 PC0 19 0 18 0 17 0 16 Gi 15 EWA 14 PH1 13 PH0 12 SI1 11 SI0 10 EOD 9 DL1 8 DL0 7 RS 6 VHPF 5 IHPF 4 iCPU 3 K3 2 K2 1 K1 0 K0 Default** = 0x000001 22 K[3:0] Clock divider. A 4 bit binary number ranging from 0 to 15 used to divide the value of MCLK to generate the internal clock DCLK. The internal clock frequency of DCLK = MCLK/K. Valid values are 1,2, and 4. 0001 = divide by 1 (default) 0010 = divide by 2 0100 = divide by 4 iCPU Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals are sampled, the logic driven by CPUCLK should not be active during the sample edge. 0 = normal operation (default) 1 = minimize noise when CPUCLK is driving rising edge logic IHPF Control the use of the High Pass Filter on the Current Channel. 0 = High-pass filter is disabled. If VHPF is set, use all-pass filter. Otherwise, no filter is used. (default) 1 = High-pass filter is enabled. VHPF Control the use of the High Pass Filter on the voltage Channel. 0 = High-pass filter is disabled. If IHPF is set, use all-pass filter. Otherwise, no filter is used. (default) 1 = High-pass filter enabled RS Start a chip reset cycle when set 1. The reset cycle lasts for less than 10 XIN cycles. The bit is automatically returned to 0 by the reset cycle. DL0 When EOD = 1, EDIR becomes a user defined pin. DL0 sets the value of the EDIR pin. Default = '0' DL1 When EOD = 1, EOUT becomes a user defined pin. DL1 sets the value of the EOUT pin. Default = '0' EOD Allows the EOUT and EDIR pins to be controlled by the DL0 and DL1 bits. EOUT and EDIR can also be accessed using the status register. 0 = Normal operation of the EOUT and EDIR pins. (default) 1 = DL0 and DL1 bits control the EOUT and EDIR pins. DS279PP6 CS5460 SI[1:0] Soft interrupt configuration. Select the desired pin behavior for indication of an interrupt. 00 = active low level (default) 01 = active high level 10 = falling edge (INT is normally high) 11 = rising edge (INT is normally low) PH[1:0] Set the phase of the EOUT and EDIR output pin pulse. The EOUT and EDIR pins, on different phases, can be wire-ORed together as a simple way of summing the frequency of different parts. 00 = phase 0 (default) 01 = phase 1 10 = phase 2 11 = phase 3 EWA Allows the output pins of EOUT and EDIR of multiple chips to be connected in a wire-AND, using an external pull-up device. 0 = normal outputs (default) 1 = only the pull-down device of the EOUT and EDIR pins are active Gi Sets the gain of the current PGA 0 = gain is 10 (default) 1 = gain is 50 Res Reserved. These bits must be set to zero. PC[3:0] Phase compensation. A 2’s complement number used to set the delay in the voltage channel. The bigger the number, the greater the delay in the voltage. The phase adjustment range is about -2.4 to +2.5 degrees at 60 Hz. Each step is about 0.34 degrees at 60 Hz. 0000 = Zero degrees phase delay (default) 4.2 Current Offset Register and Voltage Offset Register Address: RA[4:0]* = 0x01 (Current Offset Register) RA[4:0]* = 0x03 (Voltage Offset Register) MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default** = 0.000 The Offset Registers are initialized to zero on reset, allowing the device to function and perform measurements. The register is loaded after one computation cycle with the system current or voltage offset when the proper input is applied and the Calibration Command is received. The register may be read and stored so the register may be restored with the desired system offset compensation. The offset range is ± full scale. Format of the register value is two’s complement notation. DS279PP6 23 CS5460 4.3 Current Gain Register and Voltage Gain Register Address: RA[4:0]* = 0x02 (Current Gain Register) RA[4:0]* = 0x04 (Voltage Gain Register) MSB 21 LSB 20 2-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 2-22 Default** = 1.000 The Gain Registers are initialized to 1.0 on reset, allowing the device to function and perform measurements. The register is loaded after one cycle with the system gain when the proper input is applied and the Calibration Command is received. The register may be read and stored so the register may be restored with the desired system offset compensation. The value is in the range 0.0 ≤ Gain < 4.0. 4.4 Cycle Count Register Address: RA[4:0]* = 0x05 MSB 223 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default** = 4000 The Cycle Count Register determines the length of an energy and RMS conversion. A conversion cycle is derived from (MCLK/K)/(1024∗N) where MCLK is master clock, K is clock divider, and N is cycle count. N must be greater than 10 for IRMS, VRMS and energy calculations to be performed. 4.5 Pulse-Rate Register Address: RA[4:0]* = 0x06 MSB 218 LSB 217 216 215 214 213 212 211 ..... 21 20 2-1 2-2 2-3 2-4 2-5 Default** = 32000.00 Hz The Pulse-Rate Register determines the frequency of the train of pulses output on the EOUT pin. Each EOUT pulse represents a predetermined magnitude of energy.The register’s smallest valid value is 2-4 but can be in 2-5 increments. 4.6 I,V,P,E Signed Output Register Results Address: RA[4:0]* = 0x07 - 0x0A MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Access: Read Only The Signed Registers contain the last value of the measured results of I, V, P, and E. The results are in the range of -1.0 ≤ I, V, P, E < 1.0. The value is represented in two's complement notation, with the binary point place to the right of the MSB (which is the sign bit). I, V, P, and E are output results registers which contain signed values. Note that the I, V, and P registers are updated every conversion cycle, while the E register is only updated after each computation cycle. The numeric format of this register is two’s complement notation. 24 DS279PP6 CS5460 4.7 IRMS, VRMS Unsigned Output Register Results Address: RA[4:0]* = 0x0B - 0x0C MSB 2-1 LSB 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24 Access: Read Only The Unsigned Registers contain the last value of the calculated results of IRMS and VRMS. The results are in the range of 0.0 ≤ IRMS,VRMS < 1.0. The value is represented in binary notation, with the binary point place to the left of the MSB. IRMS and VRMS are output result registers which contain unsigned values. 4.8 Timebase Calibration Address: RA[4:0]* = 0x0D MSB 20 LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default** = 1.000 The Timebase Register is initialized to 1.0 on reset, allowing the device to function and perform computations. The register is user loaded with the clock frequency error to compensate for a gain error caused by the crystal/oscillator tolerance. The value is in the range 0.0 ≤ TBC < 2.0. 4.9 Status Register and Mask Register Address: RA[4:0]* = 0x0F (Status Register) RA[4:0]* = 0x1A (Mask Register) 23 DRDY 22 EOUT 21 EDIR 20 Res 19 MATH 18 Res 17 IOR 16 VOR 15 PWOR 14 IROR 13 VROR 12 EOR 11 EOOR 10 Res 9 Res 8 Res 7 Res 6 Res 5 WDT 4 VOD 3 IOD 2 LSD 1 0 0 IC Default** = 0x000001 (Status Register) 0x000000 (Mask Register) The Status Register indicates the condition of the chip. In normal operation writing a ’1’ to a bit will cause the bit to go to the ’0’ state. Writing a ’0’ to a bit will maintain the status bit in its current state. With this feature the user can simply write back the status register to clear the bits that have been seen, without concern of clearing any newly set bits. Even if a status bit is masked to prevent the interrupt, the status bit will still be set in the status register so the user can poll the status. The Mask Register is used to control the activation of the INT pin. Placing a logic ’1’ in the mask register will allow the corresponding bit in the status register to activate the INT pin when the status bit becomes active. IC DS279PP6 Invalid Command. Normally logic 1. Set to logic 0 when the part is given an invalid command. Can be deactivated only by sending a port initialization sequence to the serial port. When writing to Status Register this bit is ignored. 25 CS5460 LSD Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage threshold (with respect to VA- pin). For a given part, this threshold can anywhere between 2.3 V to 2.7 V. IOD Modulator oscillation detect on the current channel. Set when the modulator oscillates due to an input above Full Scale. Note that the level at which the modulator oscillates is significantly higher than the current channel’s Differential Input Voltage Range. VOD Modulator oscillation detect on the voltage channel. Set when the modulator oscillates due to an input above Full Scale. Note that the level at which the modulator oscillates is significantly higher than the current channel’s Differential Input Voltage Range. NOTE: This IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the power line. This event should not be confused with a DC overload situation at the inputs, when the IOD and VOD bits will re-assert themselves even after being cleared, multiple times. 26 WDT Watch-Dog Timer. Set when there has been no reading of the Energy register for more than 5 seconds. (MCLK = 4.096 MHz, K = 1) To clear this bit, first read the Energy register, then write to the Status Register with this bit set to logic '1'. EOOR /EOUT Energy Summation Register went out of range. Note that the /EOUT Energy Summing Register is different than the Energy Register available through the serial port. This register cannot be read by the user. Assertion of the this bit can be caused by having an output rate that is too small for the power being measured. The problem can be corrected by specifying a higher frequency in the Pulse-Rate Register. EOR Energy Out of Range. Set when the calibrated energy value is too large or too small to fit in the Energy Register, which can be read via the serial port. VROR RMS Voltage Out of Range. Set when the calibrated RMS voltage value is too large to fit in the RMS-Voltage Register. IROR RMS Current Out of Range. Set when the calibrated RMS current value is too large to fit in the RMS-Current Register. PWOR Power Calculation Out of Range. Set when the magnitude of the calculated power is too large to fit in the Instantaneous Power Register. VOR Voltage Out of Range. IOR Current Out of Range. Set when the magnitude of the calibrated current value is too large or too small to fit in the Instantaneous Current Register. MATH General computation Indicates that a divide operation overflowed. This can happen normally in the course of computation. If this bit is asserted but no other bits are asserted, then there is no error, and this bit should be ignored. EDIR Set whenever the EOUT bit asserted (see below) as long as the energy result is negative. EOUT Indicates that the energy limit has been reached for the /EOUT Energy Summation Register, and so this register will be cleared, and one pulse will be generated on the /EOUT pin (if enabled). The energy flow may indicate negative energy or positive energy. This must be determined by looking at the EDIR bit (above). This EOUT bit is cleared automatically when the energy rate drops below the level that produces a 4 KHz EOUT pin rate. The bit can also be cleared by writing to the Status Register. This status bit is set with a maximum frequency of 4 KHz (when MCLK/K is 4.096 MHz). DS279PP6 CS5460 DRDY Data Ready. When running in single or continuous conversion mode, this bit will indicate the end of computation cycles. When running calibrations, this bit indicates that the calibration sequence has completed, and the results have been stored in the offset or gain registers. DS279PP6 27 CS5460 5. FUNCTIONAL DESCRIPTION Step H0 - Read the Status register. 5.1 Interrupt and Watchdog Timer Step H1 - Disable all interrupts. 5.1.1 Interrupt Step H2 - Branch to the proper interrupt service routine. The INT pin is used to indicate that an event has taken place in the converter that needs attention. These events inform the system about operation conditions and internal error conditions. The INT signal is created by combining the Status register with the Mask register. Whenever a bit in the Status register becomes active, and the corresponding bit in the Mask register is a logic 1, the INT signal becomes active. The interrupt condition is cleared when the bits of the status register are returned to their inactive state. 5.1.1.1 Clearing the Status Register Unlike the other registers, the bits in the Status register can only be cleared (set to logic 0). When a word is written to the Status register, any 1s in the word will cause the corresponding bits in the Status register to be cleared. The other bits of the status register remain unchanged. This allows the clearing of particular bits in the register without having to know the state of the other bits. This mechanism is designed to facilitate handshaking and to minimize the risk of losing events that haven’t been processed yet. Step H3 - Clear the Status register by writing back the value read in step H0. Step H4 - Re-enable interrupts. Step H5 - Return from interrupt service routine. This handshaking procedure insures that any new interrupts activated between steps H0 and H3 are not lost (cleared) by step H3. 5.1.1.3 INT Active State The behavior of the INT pin is controlled by the SI1 and SI0 bits of the configuration register. The pin can be active low (default), active high, active on a return to logic 0 (rising edge), or activate on a return to logic 1 (falling edge). 5.1.1.4 Exceptions The IC (Invalid Command) bit of the Status register can only be cleared by performing the port initialization sequence. This is also the only Status register bit that is active low. To properly clear the WDT (WatchDog Timer) bit of the Status register, one must first read the Energy register, then clear the bit in the status register. 5.1.1.2 Typical use of the INT pin The steps below show how interrupts can be handled. Initialization: Step I0 - All Status bits are cleared by writing FFFFFF (Hex) into the Status register. Step I1 - The conditional bits which will be used to generate interrupts are then written to logic 1 in the Mask register. Step I3 - Enable interrupts. Interrupt Handler Routine: 28 5.1.2 Watch Dog Timer The Watch Dog Timer (WDT) is provided as means of alerting the system that there is a potential breakdown in communication with the micro-controller. By allowing the WDT to cause an interrupt, a controller can be brought back, from some unknown code space, into the proper code for processing the data created by the converter. The time-out is preprogrammed to approximately 5 seconds. The countdown restarts each time the Energy register is read. Under typical situations, the Energy register is read every second. As a result, the DS279PP6 CS5460 WDT will not time out. Other applications, that want to use the watchdog timer, will need to ensure that the Energy register is read at least once in every 5 second span. The CS5460 can be driven by a clock ranging from 2.5 to 20 MHz Table 3 shows the clock divide value K (default = 1) that the CS5460 needs to be programmed with for normal operation. 5.2 Oscillator Characteristics K XIN and XOUT are the input and output, respectively, of an inverting amplifier to provide oscillation and can be configured as an on-chip oscillator, as shown in Figure 11. The oscillator circuit is designed to work with a quartz crystal or a ceramic resonator. To reduce circuit cost two load capacitors C1 are integrated in the device, one between XIN and DGND, one between XOUT and DGND. Lead lengths should be minimized to reduce stray capacitance. With these load capacitors the oscillator circuit is capable of oscillation up to 20 MHz. To drive the device from an external clock source, XOUT should be left unconnected while XIN is driven by the external circuitry. There is an amplifier between XIN and the digital section which provides CMOS level signals. This amplifier works with sinusoidal inputs so there are no problems with slow edge times. CLK (min) MHz 2.5 5 10 1 2 4 CLK (max) MHz 5 10 20 Table 3. CPU Clock (and K) Restrictions 5.3 Analog Inputs The CS5460 accommodates a full scale range of 150 mVRMS on both input channels. System calibration can be used to increase or decrease the full scale span of the converter as long as the calibration register values stay within the limits specified. See the Calibration section for more details. The current input channel has an input range of 30 mVRMS when the internal x50 gain stage is enabled. This signal range is designed to handle low level signals from a shunt sensor. XOUT C1 Oscillator Circuit XIN C1 DGND C1 = 22 pF Figure 11. Oscillator Connection DS279PP6 29 CS5460 5.4 Voltage Reference The CS5460 is specified for operation with a +2.5 V reference between the VREFIN and VApins. The converter includes an internal 2.5 V reference (60 ppm/°C drift) that can be used by connecting the VREFOUT pin to the VREFIN pin of the device. If higher accuracy/stability is required, an external reference can be used. 5.5 Performing Calibrations The CS5460 offers two DC calibration modes: system offset and system gain. For system calibration the user must supply the converter calibration signals which represent ground and full scale. The user must provide the positive full scale point to perform a system gain calibration and a ground referenced signal when a system offset is performed. The offset and gain signals must be within the specified calibration limits for each specific calibration step and channel. Since each converter channel has its own offset and gain register associated with it, system offset, or system gain can be performed on either channel without the calibration results from one channel corrupting the other. The Cycle Count register N, determines the number of conversions averaged to obtain the calibration results. The larger N, the higher the accuracy of the calibration results. Once a calibration cycle is complete, DRDY is set and the results are stored in either the gain or offset register. Note that if additional calibrations are performed, the latest calibration results will replace the effects from the previous calibration. In any event, offset and gain calibration steps take one cycle each to complete. After the part is reset, the device is functional and can perform measurements without being calibrated. The converters will utilize the initialized values of the on-chip registers (Gain = 1.0, Offset = 0.0) to calculate power information. Although the device 30 can be used without performing an offset or gain calibration, any initial offset and gain errors in the internal circuitry of the chip will remain. 5.5.1 System Calibration For the system calibration functions, the user must supply the converters calibration signals which represent ground and full scale. When a system offset calibration is performed, a ground reference signal must be applied to the converters. Figure 12 illustrates system offset calibration. As shown in Figure 13, the user must input a signal representing the positive full scale point to perform a system gain calibration. In either case, the calibration signals must be within the specified calibration limits for each specific calibration step (refer to Full Scale DC Calibration Range). External Connections + + AIN+ 0V +- XGAIN - AIN- CM +- Figure 12. System Calibration of Offset. External Connections + + AIN+ Full Scale + - XGAIN - CM + - AIN- Figure 13. System Calibration of Gain. DS279PP6 CS5460 5.5.2 Calibration Tips 5.7 Input Current Protection To minimize digital noise near the device, the user should wait for each calibration step to be completed before reading or writing to the serial port. In Figure 3 and Figure 4, note the series resistor RPI which is connected to the IIN+ input pin. This resistor is used to provide current-limit protection for the current-channel input pin in the event of a power surge or lightening surge. The voltage/current-channel inputs have surge-current limits of 100 mA. This applies to brief voltage/current spikes (