CS5460

CS5460 Single Phase Bi-Directional Power/Energy IC Features l Energy Description The CS5460 is a highly integrated ∆Σ Analog-to-Digital Converter (ADC) which combines two ∆Σ ADCs, high speed power calculation functions, and a serial interface on a single chip. It is designed to accurately measure and calculate: Energy, Instantaneous Power, IRMS, and VRMS for single phase 2 or 3-wire power meter applications. The CS5460 interfaces to a low cost shunt or transformer to measure current, and resistive divider or transformer to measure voltage. The CS5460 features a bi-directional serial interface for communication with a micro-controller and a fixed-width programmable frequency output that is proportional to energy. The product is initialized and fully functional upon power-up, and includes facilities for system-level calibration under control of the user program. Data Linearity: 0.1% of Reading over 1000:1 Dynamic Range l On-Chip Functions: Energy, I ∗ V, IRMS and VRMS, Energy to Pulse-Rate Conversion l Complies with IEC 687/1036, JIS l Power Consumption register address bits in the Register Read/Write Command word ** “default” => bit status after reset 4.1 Configuration Register Address: RA[4:0]* = 0x00 23 PC3 15 EWA 7 RS 22 PC2 14 PH1 6 VHPF 21 PC1 13 PH0 5 IHPF 20 PC0 12 SI1 4 iCPU 19 0 11 SI0 3 K3 18 0 10 EOD 2 K2 17 0 9 DL1 1 K1 16 Gi 8 DL0 0 K0 Default** = 0x000001 K[3:0] Clock divider. A 4 bit binary number ranging from 0 to 15 used to divide the value of MCLK to generate the internal clock DCLK. The internal clock frequency of DCLK = MCLK/K. Valid values are 1,2, and 4. 0001 = divide by 1 (default) 0010 = divide by 2 0100 = divide by 4 Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals are sampled, the logic driven by CPUCLK should not be active during the sample edge. 0 = normal operation (default) 1 = minimize noise when CPUCLK is driving rising edge logic Control the use of the High Pass Filter on the Current Channel. 0 = High-pass filter is disabled. If VHPF is set, use all-pass filter. Otherwise, no filter is used. (default) 1 = High-pass filter is enabled. Control the use of the High Pass Filter on the voltage Channel. 0 = High-pass filter is disabled. If IHPF is set, use all-pass filter. Otherwise, no filter is used. (default) 1 = High-pass filter enabled Start a chip reset cycle when set 1. The reset cycle lasts for less than 10 XIN cycles. The bit is automatically returned to 0 by the reset cycle. When EOD = 1, EDIR becomes a user defined pin. DL0 sets the value of the EDIR pin. Default = '0' When EOD = 1, EOUT becomes a user defined pin. DL1 sets the value of the EOUT pin. Default = '0' Allows the EOUT and EDIR pins to be controlled by the DL0 and DL1 bits. EOUT and EDIR can also be accessed using the status register. 0 = Normal operation of the EOUT and EDIR pins. (default) 1 = DL0 and DL1 bits control the EOUT and EDIR pins. Soft interrupt configuration. Select the desired pin behavior for indication of an interrupt. 00 = active low level (default) iCPU IHPF VHPF RS DL0 DL1 EOD SI[1:0] DS279PP5 21 CS5460 01 = active high level 10 = falling edge (INT is normally high) 11 = rising edge (INT is normally low) PH[1:0] Set the phase of the EOUT and EDIR output pin pulse. The EOUT and EDIR pins, on different phases, can be wire-ORed together as a simple way of summing the frequency of different parts. 00 = phase 0 (default) 01 = phase 1 10 = phase 2 11 = phase 3 Allows the output pins of EOUT and EDIR of multiple chips to be connected in a wire-AND, using an external pull-up device. 0 = normal outputs (default) 1 = only the pull-down device of the EOUT and EDIR pins are active Sets the gain of the current PGA 0 = gain is 10 (default) 1 = gain is 50 Reserved. These bits must be set to zero. Phase compensation. A 2’s complement number used to set the delay in the voltage channel. The bigger the number, the greater the delay in the voltage. The phase adjustment range is about -2.4 to +2.5 degrees at 60Hz. Each step is about 0.34 degrees at 60Hz. 0000 = Zero degrees phase delay (default) EWA Gi Res PC[3:0] 4.2 Current Offset Register and Voltage Offset Register Address: RA[4:0]* = 0x01 (Current Offset Register) RA[4:0]* = 0x03 (Voltage Offset Register) LSB 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24 MSB SIGN Default** = 0.000 The Offset Registers are initialized to zero on reset, allowing the device to function and perform measurements. The register is loaded after one cycle with the system offset when the proper input is applied and the Calibration Command is received. The register may be read and stored so the register may be restored with the desired system offset compensation. The value is in the range ± ½ full scale. 4.3 Current Gain Register and Voltage Gain Register Address: RA[4:0]* = 0x02 (Current Gain Register) RA[4:0]* = 0x04 (Voltage Gain Register) LSB 20 2-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 2-22 MSB 21 Default** = 1.000 The Gain Registers are initialized to 1.0 on reset, allowing the device to function and perform measurements. The register is loaded after one cycle with the system gain when the proper input is applied and the Calibration Command is received. The register may be read and stored so the register may be restored with the desired system offset compensation. The value is in the range 0.0 ≤ Gain < 4.0. 22 DS279PP5 CS5460 4.4 Cycle Count Register Address: RA[4:0]* = 0x05 MSB 223 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 LSB 20 Default** = 4000 The Cycle Count Register determines the length of an energy and RMS conversion. A conversion cycle is derived from (MCLK/K)/(1024∗N) where MCLK is master clock, K is clock divider, and N is cycle count. N must be greater than 10 for IRMS, VRMS and energy calculations to be performed. 4.5 Pulse-Rate Register Address: RA[4:0]* = 0x06 MSB 218 2 17 LSB 2 16 2 15 2 14 2 13 2 12 2 11 ..... 21 2 0 2 -1 2 -2 2 -3 2 -4 2-5 Default** = 32000.00Hz The Pulse-Rate Register determines the frequency of the train of pulses output on the EOUT pin. Each EOUT pulse represents a predetermined magnitude of energy.The register’s smallest valid value is 2-4 but can be in 2-5 increments. 4.6 I,V,P,E Signed Output Register Results Address: RA[4:0]* = 0x07 - 0x0A MSB SIGN LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Access: Read Only The Signed Registers contain the last value of the measured results of I, V, P, and E. The results are in the range of -1.0 ≤ I, V, P, E < 1.0. The value is represented in two's complement notation, with the binary point place to the right of the MSB (which is the sign bit). I, V, P, and E are output results registers which contain signed values. 4.7 IRMS, VRMS Unsigned Output Register Results Address: RA[4:0]* = 0x0B - 0x0C MSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 LSB 2-24 Access: Read Only The Unsigned Registers contain the last value of the calculated results of IRMS and VRMS. The results are in the range of 0.0 ≤ IRMS,VRMS < 1.0. The value is represented in binary notation, with the binary point place to the left of the MSB. IRMS and VRMS are output result registers which contain unsigned values. DS279PP5 23 CS5460 4.8 Timebase Calibration Address: RA[4:0]* = 0x0D MSB 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Default** = 1.000 The Timebase Register is initialized to 1.0 on reset, allowing the device to function and perform computations. The register is user loaded with the clock frequency error to compensate for a gain error caused by the crystal/oscillator tolerance. The value is in the range 0.0 ≤ TBC < 2.0. 4.9 Status Register and Mask Register Address: RA[4:0]* = 0x0F (Status Register) RA[4:0]* = 0x1A (Mask Register) 22 EOUT 14 IROR 6 Res 21 EDIR 13 VROR 5 WDT 20 Res 12 EOR 4 VOD 19 MATH 11 EOOR 3 IOD 18 Res 10 Res 2 LSD 17 IOR 9 Res 1 0 16 VOR 8 Res 0 IC 23 DRDY 15 PWOR 7 Res Default** = 0x000001 (Status Register) 0x000000 (Mask Register) The Status Register indicates the condition of the chip. In normal operation writing a ’1’ to a bit will cause the bit to go to the ’0’ state. Writing a ’0’ to a bit will maintain the status bit in its current state. With this feature the user can simply write back the status register to clear the bits that have been seen, without concern of clearing any newly set bits. Even if a status bit is masked to prevent the interrupt, the status bit will still be set in the status register so the user can poll the status. The Mask Register is used to control the activation of the INT pin. Placing a logic ’1’ in the mask register will allow the corresponding bit in the status register to activate the INT pin when the status bit becomes active. IC Invalid Command. Normally logic 1. Set to logic 0 when the part is given an invalid command. Can be deactivated only by sending a port initialization sequence to the serial port. When writing to status register this bit is ignored. Low Supply detect. Set when the PFMON pin falls below 2.5 volts with respect to the VA- pin. Modulator oscillation detect on the current channel. Set when the modulator oscillates due to an input above Full Scale. Modulator oscillation detect on the voltage channel. Set when the modulator oscillates due to an input above Full Scale. Watch-Dog Timer. Set when there has been no reading of the Energy register for more than 5 seconds. (MCLK = 4.096 MHz, K = 1) To clear this bit, first read the Energy register, then write to the status register with this bit set to logic ’1’. EOUT energy/current summing register went out of range. This can be caused by having an output rate that is too small for the power being measured. The problem can be corrected by specifying a higher frequency in the pulse-rate register. DS279PP5 LSD IOD VOD WDT EOOR 24 CS5460 EOR VROR IROR PWOR VOR IOR MATH EDIR EOUT Energy Out of Range. Set when the calibrated energy value is too large or too small to fit in the output word. RMS Voltage Out of Range. Set when the calibrated RMS voltage value is too large to fit in the output word. RMS Current Out of Range. Set when the calibrated RMS current value is too large to fit in the output word. Power Calculation Out of Range. Voltage Out of Range. Set when the calibrated voltage value is too large or too small to fit in the output word. Current Out of Range. Set when the calibrated current value is too large or too small to fit in the output word. General computation error (e.g., divide by 0) Set when sum of energy is less than zero. Set or cleared at the same time as EOUT. Indicates that the energy limit has been reached for the energy to frequency conversion, and a pulse train will be generated on the EOUT pin (if enabled). This bit is cleared automatically when the energy rate drops below the level that produces a 4 KHz EOUT pin rate. The bit can also be cleared by writing to the status register. This status bit is set with a maximum frequency of 4 KHz (when MCLK/K is 4.096 MHz). Data Ready. Set at the end of a calibration or conversion cycle. DRDY DS279PP5 25 CS5460 5. FUNCTIONAL DESCRIPTION 5.1 Interrupt and Watchdog Timer 5.1.1 Interrupt The INT pin is used to indicate that an event has taken place in the converter that needs attention. These events inform the system about operation conditions and internal error conditions. The INT signal is created by combining the Status register with the Mask register. Whenever a bit in the Status register becomes active, and the corresponding bit in the Mask register is a logic 1, the INT signal becomes active. The interrupt condition is cleared when the bits of the status register are returned to their inactive state. Interrupt Handler Routine: Step H0 - Read the Status register. Step H1 - Disable all interrupts. Step H2 - Branch to the proper interrupt service routine. Step H3 - Clear the Status register by writing back the value read in step H0. Step H4 - Re-enable interrupts. Step H5 - Return from interrupt service routine. This handshaking procedure insures that any new interrupts activated between steps H0 and H3 are not lost (cleared) by step H3. 5.1.1.3 INT Active State The behavior of the INT pin is controlled by the SI1 and SI0 bits of the configuration register. The pin can be active low (default), active high, active on a return to logic 0 (rising edge), or activate on a return to logic 1 (falling edge). 5.1.1.1 Clearing the Status Register Unlike the other registers, the bits in the Status register can only be cleared (set to logic 0). When a word is written to the Status register, any 1s in the word will cause the corresponding bits in the Status register to be cleared. The other bits of the status register remain unchanged. This allows the clearing of particular bits in the register without having to know the state of the other bits. This mechanism is designed to facilitate handshaking and to minimize the risk of losing events that haven’t been processed yet. 5.1.1.4 Exceptions The IC (Invalid Command) bit of the Status register can only be cleared by performing the port initialization sequence. This is also the only Status register bit that is active low. To properly clear the WDT (WatchDog Timer) bit of the Status register, one must first read the Energy register, then clear the bit in the status register. 5.1.1.2 Typical use of the INT pin The steps below show how interrupts can be handled. Initialization: Step I0 - All Status bits are cleared by writing FFFFFF (Hex) into the Status register. Step I1 - The conditional bits which will be used to generate interrupts are then written to logic 1 in the Mask register. Step I3 - Enable interrupts. 5.1.2 Watch Dog Timer The Watch Dog Timer (WDT) is provided as means of alerting the system that there is a potential breakdown in communication with the micro-controller. By allowing the WDT to cause an interrupt, a controller can be brought back, from some unknown code space, into the proper code for processing the data created by the converter. The time-out is preprogrammed to approximately 5 seconds. The countdown restarts each time the Energy register is read. Under typical situations, the EnerDS279PP5 26 CS5460 gy register is read every second. As a result, the WDT will not time out. Other applications, that want to use the watchdog timer, will need to ensure that the Energy register is read at least once in every 5 second span. The CS5460 can be driven by a clock ranging from 2.5 to 20 MHz Table 2 shows the clock divide value K (default = 1) that the CS5460 needs to be programmed with for normal operation. K CLK (min) MHz 2.5 5 10 CLK (max) MHz 5 10 20 5.2 Oscillator Characteristics XIN and XOUT are the input and output, respectively, of an inverting amplifier to provide oscillation and can be configured as an on-chip oscillator, as shown in Figure 11. The oscillator circuit is designed to work with a quartz crystal or a ceramic resonator. To reduce circuit cost two load capacitors C1 are integrated in the device, one between XIN and DGND, one between XOUT and DGND. Lead lengths should be minimized to reduce stray capacitance. With these load capacitors the oscillator circuit is capable of oscillation up to 20 MHz. To drive the device from an external clock source, XOUT should be left unconnected while XIN is driven by the external circuitry. There is an amplifier between XIN and the digital section which provides CMOS level signals. This amplifier works with sinusoidal inputs so there are no problems with slow edge times. 1 2 4 Table 3. CPU Clock (and K) Restrictions 5.3 Analog Inputs The CS5460 accommodates a full scale range of 150 mVRMS on both input channels. System calibration can be used to increase or decrease the full scale span of the converter as long as the calibration register values stay within the limits specified. See the Calibration section for more details. The current input channel has an input range of 30 mVRMS when the internal x50 gain stage is enabled. This signal range is designed to handle low level signals from a shunt sensor. XOUT C1 Oscillator Circuit XIN C1 DGND C1 = 22 pF Figure 11. Oscillator Connection DS279PP5 27 CS5460 5.4 Voltage Reference The CS5460 is specified for operation with a +2.5 V reference between the VREFIN and VA- pins. The converter includes an internal 2.5 V reference (60 ppm/°C drift) that can be used by connecting the VREFOUT pin to the VREFIN pin of the device. If higher accuracy/stability is required, an external reference can be used. calibration, any initial offset and gain errors in the internal circuitry of the chip will remain. 5.5.1 System Calibration For the system calibration functions, the user must supply the converters calibration signals which represent ground and full scale. When a system offset calibration is performed, a ground reference signal must be applied to the converters. Figure 12 illustrates system offset calibration. As shown in Figure 13, the user must input a signal representing the positive full scale point to perform a system gain calibration. In either case, the calibration signals must be within the specified calibration limits for each specific calibration step (refer to Full Scale DC Calibration Range). 5.5 Performing Calibrations The CS5460 offers two DC calibration modes: system offset and system gain. For system calibration the user must supply the converter calibration signals which represent ground and full scale. The user must provide the positive full scale point to perform a system gain calibration and a ground referenced signal when a system offset is performed. The offset and gain signals must be within the specified calibration limits for each specific calibration step and channel. Since each converter channel has its own offset and gain register associated with it, system offset, or system gain can be performed on either channel without the calibration results from one channel corrupting the other. The Cycle Count register N, determines the number of conversions averaged to obtain the calibration results. The larger N, the higher the accuracy of the calibration results. Once a calibration cycle is complete, DRDY is set and the results are stored in either the gain or offset register. Note that if additional calibrations are performed, the latest calibration results will replace the effects from the previous calibration. In any event, offset and gain calibration steps take one cycle each to complete. After the part is reset, the device is functional and can perform measurements without being calibrated. The converters will utilize the initialized values of the on-chip registers (Gain = 1.0, Offset = 0.0) to calculate power information. Although the device can be used without performing an offset or gain External Connections + AIN+ 0V + CM + AINXGAIN + Figure 12. System Calibration of Offset. External Connections + AIN+ Full Scale + CM + - + XGAIN - AIN- Figure 13. System Calibration of Gain. 28 DS279PP5 CS5460 5.5.2 Calibration Tips To minimize digital noise near the device, the user should wait for each calibration step to be completed before reading or writing to the serial port. After a calibration is performed, the offset and gain register contents can be read by the system micro-controller and recorded in memory. The same calibration words can be uploaded into the offset and gain registers of the converters when power is first applied to the system, or when the gain range on the current channel is changed. An offset calibration must be performed before a gain calibration. Each gain calibration depends on the zero calibration point obtained from the offset calibration. The offset and gain calibration steps each take one conversion cycle to complete. At the end of the calibration step, DRDY is set to indicate that the calibration is complete. Capacitors CPV and CPI should be included to provide for attenuation of high-frequency noise that may be coupled into the input lines. In differential input configurations, such a capacitor should be added to the VIN- and IIN- pins in addition to the VIN+ and IIN+ pins. Values for RPV/I and CPV/I must be chosen with the approximate input lowpass cutoff frequency in mind. In general, the cutoff frequency should not be less than 10 times the roll-off frequencies of the internal voltage/current channel filters (see Figure 6 and Figure 7). From these figures we see that the internal voltage channel roll-off is at ~1400Hz while the current channel roll-off is at ~1600Hz. If the cutoff frequency of the external protection is much less than 10x these values (14000Hz and 16000Hz), then some of the harmonic content in the power signal may start to get attenuated by this input filtering, which is undesirable. The exact values of RPV/I and CPV/I must be calculated for each particular application. The primary goal is to make sure that the input pins never receive transient input currents greater than 100mA. Also, they should never be exposed to DC currents greater than 10mA. The user-supplied protection resistors RPV and RPI will limit the current that comes into the pins in over-voltage--where the internal protection diodes turn on inside the CS5460. For example, suppose that the value for RPI (on the current channel input) was chosen to be 500 Ohms. Then we know that the current channel can withstand brief voltage spikes of up to ~50V (referenced to GND) without damage to the part. This is because 50V / 500Ohm = 100mA. We can also say that the pin can withstand a common mode DC voltage of up to 5V. When computing appropriate values for RPV/I, the differential input impedance of the CS5460’s voltage channel and current channel should also be considered. This is especially true for the current channel, which has a lower differential input im- 5.6 Input Current Protection In Figure 3 and Figure 4, note the series resistor RPI which is connected to the IIN+ input pin. This resistor is used to provide current-limit protection for the current-channel input pin in the event of a power surge or lightening surge. The voltage/current-channel inputs have surge-current limits of 100mA. This applies to brief voltage/current spikes (