CS5460A-BSZ

CS5460A Single Phase, Bi-directional Power/Energy IC Features Energy Data Linearity: ±0.1% of Reading over 1000:1 Dynamic Range. On-Chip Functions: (Real) Energy, I ∗ V, IRMS and VRMS, Energy-to-Pulse Conversion Smart “Auto-boot” Mode from Serial EEPROM Enables Use without MCU. AC or DC System Calibration Mechanical Counter/Stepper Motor Driver Meets Accuracy Spec for IEC 687/1036, JIS Typical Power Consumption OWR = 4000 Sps.)(See Notes 1, 2, 3, 4, and 5.) Parameter Accuracy (Both Channels) Common Mode Rejection Offset Drift (Without the High Pass Filter) Analog Inputs (Current Channel) Maximum Differential Input Voltage Range {(VIIN+) - (VIIN-)} Total Harmonic Distortion Common Mode + Signal on IIN+ or IINInput Capacitance Effective Input Impedance (Gain = 10 or 50) (50, 60 Hz) (Gain = 10) (Gain = 50) (Note 6) (Gain = 10) (Gain = 50) (Gain = 10) (Gain = 50) (Note 1) (Note 1) {(VVIN+) - (VVIN-)} VOSI FSEI VIN THDV (50, 60 Hz) CinV (Note 6) ZinV Cin Crosstalk with Voltage Channel at Full Scale (Gain = 10) (Gain = 50) IIN THDI 80 -0.25 62 VA(Note 1) (Note 1) VOSV FSEV 25 25 30 30 ±0.001 ±0.001 0.2 5 ±0.01 ±0.01 500 100 VA+ -115 20 4 500 VA+ -70 250 mVP-P mVP-P dB V dB pF pF kΩ kΩ µVrms µVrms %F.S. %F.S. mVP-P dB V dB pF MΩ µVrms %F.S. %F.S. (DC, 50, 60 Hz) CMRR 80 5 dB nV/°C Symbol Min Typ Max Unit ZinI ZinI Noise (Referred to Input) Accuracy (Current Channel) Bipolar Offset Error Full-Scale Error Analog Inputs (Voltage Channel) Maximum Differential Input Voltage Range Total Harmonic Distortion Common Mode + Signal on VIN+ or VINCrosstalk with Current Channel at Full Scale Input Capacitance Effective Input Impedance Noise (Referred to Input) Accuracy (Voltage Channel) Bipolar Offset Error Full-Scale Error Notes: 1. Bipolar Offset Errors and Full-Scale Gain Errors for the current and voltage channels refer to the respective Irms Register and Vrms Register output, when the device is operating in ‘continuous computation cycles’ data acquisition mode, after offset/gain system calibration sequences have been executed. These specs do not apply to the error of the Instantaneous Current/Voltage Register output. Specifications guaranteed by design, characterization, and/or test. Analog signals are relative to VA- and digital signals to DGND unless otherwise noted. In requiring VA+ = VD+ =5 V ±10%, note that it is allowable for VA+, VD+ to differ by as much as ±200 mV, as long as VA+ > VD+. Note that “Sps” is an abbreviation for units of “samples per second”. Effective Input Impedance (Zin) is determined by clock frequency (DCLK) and Input Capacitance (IC). Zin = 1/(IC*DCLK/4). Note that DCLK = MCLK / K. 2. 3. 4. 5. 6. DS487F4 5 CS5460A ANALOG CHARACTERISTICS (Continued) Parameter Dynamic Characteristics Phase Compensation Range Input Sample Rate Full Scale DC Calibration Range Channel-to-Channel Time-Shift Error (when PC[6:0] bits are set to “0000000”) High Pass Filter Pole Frequency Power Supplies Power Supply Currents (Active State) IA+ ID+ (VD+ = 5 V) ID+ (VD+ = 3.3 V) PSCA PSCD PSCD PC 56 75 2.3 1.3 2.9 1.7 21 11.6 6.75 10 65 2.45 2.55 25 2.7 mA mA mA mW mW mW µW dB dB dB V V -3 dB (Voltage Channel, 60 Hz) (Both Channels) DCLK = MCLK/K (Note 7) FSCR OWR -2.4 25 DCLK/1024 DCLK/8 1.0 0.5 +2.5 100 ° Sps Sps %F.S. µs Hz High Rate Filter Output Word Rate Symbol Min Typ Max Unit Power Consumption (Note 8) Active State (VD+ = 5 V) Active State (VD+ = 3.3 V) Stand-By State Sleep State (50, 60 Hz) (Gain = 10) (Gain = 50) (50, 60 Hz) (Note 9) (Note 10) (Note 11) Power Supply Rejection Ratio for Current Channel (Note 9) Power Supply Rejection Ratio for Voltage Channel PFMON Power-Fail Detect Threshold PFMON “Power-Restored” Detect Threshold PSRR PSRR PSRR PMLO PMHI Notes: 7. The minimum FSCR is limited by the maximum allowed gain register value. 8. All outputs unloaded. All inputs CMOS level. 9. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV zero-to-peak sinewave (frequency = 60 Hz) is imposed onto the +5 V supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to VA-. Then the CS5460A is commanded to ’continuous computation cycles’ data acquisition mode, and digital output data is collected for the channel under test. The zero-peak value of the digital sinusoidal output signal is determined, and this value is converted into the zero-peak value of the sinusoidal voltage that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB): ⎧ 0.150V ⎫ PSRR = 20 ⋅ log ⎨ ------------------ ⎬ ⎩ V eq ⎭ 10. When voltage level on PFMON is sagging, and LSD bit is 0, the voltage at which LSD bit is set to 1. 11. Assuming that the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), then if/when the PFMON voltage starts to rise again, PMHI is the voltage level (on PFMON pin) at which the LSD bit can be permanently reset back to 0 (without instantaneously changing back to 1). Attempts to reset the LSD bit before this condition is true will not be successful. This condition indicates that power has been restored. Typically, for a given sample, the PMHI voltage will be ~100 mV above the PMLO voltage. 6 DS487F4 CS5460A VREFOUT REFERENCE OUTPUT VOLTAGE Parameter Reference Output Output Voltage VREFOUT Temperature Coefficient (Note 12) Load Regulation (Output Current 1 µA Source or Sink) Reference Input Input Voltage Range Input Capacitance Input CVF Current Symbol REFOUT TVREFOUT ∆ VR VREFIN Min +2.4 +2.4 Typ 30 6 +2.5 4 25 Max +2.6 60 10 +2.6 Unit V ppm/°C mV V pF nA Notes: 12. The voltage at VREFOUT is measured across the temperature range. From these measurements the following formula is used to calculate the VREFOUT Temperature Coefficient:. TVREFOUT = ( (VREFOUTMAX - VREFOUTMIN) VREFOUTAVG )( 1 TAMAX - TAMIN )( 1.0 x 10 6 ) Typ ±1 5 Max 0.8 1.5 0.2 VD+ 0.4 ±10 ±10 Unit V V V V V V V V µA µA pF 5V DIGITAL CHARACTERISTICS (TA = -40 °C to +85 °C; VA+ = VD+ = 5 V ±10% VA-, DGND = 0 V) (See Notes 3, 4, and 13) Parameter High-Level Input Voltage All Pins Except XIN, SCLK and RESET XIN SCLK and RESET Low-Level Input Voltage All Pins Except XIN, SCLK, and RESET XIN SCLK and RESET High-Level Output Voltage (except XOUT) Low-Level Output Voltage (except XOUT) Input Leakage Current High Impedance State Leakage Current Digital Output Pin Capacitance Iout = +5 mA Iout = -5 mA (Note 14) Symbol VIH 0.6 VD+ (VD+) - 0.5 0.8 VD+ VIL VOH VOL Iin IOZ Cout (VD+) - 1.0 Min 13. Note that the 5 V characteristics are guaranteed by characterization. Only the more rigorous 3.3 V digital characteristics are actually verified during production test. 14. Applies to all INPUT pins except XIN pin (leakage current < 50 µA) and MODE pin (leakage current < 25 µA). DS487F4 7 CS5460A 3.3 V DIGITAL CHARACTERISTICS (TA = -40 °C to +85 °C; VA+ = 5 V ±10%, VD+ = 3.3 V ±10%; VA-, DGND = 0 V) (See Notes 3, 4, and 13) Parameter High-Level Input Voltage All Pins Except XIN, XOUT, SCLK, and RESET XIN SCLK and RESET Low-Level Input Voltage All Pins Except XIN, XOUT, SCLK, and RESET XIN SCLK and RESET High-Level Output Voltage (except XIN, XOUT) Iout = +5 mA Low-Level Output Voltage (except XIN, XOUT) Iout = -5 mA Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance (Note 14) Symbol VIH 0.6 VD+ (VD+) - 0.5 0.8 VD+ VIL VOH VOL Iin IOZ Cout (VD+) - 1.0 ±1 5 0.48 0.3 0.2 VD+ 0.4 ±10 ±10 V V V V V µA µA pF V V V Min Typ Max Unit Notes: 15. All measurements performed under static conditions. 16. If VD+ = 3 V and if XIN input is generated using crystal, then XIN frequency must remain between 2.5 MHz - 5.0 MHz. If using oscillator, full XIN frequency range is available, see Switching Characteristics. ABSOLUTE MAXIMUM RATINGS (DGND = 0 V; See Note 17) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter DC Power Supplies (Notes 18 and 19) Positive Digital Positive Analog Negative Analog Symbol VD+ VA+ VAIIN IOUT (Note 23) All Analog Pins All Digital Pins PD VINA VIND TA Tstg Min -0.3 -0.3 +0.3 (VA-) - 0.3 DGND - 0.3 -40 -65 Typ Max +6.0 +6.0 -6.0 ±10 ±25 500 (VA+) + 0.3 (VD+) + 0.3 85 150 Unit V V V mA mA mW V V °C °C Input Current, Any Pin Except Supplies(Note 20, 21, and 22) Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature Notes: 17. 18. 19. 20. 21. 22. 23. 8 All voltages with respect to ground. VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.0 V. VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +6.0 V. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins. Transient current of up to 100 mA will not cause SCR latch-up. Maximum DC input current for a power supply pin is ±50 mA. Total power dissipation, including all input currents and output currents. DS487F4 CS5460A SWITCHING CHARACTERISTICS (TA = -40 °C to +85 °C; VA+ = 5.0 V ±10%; VD+ = 3.0 V ±10% or 5.0 V ±10%; VA- = 0.0 V; Logic Levels: Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50 pF)) Parameter Master Clock FrequencyCrystal/Internal Gate Oscillator (Note 24) Master Clock Duty Cycle CPUCLK Duty Cycle (Note 25) Rise Times Any Digital Input Except SCLK (Note 26) SCLK Any Digital Output Fall Times Any Digital Input Except SCLK (Note 26) SCLK Any Digital Output Start-up Oscillator Start-Up Time XTAL = 4.096 MHz (Note 27) Serial Port Timing Serial Clock Frequency Serial Clock SDI Timing CS Falling to SCLK Rising Data Set-up Time Prior to SCLK Rising Data Hold Time After SCLK Rising SCLK Falling Prior to CS Disable SDO Timing CS Falling to SDI Driving SCLK Falling to New Data Bit CS Rising to SDO Hi-Z Auto-boot Timing Serial Clock MODE setup time to RESET Rising RESET rising to CS falling CS falling to SCLK rising SCLK falling to CS rising CS rising to driving MODE low (to end auto-boot sequence). SDO guaranteed setup time to SCLK rising Pulse Width High Pulse Width Low Symbol MCLK Min 2.5 40 40 200 200 50 50 100 100 Typ 4.096 50 50 60 20 20 20 8 8 50 48 100 50 100 8 16 Max 20 60 60 1.0 100 1.0 100 2 50 50 50 Unit MHz % % µs µs ns µs µs ns ms MHz ns ns ns ns ns ns ns ns ns MCLK MCLK ns MCLK MCLK MCLK ns ns trise tfall tost SCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 Pulse Width High Pulse Width Low Notes: 24. Device parameters are specified with a 4.096 MHz clock, yet, clocks between 3 MHz to 20 MHz can be used. However, for input frequencies over 5 MHz, an external oscillator must be used. 25. If external MCLK is used, then duty cycle must be between 45% and 55% to maintain this specification. 26. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF. 27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. DS487F4 9 10 t 6 t 4 LSB MSB LSB MSB - 1 MSB MSB - 1 CS t3 t1 t2 SCLK t 5 LSB SDI LSB MSB MSB - 1 MSB MSB - 1 Command Time 8 SCLKs High Byte Mid Byte Low Byte SDI Write Timing (Not to Scale) CS t 7 MSB LSB MSB - 1 MSB MSB - 1 High Byte Mid Byte Low Byte t9 LSB MSB MSB - 1 LSB SDO t1 t 8 t2 SCLK Figure 1. CS5460A Read and Write Timing Diagrams LSB SDI MSB MSB - 1 Command Time 8 SCLKs Must strobe "SYNC0" command on SDI when reading each byte of data from SDO. SDO Read Timing (Not to Scale) CS5460A DS487F4 DS487F4 t 16 t 15 t8 t 10 t17 t1 1 t 12 MODE (Input) RES (Input) t 13 (Output) CS t 14 SCLK t5 t4 STOP BIT LAST 8 BITS (Output) SDO (Output) SDI (Input) Data from EEPROM CS5460A Figure 2. CS5460A Auto-boot Sequence Timing 11 CS5460A 2. OVERVIEW The CS5460A is a CMOS monolithic power measurement device with a real power/energy computation engine. The CS5460A combines two programmable gain amplifiers, two ∆Σ modulators, two high rate filters, system calibration, and rms/power calculation functions to provide instantaneous voltage/current/power data samples as well as periodic computation results for real (billable) energy, VRMS, and IRMS. In order to accommodate lower cost metering applications, the CS5460A can also generate pulse-train signals on certain output pins, for which the number of pulses emitted on the pins is proportional to the quantity of real (billable) energy registered by the device. The CS5460A is optimized for power measurement applications and is designed to interface to a shunt or current transformer to measure current, and to a resistive divider or potential transformer to measure voltage. To accommodate various input voltage levels, the current channel includes a programmable gain amplifier (PGA) which provides two full-scale input levels, while the voltage channel’s PGA provides a single input voltage range. With a single +5 V supply on VA+/-, both of the CS5460A’s input channels can accomodate common mode + signal levels between -0.25 V and VA+. The CS5460A includes two high-rate digital filters (one per channel), which decimate/integrate the output from the 2 ∆Σ modulators. The filters yield 24-bit output data at a (MCLK/K)/1024 output word rate (OWR). The OWR can be thought of as the effective sample frequency of the voltage channel and the current channel. To facilitate communication to a microcontroller, the CS5460A includes a simple three-wire serial interface which is SPI™ and Microwire™ compatible. The serial port has a Schmitt Trigger input on its SCLK (serial clock) and RESET pins to allow for slow rise time signals. 2.1.1 ∆Σ Modulators The analog waveforms at the voltage/current channel inputs are subject to the gains of the input PGAs (not shown in Figure 3). These waveforms are then sampled by the delta-sigma modulators at a rate of (MCLK/K)/8 Sps. 2.1.2 High-rate Digital Low-pass Filters The data is then low-pass filtered, to remove high-frequency noise from the modulator output. Referring to Figure 3, the high rate filter on the voltage channel is implemented as a fixed Sinc2 filter. The current channel uses a Sinc4 filter, which allows the current channel to make accurate measurements over a wider span of the total input range, in comparison to the accuracy range of the voltage channel. (This subject is discussed more in Section 2.2.1) Also note from Figure 3 that the digital data on the voltage channel is subjected to a variable time-delay filter. The amount of delay depends on the value of the seven phase compensation bits (see Phase Compensation). Note that when the phase compensation bits PC[6:0] are set to their default setting of “0000000” (and if MCLK/K = 4.096 MHz) then the nominal time delay that is imposed on the original analog voltage input signal, with respect to the original analog current input signal, is ~1.0 µs. This translates into a delay of ~0.0216 degrees at 60 Hz. 2.1.3 Digital Compensation Filters The data from both channels is then passed through two FIR compensation filters, whose purpose is to compensate for the magnitude roll-off of the low-pass filtering operation (mentioned earlier). 2.1.4 Digital High-pass Filters Both channels provide an optional high-pass filter (denoted as “HPF” in Figure 3) which can be engaged into the signal path, to remove the DC content from the current/voltage signal before the RMS/energy calculations are made. These filters are activated by enabling certain bits in the Configuration Register. If the high-pass filter is engaged in only one of the two channels, then the all-pass filter (see “APF” in 2.1 Theory of Operation A computational flow diagram for the two data paths is shown in Fig. 3. The reader should refer to this diagram while reading the following data processing description, which is covered block-by-block. 12 DS487F4 CS5460A VDCoff* V gn * V* VACoff* VOLTAGE ∆Σ DELAY REG SINC 2 DELAY REG FIR HPF + x x - SINC 2 N ÷N V RMS * APF Configuration Register * PC[6:0] Bits Poff* N x TBC * x ÷ 4096 + P* Σ E* E out E dir E to F PULSE-RATE* CURRENT ∆Σ SINC 4 FIR HPF + x I* x - SINC 2 N ÷N I RMS * APF IDCoff* I gn * IACoff* * DENOTES REGISTER NAME Figure 3. Data Flow. Figure 3) will be enabled on the other channel; in order to preserve the relative phase relationship between the voltage-sense and current-sense input signals. For example, if the HPF is engaged for the voltage channel, but not the current channel, then the APF will be engaged in the current channel, to nullify the additional phase delay introduced by the high-pass filter in the current channel. instantaneous voltage/current data samples are multiplied together (one multiplication for each pair of voltage/current samples) to form instantaneous (real) power samples. After each A/D conversion cycle, the new instantaneous power sample is stored in the Instantaneous Power Register. The instantaneous power samples are then grouped into sets of N samples (where N = value in Cycle Count Register). The cumulative sum of each successive set of N instantaneous power is used to compute the result stored in the Energy Register, which will be proportional to the amount of real energy registered by the device during the most recent N A/D conversion cycles. Note from Figure 3 that the bits in this running energy sum are right-shifted 12 times (divided by 4096) to avoid overflow in the Energy Register. RMS calculations are also performed on the data using the last N instantaneous voltage/current samples, and these results can be read from the RMS Voltage Register and the RMS Current Register. 2.1.5 Overall Filter Response When the CS5460A is driven with a 4.096 MHz clock (K = 1), the composite magnitude response (over frequency) of the voltage channel’s input filter network is shown in Figure 4, while the composite magnitude response of the current channel’s input filter network is given in Figure 5. Note that the composite filter response of both channels scales with MCLK frequency and K. 2.1.6 Gain and DC Offset Adjustment After filtering, the instantaneous voltage and current digital codes are subjected to offset/gain adjustments, based on the values in the DC offset registers (additive) and the gain registers (multiplicative). These registers are used for calibration of the device (see Section 3.8, Calibration). After offset and gain, the 24-bit instantaneous data sample values are stored in the Instantaneous Voltage and Current Registers. 2.2 Performing Measurements To summarize Section 2.1, the CS5460A performs measurements of instantaneous current and instantaneous voltage, and from this, performs computations of the corresponding instantaneous power, as well as periodic calculations of real energy, RMS current, and RMS voltage. These measurement/calculation results are available in the form of 24-bit signed and unsigned words. The scaling of all output words is normalized to unity 2.1.7 Real Energy and RMS Computations The digital instantaneous voltage and current data is then processed further. Referring to Figure 3, the DS487F4 13 CS5460A full-scale. Note that the 24-bit signed output words are expressed in two’s complement format. The 24-bit data words in the CS5460A output registers represent values between 0 and 1 (for unsigned output registers) or between -1 and +1 (for signed output registers). A register value of 1 represents the maximum possible value. Note that a value of 1.0 is never actually obtained in the registers of the CS5460A. As an illustration, in any of the signed output registers, the maximum register value is [(2^23 - 1) / (2^23)] = 0.999999880791. After each A/D conversion, the CRDY bit will be asserted in the Status Register, and the INT pin will also become active if the CRDY bit is unmasked (in the Mask Register). The assertion of the CRDY bit indicates that new instantaneous 24-bit voltage and current samples have been collected, and these two samples have also been multiplied together to provide a corresponding instantaneous 24-bit power sample. Table 1 conveys the typical relationship between the differential input voltage (across the “+” and “-” input pins of the voltage channel input) and the corresponding output code in the Instantaneous Voltage Register. Note that this table is applicable for the current channel if the current channel’s PGA gain is set for the “10x” gain mode. Output Code Output Code Input Voltage (DC) (hexidecimal) (decimal) +250 mV 14.9 nV to 44.7 nV -14.9 nV to 14.9 nV -44.7 nV to -14.9 nV -250 mV 7FFFFF 000001 000000 FFFFFF 800000 8388607 1 0 -1 -8388608 Table 1. Differential Input Voltage vs. Output Code The VRMS, IRMS, and energy calculations are updated every N conversions (which is known as 1 “computation cycle”), where N is the value in the Cycle Count Register. At the end of each computation cycle, the DRDY bit in the Mask Register will be set, and the INT pin will become active if the DRDY bit is unmasked. DRDY is set only after each computation cycle has completed, whereas the CRDY bit is asserted after each individual A/D conversion. Bits asserted by the CS5460A must be cleared before being asserted again. If the Cycle Count Register value (N) is set to 1, all output calculations are instantaneous, and DRDY will indicate when instantaneous calculations are finished, just like the CRDY bit. For the RMS results to be valid, the Cycle-Count Register must be set to a value greater than 10. The computation cycle frequency is derived from the master clock, and has a value of (MCLK/K)/(1024*N). Under default conditions, with 0.5 0.5 0 -0.5 0.0 Gain (dB) -0.5 -1.0 Gain (dB) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 -1 -1.5 -2 -2.5 0 -1.5 -2.0 -2.5 Frequency (Hertz) 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (Hertz) Figure 4. Voltage Input Filter Characteristics Figure 5. Current Input Filter Characteristics 14 DS487F4 CS5460A a 4.096 MHz clock at XIN, and K = 1, instantaneous A/D conversions for voltage, current, and power are performed at a 4000 Sps rate, whereas IRMS, VRMS, and energy calculations are performed at a 1 Sps rate. cle), the voltage level of this signal would exceed the maximum differential input voltage range of the input channels. The largest sine wave voltage signal that can be presented across the inputs, with no saturation of the inputs, is: 250 mV / sqrt(2) = ~176.78 mV (RMS), which is ~70.7% of full-scale. This would imply that for the current channel, the (linearity+variation) tolerance of the RMS measurements for a purely sinusoidal 60 Hz input signal could be measured to within ±0.1% of reading over a magnitude range of 0.2% - 70.7% of the maximum full-scale differential input voltage level. The range over which the (linearity + variation) will remain within ±0.1% can often be increased by selecting a value for the Cycle-Count Register such that the time duration of one computation cycle is equal to (or very close to) a whole-number of power-line cycles (and N must be greater than or equal to 4000). For example, with the cycle count set to 4200, the ±0.1% of reading (linearity + variation) range for measurement of a 60 Hz sinusoidal current-sense voltage signal can be increased beyond the range of 0.2% - 70.7%. The accuracy range will be increased because (4200 samples / 60 Hz) is a whole number of cycles (70). Note that this increase in the measurement range refers to an extension of the low end of the input scale (i.e., this does not extend the high-end of the range above 100% of full-scale). This enables accurate measurement of even smaller power-line current levels, thereby extending the load range over which the power meter can make accurate energy measurements. Increasing the accuracy range can be beneficial for power metering applications which require accurate power metering over a very large load range. 2.2.1 CS5460A Linearity Performance Table 2 lists the range of input levels (as a percentage of full-scale) over which the (linearity + variation) of the results in the Vrms, Irms and Energy Registers are guaranteed to be within ±0.1 % of reading after the completion of each successive computation cycle. Note that until the CS5460A is calibrated (see Calibration) the accuracy of the CS5460A with respect to a reference line-voltage and line-current level on the power mains is not guaranteed to within ±0.1%. After both channels of the device are calibrated for offset/gain, the ±0.1% of reading spec will also reflect accuracy of the Vrms, Irms, and Energy Register results. Finally, observe that the maximum (full-scale) differential input voltage for the voltage channel (and current channel, when its PGA is set for 10x gain) is 250 mV (nominal). If the gain registers of both channels are set to 1 (default) and the two DC offset registers are set to zero (default), then a 250mV DC signal applied to the voltage/current inputs will measure at (or near) the maximum value of 0.9999... in the RMS Current/Voltage Registers. Remember that the RMS value of a 250 mV (DC) signal is also 250 mV. However, for either input channel, it would not be practical to inject a sinusoidal voltage with RMS value of 250 mV. This is because when the instantaneous value of such a sine wave is at or near the level of its positive/negative peak regions (over each cy- Energy Vrms 50% - 100% V-channel: ±250 mV Irms 0.2% - 100% I-channel: ±250 mV 10x ±50 mV 50x 2.2.2 Single Computation Cycle (C=0) Note that ‘C’ refers to the value of the C bit, contained in the ‘Start Conversions’ command (see Section 4.1). This commands instructs the CS5460A to perform conversions in ‘single computation cycle’ data acquisition mode. Based on the value in the Cycle Count Register, a single computation cycle is performed after a ‘Start Conversions’ command is sent to the serial interface. After the computations are complete, DRDY is set. 32 SCLKs are then needed to read out a calculation 15 Range (% of FS) Max. Differential Input Linearity 0.1% - 100% not applicable 0.1% of reading 0.1% of reading 0.1% of reading Table 2. Available range of ±0.1% output linearity, with default settings in the gain/offset registers. DS487F4 CS5460A result from one of several result registers. The first 8 SCLKs are used to clock in the command to determine which register is to be read. The last 24 SCLKs are used to read the desired register. After reading the data, the serial port remains in the active state, and waits for a new command to be issued. (See Section 3 for more details on reading register data from the CS5460A). cycles data acquisition mode, the CS5460A will continue to perform A/D conversions on the voltage/current channels, as well as all subsequent calculations, until: 1) the ‘Power-Up/Halt’ command is received through the serial interface, or 2) loss of power, or 3) the RS bit in the Configuration Register is asserted (‘software reset’), or 4) the /RESET pin is asserted and then de-asserted (‘hardware reset’). 2.2.3 Continuous Computation Cycles (C=1) When C = 1, the CS5460A will perform conversions in ‘continuous computation cycles’ data acquisition mode. Based on the information provided in the Cycle Count Register, computation cycles are repeatedly performed on the voltage and current channels (after every N conversions). Computation cycles cannot be started/stopped on a ‘per-channel’ basis. After each computation cycle is completed, DRDY is set. Thirty-two SCLKs are then needed to read a register. The first 8 SCLKs are used to clock in the command to determine which results register is to be read. The last 24 SCLKs are used to read out the 24-bit calculation result. While in this acquisition mode, the designer/programmer may choose to acquire (read) only those calculations required for their particular application, as DRDY repeatedly indicates the availability of new data. Note again that the MCU firmware must reset the DRDY bit to “0” before it can be asserted again. Referring again to Figure 3, note that within the Irms and Vrms data paths, prior to the square-root operation, the instantaneous voltage/current data is low-pass filtered by a Sinc2 filter. Then the data is decimated to every Nth sample. Because of the Sinc2 filter operation, the first output for each channel will be invalid (i.e. all RMS calculations are invalid in the ‘single computation cycle’ data acquisition mode and the first RMS calculation results will be invalid in the ‘continuous computation cycles’ data acquisition mode). However, all energy calculations will be valid since energy calculations do not require this Sinc2 operation. If the ’Start Conversions’ command is issued to the CS5460A (see Section 4.1, Commands (Write Only)), and if the ‘C’ bit in this command is set to a value of ‘1’, the device will remain in its active state. Once commanded into continuous computation 2.3 Basic Application Circuit Configurations Figure 6 shows the CS5460A connected to a service to measure power in a single-phase 2-wire system operating from a single power supply. Note that in this diagram the shunt resistor used to monitor the line current is connected on the “Line” (hot) side of the power mains. In most residential power metering applications, the power meter’s current-sense shunt resistor is intentionally placed on the ‘hot’ side of the power mains in order to help detect any attempt by the subscriber to steal power. In this type of shunt-resistor configuration, note that the common-mode level of the CS5460A must be referenced to the hot side of the power line. This means that the common-mode potential of the CS5460A will typically oscillate to very high positive voltage levels, as well as very high negative voltage levels, with respect to earth ground potential. The designer must therefore be careful when attempting to interface the CS5460A’s digital output lines to an external digital interface (such as a LAN connection or other communication network). Such digital communication networks may require that the CMOS-level digital interface to the meter is referenced to an earth-ground. In such cases, the CS5460A’s digital serial interface pins must be isolated from the external digital interface, so that there is no conflict between the ground references of the meter and the external interface. The CS5460A and associate circuitry should be enclosed in a protective insulated case when used in this configuration, to avoid risk of harmful electric shock to humans/animals/etc. Figure 7 shows how the same single-phase two-wire system can be metered while achieving DS487F4 16 CS5460A complete isolation from the power lines. This isolation is achieved using three transformers. One transformer is a general-purpose voltage transformer, used to supply the on-board DC power to the CS5460A. A second transformer is a high-precision, low-impedance voltage transformer (often called a ‘potential transformer’) with very little roll-off/phase delay, even at the higher harmonics. A current transformer is then used to sense the line current. A burden resistor placed across the secondary of the current transformer creates the current-sense voltage signal, for the CS5460A’s current channel inputs. Because the CS5460A is not directly connected to the power mains, isolation is not required for the CS5460A’s digital interface. Figure 8 shows the CS5460A configured to measure power in a single-phase 3-wire system. In many 3-wire residential power systems within the United States, only the two Line terminals are available (neutral is not available). Figure 9 shows how the CS5460A can be configured to meter a 3-wire system when no neutral is available. 5 kΩ N 120 VAC 10 kΩ L 500 Ω 470 nF 500 Ω + 100 µF 0.1 µF 10 Ω 0.1 µF 14 VA+ 3 VD+ CS5460A 9 C* * V+ R2 R1 VIN+ C* * Vdiff 10 15 17 PFMON 2 CPUCLK 1 XOUT 24 2.5 MHz to 20 MHz Optional Clock Source R* V- C* * V- VINIIN- XIN R* IRShunt R* I+ C* * I* C*Idiff NOTE: Current channel input measures voltage (just like voltage input). RESET 19 ISOLATION Serial Data Interface 16 C* * I+ 12 11 IIN+ VREFIN VREFOUT VA13 0.1 µF 7 CS 23 SDI 6 SDO 5 SCLK 20 INT 22 EDIR 21 EOUT DGND 4 To Service * Refer to Input Protection ** Refer to Input Filtering Mech. Counter or Stepper Motor Figure 6. Typical Connection Diagram (One-Phase 2-Wire, Direct Connect to Power Line) DS487F4 17 CS5460A 5 kΩ L Voltage Transformer 12 VAC 120 VAC 10 kΩ N 200 Ω + 200 Ω 0.1µF 200µF 14 VA+ 10 Ω 0.1 µF 3 VD+ 12 VAC CS5460A M:1 1kΩ R* V+ C* * V+ C* * Vdiff 10 9 VIN+ 17 PFMON 2 CPUCLK 1 XOUT 24 2.5 MHz to 20 MHz Optional Clock Source 1kΩ Low Phase-Shift Potential Transformer C* * VR* VR* I1kΩ C* * I+ VIN- XIN N:1 15 C* * Idiff 16 12 11 IINNOTE: Current channel input measures voltage (just like voltage input). RESET 19 Serial Data Interface RBurden 1kΩ Current Transformer C* * IR* I+ IIN+ VREFIN VREFOUT VA13 7 CS 23 SDI 6 SDO 5 SCLK 20 INT 0.1 µF 22 EDIR 21 EOUT DGND 4 To Service * Refer to Input Protection ** Refer to Input Filtering Mech. Counter or Stepper Motor Figure 7. Typical Connection Diagram (One-Phase 2-Wire, Isolated from Power Line) 18 DS487F4 CS5460A 240 VAC 120 VAC 120 VAC 5 kΩ L2 500 Ω + 10 kΩ L1 N 500 Ω 0.1 µF 10 Ω 0.1 µF 470 nF Earth Ground 100 µF 14 VA+ 3 VD+ CS5460A 9 C ** V+ R3 R2 R1 1kΩ VIN+ R4 ** CV- C* * Vdiff 17 PFMON 2 CPUCLK 1 XOUT 24 2.5 MHz to 20 MHz Optional Clock Source 10 C ** I+ VIN16 IIN+ XIN * R I+ RBurden 1kΩ C* * Idiff NOTE: Current channel input measures voltage (just like voltage input). RESET 19 Serial Data Interface C ** IR* I- 15 IIN- 12 VREFIN 11 VREFOUT 0.1 µF VA13 7 CS 23 SDI 6 SDO 5 SCLK 20 INT 22 EDIR 21 EOUT DGND 4 To Service To Service * Refer to Input Protection ** Refer to Input Filtering Mech. Counter or Stepper Motor Figure 8. Typical Connection Diagram (One-Phase 3-Wire) DS487F4 19 CS5460A 240 VAC 5 kΩ L2 1 kΩ + 10 kΩ L1 500 Ω 0.1 µF 10 Ω 0.1 µF 235 nF 100 µF 14 VA+ 3 VD+ CS5460A 9 C* * V+ R1 R2 R* V** CVC* * Vdiff VIN+ 17 PFMON 2 CPUCLK 1 XOUT 24 2.5 MHz to 20 MHz Optional Clock Source 10 C ** I+ VIN16 IIN+ RBurden 1kΩ XIN R* I+ C* * Idiff 1kΩ ISOLATION NOTE: Current channel input measures voltage (just like voltage input). C ** IR* I- 15 12 11 IINVREFIN VREFOUT VA13 RESET 19 7 CS 23 SDI 6 SDO 5 SCLK 20 INT EDIR 22 21 Serial Data Interface 0.1 µF EOUT DGND 4 To Service To Service * Refer to Input Protection ** Refer to Input Filtering Mech. Counter or Stepper Motor Figure 9. Typical Connection Diagram (One-Phase 3-Wire - No Neutral Available) 20 DS487F4 CS5460A 3. FUNCTIONAL DESCRIPTION 3.1 Pulse-Rate Output As an alternative to reading the real energy through the serial port, the EOUT and EDIR pins provide a simple interface with which signed energy can be accumulated. Each EOUT pulse represents a predetermined quantity of energy. The quantity of energy represented in one pulse can be varied by adjusting the value in the Pulse-Rate Register. Corresponding pulses on the EDIR output pin signify that the sign of the energy is negative. Note that these pulses are not influenced by the value of the Cycle-Count Register, and they have no reliance on the computation cycle, described earlier. With MCLK = 4.096 MHz, K = 1, the pulses will have an average frequency (in Hz) equal to the frequency setting in the Pulse Rate Register when the input signals into the voltage and current channels cause full-scale readings in the Instantaneous Voltage and Current Registers. When MCLK/K is not equal to 4.096 MHz, the pulse-rate should be scaled by a factor of 4.096 MHz / (MCLK/K) to get the actual output pulse-rate. EXAMPLE #1: For a power line with maximum rated levels of 250 V (RMS) and 20 A (RMS), the pulse-frequency on the EOUT pin needs to be ‘IR’ = 100 pulses-per-second (100 Hz) when the RMS-voltage and RMS-current levels on the power line are 220 V and 15 A respectively. To meet this requirement, the pulse-rate frequency (‘PR’) in the Pulse-Rate Register must be set accordingly. After calibration, the first step to finding the value of ‘PR’ is to set the voltage and current sensor gain constants, KV and KI, such that there will be acceptable voltage levels on the CS5460A inputs when the power line voltage and current levels are at the maximum values of 250 V and 20 A. KV and KI are needed to determine the appropriate ratios of the voltage/current transformers and/or shunt resistor values to use in the front-end voltage/current sensor networks. For a sinewave, the largest RMS value that can be accurately measured (without over-driving the inputs) will register ~0.7071 of the maximum DC input level. Since power signals are often not perfectly sinusoidal in real-world situations, and to provide for some over-range capability, the RMS Voltage Register and RMS Current Register is set to measure 0.6 when the RMS-values of the line-voltage and line-current levels are 250 V and 20 A. Therefore, when the RMS registers measure 0.6, the voltage level at the inputs will be 0.6 x 250 mV = 150 mV. The sensor gain constants, KV and KI, are determined by demanding that the voltage and current channel inputs should be 150 mV RMS when the power line voltage and current are at the maximum values of 250 V and 20 A. KV = 150 mV / 250 V = 0.0006 KI = 150 mV / 20 A = 0.0075 Ω These sensor gain constants are used to calculate what the input voltage levels will be on the CS5460A inputs when the line-voltage and line-current are 220 V and 15 A. These values are VVnom and VInom. VVnom = KV * 220 V = 132 mV VInom = KI * 15 A = 112.5 mV The pulse rate on EOUT will be at ‘PR’ pulses per second (Hz) when the RMS-levels of voltage/current inputs are at 250 mV. When the voltage/current inputs are set at VVnom and VInom, the pulse rate needs to be ‘IR’ = 100 pulses per second. IR will be some percentage of PR. The percentage is defined by the ratios of VVnom/250 mV and VInom/250 mV with the following formula: V Vnom V Inom PulseRate = IR = PR ⋅ ------------------ ⋅ -----------------250mV 250mV From this equation the value of ‘PR’ is shown as:. 100Hz IR PR = ------------------------------------------- = ----------------------------------------------132mV 112.5mV V Vnom V Inom ----------------- × -------------------------------------- × ----------------250mV 250mV 250mV 250mV Therefore the Pulse-Rate Register is set to ~420.875 Hz, or 0x00349C. The above equation is valid when current channel is set to x10 gain. If current channel gain is set to x50, then the equation becomes: IR P R = ---------------------------------------V Vnom V Inom ----------------- × -------------250mV 50mV DS487F4 21 CS5460A EXAMPLE #2: The required number of pulses per unit energy present at EOUT is specified to be 500 pulses/kW-hr; given that the maximum line-voltage is 250 V (RMS) and the maximum line-current is 20 A (RMS). In such a situation, the nominal line voltage and current do not determine the appropriate pulse-rate setting. Instead, the maximum line levels must be considered. As before, the given maximum line-voltage and line-current levels are used to determine KV and KI: KV = 150 mV / 250 V = 0.0006 KI = 150 mV / 20 A = 0.0075 Ω Again the sensor gains are calculated such that the maximum line-voltage and line-current levels will measure as 0.6 in the RMS Voltage Register and RMS Current Register. The required Pulse-Rate Register setting is now determined by using the following equation: pulses 1hr 1kW 250mV 250mV PR = 500 ------------------ ⋅ ------------- ⋅ ----------------- ⋅ ----------------- ⋅ ----------------KI kW ⋅ hr 3600s 1000W KV of the other two formats, the time duration and/or the relative timing of the EOUT and EDIR pulses is increased/varied such that the pulses can drive either an electro-mechanical counter or a stepper motor. The EOUT and EDIR output pins are capable of driving certain low-voltage/low-power counters/stepper motors directly. This depends on the drive current and voltage level requirements of the counter/motor. The ability to set the pulse output format to one of the three available formats is controlled by setting certain bits in the Control Register. 3.2.1 Normal Format Referring to the description of the Control Register in Section 5., Register Descriptions, if both the MECH and STEP bits are set to ‘0’, the pulse output format at the EOUT and EDIR pins is illustrated in Figure 10. These are active-low pulses with very short duration. The pulse duration is an integer multiple of MCLK cycles, approximately equal to 1/16 of the period of the contents of the Pulse-Rate Register. However for Pulse-Rate Register settings less than the sampling rate (which is [MCLK/8]/1024), the pulse duration will remain at a constant duration, which is equal to the duration of the pulses when the Pulse-Rate Register is set to [MCLK/K]/1024. The maximum pulse frequency from the EOUT pin is therefore [MCLK/K]/16. When energy is positive, EDIR is always high. When energy is negative, EDIR has the same output as EOUT. When MCLK/K is not equal to 4.096 MHz, the true pulse-rate can be found by first calculating what the pulse-rate would be if a 4.096 MHz crystal is used (with K = 1) and then scaling the result by a factor of (MCLK/K) / 4.096 MHz. When set to run in Normal pulse output format, the pulses may be sent out in “bursts” depending on both the value of the Pulse-Rate Register as well as the amount of billable energy that was registered by the CS5460A over the most recent A/D sampling period, which is (in Hz): 1 / [(MCLK/K) / 1024]. A running total of the energy accumulation is maintained in an internal register (not accessible to the user) inside the CS5460A. If the amount of energy that has accumulated in this register over the most recent A/D sampling period is equal to or greater than the amount of energy that is repreDS487F4 Therefore PR = ~1.929 Hz. Note that the Pulse-Rate Register cannot be set to a frequency of exactly 1.929 Hz. The closest setting that the Pulse-Rate Register can obtain is 0x00003E = 1.9375 Hz. To improve the accuracy, either gain register can be programmed to correct for the round-off error in PR. This value would be calculated as PR Ign or Vgn = ------------ ≅ 1.00441 = 0x404830 1.929 In the last example, suppose a value for MCLK/K of 3.05856 MHz. When MCLK/K is not equal to 4.096 MHz, the result for ‘PR’ that is calculated for the Pulse-Rate Register must be scaled by a correction factor of: 4.096 MHz / (MCLK/K). In this case the result is scaled by 4.096/3.05856 to get a final PR result of ~2.583 Hz. 3.2 Pulse Output for Normal Format, Stepper Motor Format and Mechanical Counter Format The duration and shape of the pulse outputs at the EOUT and EDIR pins can be set for three different output formats. The default setting is for Normal output pulse format. When the pulse is set to either 22 CS5460A 128 ms EOUT EDIR ... ... Positive Energy 128 ms ... ... Negative Energy Figure 11. Mechanical Counter Format on EOUT and EDIR sented by one pulse, the CS5460A will issue a “burst” of one or more pulses on EOUT (and also possibly on EDIR). The CS5460A will issue as many pulses as are necessary to reduce the running energy accumulation value in this register to a value that is less than the energy represented in one pulse. If the amount of energy that has been registered over the most recent sampling period is large enough that it cannot be expressed with only one pulse, then a burst of pulses will be issued, possibly followed by a period of time during which there will be no pulses, until the next A/D sampling period occurs. After the pulse or pulses are issued, a certain residual amount of energy may be left over in this internal energy accumulation register, which is always less (in magnitude) than the amount of energy represented by one pulse. In this situation, the residual energy is not lost or discarded, but rather it is maintained and added to the energy that is accumulated during the next A/D conversion cycle. The amount of residual energy that can be left over becomes larger as the Pulse-Rate Register is set to lower and lower values, because lower Pulse-Rate Register values correspond to a higher amount of energy per pulse (for a given calibration). 3.2.2 Mechanical Counter Format Setting the MECH bit in the Control Register to ‘1’ and the STEP bit to ‘0’ enables wide-stepping pulses for mechanical counters and similar discrete counter instruments. In this format, active-low pulses are 128 ms wide when using a 4.096 MHz crystal and K = 1. When energy is positive, the pulses appear on EOUT. When energy is negative, pulses appear on EDIR. To insure that pulses will not occur at a rate faster than the 128 ms pulse duration, or faster than the mechanical counter can accommodate, the Pulse-Rate Register should be set to an appropriate value. Because the duration of each pulse is set to 128 ms, the maximum output pulse frequency is limited to ~7.8 Hz (for MCLK/K = 4.096 MHz). For values of MCLK / K different than 4.096 MHz, the duration of one pulse is (128 * 4.096 MHz) / (MCLK / K) milliseconds. See Figure 11 for a diagram of the typical pulse output. 3.2.3 Stepper Motor Format Setting the STEP bit in the Control Register to ‘1’ and the MECH bit to ‘0’ transforms the EOUT and EDIR pins into two stepper motor phase outputs. When enough energy has been registered by the CS5460A to register one positive/negative energy Negative Energy Burst Positive Energy Burst EOUT EDIR ... ... t ... ... t = P u lse -R a te R e g iste r P eriod 16 = n 2 x (MCLK / K) fo r In te ge r n Figure 10. Time-plot representation of pulse output for a typical burst of pulses (Normal Format) DS487F4 23 CS5460A pulse, one of the output pins (either EOUT or EDIR) changes state. When the CS5460A must issue another energy pulse, the other output changes state. The direction the motor will rotate is determined by the order of the state changes. ... ... Positive Energy Negative Energy When energy is positive, EOUT will lead EDIR such that the EOUT pulse train will lead the EDIR pulse train by ~1/4 of the periods of these two pulse train signal. When energy is negative, EDIR will lead EOUT in a similar manner. See Figure 12. ... ... EOUT EDIR Figure 12. Stepper Motor Format on EOUT and EDIR 3.3 Auto-boot Mode Using EEPROM The CS5460A has a MODE pin. When the MODE pin is set to logic low, the CS5460A is in normal operating mode, called host mode. This mode denotes the normal operation of the part, that has been described so far. But when this pin is set to logic high, the CS5460A auto-boot mode is enabled. In auto-boot mode, the CS5460A is configured to request a memory download from an external serial EEPROM. The download sequence is initiated by driving the RESET pin to logic high. Auto-boot mode allows the CS5460A to operate without the need for a microcontroller. Note that if the MODE pin is left unconnected, it will default to logic low because of an internal pull-down on the pin. VD+ /EOUT /EDIR 5K 3.3.1 Auto-boot Configuration Figure 13 shows the typical connections between the CS5460A and a serial EEPROM for proper auto-boot operation. In this mode, CS and SCLK are driven outputs. SDO is always an output. During the auto-boot sequence, the CS5460A drives CS low, provides a clock output on SCLK, and drives out-commands on SDO. It receives the EEPROM data on SDI. The serial EEPROM must be programmed with the user-specified commands and register data that will be used by the CS5460A to change any of the default register values (if desired) and begin conversions. Figure 13 also shows the external connections that would be made to a calibrator device, such as a PC Mech. Counter or Stepper Motor CS5460A SCK SDI SDO MODE /CS 5K EEPROM SCK SO SI /CS Connector to Calibrator Figure 13. Typical Interface of EEPROM to CS5460A 24 DS487F4 CS5460A or custom calibration board. When the metering system is installed, the calibrator would be used to control calibration and/or to program user-specified commands and calibration values into the EEPROM. The commands/data will determine the CS5460A’s exact operation, when the auto-boot initialization sequence is running. Any of the valid commands can be used. Register. 4C 00 00 14 74 00 00 04 E8 78 00 01 40 ;Set Pulse Rate Register to 0.625 Hz. ;Unmask bit #2 (“LSD” bit in the Mask Register). ;Start performing continuous computation cycles. ;Write STOP bit to Control Register, to terminate auto-boot initialization sequence, and also set the EOUT pulse output to Mechanical Counter Format. 3.3.2 Auto-boot Data for EEPROM This section illustrates what a typical set of code would look like for an auto-boot sequence. This code is what would be written into the EEPROM. In the sequence below, the EEPROM is programmed so that it will first send out commands that write calibration values to the calibration registers inside the CS5460A. This is followed by the commands used to set (write) the desired Pulse-Rate Register value, and also to un-mask the ‘LSD’ status bit in the Mask Register. Finally, the EEPROM code will initiate ‘continuous computation cycles’ data acquisition mode and select one of the alternate pulse-output formats (e.g., set the MECH bit in the Control Register). The serial data for such a sequence is shown below in single-byte hexidecimal notation: 40 00 00 61 ;Write to Configuration Register, turn high-pass filters on, set K = 1. ;Write value of 0x7FC4A9 to Current Channel Gain Register. ;Write value of 0x7FB253 to Voltage Channel DC Offset This data from the EEPROM will drive the SDI pin of the CS5460A during the auto-boot sequence. The following sequence of events will cause the CS5460A to execute the auto-boot mode initialization sequence: (A simple timing diagram for this sequence is shown below in Figure 14.) If the MODE pin is set to logic high (or if the MODE pin was set/tied to logic high during/after the CS5460A has been powered on), then changing the RESET pin from active state to inactive state (low to high) will cause the CS5460A to drive the CS pin low, and after this, to issue the standard EEPROM block-read command on the CS5460A’s SDO line. Once these events have completed, the CS5460A will continue to issue SCLK pulses, to accept data/commands from the EEPROM. The serial port will become a master-mode interface. For a more detailed timing diagram, see Switching Characteristics (in Section 1.) 44 7F C4 A9 46 7F B2 53 MODE RES CS SCLK SDO SDI 5460A Commands Stop EE Read Address 0 Figure 14. Timing Diagram for Auto-boot Sequence DS487F4 25 CS5460A 3.3.3 Application Note AN225 For more information on Auto-boot mode, see the AN225, “USING THE CS5460A AUTO-BOOT MODE”. Step H3 - Clear the Status Register by writing back the value read in step H0. Step H4 - Re-enable interrupts. Step H5 - Return from interrupt service routine. This handshaking procedure insures that any new interrupts activated between steps H0 and H3 are not lost (cleared) by step H3. 3.4 Interrupt and Watchdog Timer 3.4.1 Interrupt The INT pin is used to indicate that an event has taken place in the CS5460A that (may) need attention. These events inform the meter system about operation conditions and internal error conditions. The INT signal is created by combining the Status Register with the Mask Register. Whenever a bit in the Status Register becomes active, and the corresponding bit in the Mask Register is a logic 1, the INT signal becomes active. 3.4.1.3 INT Active State The behavior of the INT pin is controlled by the SI1 and SI0 bits of the Configuration Register. The pin can be active low (default), active high, active on a return to logic 0 (pulse-low), or active on a return to logic 1 (pulse-high). If the interrupt output signal format is set for either active-high or active-low assertion, the interrupt condition is cleared when the bits of the Status Register are returned to their inactive state. If the interrupt output signal format is set for either pulse-high or pulse-low, note that the duration of the INT pulse will be at least one MCLK/K cycle, although in some cases the pulse may last for 2 MCLK/K cycles. 3.4.1.1 Clearing the Status Register Unlike the other registers, the bits in the Status Register can only be cleared (set to logic 0). When a word is written to the Status Register, any 1s in the word will cause the corresponding bits in the Status Register to be cleared. The other bits of the Status Register remain unchanged. This allows the clearing of particular bits in the register without having to know the state of the other bits. This mechanism is designed to facilitate handshaking and to minimize the risk of losing events that haven’t been processed yet. 3.4.1.4 Exceptions The IC (Invalid Command) bit of the Status Register can only be cleared by performing the port initialization sequence. This is also the only Status Register bit that is active low. To properly clear the WDT (Watch Dog Timer) bit of the Status Register, first read the Energy Register, then clear the bit in the Status Register. 3.4.1.2 Typical use of the INT pin The steps below show how interrupts can be handled by the on-board MCU. • Initialization: Step I0 - All Status bits are cleared by writing FFFFFF (Hex) into the Status Register. Step I1 - The conditional bits which will be used to generate interrupts are then written to logic 1 in the Mask Register. Step I2 - Enable interrupts. • Interrupt Handler Routine: Step H0 - Read the Status Register. Step H1 - Disable all interrupts. Step H2 - Branch to the proper interrupt service routine. 3.4.2 Watch Dog Timer The Watch Dog Timer (WDT) is provided as a means of alerting the system that there is a potential breakdown in communication with the microcontroller. By allowing the WDT to cause an interrupt, a controller can be brought back, from some unknown code space, into the proper code for processing the data created by the converter. The time-out is preprogrammed to approximately 5 seconds. The countdown restarts each time the Energy Register is read. Under typical situations, the Energy Register is read every second. As a result, the WDT will not time out. Other applications that use the watchdog timer will need to ensure 26 DS487F4 CS5460A that the Energy Register is read at least once in every 5 second span. 3.6 Analog Inputs The CS5460A accommodates a full-scale differential input voltage range of ±250 mV on both input channels. (If the PGA setting on the current channel is set for the 50x gain setting instead of the 10x gain setting, then the differential full-scale input range on the current channel reduces to ±50 mV.) System calibration can be used to increase or decrease the full scale span of the converter as long as the calibration register values stay within the limits specified. See Section 3.8, Calibration, for more details. 3.5 Oscillator Characteristics XIN and XOUT are the input and output, respectively, of an inverting amplifier to provide oscillation and can be configured as an on-chip oscillator, as shown in Figure 15. The oscillator circuit is designed to work with a quartz crystal or a ceramic resonator. To reduce circuit cost, two load capacitors C1 are integrated in the device, one between XIN and DGND, one between XOUT and DGND. Lead lengths should be minimized to reduce stray capacitance. To drive the device from an external clock source, XOUT should be left unconnected while XIN is driven by the external circuitry. There is an amplifier between XIN and the digital section which provides CMOS level signals. This amplifier works with sinusoidal inputs so there are no problems with slow edge times. The CS5460A can be driven by a clock ranging from 2.5 to 20 MHz. The K divider must be set to the appropriate value such that MCLK/K will be between 2.5 MHz and 5 MHz. The K divider value is set with the K[3:0] bits in the Configuration Register. As an example, if XIN = MCLK = 15 MHz, and K is set to 5, then MCLK/K = 3 MHz, which is a valid value for MCLK/K. Note that if the K[3:0] bits are all set to zero, the value of the K divider value is 16. 3.7 Voltage Reference The CS5460A is specified for operation with a +2.5 V reference between the VREFIN and VApins. A reference voltage must be supplied to the VREFIN pin for proper operation of the two ADCs. The CS5460A includes an internal 2.5 V reference, available on the VREFOUT pin, that can be used as the reference input voltage by connecting the VREFOUT pin to the VREFIN pin. If lower temperature drift is desired, an external reference can be used; in which case the VREFOUT pin should be left unconnected. 3.8 Calibration 3.8.1 Overview of Calibration Process The CS5460A offers digital calibration. Each calibration sequence will be executed by setting/clearing one or more of the 8 bits in the calibration command word. For both channels, there are calibration sequences for both AC and DC purposes. Regardless of whether an AC or DC calibration sequence is desired, there are two basic types of calibrations: system offset and system gain. During the calibration sequences, proper input calibration signals to the “+” and “-” pins of the voltage-/current-channel inputs must be supplied. These input calibration signals represent full-scale levels (for gain calibrations) and ground input levels (for offset calibrations). The AC and DC calibration sequences are different. Depending on the specific metering application and accuracy requirements, some or all of the calibration sequences may not be executed. (This XOUT C1 Oscillator Circuit XIN C2 DGND C1 = C2 = 22 pF Figure 15. Oscillator Connection DS487F4 27 CS5460A is explained in more detail in the following paragraphs). sults in the gain registers reflect either the AC or DC gain calibration results, whichever was performed most recently. Therefore, both a DC and AC offset can be applied to a channel at the same time, but only one gain calibration can be applied to each channel. Either AC or DC gain calibration can be used, but not both. For both the voltage channel and the current channel, while the AC offset calibration sequence performs an entirely different function than the DC offset calibration sequence, the AC gain and DC gain calibration sequences perform the same function (but they accomplish the function using different techniques). Since both the voltage and current channels have separate offset and gain registers associated with them, system offset or system gain can be performed on either channel without the calibration results from one channel affecting the other. 3.8.2 The Calibration Registers Refer to Figure 3 and Figure 21. Voltage Channel DC Offset Register and Current Channel DC Offset Register - Store additive correction values that are used to correct for DC offsets which may be present on the voltage/current channels within the entire meter system. These registers are updated by the CS5460A after a DC offset calibration sequence has been executed. Voltage Channel Gain Register and Current Channel Gain Register - Store the multiplicative correction values determined by the full-scale gain calibration signals that are applied to the meter’s voltage/current channels. These registers are updated by the CS5460A after either an AC or DC gain calibration sequence has been executed. Voltage Channel AC Offset Register and Current Channel AC Offset Register - Store additive offset correction values that are used to correct for AC offsets which may be created on the voltage/current channels within the entire meter system. Although a noise signal may have an average value of zero [no DC offset] the noise may still have a non-zero rms value, which can add an undesirable offset in the CS5460A’s Irms and Vrms results. These registers are updated by the CS5460A after an AC offset calibration sequence has been executed. Referring to Figure 3, one should note that the AC offset registers affect the output results differently than the DC offset registers. The DC offset values are applied to the voltage/current signals very early in the signal path; the DC offset register value affects all CS5460A results. This is not true for the AC offset correction. The AC offset registers only affect the results of the rms-voltage/rms-current calculations. Referring to Figure 3, the reader should note that there are separate calibration registers for the AC and DC offset corrections (for each channel). This is not true for gain corrections, as there is only one gain register per channel--AC and DC gain calibration results are stored in the same register. The re- 3.8.3 Calibration Sequence 1. The CS5460A must be operating in its active state, and ready to accept valid commands via the SPI interface, before a calibration sequence can be executed. Clearing the ‘DRDY’ bit in the Status Register is also recommended. 2. Apply appropriate calibration signal(s) to the “+” and “-” signals of the voltage/current channel input pairs. (The appropriate calibration signals for each type of calibration sequence are discussed next, in Sections 3.8.4 and 3.8.5.). The recommended sequence of calibration, if both gain and offset calibration are required, is to run offset calibration before gain calibration; and if both AC and DC offset calibration are required, DC offset should be calibrated first. 3. Next send the 8-bit calibration command to the CS5460A serial interface. 4. After the CS5460A has finished running the desired internal calibration sequence and has stored the updated calibration results in the appropriate calibration registers, the DRDY bit is set in the Status Register to indicate that the calibration sequence has been completed. If desired, the results of the calibration can now be read from the appropriate gain/offset registers, via the serial port. 28 DS487F4 CS5460A Note that when the calibration command is sent to the CS5460A, the device must not be performing A/D conversions (in either of the two acquisitions modes). If the CS5460A is running A/D conversions/computations in the ‘continuous computation cycles’ acquisition mode (C = 1), the Power-Up/Halt Command must be issued first to terminate A/D conversions/computations. If the CS5460A is running A/D conversions/computations in the ‘single computation cycle’ data acquisition mode (C = 0), the Power-Up/Halt Command must be issued first (unless the computation cycle has completed) before executing any calibration sequence. The calibration sequences will not run if the CS5460A is running in either of the two available acquisition modes. 3.8.6 Input Configurations for Calibrations Figure 16 shows the basic setup for gain calibration. If a DC gain calibration is desired, a positive DC voltage level must be applied, such that it truly represents the absolute maximum peak instantaneous voltage level that needs to be measured across the inputs (including the maximum over-range level that must be accurately measured). In other words, the input signal must be a positive DC voltage level that represents the desired absolute peak full-scale value. However, in many practical power metering situations, an AC signal is preferred over a DC signal to calibrate the gain. To perform AC gain calibration instead of DC, an AC reference signal should be applied that is set to the desired maximum RMS level. Because the voltage/current waveforms that must be measured in most power systems are approximately sinusoidal in nature, the RMS levels of the AC gain calibration input signals may need to be set significantly lower than the voltage/current channel’s maximum DC voltage input level. This must be done in order to avoid the possibility that the peak values of the AC waveforms that are to be measured will not register a value that would be outside the available output code range of the voltage/current A/D converters. For example, on the voltage channel, if the Voltage Channel Gain Register is set to it’s default power-on value of 1.000... before calibration, then the largest pure sinusoidal waveform that can be used in AC calibration is one whose RMS-value is ~0.7071 of the value of the voltage channel’s peak DC input voltage value of 500 mVP-P. Thus the maximum value of the input sinusoid would be ~176.78 mV (rms). But in many practical power metering situations, the RMS voltage input level of the AC gain calibration signal may be reduced even further, to allow for some over-ranging capability. A typical sinusoidal calibration value which allows for reasonable over-range margin would be 0.6 of the voltage/current channel’s maximum input voltage level. For the voltage channel, such a sine-wave would have a value of 0.6 x 250 mVrms = 150 mVrms. For the offset calibrations, there is no difference between the AC and DC calibration signals that must be supplied: simply connect the “+” and “-’ 3.8.4 Calibration Signal Input Level For both the voltage and current channels, the differential voltage levels of the calibration signals must be within the specified voltage input limits (refer to “Differential Input Voltage Range” in Section 1., Characteristics & Specifications). For the voltage channel the peak differential voltage level can never be more than 500 mVP-P. The same is true for the current channel if the current channel input PGA is set for 10x gain. If the the current channel’s PGA gain is set to 50x, then the current channel’s input limits are 100 mVP-P. Note that for the AC/DC gain calibrations, there is an absolute limit on the RMS/DC voltage levels (respectively) that are selected for the voltage/current channel gain calibration input signals. The maximum value that the gain register can attain is 4. Therefore, for either channel, if the voltage level of a gain calibration input signal is low enough that it causes the CS5460A to attempt to set either gain register higher than 4, the gain calibration result will be invalid, and after this occurs, all CS5460A results obtained when the part is running A/D conversions will be invalid. 3.8.5 Calibration Signal Frequency The frequency of the calibration signals must be less than 1 kHz (assume MCLK/K = 4.096 MHz and K = 1). Optimally, the frequency of the calibration signal will be at the same frequency as the fundamental power line frequency of the power system that is to be metered. DS487F4 29 CS5460A to V *, I*, P *, E * R egisters In M odulator Filter + + + x X 2 + + - S IN C 2 N X ÷N V R M S* D C O ffse t* G a in * Σ ÷N N A C O ffse t* 2 X 1 x -X 0 .6 x * Denotes readable/writable register Figure 18. Calibration Data Flow pins of the voltage/current channels to their ground reference level. (See Figure 17.) Offset and gain calibration cannot be done at the same time. This will cause undesirable calibration results. External Connections + Full Scale (DC or AC) + following descriptions of calibration sequences will focus on the voltage channel, but apply equally to the current channel. Note: For proper calibration, it is assumed that the value of the Voltage-/Current-Channel Gain Registers are set to default (1.0) before running the gain calibration(s), and the value in the Voltage-/Current Channel AC and DC Offset Registers is set to default (0) before running calibrations. This can be accomplished by a software or hardware reset of the device. The values in the voltage/current calibration registers do affect the results of the calibration sequences. + XGAIN AIN+ AIN- - CM + - 3.8.7.1 AC Offset Calibration Sequence Figure 16. System Calibration of Gain. External Connections + AIN+ 0V + CM + AINXGAIN + Figure 17. System Calibration of Offset. The idea of the AC offset calibration is to obtain an offset value that reflects the square of the RMS output level when the inputs are grounded. During normal operation, when the CS5460A is calculating the latest result for the RMS Voltage Register, this AC offset register value will be subtracted from the square of each successive voltage sample in order to nullify the AC offset that may be inherent in the voltage-channel signal path. Note that the value in the AC offset register is proportional to the square of the AC offset. First, the inputs are grounded, and then the AC offset calibration command is sent to the CS5460A. When the AC offset calibration sequence is initiated, a valid RMS Voltage Register value is acquired and squared. This value is then subtracted from the square of each voltage sample that comes through the RMS data path. See Figure 18. 3.8.7 Description of Calibration Algorithms The computational flow of the CS5460A’s AC and DC gain/offset calibration sequences are illustrated in Figure 18. This figure applies to both the voltage channel and the current channel. The 30 DS487F4 CS5460A ues over one computation cycle (N samples) and then dividing this average into 1. Therefore, after the DC voltage gain calibration has been executed, the Instantaneous Voltage Register will read full-scale whenever the DC level of the input signal is equal to the level of the DC calibration signal that was applied to the voltage channel inputs during the DC gain calibration. For example, if a +230 mV DC signal is applied to the voltage channel inputs during the DC gain calibration for the current channel, then the Instantaneous Voltage Register will measure unity whenever a 230 mV DC level is applied to the voltage channel inputs. Before AC Gain Calibration (Vgain Register = 1) 250 mV Sinewave 0.9999... 0.92 Instantaneous Voltage Register Values -0.92 -1.0000... 230 mV INPUT 0V SIGNAL -230 mV -250 mV VRMS Register = 230/250 x 1/√2 ≈ 0.65054 After AC Gain Calibration (Vgain Register changed to ~0.9223) 250 mV Sinewave 0.92231 0.84853 Instantaneous Voltage Register Values -0.84853 -0.92231 230 mV 3.8.8 Duration of Calibration Sequence The value of the Cycle Count Register (N) determines the number of conversions that will be performed by the CS5460A during a given calibration sequence. For DC offset/gain calibrations, the calibration sequence always takes at least N + 30 conversion cycles to complete. For AC offset/gain calibrations, the calibration sequence takes at least 6N + 30 A/D conversion cycles to complete, (about 6 computation cycles). If N is increased, the accuracy of calibration results will increase. For more information on Calibration, see AN227, “CALIBRATING THE CS5460A”. INPUT 0V SIGNAL -230 mV -250 mV VRMS Register = 0.6000... Figure 19. Example of AC Gain Calibration 3.8.7.2 DC Offset Calibration Sequence The Voltage Channel DC Offset Register holds the negative of the simple average of N samples taken while the DC voltage offset calibration was executed. The inputs should be grounded during DC offset calibration. The DC offset value is added to the signal path to nullify the DC offset in the system. 3.9 Phase Compensation The values of bits 23 to 17 in the Configuration Register can be altered to adjust the amount of time delay that is imposed on the digitally sampled voltage channel signal. This time delay is applied to the voltage channel signal in order to compensate for the relative phase delay (with respect to the fundamental frequency) between the sensed voltage and current signals. Voltage and current transformers, as well as other sensor/filter/protection devices deployed at the front-end of the voltage/current sensor networks can often introduce a phase-delay in the system that distorts/corrupts the phase relationship between the line-voltage and line-current signals that are to be measured. The phase compensation bits PC[6:0] in the Configuration Register can be set to nullify this undesirable phase distortion between the digitally sampled signals in the two channels. The value in the 7-bit phase compensation word indicates the amount of time delay that is imposed on the volt31 3.8.7.3 AC Gain Calibration Sequence The AC voltage gain calibration algorithm attempts to adjust the Voltage Channel Gain Register value such that the calibration reference signal level presented at the voltage inputs will result in a value of 0.6 in the RMS Voltage Register. The AC calibration signal is applied to the “+” and “-” input pins of the channel under calibration. During AC voltage gain calibration, the value in the RMS Voltage Register is divided into 0.6. This result is the AC gain calibration value stored in the Voltage Channel Gain Register. 3.8.7.4 DC Gain Calibration Sequence Based on the level of the positive DC calibration voltage that should be applied across the “+” and “-” inputs, the CS5460A determines the Voltage Channel Gain Register value by averaging the Instantaneous Voltage Register’s output signal valDS487F4 CS5460A age channel’s analog input signal with respect to the current channel’s analog input signal. With the default setting, the phase delay on the voltage channel signal is ~0.995 µs (~0.0215 degrees assuming a 60 Hz power signal). With MCLK = 4.096 MHz and K = 1, the range of the internal phase compensation ranges from -2.8 degrees to +2.8 degrees when the input voltage/current signals are at 60 Hz. In this condition, each step of the phase compensation register (value of one LSB) is ~0.04 degrees. For values of MCLK other than 4.096 MHz, these values for the span (-2.8 to +2.8 degrees) and for the step size (0.04 degrees) should be scaled by 4.096 MHz / (MCLK / K). For power line frequencies other than 60Hz (e.g., 50 Hz), the values of the range and step size of the PC[6:0] bits can be determined by converting the above values to time-domain (seconds), and then computing the new range and step size (in degrees) with respect to the new line frequency. Unlike offset/gain calibration, the CS5460A does not provide an automated on-chip phase calibration sequence. To calibrate the phase delay, the phase compensation bits can be adjusted while the CS5460A is running in ‘continuous computation cycles’ data acquisition mode. For example, the CS5460A can be set up to perform continuous computations on a purely resistive load (no inductance or capacitance). The PC[6:0] bits can then be adjusted until the Energy Register value is maximized. the actual frequency is 4.096 MHz/4.091 MHz = ~1.00122219506. The TBC Register can be set to 1.00122213364 = 0x80280C(h), which is very close to the desired ratio. 3.11 Power Offset Register Referring to Figure 3, note the “Poff” Register that appears just after the power computation. This register can be used to offset system power sources that may be resident in the system, but do not originate from the power line signal. These sources of extra energy in the system contribute undesirable and false offsets to the power/energy measurement results. For example, even after DC offset and AC offset calibrations have been run on each channel, when a voltage signal is applied to the voltage channel inputs and the current channel is grounded (i.e., there is zero input on the current channel), the current channel may still register a very small amount of RMS current caused by leakage of the voltage channel input signal into the current channel input signal path. Although the CS5460A has high channel-to-channel crosstalk rejection, such crosstalk may not totally be eliminated.) If the amount of ‘artificial’ power that might be induced into the voltage/current channel signals due to such crosstalk/system noise/etc. can be determined, then the Power Offset Register can be programmed to nullify the effects of this unwanted energy. 3.12 Input Protection - Current Limit In Figures 6, 7, 8, and 9, note the series resistor RI+ which is connected to the IIN+ input pin. This resistor serves two purposes. First, this resistor functions in coordination with CIdiff and/or CIdiff to form a low-pass filter. The filter will a) remove any broadband noise that is far outside of the frequency range of interest, and also b) this filter serves as the anti-aliasing filter, which is necessary to prevent the A/D converter from receiving input signals whose frequency is higher than one-half of the sampling frequency (the Nyquist frequency). The second purpose of this resistor is to provide current-limit protection for the Iin+ input pin, in the event of a power surge or lightning surge. The role that RI+ contributes to input filtering will be discussed in the Section 3.13. But first the current-limit protection requirements for the Iin+/Iin- and Vin+/Vin- pins are discussed. DS487F4 3.10 Time-Base Calibration Register The Time-Base Calibration Register (notated as “TBC” in Figure 3) is used to compensate for slight errors in the XIN input frequency. External oscillators and crystals have certain tolerances. If there is a concern about improving the accuracy of the clock for energy measurements, the Time-Base Calibration Register value can be manipulated to compensate for the frequency error. Note from Figure 3 that the TBC Register only affects the value in the Energy Register. As an example, if the desired XIN frequency is 4.096 MHz, but during production-level testing, suppose that the average frequency of the crystal on a particular board is measured to actually be 4.091 MHz. The ratio of the desired frequency to 32 CS5460A The voltage/current-channel inputs have surge-current limits of 100 mA. This applies to brief voltage/current spikes ( bit status after software or hardware reset 2. Note that all registers can be read from, and written to. 5.1 Configuration Register Address: 0 23 PC6 15 EWA 7 RS 22 PC5 14 Res 6 VHPF 21 PC4 13 Res 5 IHPF 20 PC3 12 SI1 4 iCPU 19 PC2 11 SI0 3 K3 18 PC1 10 EOD 2 K2 17 PC0 9 DL1 1 K1 16 Gi 8 DL0 0 K0 Default** = 0x000001 K[3:0] Clock divider. A 4 bit binary number used to divide the value of MCLK to generate the internal clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range between 1 and 16. Note that a value of “0000” will set K to 16 (not zero). Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals are sampled, the logic driven by CPUCLK should not be active during the sample edge. 0 = normal operation (default) 1 = minimize noise when CPUCLK is driving rising edge logic Control the use of the High Pass Filter on the Current Channel. 0 = High-pass filter is disabled. If VHPF is set, use all-pass filter. Otherwise, no filter is used. (default) 1 = High-pass filter is enabled. Control the use of the High Pass Filter on the voltage Channel. 0 = High-pass filter is disabled. If IHPF is set, use all-pass filter. Otherwise, no filter is used. (default) 1 = High-pass filter enabled iCPU IHPF VHPF 44 DS487F4 CS5460A RS DL0 DL1 EOD Start a chip reset cycle when set 1. The reset cycle lasts for less than 10 XIN cycles. The bit is automatically returned to 0 by the reset cycle. When EOD = 1, EDIR becomes a user defined pin. DL0 sets the value of the EDIR pin. Default = '0' When EOD = 1, EOUT becomes a user defined pin. DL1 sets the value of the EOUT pin. Default = '0' Allows the EOUT and EDIR pins to be controlled by the DL0 and DL1 bits. EOUT and EDIR can also be accessed using the Status Register. 0 = Normal operation of the EOUT and EDIR pins. (default) 1 = DL0 and DL1 bits control the EOUT and EDIR pins. Soft interrupt configuration. Select the desired pin behavior for indication of an interrupt. 00 = active low level (default) 01 = active high level 10 = falling edge (INT is normally high) 11 = rising edge (INT is normally low) Reserved. These bits must be set to zero. Allows the output pins of EOUT and EDIR of multiple chips to be connected in a wire-AND, using an external pull-up device. 0 = normal outputs (default) 1 = only the pull-down device of the EOUT and EDIR pins are active Sets the gain of the current PGA 0 = gain is 10 (default) 1 = gain is 50 Phase compensation. A 2’s complement number used to set the delay in the voltage channel. When MCLK = 4.096 MHz and K = 1, the phase adjustment range is about -2.8 to +2.8 degrees and each step is about 0.04 degrees (this assumes that the power line frequency is 60 Hz). If (MCLK / K) is not 4.096 MHz, the values for the range and step size should be scaled by the factor 4.096 MHz / (MCLK / K). Default setting is 0000000 = 0.0215 degrees phase delay (when MCLK = 4.096 MHz). SI[1:0] Res EWA Gi PC[6:0] DS487F4 45 CS5460A 5.2 Current Channel DC Offset Register and Voltage Channel DC Offset Register Address: 1 (Current Channel DC Offset Register) 3 (Voltage Channel DC Offset Register) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 MSB -(20) Default** = 0.000 The DC offset registers are initialized to zero on reset, allowing the device to function and perform measurements. The register is loaded after one computation cycle with the current or voltage offset when the proper input is applied and the DC Calibration Command is received. DRDY will be asserted at the end of the calibration. The register may be read and stored so the register may be restored with the desired system offset compensation. The value is in the range ± full scale. The numeric format of this register is two’s complement notation. 5.3 Current Channel Gain Register and Voltage Channel Gain Register Address: 2 (Current Channel Gain Register) 4 (Voltage Channel Gain Register) LSB 20 2-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 2-22 MSB 21 Default** = 1.000 The gain registers are initialized to 1.0 on reset, allowing the device to function and perform measurements. The gain registers hold the result of either the AC or DC gain calibrations, whichever was most recently performed. If DC calibration is performed, the register is loaded after one computation cycle with the system gain when the proper DC input is applied and the Calibration Command is received. If AC calibration is performed, then after ~(6N + 30) A/D conversion cycles (where N is the value of the Cycle-Count Register) the register(s) is loaded with the system gain when the proper AC input is applied and the Calibration Command is received. DRDY will be asserted at the end of the calibration. The register may be read and stored so the register may be restored with the desired system offset compensation. The value is in the range 0.0 ≤ Gain < 4.0. 5.4 Cycle Count Register Address: 5 MSB 223 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 LSB 20 Default** = 4000 The Cycle Count Register value (denoted as ‘N’) specifies the number of A/D conversion cycles per computation cycle. For each computation cycle, the updated results in the RMS and Energy Registers are computed using the most recent set of N continuous instantaneous voltage/current samples. When the device is commanded to operate in ’continuous computation cycles’ data acquisition mode, the computation cycle frequency is (MCLK / K) / (1024 ∗ N) where MCLK is master clock input frequency (into XIN / XOUT pins), K is the clock divider value (as specified in the Configuration Register), and N is Cycle Count Register value. 46 DS487F4 CS5460A 5.5 Pulse-Rate Register Address: 6 MSB 2 18 LSB 2 17 2 16 2 15 2 14 2 13 2 12 2 11 ..... 21 2 0 2 -1 2 -2 2 -3 2 -4 2-5 Default** = 32000.00Hz The Pulse-Rate Register determines the frequency of the train of pulses output on the EOUT pin. Each EOUT pulse represents a predetermined magnitude of real (billable) energy. The register’s smallest valid value is 2-4 but can be in 2-5 increments. 5.6 I,V,P,E Signed Output Register Results Address: 7 - 10 MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 These signed registers contain the last value of the measured results of I, V, P, and E. The results are in the range of -1.0 ≤ I, V, P, E < 1.0. The value is represented in two's complement notation, with the binary point place to the right of the MSB (which is the sign bit). I, V, P, and E are output results registers which contain signed values. Note that the I, V, and P Registers are updated every conversion cycle, while the E Register is only updated after each computation cycle. The numeric format of this register is two’s complement notation. 5.7 IRMS, VRMS Unsigned Output Register Results Address: 11,12 MSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 LSB 2-24 These unsigned registers contain the last value of the calculated results of IRMS and VRMS. The results are in the range of 0.0 ≤ IRMS,VRMS < 1.0. The value is represented in binary notation, with the binary point place to the left of the MSB. IRMS and VRMS are output result registers which contain unsigned values. 5.8 Timebase Calibration Register Address: 13 MSB 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Default** = 1.000 The Timebase Calibration Register is initialized to 1.0 on reset, allowing the device to function and perform computations. The register can be loaded with the clock frequency error to compensate for a gain error caused by the crystal/oscillator tolerance. The value is in the range 0.0 ≤ TBC < 2.0. DS487F4 47 CS5460A 5.9 Power Offset Register Address: MSB -(2 ) 0 14 LSB 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2-17 2 -18 2 -19 2 -20 2 -21 2 -22 2-23 Default** = 0.000 This offset value is added to each power value that is computed for each voltage/current sample pair before being accumulated in the Energy Register. The numeric format of this register is two’s complement notation. This register can be used to offset contributions to the energy result that are caused by undesirable sources of energy that are inherent in the system. 5.10 Current Channel AC Offset Register and Voltage Channel AC Offset Register Address: 16 (Current Channel AC Offset Register) 17 (Voltage Channel AC Offset Register) LSB 2-14 2-15 2-16 2-17 2-18 2-19 2-20 ..... 2-30 2-31 2-32 2-33 2-34 2-35 2-36 MSB 2-13 Default** = 0.000 The AC offset registers are initialized to zero on reset, allowing the device to function and perform measurements. First, the ground-level input should be applied to the inputs. Then the AC Offset Calibration Command is should be sent to the CS5460A. After ~(6N + 30) A/D conversion cycles (where N is the value of the Cycle-Count Register), the gain register(s) is loaded with the square of the system AC offset value. DRDY will be asserted at the end of the calibration. The register may be read and stored so the register may be restored with the desired system offset compensation. Note that this register value represents the square of the AC current/voltage offset. 5.11 Status Register and Mask Register Address: 15 (Status Register) 26 (Mask Register) 22 EOUT 14 IROR 6 ID0 21 EDIR 13 VROR 5 WDT 20 CRDY 12 EOR 4 VOD 19 MATH 11 EOOR 3 IOD 18 Res 10 Res 2 LSD 17 IOR 9 ID3 1 0 16 VOR 8 ID2 0 IC 23 DRDY 15 PWOR 7 ID1 Default** = Binary: 00000000000000xxxx000001 (Status Register) Binary: 000000000000000000000000 (Mask Register) {x = state depends on device revision} The Status Register indicates the condition of the chip. In normal operation writing a '1' to a bit will cause the bit to go to the '0' state. Writing a '0' to a bit will maintain the status bit in its current state. With this feature the user can write logic ‘1’ values back to the Status Register to selectively clear only those bits that have been resolved/registered by the system MCU, without concern of clearing any newly set bits. Even if a status bit is masked to prevent the interrupt, the corresponding status bit will still be set in the Status Register so the user can poll the status. The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in the Mask Register will 48 DS487F4 CS5460A allow the corresponding bit in the Status Register to activate the INT pin when the status bit becomes active. IC Invalid Command. Normally logic 1. Set to logic 0 when the part is given an invalid command. Can be deactivated only by sending a port initialization sequence to the serial port (or by executing a software/hardware reset). When writing to the Status Register, this bit is ignored. Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage threshold (PMLO), with respect to VA- pin. For a given part, PMLO can be as low as 2.3 V. LSD bit cannot be permanently reset until the voltage at PFMON pin rises back above the high-voltage threshold (PMHI), which is typically 100mV above the device’s low-voltage threshold. PMHI will never be greater than 2.7 V. Modulator oscillation detect on the current channel. Set when the modulator oscillates due to an input above Full Scale. Note that the level at which the modulator oscillates is significantly higher than the current channel’s Differential Input Voltage Range. Modulator oscillation detect on the voltage channel. Set when the modulator oscillates due to an input above Full Scale. Note that the level at which the modulator oscillates is significantly higher than the current channel’s Differential Input Voltage Range. Note: The IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the power line. This event should not be confused with a DC overload situation at the inputs, when the IOD and VOD bits will re-assert themselves even after being cleared, multiple times. LSD IOD VOD WDT Watch-Dog Timer. Set when there has been no reading of the Energy Register for more than 5 seconds. (MCLK = 4.096 MHz, K = 1) To clear this bit, first read the Energy Register, then write to the Status Register with this bit set to logic '1'. When MCLK/K is not 4.096 MHz, the time duration is 5 * [4.096 MHz / (MCLK/K)] seconds. Revision/Version Identification. The internal EOUT Energy Accumulation Register went out of range. Note that the EOUT Energy Accumulation Register is different than the Energy Register available through the serial port. This register cannot be read by the user. Assertion of this bit can be caused by having an output rate that is too small for the power being measured. The problem can be corrected by specifying a higher frequency in the Pulse-Rate Register. Energy Out of Range. Set when the Energy Register overflows, because the amount of energy that has been accumulated during the pending computation cycle is greater than the register’s highest allowable positive value or below the register’s lowest allowable negative value. RMS Voltage Out of Range. Set when the calibrated RMS voltage value is too large to fit in the RMS Voltage Register. RMS Current Out of Range. Set when the calibrated RMS current value is too large to fit in the RMS Current Register. Power Calculation Out of Range. Set when the magnitude of the calculated power is too large to fit in the Instantaneous Power Register. Voltage Out of Range. Current Out of Range. Set when the magnitude of the calibrated current value is too large or too small to fit in the Instantaneous Current Register. General computation Indicates that a divide operation overflowed. This can happen normally in the course of computation. If this bit is asserted but no other bits are asserted, then there is no error, and this bit should be ignored. 49 ID3:0 EOOR EOR VROR IROR PWOR VOR IOR MATH DS487F4 CS5460A CRDY EDIR EOUT Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate, which is usually 4 kHz. Set whenever the EOUT bit asserted (see below) if the accumulated energy is negative. Indicates that enough positive/negative energy has been reached within the internal EOUT Energy Accumulation Register (not accessible to user) to mandate the generation of one or more pulses on the EOUT pin (if enabled, see Configuration Register). The energy flow may indicate negative energy or positive energy. (The sign is determined by the EDIR bit, described above). This EOUT bit is cleared automatically when the energy rate drops below the level that produces a 4 kHz EOUT pin rate. The bit can also be cleared by writing to the Status Register. This status bit is set with a maximum frequency of 4 kHz (when MCLK/K is 4.096 MHz). When MCLK/K is not equal to 4.096 MHz, the user should scale the pulse-rate by a factor of 4.096 MHz / (MCLK/K) to get the actual pulse-rate. Data Ready. When running in ’single computation cycle’ or ’continuous computation cycles’ data acquisition modes, this bit will indicate the end of computation cycles. When running calibrations, this bit indicates that the calibration sequence has completed, and the results have been stored in the offset or gain registers. DRDY 5.12 Control Register Address: 28 23 Res 15 Res 7 Res 22 Res 14 Res 6 MECH 21 Res 13 Res 5 Res 20 Res 12 Res 4 INTL 19 Res 11 Res 3 SYNC 18 Res 10 Res 2 NOCPU 17 Res 9 Res 1 NOOSC 16 Res 8 STOP 0 STEP Default** = 0x000000 STOP Res MECH INTL SYNC NOCPU NOOSC STEP 1 = used to terminate the new EEBOOT sequence. Reserved. These bits must be set to zero. 1 = widens EOUT and EDIR pulses for mechanical counters. 1 = converts the INT output to open drain configuration. 1 = forces internal A/D converter clock to synchronize to the initiation of a conversion command. 1 = converts the CPUCLK output to a one-bit output port. Reduces power consumption. 1 = saves power by disabling the crystal oscillator for external drive. 1 = enables stepper-motor signals on the EOUT/EDIR pins. 50 DS487F4 CS5460A 6. PIN DESCRIPTIONS Crystal Out CPU Clock Output Positive Digital Supply Digital Ground Serial Clock Input Serial Data Output Chip Select Mode Select Differential Voltage Input Differential Voltage Input Voltage Reference Output Voltage Reference Input XOUT CPUCLK VD+ DGND SCLK SDO CS MODE VIN+ VINVREFOUT VREFIN 1 2 3 4 24 23 22 21 XIN SDI EDIR EOUT INT RESET NC PFMON IIN+ IINVA+ VA- Crystal In Serial Data Input Energy Direction Indicator Energy Output Interrupt Reset No Connect Power Fail Monitor Differential Current Input Differential Current Input Positive Analog Supply Analog Ground 5 6 7 20 19 18 8 9 10 11 12 17 16 15 14 13 Clock Generator Crystal Out Crystal In CPU Clock Output Serial Clock Input 1,24 XOUT, XIN - A gate inside the chip is connected to these pins and can be used with a crystal to provide the system clock for the device. Alternatively, an external (CMOS compatible clock) can be supplied into XIN pin to provide the system clock for the device. CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load. 2 Control Pins and Serial Data I/O 5 SCLK - A clock signal on this pin determines the input and output rate of the data for the SDI and SDO pins respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin will recognize clocks only when CS is low. SDO - SDO is the output pin of the serial data port. Its output will be in a high impedance state when CS is high. CS - When low, the port will recognize SCLK. An active high on this pin forces the SDO pin to a high impedance state. CS should be changed when SCLK is low. MODE - When at logic high, the CS5460A can perform the auto-boot sequence with the aid of an external serial EEPROM to receive commands and settings. When at logic low, the CS5460A assumes normal “host mode” operation. This pin is pulled down to logic low if left unconnected, by an internal pull-down resistor to DGND. INT - When INT goes low it signals that an enabled event has occurred. INT is cleared (logic 1) by writing the appropriate command to the CS5460A. EOUT - The energy output pin output a fixed-width pulse rate output with a rate (programmable) proportional to real (billable) energy. EDIR - The energy direction indicator indicates if the measured energy is negative. SDI - the input pin of the serial data port. Data will be input at a rate determined by SCLK. Serial Data Output Chip Select Mode Select 6 7 8 Interrupt Energy Output Energy Direction Indicator Serial Data Input Differential Voltage Inputs 20 21 22 23 Measurement and Reference Input 9,10 VIN+, VIN- - Differential analog input pins for voltage channel. DS487F4 51 CS5460A Voltage Reference Output Voltage Reference Input Differential Current Inputs Positive Digital Supply Digital Ground Negative Analog Supply Positive Analog Supply Power Fail Monitor 11 12 15,16 VREFOUT - The on-chip voltage reference is output from this pin. The voltage reference has a nominal magnitude of 2.5 V and is reference to the VA- pin on the converter. VREFIN - The voltage input to this pin establishes the voltage reference for the on-chip modulator. IIN+, IIN- - Differential analog input pins for current channel. Power Supply Connections 3 4 13 14 17 VD+ - The positive digital supply is nominally +5 V ±10% relative to DGND. DGND - The common-mode potential of digital ground must be equal to or above the common-mode potential of VA-. VA- - The negative analog supply pin must be at the lowest potential. VA+ - The positive analog supply is nominally +5 V ±10% relative to VA-. PFMON - The power fail Monitor pin monitors the analog supply. Typical threshold level (PMLO) is 2.45 V with respect to the VA- pin. If PFMON voltage threshold is tripped, the LSD (low-supply detect) bit is set in the Status Register. Once the LSD bit has been set, it will not be able to be reset until the PFMON voltage increases ~100 mV (typical) above the PMLO voltage. Therefore, there is hysteresis in the PFMON function. Reset - When reset is taken low, all internal registers are set to their default states. RESET Other No Connection 19 18 NC - No connection. Pin should be left floating. 52 DS487F4 CS5460A 7. PACKAGE DIMENSIONS 24L SSOP PACKAGE DRAWING N D E11 A2 A1 A E ∝ L e b2 SIDE VIEW END VIEW SEATING PLANE 123 TOP VIEW DIM A A1 A2 b D E E1 e L ∝ MIN -0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025 0° INCHES NOM -0.006 0.068 -0.323 0.307 0.209 0.026 0.03 4° MAX 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041 8° MIN -0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63 0° MILLIMETERS NOM -0.13 1.73 -8.20 7.80 5.30 0.65 0.75 4° NOTE MAX 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.75 1.03 8° 2,3 1 1 JEDEC #: MO-150 Controlling Dimension is Millimeters. Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. DS487F4 53 CS5460A 8. ORDERING INFORMATION CS5460A-BS CS5460A-BSZ 24-pin SSOP 24-pin SSOP -40 to 85 °C -40 to 85 °C Lead Free 9. REVISION HISTORY Revision F2 F3 F4 Date September 2004 August 2005 November 2007 Added Lead Free part numbers Updated legal notice. Changed PSSR for voltage channel from 48 dB min. to 65 dB typical. Changes Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY, SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a registered trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. 54 DS487F4