CS5461-IS

CS5461 Single Phase Bi-Directional Power/Energy IC Features Energy Data Linearity: ±0.1% of Reading over 1000:1 Dynamic Range On-Chip Functions: Energy, I ∗ V, IRMS and VRMS, Energy-to-Pulse Conversion AC/DC System Calibrations Meets Accuracy Spec for IEC 687/1036, JIS Power Consumption bit status after power-on or reset 2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits. 7.1 Configuration Register Address: 0 23 PC6 15 EWA 7 22 PC5 14 6 VHPF 21 PC4 13 5 IHPF 20 PC3 12 IMODE 4 iCPU 19 PC2 11 IINV 3 K3 18 PC1 10 EPP 2 K2 17 PC0 9 EOP 1 K1 16 Igain 8 EDP 0 K0 Default** = 0x000001 PC[6:0] Phase compensation. A 2’s complement number which sets the delay in the voltage channel. When MCLK=4.096 MHz and K=1, the phase adjustment range is about -2.8 to +2.8 degrees and each step is about 0.04 degrees (assuming a power line frequency of 60 Hz). If (MCLK / K) is not 4.096 MHz, the values for the range and step size should be scaled by the factor 4.096MHz / (MCLK / K). Default setting is 0000000 = 0.0215 degrees phase delay at 60 Hz (when MCLK = 4.096 MHz). Igain Sets the gain of the current PGA 0 = gain is 10 (default) 1 = gain is 50 Allows the EOUT and EDIR pins to be configured as open-collector output pins. 0 = normal outputs (default) 1 = only the pull-down device of the EOUT and EDIR pins are active EWA [IMODE IINV] Soft interrupt configuration bits. Select the desired pin behavior for indication of an interrupt. 00 = active low level (default) 01 = active high level 10 = falling edge (INT is normally high) 11 = rising edge (INT is normally low) EPP Allows the EOUT and EDIR pins to be controlled by the DL0 and DL1 bits. EOUT and EDIR can also be accessed using the Status Register. 0 = Normal operation of the EOUT and EDIR pins. (default) 1 = EOP and EDP bits control the EOUT and EDIR pins. When EPP = 1, EOUT becomes a user defined pin, and EOP sets the value of the EOUT pin. Default = '0' When EPP = 1, EDIR becomes a user defined pin, EDP sets the value of the EDIR pin. Default = '0' Control the use of the High Pass Filter on the voltage Channel. 0 = High-pass filter disabled (default) 1 = High-pass filter enabled Control the use of the High Pass Filter on the Current Channel. EOP EDP VHPF IHPF DS546F2 33 CS5461 0 = High-pass filter disabled (default) 1 = High-pass filter enabled iCPU Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals are sampled, the logic driven by CPUCLK should not be active during the sample edge. 0 = normal operation (default) 1 = minimize noise when CPUCLK is driving rising edge logic Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range between 1 and 16. Note that a value of “0000” will set K to 16 (not zero). K[3:0] 7.2 DC Current Offset Register and DC Voltage Offset Register Address: 1 (DC Current Offset Register); 3 (DC Voltage Offset Register) MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Default** = 0.000 The DC Offset Registers are initialized to zero on reset, allowing for uncalibrated normal operation. If DC Offset Calibration is performed, this register is updated after one computation cycle with the current or voltage offset if the proper DC input signals are applied. DRDY will be asserted at the end of the calibration. This register may be read and stored for future system offset compensation. The value is in the range ± full scale. The numeric format of this register is two’s complement notation. 7.3 AC/DC Current Gain Register and AC/DC Voltage Gain Register Address: 2 (Current Gain Register); 4 (Voltage Gain Register) MSB 21 20 2-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 LSB 2-22 Default** = 1.000 The Gain Registers are initialized to 1.0 on reset, allowing for uncalibrated normal operation. The Gain registers hold the result of either the AC or DC gain calibrations, whichever was most recently performed. If DC calibration is performed, the register is updated after one computation cycle with the system gain when the proper DC input is applied. If AC calibration is performed, then after ~(6N + 30) A/D conversion cycles (where N is the value of the Cycle-Count Register) the register(s) is updated with the system gain when the proper AC input is applied. DRDY will be asserted at the end of the calibration. The register may be read and stored for future system gain compensation. The value is in the range 0.0 ≤ Gain < 3.9999. 7.4 Cycle Count Register Address: 5 MSB 223 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 LSB 20 Default** = 4000 The Cycle Count Register value (denoted as ‘N’) determines the length of one energy and RMS computation cycle. During continuous conversions, the computation cycle frequency is (MCLK/K)/(1024∗N). 34 DS546F2 CS5461 7.5 PulseRateE Register Address: 6 MSB 218 217 216 215 214 213 212 211 ..... 21 20 2-1 2-2 2-3 2-4 LSB 2-5 Default** = 32000.00 Hz The PulseRateE Register determines the average frequency of the pulses issued on the EOUT output pin. The register’s smallest valid value is 2-4 but can be in 2-5 increments. A pulserate higher than MCLK/K/8 will result in a pulse rate setting of MCLK/K/8. 7.6 I, V, P, & PAvg: Instantaneous Current, Voltage, Power, and Average Power (Signed) Output Register Address: 7 - 10 MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 These signed registers contain the last measured value of I, V, P, and PAVG. The results will be within in the range of -1.0 ≤ I,V,P,PAvg< 1.0. The value is represented in two's complement notation, with the binary point place to the right of the MSB (MSB has a negative weighting). These values are 22 bits in length. The two least significant bits have no meaning, and will always have a value of “0”. 7.7 IRMS, VRMS Unsigned Output Register Address: 11,12 MSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 LSB 2-24 These unsigned registers contain the last values of IRMS and VRMS. The results are in the range of 0.0 ≤ IRMS,VRMS < 1.0. The value is represented in (unsigned) binary notation, with the binary point place to the left of the MSB. These results are updated after each computation cycle. 7.8 Timebase Calibration Register Address: 13 MSB 20 2 -1 LSB 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2-17 2 -18 2 -19 2 -20 2 -21 2 -22 2-23 Default** = 1.000 This register can be set with a clock frequency error compensation value, to correct for a gain/timing error caused by the crystal/oscillator tolerance. The value is in the range 0.0 ≤ TBC < 2.0. DS546F2 35 CS5461 7.9 Power Offset Register Address: MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 14 LSB 2-23 Default** = 0.000 This offset value is added to each power value that is computed for each voltage/current sample pair before being accumulated in the Energy Register. This register can be used to offset contributions to the energy result that are caused by undesirable sources of energy that are inherent in the system. This value is in two’s complement notation. 7.10 Status Register and Mask Register Address: 23 DRDY 15 7 15 (Status Register); 26 (Mask Register) 22 EOUT 14 IROR 6 21 EDIR 13 VROR 5 20 CRDY 12 4 VOD 19 11 EOOR 3 IOD 18 10 2 LSD 17 IOR 9 1 VSAG 16 VOR 8 0 IC Default** = 0x000000 (Status Register) 0x000000 (Mask Register) The Status Register indicates the condition of the chip. In normal operation writing a '1' to a bit will cause the bit to go to the '0' state. Writing a '0' to a bit will maintain the status bit in its current state. With this feature the user can simply write to the Status Register to clear the bits that have been seen, without concern of clearing any newly set bits. Even if a status bit is masked to prevent an interrupt, the status bit will still be set in the Status Register. The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in the Mask Register will allow the corresponding bit in the Status Register to activate the INT pin when the status bit is asserted. DRDY Data Ready. When running in single or continuous conversion acquisition mode, this bit will indicate the end of computation cycles. When running calibrations, this bit indicates the end of a calibration sequence. Indicates that the energy limit has been reached for the EOUT Energy Accumulation Register, and so this register will be cleared, and one pulse will be generated on the EOUT pin (if enabled). If EOUT is asserted, this bit will be cleared automatically just after the beginning of any subsequent A/D conversion cycle in which no EOUT pulses need to be issued. The bit can also be cleared by writing to the Status Register. This status bit is set with a maximum frequency of 4 kHz (when MCLK/K is 4.096 MHz). When MCLK/K is not equal to 4.096 MHz, the user should scale the pulse-rate would be expected with MCLK/K = 4.096 MHz by a factor of 4.096 MHz / (MCLK/K), to get the actual pulse-rate. Set whenever the EOUT bit is asserted as long as the energy result is negative. Reset/Clear behavior of the EDIR status bit is similar to the EOUT status bit. Current Out of Range. Set when the magnitude of the calibrated current value is too large or too small to fit in the Instantaneous Current Register. DS546F2 EOUT EDIR IOR 36 CS5461 CRDY VOR VSAG VROR IROR EOOR Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate. Voltage Out of Range. Indicates that the voltage threshold/duration conditions, specified in the VSAGlevel and VSAGduration Registers, have been met. RMS Voltage Out of Range. Set when the calibrated RMS voltage value is too large to fit in the RMS Voltage Register. RMS Current Out of Range. Set when the calibrated RMS current value is too large to fit in the RMS Current Register. EOUT Energy Summation Register Out of Range. Assertion of this bit can be caused by having a pulse output frequency that is too small for the power being measured. This problem can be corrected by specifying a higher frequency in the PulseRateE register. Modulator oscillation detect on the voltage channel. Set when the modulator oscillates due to an input above Full Scale. Note that the level at which the modulator oscillates is significantly higher than the voltage channel’s Differential Input Voltage Range. Modulator oscillation detect on the current channel. Set when the modulator oscillates due to an input above Full Scale. Note that the level at which the modulator oscillates is significantly higher than the current channel’s Differential Input Voltage Range. Note: The IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the power line. This event should not be confused with a DC overload situation at the inputs, when the IOD and VOD bits will re-assert themselves even after being cleared, multiple times. VOD IOD LSD Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage threshold (PMLO), with respect to VA- pin. For a given part, PMLO can be as low as 2.3 V. LSD bit cannot be permanently reset until the voltage at PFMON pin rises back above the high-voltage threshold (PMHI), which is typically 100 mV above the device’s low-voltage threshold. PMHI will never be greater than 2.7 V. Invalid Command. Normally logic 1. Set to logic 0 if the host interface is strobed with an 8-bit word that is not recognized as one of the valid commands (see Section 6.1, Commands). IC 7.11 AC Current Offset Register and AC Voltage Offset Register Address: MSB 2-1 2 -2 16 (AC Current Offset Register); 17 (AC Voltage Offset Register) LSB 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2-18 2 -19 2 -20 2 -21 2 -22 2 -23 2-24 Default** = 0x000000 The AC Offset Registers are initialized to zero on reset, allowing for uncalibrated normal operation. When AC Offset Calibration is performed, the offset register(s) is updated with the square of the system AC offset value. This sequence lasts ~(6N + 30) A/D conversion cycles (where N is the value of the Cycle-Count Register). DRDY will be asserted at the end of the calibration. The register value may be read and stored for future system offset compensation. DS546F2 37 CS5461 7.12 PulseRateF Register Address: 18 MSB 218 217 216 215 214 213 212 211 ..... 21 20 2-1 2-2 2-3 2-4 LSB 2-5 Default** = 32000.00 Hz The PulseRateF Register sets the average pulse frequency of the FOUT output pin. The register’s smallest valid value is 2-4 but can be in 2-5 increments. A pulserate higher than MCLK/K/8 will result in a pulse rate setting of MCLK/K/8. 7.13 Temperature Sensor Output Register Address: 19 MSB -(27) 26 25 24 23 22 21 20 ..... 2-10 2-11 2-12 2-13 2-14 2-15 LSB 2-16 This signed register contains the output of the On-Chip Temperature Sensor. The results are in the range of -128.0 ≤ T < 128.0. The value is represented in unsigned binary notation, with the binary point place to the left of the MSB. This result is updated after each computation cycle. 7.14 Pulsewidth Address: 21 MSB 223 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 LSB 20 Default** = 512 sample periods This signed register determines the pulsewidth of EOUT and EDIR pulses in Mechanical Counter Mode. The width is set in number of sample periods. The default is 512. This corresponds to a pulsewidth of 512 samples / [(MCLK/K)/1024] = 128 msec with MCLK = 4.096 MHz and K = 1. Although this is a signed register a negative value will have no meaning; pulsewidth settings must be positive. 7.15 VSAGLevel: Voltage Sag-Detect Threshold Level Address: 23 MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Default** = 0x000000 This signed register sets the threshold level for the Voltage Sag Detect feature. To activate the VSAG bit the Status Register, the value of the VRMS register must remain below this threshold level for a set number of samples (defined in the VSAGDuration Register). Voltage threshold levels must be positive values; a negative value can be used to disable the feature. For more information about the voltage sag detect functionality, refer to Section 4.10 of the data sheet. 38 DS546F2 CS5461 7.16 VSAGDuration: Voltage Sag-Detect Duration Level Address: 24 MSB 223 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 LSB 20 Default** = 0x000000 This Register sets the number of conversions over to accumulate RMS voltage for comparison against the VSAGLEVEL. Setting this register to zero will disable the VSAG feature. 7.17 Control Register Register Address: 28 23 15 7 22 14 6 MECH 21 13 5 20 12 4 INTOD 19 11 3 18 10 FAC 2 NOCPU 17 9 EAC 1 NOOSC 16 8 STOP 0 STEP Default** = 0x000000 FAC EAC STOP MECH INTOD NOCPU NOOSC STEP 1 = enable anti-creep for FOUT pulse output function. 1 = enable anti-creep for EOUT pulse output function. 1 = used to terminate the new EEBOOT sequence. 1 = widens EOUT and EDIR pulses for mechanical counters. 1 = Converts INT output to open drain configuration. 1 = saves power by disabling the CPUCLK external drive pin. 1 = saves power by disabling the crystal oscillator circuit. 1 = enables stepper-motor signals on the EOUT/EDIR pins. DS546F2 39 CS5461 8. BASIC APPLICATION CIRCUITS Figure 14 shows the CS5461 connected to a service to measure power in a single-phase 2-wire system while operating in a single supply configuration. Note that in this diagram the shunt resistor used to monitor the line current is connected on the “Line” (hot) side of the power mains. In most residential power metering applications, the power meter’s current-sense shunt resistor is intentionally placed on the hot side of the power mains in order to detect a subscriber’s attempt to steal power. In this type of shunt-resistor configuration, the common-mode level of the CS5461 must be referenced to the hot side of the power line; which means the common-mode potential of the CS5461 will typically oscillate to very high voltage levels with respect to earth ground potential. If digital communication networks require that the CMOS-level digital interface be referenced to an earth ground, the serial interface pins on the CS5461 must be isolated from the external digital interface. Figure 15 shows the same single-phase two-wire system with complete isolation from the power lines. This isolation is achieved using three transformers: a general purpose transformer to supply the on-board DC power; a high-precision, low impedance voltage transformer, with very little roll-off/phase-delay, to measure voltage; and a current transformer to sense the line current. Because the CS5461 is not directly connected to the power mains, no isolation is necessary on the CS5461’s digital interface. Figure 16 shows a single-phase 3-wire system. In many 3-wire residential power systems within the United States, only the two line terminals are available (neutral is not available). Figure 17 shows the CS5461 configured to meter a three-wire system with no neutral available. 5 kΩ N 120 VAC 10 kΩ L 500 Ω 470 nF 500 100 µF 0.1 µF 10 Ω 0.1 µF 14 VA+ 3 VD+ CS5461 9 R2 R1 VIN+ C V+ R V10 15 R IRShunt R I+ C I+ 16 12 PFMON CPUCLK XOUT 17 2 1 2.5 MHz to 20 MHz Optional Clock Source VINIIN- XIN 24 RESET CS SDI SDO SCLK INT EDIR EOUT DGND 4 19 ISOLATION 7 23 6 5 20 22 21 IIN+ Serial Data Interface VREFIN 11 VREFOUT VA13 0.1 µF To Service Mech. Counter or Stepper Motor Figure 14. Typical Connection Diagram (One-Phase 2-Wire, Direct Connect to 40 DS546F2 CS5461 120 VAC 5 kΩ L Voltag Transforme e r 12 VAC 10 kΩ N 200 Ω 200 Ω 0.1µF 200µF 14 VA+ 10 Ω 0.1 µF 3 VD+ 12 VAC CS5461 M:1 1kΩ R V+ RVC Vdiff 10 VIN9 VIN+ 17 PFMON 2 CPUCLK 1 XOUT 24 2.5 MHz to 20 MHz Optional Clock Source 1kΩ Low Phase-Shift Potential Transformer XIN N:1 1kΩ RBurden 1kΩ Current Transformer RIC Idiff 15 IIN- RESET 19 16 RI+ 12 11 IIN+ VREFIN VREFOUT VA13 7 CS 23 SDI 6 SDO 5 SCLK INT EDIR 20 22 21 Serial Data Interface 0.1 µF EOUT DGND 4 To Service Mech. Counter or Stepper Motor Figure 15. Typical Connection Diagram (One-Phase 2-Wire, Isolated from Power Line) 240 VAC 120 VAC 120 VAC 5 kΩ L2 500 Ω 500 Ω 100 µF 0.1 µF 10 Ω 0.1 µF 10 kΩ L1 N 470 nF Earth Ground 14 VA+ 3 VD+ CS5461 9 VIN+ 17 PFMON 2 CPUCLK 1 XOUT 24 R3 R2 R1 R4 CIdiff 2.5 MHz to 20 MHz Optional Clock Source 10 1kΩ VIN16 IIN+ XIN R I+ RESET C Idiff 19 RBurden 1kΩ 15 R I- IIN- 12 VREFIN 11 VREFOUT VA13 7 CS 23 SDI 6 SDO 5 SCLK 20 INT Serial Data Interface 0.1 µF 22 EDIR 21 EOUT DGND 4 To Service To Service Mech. Counter or Stepper Motor Figure 16. Typical Connection Diagram (One-Phase 3-Wire) DS546F2 41 CS5461 240 VAC 5 kΩ L2 1 kΩ 500 Ω 100 µF 0.1 µF 10 Ω 0.1 µF 10 kΩ L1 235 nF 14 VA+ 3 VD+ CS5461 9 R1 R2 R VC V+ 10 16 1kΩ VIN+ 17 PFMON 2 CPUCLK 1 XOUT 24 2.5 MHz to 20 MHz Optional Clock Source VINIIN+ XIN R I+ RESET 19 7 23 6 5 20 ISOLATION Serial Data Interface RBurden 1kΩ 15 R I- IIN- CS SDI SDO SCLK INT 12 VREFIN 11 VREFOUT VA13 0.1 µF 22 EDIR 21 EOUT DGND 4 To Service To Service Mech. Counter or Stepper Motor Figure 17. Typical Connection Diagram (One-Phase 3-Wire - No Neutral Avail- 42 DS546F2 CS5461 9. PACKAGE DIMENSIONS 24L SSOP PACKAGE DRAWING N D E11 A2 A1 A E b2 SIDE VIEW 123 ∝ L e END VIEW SEATING PLANE TOP VIEW DIM A A1 A2 b D E E1 e L ∝ MIN -0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025 0° INCHES NOM -0.006 0.068 -0.323 0.307 0.209 0.026 0.03 4° MAX 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041 8° MIN -0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63 0° MILLIMETERS NOM -0.13 1.73 -8.20 7.80 5.30 0.65 0.75 4° NOTE MAX 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.75 1.03 8° 2,3 1 1 JEDEC #: MO-150 Controlling Dimension is Millimeters. Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. DS546F2 43 CS5461 10. REVISIONS Revision A1 PP1 PP2 F1 F2 Date March 2003 Initial Release Changes 13 October 2003 Initial release for Preliminary Product Information 5 December 2003 1) Added Auto-boot Feature Description (Page 1, 6, 12, 27, 28, 37, 13) 2) Added Mode Pin Functionality (Page 6, 12, 27) 8 June 2004 10 Aug 2004 1) Specification change: THD, Nv, PSRR (Page 8, 9, 10) Changed Noise Spec from 125uV to 150uV. Contacting Cirrus Logic Support F or all product questions and inquiries contact a Cirrus Logic Sales Representative. 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