CS5471-BS

CS5471 Dual-Channel Delta-Sigma Analog-to-Digital Converter Features Description l Synchronous The CS5471 is a highly integrated Delta-Sigma (∆Σ) Analog-to-Digital Converter (ADC) developed for the Power Measurement Industry. The CS5471 combines two ∆Σ ADCs, decimation filters, and a serial interface on a single chip. The CS5471 interfaces directly to a current transformer or shunt to measure current, and resistive divider or transformer to measure voltage. The product features a serial interface for communication with a micro-controller or DSP. The product is initialized and fully functional upon reset, and includes a Voltage Reference. Sampling l On-chip 1.2 V Reference (25 ppm/°C typ.) l Power Supply Configurations: – VA+ = +3 V; VA- = -2 V; VD+ = +3 V – Supply tolerances ±10% l Power Consumption – 10 mW Typical at VD+ = +3 V l Simple Four-wire Serial Interface l Charge Pump Driver output generates negative power supply. l Ground-Referenced Bipolar Inputs ORDERING INFORMATION: CS5471-BS VA+ -40°C to +85°C RESET 20-pin SSOP VD+ SE GAIN IIN + IIN - x1, 20 VIN + VIN - x1 4th Order ∆Σ Modulator OWRS Decimation Filter Serial Interface 2nd Order ∆Σ Modulator SDO FSO Decimation Filter SCLK VREFIN VREFOUT x1 Voltage Reference AGND Preliminary Product Information P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com CLOCK VA- Pulse Output Regulator XIN CPD DGND This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright  Cirrus Logic, Inc. 2001 (All Rights Reserved) JUL ‘01 DS480PP5 1 CS5471 TABLE OF CONTENTS 3. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 3 ANALOG CHARACTERISTICS ................................................................................................ 3 DIGITAL CHARACTERISTICS ................................................................................................. 4 RECOMMENDED OPERATING CONDITIONS ....................................................................... 5 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5 SWITCHING CHARACTERISTICS .......................................................................................... 6 4. GENERAL DESCRIPTION ....................................................................................................... 7 4.1 Theory of Operation ........................................................................................................... 7 4.2 Performing Measurements ................................................................................................. 7 4.3 High Rate Digital Filters ..................................................................................................... 8 4.4 Serial Interface ................................................................................................................... 8 4.5 System Initialization ........................................................................................................... 9 4.6 Analog Inputs ..................................................................................................................... 9 4.7 Voltage Reference ............................................................................................................. 9 4.8 Using the Charge Pump Drive Pin ..................................................................................... 9 4.9 PCB Layout ...................................................................................................................... 10 5. PIN DESCRIPTION.................................................................................................................. 11 6. PACKAGE DIMENSIONS........................................................................................................ 13 LIST OF FIGURES Figure 1. Serial Port Timing............................................................................................................. 6 Figure 2. Typical Connection Diagram ............................................................................................ 7 Figure 3. Serial Port Data Transfer ................................................................................................. 8 Figure 4. Close-up of One Frame.................................................................................................... 9 Figure 5. Generating VA- with a Charge Pump............................................................................. 10 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales/cfm Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 CS5471 1. CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (TA = -40 °C to +85 °C; +2.7V < VA+ < +3.5V; +2.7V < VD+ < +3.5V; VA- = -2 V ±10%; External VREF+ = 1.2 V; XIN = 4.000 MHz; AGND, DGND = 0.0V.) (See Notes 1 and 2) Parameter Symbol Min Typ Max Unit THD 74 - - dB CMRR 80 - - dB VA- - VA+ V - XIN/4 - Hz Accuracy (All Channels) Total Harmonic Distortion Common Mode Rejection (DC, 50, 60 Hz) Common Mode + Signal on Input Input Sampling Rate Analog Inputs (Current Channel) Differential Input Voltage Range [ (vIIN+) - (vIIN-) ] Gain=20 Gain=1 IIN - ±40 ±800 - mV mV Bipolar Offset Gain=20 Gain=1 VOS VOS - 0.500 10 1 20 mV mV Crosstalk (Channel-to-Channel) - - -120 dB Input Capacitance Gain=20 Gain=1 IC IC - - 20 1 pF pF Effective Input Impedance (Note 3) Gain=20 Gain=1 EII EII 50 - 500 600 kΩ kΩ - 1 20 2.5 50 3.75 75 µVrms µVrms µVrms µVrms µVrms µVrms Noise (Referred to Input) 0-60 Hz 0-1 kHz 0-2 kHz (50, 60 Hz) Gain=20 Gain=1 Gain=20 Gain=1 Gain=20 Gain=1 Analog Inputs (Voltage Channel) Differential Input Voltage Range [ (vVIN+) - (vVIN-) ] Bipolar Offset Crosstalk with Current Channel Gain=1 - ±800 - mV0-pk VOS - 20 25 mV - - -120 dB (50, 60 Hz) Input Capacitance Effective Input Impedance VIN (Note 3) IC - - 0.2 pF EII - 3 4 MΩ - - 20 50 75 µVrms µVrms µVrms - XIN/2048 XIN/1024 - Hz Hz Noise (Referred to Input) 0-60 Hz 0-1 kHz 0-2 kHz Dynamic Characteristics High Rate Filter Output Word Rate OWRS = “0” OWRS = “1” OWR OWR Notes: 1. Specifications guaranteed by design, characterization, and/or test. 2. Analog signals are relative to AGND and digital signals to DGND unless otherwise noted. 3. Effective Input Impedance (EII) varies with clock frequency (XIN) and Input Capacitance (IC) EII = 1/(IC*XIN/4) 3 CS5471 ANALOG CHARACTERISTICS (Continued) Parameter Symbol Min Typ Max Unit REFOUT 1.15 - 1.25 V - 20 50 ppm/°C ∆VR - 6 10 mV PSRR 60 - - dB VREF+ 1.15 1.2 1.25 V Input Capacitance - - 10 pF Input CVF Current - - 1 µA PSCA PSCD - - 1.5 2.5 mA mA PC - - 15 mW PSRR 60 - - dB Reference Output Output Voltage Temperature Coefficient Load Regulation (Output Current 1µA Source or Sink) Power Supply Rejection Reference Input Input Voltage Range Power Supplies Power Supply Currents IA+ ID+ Power Consumption (Note 4) Power Supply Rejection (see Note 5) (DC, 50, 60 Hz) Notes: 4. All outputs unloaded. All inputs CMOS level. 5. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3V, AGND = DGND = 0V, VA- = -2V (using charge-pump circuit with CPD). In addition, a 106.07 mV rms (60 Hz) sinewave is imposed onto the VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to VA-. Instantaneous digital output data words are then collected for the channel under test. From these data samples, the rms value (standard deviation) of the digital sinusoidal output signal is calculated, and this rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB)  106.07  PSRR = 20 ⋅ log  ----------------   V eq  DIGITAL CHARACTERISTICS (TA = -40 °C to +85 °C; +2.7V < VA+ < +3.5V; +2.7V < VD+ < +3.5V; VA- = -2 V ±10%; AGND, DGND = 0.0 V) (See Note 6) Parameter Symbol Min Typ Max Unit High-Level Input Voltage VIH 0.6 VD+ - VD+ V Low-Level Input Voltage VIL 0.0 - 0.8 V High-Level Output Voltage Iout = -5.0 mA VOH (VD+) - 1.0 - - V Low-Level Output Voltage Iout = 5.0 mA VOL - - 0.4 V Iin - ±1 ±10 µA 3-State Leakage Current IOZ - - ±10 µA Digital Output Pin Capacitance Cout - 9 - pF Input Leakage Current (Note 7) Notes: 6. All measurements performed under static conditions. 7. For OWRS and GAIN pins, input leakage current is 30 µA (Max). 4 CS5471 RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0.0 V) Parameter DC Power Supplies Positive Digital Positive Analog Negative Analog Voltage Reference Input Symbol Min Typ Max Unit VD+ VA+ VA- 2.7 2.7 -2.2 3.0 3.0 -2.0 3.5 3.5 -1.8 V V V VREF+ - 1.2 - V ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0.0 V; See Note 8.) Parameter Symbol Min Typ Max Unit Positive Digital Positive Analog Negative Analog VD+ VA+ VA- -0.3 -0.3 -2.5 - +3.5 +3.5 -0.3 V V V (Note 9 and 10) IIN - - ±10 mA IOUT - - ±25 mA (Note 11) PDN - - 500 mW Analog Input Voltage All Analog Pins VINA VA- - 0.3 - (VA+) + 0.3 V Digital Input Voltage All Digital Pins VIND -0.3 - (VD+) + 0.3 V Ambient Operating Temperature TA -40 - 85 °C Storage Temperature Tstg -65 - 150 °C DC Power Supplies Input Current, Any Pin Except Supplies Output Current Power Dissipation Notes: 8. All voltages with respect to AGND. 9. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins. 10. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA. 11. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 5 CS5471 SWITCHING CHARACTERISTICS (TA = -40 °C to +85 °C; VA+, VD+ = 3.0 V ±10%; VA- = -2 V ±10%; DGND = AGND = 0.0 V; Logic Levels: Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50pF)) Parameter Master Clock Frequency (Note 12) Master Clock Duty Cycle Symbol Min Typ Max Unit XIN 3 4.000 5 MHz - 40 - 60 % Rise Times Any Digital Input (Note 13) Any Digital Output trise - 50 1.0 - µs ns Fall Times Any Digital Input (Note 13) Any Digital Output tfall - 50 1.0 - µs ns SCLK SCLK - 500 1000 - kHz kHz t1 t2 - 0.5 0.5 - SCLK SCLK t3 - - 50 ns Serial Port Timing Serial Clock Frequency (Note 12) OWRS = “0” OWRS = “1” Serial Clock Pulse Width High (Note 12) Pulse Width Low (Note 12) SCLK falling to New Data Bit FSO Falling to SCLK Rising Delay (Note 12) t4 - 0.5 - SCLK FSO Pulse Width (Note 12) t5 - 1 - SCLK SE Rising to Output Enabled t6 - - 50 ns SE Falling to Output in Tri-state t7 - - 50 ns Notes: 12. Device parameters are specified with a 4.000 MHz clock, OWRS = 1. 13. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF. MSB(V1) SDO t3 MSB(V1) - 1 t1 LSB(I2) t2 SCLK t4 FSO t5 t6 SE t6 Figure 1. Serial Port Timing 6 CS5471 2. GENERAL DESCRIPTION 2.1 The CS5471 is designed for single-phase power meter applications and interfaces to a current transformers or shunt to measure current, and a resistive divider or transformer to measure voltage. The CS5471 is designed to operate from a single +3V supply and provides a ±40 mV and ±800 mV input range for the current channel and ±800 mV range for the voltage channel. These voltages represent the maximum zero-to-peak voltage levels that can be presented to the inputs. The CS5471 is designed to accommodate common mode + signal levels from VA- to VA+. Figure 2 illustrates the CS5471 typical inputs and power supply connections. The CS5471 combines two ∆Σ modulators and decimation filters, one channel assigned for current input that has programmable input gain amplifiers, and one channel assigned for voltage input. The CS5471 includes two decimation filters that output data at a 2000 Hz or 4000 Hz output word rate (OWR) when the input frequency at XIN = 4.096 MHz. 2.2 Theory of Operation Performing Measurements The converter outputs are transferred in 16-bit signed (two’s complement) data formats as a per- The device outputs data on a serial output port. +3 V VA+ VD+ REFIN Optional External Reference V 1.2 V REFOUT VIN + + PHASE VIN- IIN+ I PHASE NOTE: Current input channel actually measures voltage. IIN - AGND VA- DGND -2 V Figure 2. Typical Connection Diagram 7 CS5471 centage of full scale. Table 1 below illustrates the ideal relationship between the differential voltage presented any one of the input channels and the corresponding output code. Note that for the current channels, the state of the GAIN input pin is assumed to driven low, such that the PGA gain on the current channels is 1x. If the PGA gain of the current channels is set to 20x, then a +40 mV differential voltage presented across the “IIN+” and “IIN-” pins will cause a (nominal) output code of 32767. Input Voltage (mV0-pk)  1 – z – 256 3 H ( z ) =  ----------------------  1 – z–1  If the OWRS pin is set to logic high, then the transfer function is Output Code Output Code (hexadecimal) (decimal) +800 7FFF 32767 0.0122 to 0.0366 0001 1 -0.0122 to 0.0122 0000 0 -0.0122 to -0.0366 FFFF -1 -800 8000 -32768  1 – z – 128 3 H ( z ) =  ----------------------  1 – z–1  The above filter samples the modulator bit stream at XIN/8 Hz and decimates to XIN/1024 Hz. 2.4 Table 1. Nominal Relationship for Differential Input Voltage vs. Output Code, for all channels. (Assume PGA gain is set to 1x.) 2.3 High Rate Digital Filters If the OWRS pin is set to logic low, the high-rate filters are implemented as fixed sinc3 filters with the following transfer function: This filter samples the modulator bit stream at XIN/8 Hz and decimates to XIN/2048 Hz. Serial Interface The CS5471 communicates with a target device via a master serial data output port. Output data is provided on the SDO output synchronous with the SCLK output. A third output, FSO, is a framing signal used to signal the start of output data. These three outputs will be driven as long as the SE (serial enable) input is held high. Otherwise, these outputs will be high impedance. SCLK FSO Each data segment is 16 bits long. SDO Channel 1 (V) 64 0-value bits Channel 1 (I) Figure 3. Serial Port Data Transfer 8 CS5471 96 SCLK Cycles . . . SCLK . . . FSO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDO Channel 1 ( V ) Channel 1 ( I ) . . . All 0’s Figure 4. Close-up of One Frame Data out (SDO) changes as a result of SCLK falling, and always outputs valid data with SCLK rising. When data is being transferred, the SCLK frequency is either 1/8 of the XIN input frequency (when OWRS is held low) or 1/4 of the XIN input frequency (when OWRS is held high). Any other time, SCLK is held low. (See Figures 3 and 4.) The framing signal (FSO) output is normally low, but produces a high level pulse lasting one SCLK period when the instantaneous voltage/current data samples are about to be transmitted out of the serial interface (after each A/D conversion cycle). Note that SCLK is not active during FSO high. For 96 SCLK periods after FSO falls, SCLK is active and SDO produces valid output. Six channels of 16 bit data are output, MSB first. First, the voltage and current measurements are output (in that order). This is followed by four more 16-bit words of zero-value data. SCLK will then be held low until the next sample period. 2.5 System Initialization When power to the CS5471 is applied, the chip must be held in a reset condition using the RESET input. A hardware reset is initiated when the RESET pin is forced low with a minimum pulse width of 50 ns. 2.6 Analog Inputs The analog inputs of the CS5471 are bipolar voltage inputs: One voltage channel input pair (VIN+ and VIN-) and current channel input pair (IIN+ and IIN-). The CS5471 accommodates a full scale range of ±40 mV or ±800 mV on the Current Channel and ±800 mV on the Voltage Channel. 2.7 Voltage Reference The CS5471 is specified for operation with a +1.2 V reference between the VREFIN and AGND pins. The converter includes an internal 1.2 V reference (50 ppm/°C drift) that can be used by connecting the VREFOUT pin to the VREFIN pin of the device. If higher accuracy/stability is required, an external reference can be used. 2.8 Using the Charge Pump Drive Pin The low, stable analog power consumption and superior supply rejection of the CS5471 allow for the use of a simple charge-pump negative supply generator. The use of a negative supply alleviates the need for level shifting of the analog inputs. The CPD pin and capacitor C1 provide the necessary analog supply current as shown in Figure 5. The Schottky diodes D1 and D2 are chosen for their low forward voltages and high-speed capabilities. The capacitor C2 provides the required charge storage 9 CS5471 and bypassing of the negative supply. The CPD output signal provides the charge pump driver signal. The frequency of the charge pump driver signal is synchronous to XIN. The nominal average frequency is 1 Mhz. The level on the VA- pin is fed back internally so that the CPD output will regulate the VA- level to -2/3 of VA+ level. 12.5%. Therefore, the value of C1 should be reduced by 12.5%, making the new value for C1 to be 35 nF. For more information about the operation of this type of charge pump circuit, the reader can refer to Cirrus Logic, Inc.’s application note AN152: Using the CS5521/24/28, and CS5525/26 Charge Pump Drive for External Loads. 2.9 CPD AGND 40 nF C1 VA- D2 BAT 85 D1 BAT 85 C2 1 µF Figure 5. Generating VA- with a Charge Pump Note the value of C1 in Figure 5. The 40 nF value is recommended when the input frequency presented to the XIN pin is 4.00 MHz. If the user decides to use an XIN frequency that is significantly different than 4.00 MHz (if the XIN frequency is increased/decreased by more than 5% of 4.00 MHz, then it is recommended that the user should alter the value of C1. The percentage change in the value of C1 (with respect to a reference value of 40 nF) should be inversely proportional to the percentage change in the XIN frequency. For example, if the XIN frequency is increased from 4.00 MHz to 4.5 MHz, this represents a percentage increase of 10 PCB Layout For optimal performance, the CS5460A should be placed entirely over an analog ground plane with both the VA- and DGND pins of the device connected to the analog plane. Place the analog-digital plane split immediately adjacent to the digital portion of the chip. Note: Refer to the CDB5460A Evaluation Board for suggested layout details and Applications Note 18 for more detailed layout guidelines. Before layout, please call for our Free Schematic Review Service. CS5471 3. PIN DESCRIPTION Serial Clock Output SCLK Serial Data Output SDO Frame Sync FSO Serial Port Enable SE Current Input Gain GAIN Analog Ground AGND Reference Input VREFIN Reference Output VREFOUT Positive Analog Supply VA+ Negative Analog Supply VA- 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VD+ DGND CPD XIN RESET OWRS VIN+ VINIIN+ IIN- Digital Supply Digital Ground Charge Pump Drive Master Clock Reset Output Word Rate Select Differential Voltage Input 1 Differential Voltage Input 1 Differential Current Input 1 Differential Current Input 1 Clock Generator XIN - Master Clock Input Control Pins and Serial Data I/O SE - Serial Port Enable. When SE is low, the output pins of the serial port are 3-stated. SDO - Serial Port Output. Data will be at a rate determined by SCLK. FSO - Frame Signal Output. Framing signal output for data transfer from SDO pin. SCLK - Serial Clock Output. A clock signal on this pin determines the output rate of data for SDO pin. Rate of SCLK is determined by XIN frequency and state of OWRS input pin. RESET - Reset. When reset is taken low, all internal registers are set to their default states. GAIN - Input Gain Control. Sets input gain for current channel. A logic high sets internal gain to 1, a logic low level sets the gain to 20. If no connection is made to this pin, it will default to logic low level (through internal 200K resistor to DGND). OWRS - Output Word Rate Select. When OWRS is set to logic low, the output word rate (OWR) at SDO pin is XIN/2048 (Hz). When set to logic high, the OWR at SDO pin is XIN/1024 (Hz). If no connection is made to this pin, then OWRS will default to logic low level (through internal 200K resistor to DGND). 11 CS5471 Measurement and Reference Input IIN+, IIN- - Differential Current Input. Differential analog input pins for current channel. VIN+, VIN- - Differential Voltage Inputs. Differential analog input pins for voltage channel. VREFOUT - Voltage Reference Output. The on-chip voltage reference is output from this pin. The voltage reference has a nominal magnitude of 1.2 V and is referenced to the AGND pin on the converter. VREFIN - Voltage Reference Input. The voltage input to this pin establishes the voltage reference for the on-chip modulator. Power Supply Connections VA+ - Positive Analog Supply. The positive analog supply is nominally +3 V ±10% relative to AGND. VA- - Negative Analog Supply. The negative analog supply is nominally -2 V ±10% relative to AGND. AGND - Analog Ground. The analog ground pin for input signals. VD+ - Positive Digital Supply. The positive digital supply is nominally +3 V ±10% relative to DGND. DGND - Digital Ground. The digital ground is typically at the same level as AGND. CPD - Charge Pump Drive This output pin drives the external charge pump circuitry to create a negative supply voltage. 12 CS5471 4. PACKAGE DIMENSIONS 20L SSOP PACKAGE DRAWING N D E11 A2 E e b2 SIDE VIEW A ∝ A1 L END VIEW SEATING PLANE 1 2 3 TOP VIEW DIM A A1 A2 b D E E1 e L ∝ MIN -0.002 0.064 0.009 0.272 0.291 0.197 0.022 0.025 0° INCHES NOM -0.006 0.068 -0.2834 0.307 0.209 0.026 0.03 4° MAX 0.084 0.010 0.074 0.015 0.295 0.323 0.220 0.030 0.041 8° MIN -0.05 1.62 0.22 6.90 7.40 5.00 0.55 0.63 0° MILLIMETERS NOM -0.13 1.73 -7.20 7.80 5.30 0.65 0.75 4° NOTE MAX 2.13 0.25 1.88 0.38 7.50 8.20 5.60 0.75 1.03 8° 2,3 1 1 JEDEC #: MO-150 Controlling Dimension is Millimeters. Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. 13