CS5503-BP

CS5501 CS5501 CS5503 CS5503 16 & 20-Bit Converter Non-aliasing, 16- & A/D 20-bit A/D Converters Features I Description Monolithic CMOS ADC with Filtering The CS5501 and CS5503 are CMOS A/D converters ideal for measuring low-frequency signals representing physical, chemical, and biological processes. They utilize charge-balance techniques to achieve 16-bit (CS5501) and 20-bit (CS5503) performance with up to 4 kSps word rates. - 6-pole, Low-pass Gaussian Filter Up to 4 kHz Output Word Rates - On Chip Self-calibration Circuitry - Linearity Error: ±0.0003% - Differential Nonlinearity: CS5501: 16-bit, No Missing Codes (DNL ±1/8 LSB) CS5503: 20-bit, No Missing Codes The converters continuously sample at a rate set by the user in the form of either a CMOS clock or a crystal. Onchip digital filtering processes the data and updates the output register at up to a 4 kSps rate. The converters' lowpass, 6-pole Gaussian response filter is designed to allow corner frequency settings from 0.1 Hz to 10 Hz in the CS5501 and 0.5 Hz to 10 Hz in the CS5503. Thus, each converter rejects 50 Hz and 60 Hz line frequencies as well as any noise at spurious frequencies. System Calibration Capability Flexible Serial Communications Port - Microcontroller-compatible Formats - 3-state Data and Clock Outputs - UART Format (CS5501 only) Pin-selectable Unipolar/Bipolar Ranges Low Power Consumption: 25 mW - 10 µW Sleep Mode for Portable Applications The CS5501 and CS5503 include on-chip self-calibration circuitry which can be initiated at any time or temperature to insure offset and full-scale errors of typically less than 1/2 LSB for the CS5501 and less than 4 LSB for the CS5503. The devices can also be applied in system calibration schemes to null offset and gain errors in the input channel. Each device's serial port offers two general purpose modes of operation for direct interface to shift registers or synchronous serial ports of industry-standard microcontrollers. In addition, the CS5501's serial port offers a third, UART-compatible mode of asynchronous communication. ORDERING INFORMATION See page 33. I BP/UP SLEEP BP/UPSLEEP 12 CS550112 11 SC1 SC2 SC1 4 SC2 17 4 13 CS5503 Calibration Calibration CAL Calibration Calibration SRAM Microcontroller13 CAL Microcontroller SRAM 14 14 10 VA+ VA+ Charge-balanced A/D Converter VREF 10 Charge-Balanced A/D Converter 7 7 VREF VAAnalog 6-pole Gaussian VA9 Digital Filter 15 Analog Modulator 6-PoleLow-pass Gaussian VD+ 9 AIN 15 AIN Modulator Low-Pass Digital Filter 6 VD- VD+ 6 8 VDAGND AGND 8 20 20 Clock Generator Serial Interface Logic SDATA Clock Generator Serial Interface Logic SDATA DGND5 5 DGND 2 18 18 1 19 23 3 16 116 19 CLKIN CLKOUT CS MODE SCLK CLKOUTCLKIN DRDYDRDY CS MODESCLK Cirrus Logic, Inc. www.cirrus.com http://www.cirrus.com 11 Copyright  Cirrus Logic, 2003 Copyright © Cirrus Logic, Inc.Inc. 2005 Rights Reserved) (All(All Rights Reserved) SEP ‘04 AUG ‘05 DS31F4 DS31F5 1 CS5501 CS5503 CS5501/CS5503 CS5501 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 2.5V; CLKIN = 4.096MHz; Bipolar Mode; MODE = +5V; Rsource = 750Ω with a 1nF to AGND at AIN (see Note 1); Digital Inputs: Logic 0 = GND; Logic 1 = VD+; unless otherwise specified.) CS5501-A, B, C Parameter* Min Specified Temperature Range Typ CS5501-S, T Max Min -40 to +85 Typ Max Units °C -55 to +125 Accuracy -A, S -B, T -C - 0.0015 0.0007 0.0003 0.003 0.0015 0.0012 - 0.0007 0.003 0.0015 ±%FS ±%FS ±%FS TMIN to TMAX - ±1/8 ±1/2 - ±1/8 ±1/2 LSB16 Full Scale Error (Note 2) - ±0.13 ±0.5 - ±0.13 ±0.5 LSB16 Full Scale Drift (Note 3) - ±1.2 - - ±2.3 - LSB16 Unipolar Offset (Note 2) - ±0.25 ±1 - ±0.25 ±1 LSB16 Unipolar Offset Drift (Note 3) - ±4.2 - - +3.0 -25.0 - LSB16 Bipolar Offset (Note 2) - ±0.25 ±1 - ±0.25 ±1 LSB16 Bipolar Offset Drift (Note 3) - ±2.1 - - +1.5 -12.5 - LSB16 Bipolar Negative Full Scale Error (Note 2) - ±0.5 ±2 - ±0.5 ±2 LSB16 Bipolar Negative Full Scale Drift (Note 3) - ±0.6 - - ±1.2 - LSB16 - 1/10 - - 1/10 - LSBrms Linearity Error Differential Nonlinearity Noise (Referred to Output) Notes: 1. The AIN pin presents a very high input resistance at dc and a minor dynamic load which scales to the master clock frequency. Both source resistance and shunt capacitance are therefore critical in determining the CS5501’s source impedance requirements. For more information refer the text section Analog Input Impedance Considerations. 2. Applies after calibration at the temperature of interest. 3. Total drift over the specified temperature range since calibration at power-up at 25°C (see Figure 11). This is guaranteed by design and /or characterization. Recalibration at any temperature will remove these errors. µV Unipolar Mode Bipolar Mode LSB’s %FS ppm FS LSB’s %FS ppm FS 10 0.26 0.0004 4 0.13 0.0002 2 19 0.50 0.0008 8 0.26 0.0004 4 38 1.00 0.0015 15 0.50 0.0008 8 76 2.00 0.0030 30 1.00 0.0015 15 152 4.00 0.0061 61 2.00 0.0030 30 CS5501 Unit Conversion Factors, VREF = 2.5V * Refer to the Specification Definitions immediately following the Pin Description Section. 22 DS31F5 DS31F4 CS5501 CS5503 CS5501/CS5503 CS5503 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 2.5V; CLKIN = 4.096MHz; Bipolar Mode; MODE = +5V; Rsource = 750. with a 1nF to AGND at AIN (see Note 1): unless otherwise specified.) CS5503-A, B, C Parameter* Min Specified Temperature Range Typ CS5503-S, T Max Min -40 to +85 Accuracy Linearity Error Typ Max Units °C -55 to +125 -A, S -B, T -C - 0.0015 0.0007 0.0003 0.003 0.0015 0.0012 - 0.0007 0.003 TBD ±%FS ±%FS ±%FS TMIN to TMAX - 20 - - 20 - Bits Full Scale Error (Note 2) - ±4 ±16 - ±4 ±16 LSB20 Full Scale Error Drift (Note 3) - ±19 - - ±37 - LSB20 ±16 - ±4 ±16 LSB20 +48 -400 ±4 - LSB20 ±16 LSB20 Differential Nonlinearity (Not Missing Codes) Unipolar Offset (Note 2) - ±4 Unipolar Offset Drift (Note 3) - ±67 - - Bipolar Offset (Note 2) - ±4 ±16 - Bipolar Offset Drift (Note 3) - ±34 - - Bipolar Negative Full Scale Error (Note 2) - ±8 ±32 Bipolar Negative Full Scale Drift (Note 3) - ±10 - 1.6 Noise (Referred to Output) . V - LSB20 - +24 -200 ±8 ±32 LSB20 - - ±20 - LSB20 - - 1.6 - LSBrms (20) Unipolar Mode Bipolar Mode %FS ppm Fs LSB’s %FS ppm FS LSB’s 0.596 0.25 0.0000238 0.24 0.13 0.0000119 0.12 1.192 0.50 0.0000477 0.47 0.26 0.0000238 0.24 2.384 1.00 0.0000954 0.95 0.50 0.0000477 0.47 4.768 2.00 0.0001907 1.91 1.00 0.0000954 0.95 9.537 4.000 0.0003814 3.81 2.00 0.0001907 1.91 CS5503 Unit Conversion Factors, VREF = 2.5V * Refer to the Specification Definitions immediately following the Pin Description Section. DS31F5 DS31F4 3 3 CS5501 CS5503 CS5501/CS5503 ANALOG CHARACTERISTICS (Continued) CS5501/3-A, B, C Parameter* CS5501/3-S, T Min Typ Max Min Typ Max Units (Note 4) - 2 2 1 0.03 3.2 3.2 1.5 0.1 - 2 2 1 0.03 3.2 3.2 1.5 0.1 mA mA mA mA (Note 4) - 25 10 40 20 - 25 10 40 40 mW µW (Note 5) - 70 75 - - 70 75 - dB dB Power Supplies DC Power Supply Currents IA+ IAID+ IDPower Dissipation SLEEP High SLEEP Low Power Supply Rejection Positive Supplies Negative Supplies Analog Input Analog Input Range Unipolar 0 to +2.5 0 to +2.5 Bipolar Input Capacitance DC Bias Current (Note 1) V - ±2.5 - - ±2.5 - V - 20 - - 20 - pF - 1 - - 1 - nA System Calibration Specifications Positive Full Scale Calibration Range VREF+0.1 VREF+0.1 V Positive Full Scale Input Overrange VREF+0.1 VREF+0.1 V Negative Full Scale Input Overrange -(VREF+0.1) -(VREF+0.1) V -(VREF +0.1) -40%VREF to +40%VREF -(VREF +0.1) -40%VREF to +40%VREF V V 80% VREF 80% VREF V Maximum Offset Calibration Range Unipolar Mode Bipolar Mode Input Span (Notes 6, 7) (Note 8) 2VREF +0.2 2VREF +0.2 Notes: 4. All outputs unloaded. 5. 0.1Hz to 10Hz. PSRR at 60 Hz will exceed 120 dB due to the benefit of the digital filter. 6. In unipolar mode the offset can have a negative value (-VREF) such that the unipolar mode can mimic bipolar mode operation. 7. The specifications for Input Overrange and for Input Span apply additional constraints on the offset calibration range. 8. For Unipolar mode, Input Span is the difference between full scale and zero scale. For Bipolar mode, Input Span is the difference between positive and negative full scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ±(VREF + 0.1). Specifications are subject to change without notice. 44 DS31F5 DS31F4 CS5501 CS5503 CS5501/CS5503 DYNAMIC CHARACTERISTICS Symbol Ratio Units Sampling Frequency fs CLKIN/ 256 Hz Output Update Rate f out CLKIN /1024 Sps CLKIN /409,600 Hz 506,880/CLKIN s Parameter f -3dB Filter Corner Frequency Settling Time to ts +0.0007% _ FS (FS Step) 20 0 Output Amplitude in dB -20 CLKIN = 4 MHz -40 -60 CLKIN = 2 MHz -80 -100 CLKIN = 1 MHz -120 -140 1 10 100 1000 Frequency in Hz Frequency Response j2 j1 -σ -2 jω S1,2 = -1.4667 ± j1.8199 S3,4 = -1.7559 ± j1.0008 -1 -j1 S5,6 = -1.8746 ± j0.32276 -j2 S-Domain Pole/Zero Plot (Continuous-Time Representation) H(x) = [1 + 0.694x2 + 0.241x4 + 0.0557x6 + 0.009664x8 + 0.00134x10 + 0.000155x12]-1/2 where x = f/f-3dB, f-3dB = CLKIN/409,600, and f is the frequency of interest. Continuous-Time Representation of 6-Pole Gaussian Filter DS31F5 DS31F4 55 CS5501 CS5503 CS5501/CS5503 DIGITAL CHARACTERISTICS (TA = Tmin to Tmax; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%) Parameter Symbol Min Typ Max Units Calibration Memory Retention Power Supply Voltage (VD+ and VA+) VMR 2.0 - - V High-Level Input Voltage All Except CLKIN VIH 2.0 - - V High-Level Input Voltage CLKIN VIH 3.5 - - V Low-Level Input Voltage All Except CLKIN VIL - - 0.8 V Low-Level Input Voltage CLKIN VIL - - 1.5 V VOH (VD+)-1.0V - - V VOL - - 0.4 V Input Leakage Current Iin - - 10 µA 3-State Leakage Current IOZ - - ±10 µA Digital Output Pin Capacitance Cout - 9 - pF High-Level Output Voltage Low-Level Output Voltage (Note 9) Iout=1.6mA Notes: 9. Iout = -100 µA. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ Iout = -40 µA). ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Units VD+ VDVA+ VA- -0.3 0.3 -0.3 0.3 (VA+)+0.3 -6.0 6.0 -6.0 V V V V Iin - ±10 mA Analog Input Voltage (AIN and VREF pins) VINA (VA-)-0.3 (VA+)+0.3 V Digital Input Voltage VIND -0.3 (VA+)+0.3 V TA -55 125 C° Tstg -65 150 C° DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog Input Current, Any Pin Except Supplies (Notes 10, 11) Ambient Operating Temperature Storage Temperature Notes: 10. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin. 11. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power supply pin is ± 50 mA. 66 DS31F5 DS31F4 CS5501 CS5503 CS5501/CS5503 RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V) (Note 12) Parameter DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog Analog Reference Voltage Analog Input Voltage: Symbol Min Typ Max Units VD+ VDVA+ VA- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 VA+ -5.5 5.5 -5.5 V V V V VREF 1.0 2.5 3.0 V VAIN VAIN AGND -VREF - VREF VREF V V (Note 13) Unipolar Bipolar Notes: 12. All voltages with respect to ground. 13. The CS5501 and CS5503 can accept input voltages up to the analog supplies (VA+ and VA-). They will accurately convert and filter signals with noise excursions up to 100mV beyond |VREF|. After filtering, the devices will output all 1’s for any input above VREF and all 0’s for any input below AGND in unipolar mode and -VREF in bipolar mode. SWITCHING CHARACTERISTICS (TA = Tmin to Tmax; CLKIN=4.096 MHz; VA+, VD+ = 5V±10%; VA-, VD- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF; unless otherwise specified.) Parameter Master Clock Frequency: Symbol Internal Gate Oscillator CLKIN (See Table 1) Externally Supplied: (Note 14) CLKIN Maximum Minimum (Note 15) CLKIN CLKIN Duty Cycle Rise Times: Fall Times: Set Up Times: Hold Time: Min Typ Max Units 200 4096 5000 kHz 200 40 5000 - kHz kHz 20 - 80 % Any Digital Input Any Digital Output (Note 16) trise trise - 20 1.0 - µs ns Any Digital Input Any Digital Output (Note 16) tfall tfall - 20 1.0 - µs ns SC1, SC2 to CAL Low SLEEP High to CLKIN High (Note 17) tscs tsls 100 1 - - ns µs SC1, SC2 hold after CAL falls tsch 100 - - ns Notes: 14. CLKIN must be supplied whenever the CS5501 or CS5503 is not in SLEEP mode. If no clock is present when not in SLEEP mode, the device can draw higher current than specified and possibly become uncalibrated. 15. The CS5501/CS5503 is production tested at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz. 16. Specified using 10% and 90% points on waveform of interest. 17. In order to synchronize several CS5501’s or CS5503’s together using the SLEEP pin, this specification must be met. DS31F5 DS31F4 7 7 CS5501 CS5503 CS5501/CS5503 SWITCHING CHARACTERISTICS (continued) (TA = Tmin to Tmax; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) Parameter Symbol Min Typ Max Units SSC Mode (Mode = VD+) Access Time CS Low to SDATA Out tcsd1 3/CLKIN - - ns SDATA Delay Time SCLK Falling to New SDATA bit tdd1 - 25 100 ns SCLK Delay Time (at 4.096 MHz) SDATA MSB bit to SCLK Rising tcd1 250 380 - ns Serial Clock (Out) Pulse Width High (at 4.096 MHz) Pulse Width Low tph1 tpl1 - 240 730 300 790 ns Output Float Delay SCLK Rising to Hi-Z tfd2 - 1/CLKIN + 100 1/CLKIN + 200 ns Output Float Delay CS High to Output Hi-Z (Note 18) tfd1 - - 4/CLKIN +200 ns fsclk dc - 4.2 MHz tph2 tpl2 50 180 - - ns SEC Mode (Mode = DGND) Serial Clock (In) Serial Clock (In) Pulse Width High Pulse Width Low Access Time CS Low to Data Valid (Note 19) tcsd2 - 80 160 ns Maximum Data Delay Time (Note 20) SCLK Falling to New SDATA bit tdd2 - 75 150 ns CS High to Output Hi-Z tfd3 - - 250 ns Output Float Delay 100 200 ns Output Float Delay SCLK Falling to Output Hi-Z tfd4 Notes: 18. If CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance. 19. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for 4 clock cycles. The propagation delay time may be as great as 4 CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asychronous CS, SCLK(i) should not be taken high sooner than 4 CLKIN cycles plus 160ns after CS goes low. 20. SDATA transitions on the falling edge of SCLK(i). CLKIN CAL t scs SC1, SC2 VALID Calibration Control Timing 88 CS t sls t sch SLEEP Sleep Mode Timing for Synchronization tfd1 SDATA Output Float Delay SSC Mode (Note 19) DS31F5 DS31F4 CS5501 CS5503 CS5501/CS5503 CLKIN CS t csd1 SDATA Hi-Z MSB MSB-1 MSB-2 t dd1 Hi-Z t fd2 t cd1 SCLK (o) LSB Hi-Z Hi-Z t ph1 t pl1 SSC MODE Timing Relationships DRDY CS t csd2 SDATA t fd3 Hi-Z MSB MSB-1 Hi-Z t dd2 SCLK (i) t pl2 t ph2 CS t csd2 SDATA Hi-Z MSB MSB-1 t dd2 SCLK (i) LSB Hi-Z t fd4 t ph2 SEC MODE Timing Relationships DS31F5 DS31F4 9 9 CS5501 CS5503 CS5501/CS5503 SWITCHING CHARACTERISTICS (continued) (TA = Tmin to Tmax; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C L = 50 pF) Parameter Symbol Min Typ Max Units fsclk dc - 4.2 MHz AC Mode (Mode = VD-) CS5501 only Serial Clock (In) Serial Clock (In) Pulse Width High Pulse Width Low tph3 tpl3 50 180 - - ns ns Set-up Time CS Low to SCLK Falling tcss - 20 40 ns Maximum Data Delay Time SCLK Fall to New SDATA bit tdd3 - 90 180 ns Output Float Delay tfd5 - 100 200 ns CS High to Output Hi-Z (Note 21) Notes: 21. If CS is returned high after an 11-bit data packet is started, the SDATA output will continue to output data until the end of the second stop bit. At that time the SDATA output will go to high impedance. DRDY CS t css t ph3 SCLK(i) t pl3 t dd3 SDATA Hi-Z START BIT8 High Byte BIT9 BIT6 t fd5 BIT7 STOP1 STOP2 Hi-Z Low Byte AC MODE Timing Relationships (CS5501 only) 10 10 DS31F5 DS31F4 CS5501 CS5503 CS5501/CS5503 GENERAL DESCRIPTION The CS5501/CS5503 are monolithic CMOS A/D converters designed specifically for high resolution measurement of low-frequency signals. Each device consists of a charge-balance converter (16Bit for the CS5501, 20-Bit for the CS5503), calibration microcontroller with on-chip SRAM, and serial communications port. mation in the form of frequency (or duty cycle), which is then filtered (averaged) by the counter for higher resolution. LP Filter S/H Amp 1-bit Digital Filter Comparator DAC 16-bits The CS5501/CS5503 A/D converters perform conversions continuously and update their output ports after every conversion (unless the serial port is active). Conversions are performed and the serial port is updated independent of external control. Both devices are capable of measuring either unipolar or bipolar input signals, and calibration cycles may be initiated at any time to ensure measurement accuracy. The CS5501/CS5503 perform conversions at a rate determined by the master clock signal. The master clock can be set by an external clock or with a crystal connected to the pins of the on-chip gate oscillator. The master clock frequency determines: 1. The sample rate of the analog input signal. 2. The corner frequency of the on-chip digital filter. 3. The output update rate of the serial output port. The CS5501/CS5503 design includes several selfcalibration modes and several serial port interface modes to offer users maximum system design flexiblity. The Delta-Sigma Conversion Method The CS5501/CS5503 A/D converters use chargebalance techniques to achieve low cost, high resolution measurements. A charge-balance A/D converter consists of two basic blocks: an analog modulator and a digital filter. An elementary example of a charge-balance A/D converter is a conventional voltage-to-frequency converter and counter. The VFC’s 1-bit output conveys inforDS31F5 DS31F4 Figure 1. Charge Balance (Delta-Sigma) A/D Converter The analog modulator of the CS5501/CS5503 is a multi-order delta-sigma modulator. The modulator consists of a 1-bit A/D converter (that is, a comparator) embedded in an analog feedback loop with high open loop gain (see Figure 1). The modulator samples and converts the input at a rate well above the bandwidth of interest. The 1-bit output of the comparator is sampled at intervals based on the clock rate of the part and this information (either a 1 or 0) is conveyed to the digital filter. The digital filter is much more sophisticated than a simple counter. The filter on the chip has a 6-pole low pass Gaussian response which rolls off at 120 dB/decade (36 dB/octave). The corner frequency of the digital filter scales with the master clock frequency. In comparison, VFC’s and dual slope converters offer (sin x)/x filtering for high frequency rejection (see Figure 2 for a comparison of the characteristics of these two filter types). When operating from a 1 MHz master clock the digital filter in the CS5501/CS5503 offers better than 120 dB rejection of 50 and 60 Hz line frequencies and does not require any type of line synchronization to achieve this rejection. It should be noted that the CS5501/CS5503 will update its output port almost at 1000 times per second when operating from the 1 MHz clock. This is a much higher update rate (typically by a factor of at least 50 times) than either VFCs or dual-slope converters can offer. For a more detailed discussion on the delta-sigma modulator see the Application note "Delta-Sigma 11 11 CS5501 CS5503 0 0 -20 -20 Magnitude (dB) Magnitude (dB) CS5501/CS5503 -40 -60 -40 CLKIN = 4 MHz -60 CLKIN = 2 MHz -80 -80 -100 -100 CLKIN=1 MHz 0 20 40 60 Frequency (Hz) 80 100 0 20 a. Averaging (Integrating) Filter Response (tavg = 100 ms) 40 60 Frequency (Hz) 80 100 b. 6-Pole Gaussian Filter Response Figure 2. Filter Responses A/D Conversion Technique Overview" in the application note section of the data book. The application note discusses the delta-sigma modulator and some aspects of digital filtering. OVERVIEW As shown in the block diagram on the front page of the data sheet, the CS5501/CS5503 can be segmented into five circuit functions. The heart of the chip is the charge balance A/D converter (16-bit for the CS5501, 20-bit for the CS5503). The converter and all of the other circuit functions on the chip must be driven by a clock signal from the clock generator. The serial interface logic outputs the converted data. The calibration microcontroller along with the calibration SRAM (static RAM), supervises the device calibration. Each segment of the chip has control lines associated with it. The function of each of the pins is described in the pin description section of the data sheet. Clock Generator The CS5501/CS5503 both include gates which can be connected as a crystal oscillator to provide the master clock signal for the chip. Alternatively, an external (CMOS compatible) clock can be input to the CLKIN pin as the master clock for the device. Figure 3 illustrates a simple model of the on-chip gate oscillator. The gate has a typical transconductance of 1500 µmho. The gate model includes 10 pf capacitors at the input and output pins. These capacitances include the typical stray capacitance of the pins of the device. The on-chip R1 500 k Ω CLKIN 3 CLKOUT 2 10pF 10pF g m C1 * 1500 umho Y1 C2 * * See Table 1 Figure 3. On-chip Gate Oscillator Model 12 12 DS31F5 DS31F4 CS5501 CS5503 CS5501/CS5503 gate oscillator is designed to properly operate without additional loading capacitors when using a 4.096 MHz (or 4 MHz) crystal. If other crystal frequencies or if ceramic resonators are used, loading capacitors may be necessary for reliable operation of the oscillator. Table 1 illustrates some typical capacitor values to be used with selected resonating elements. Resonators C1 C2 200 kHz 330pF 470pF 455 kHz 100pF 100pF 1.0 MHz 50pF 50pF 2.0 MHz 20pF 20pF 2.000 MHz 30pF 30pF 3.579 MHz 20pF 20pF 4.096 MHz None None Ceramic Crystals Table 1. Resonator Loading Capacitors CLKOUT (pin 2) can be used to drive one external CMOS gate for system clock requirements. In this case, the external gate capacitance must be taken into account when choosing the value of C2. Caution: A clock signal should always be present whenever the SLEEP is inactive (SLEEP = VD+). If no clock is provided to the part when not in SLEEP, the part may draw excess current and possibly even lose its calibration data. This is because the device is built using dynamic logic. Serial Interface Logic The CS5501 serial data output can operate in any one of the following three different serial interface modes depending upon the MODE pin selection: SSC (Synchronous Self-Clocking) mode; MODE pin tied to VD+ (+5V). SEC (Synchronous External Clocking) mode; MODE pin tied to DGND. DS31F5 DS31F4 and AC (Asynchronous Communication) mode; CS5501 only MODE pin tied to VD- (-5V) The CS5503 can only operate in the first two modes, SEC and SSC. Synchronous Self-Clocking Mode When operated in the SSC mode (MODE pin tied to VD+), the CS5501/CS5503 furnish both serial output data (SDATA) and an internally-generated serial clock (SCLK). Internal timing for the SSC mode is illustrated in Figure 4. Figure 5 shows detailed SSC mode timing for both the CS5501/CS5503. A filter cycle occurs every 1024 cycles of CLKIN. During each filter cycle, the status of CS is polled at eight specific times during the cycle. If CS is low when it is polled, the CS5501/CS5503 begin clocking the data bits out, MSB first, at a SCLK output rate of CLKIN/4. Once transmission is complete, DRDY rises and both SDATA and SCLK outputs go into a high impedance state. A filter cycle begins each time DRDY falls. If the CS line is not active, DRDY will return high 1020 clock cycles after it falls. Four clock cycles later DRDY will fall to signal that the serial port has been updated with new data and that a new filter cycle has begun. The first CS polling during a filter cycle occurs 76 clock cycles after DRDY falls (the rising edge of CLKIN on which DRDY falls is considered clock cycle number one). Subsequent pollings of CS occur at intervals of 128 clock cycles thereafter (76, 204, 332, etc.). The CS signal is polled at the beginning of each of eight data output windows which occur in a filter cycle. To transmit data during any one of the eight output windows, CS must be low at least three CLKIN cycles before it is polled. If CS does not meet this set-up time, data will not be transmitted during the window time. Furthermore, CS is not latched internally and therefore must be held low during the entire data transmission to obtain all of the data bits. 13 13 CS5501 CS5503 CS5501/CS5503 64/CLKIN Internal Status Note 1 Analog Time 0 fout =1024/CLKIN 64/CLKIN Digital Time 0 76/CLKIN Analog Time 1 Digital Time1 CS Polled DRDY (o) CS (i) CS5501 SCLK (o) Hi-Z CS5501 SDATA (o) Hi-Z CS5503 SCLK (o) Hi-Z CS5503 SDATA (o) Hi-Z Hi-Z (MSB) (LSB) Hi-Z Hi-Z (MSB) (LSB) Hi-Z Note: 1. There are 16 analog and digital settling periods per filter cycle (4 are shown). Data can be output in the SSC mode in only 1 of the 8 digital time periods in each filter cycle. Figure 4. Internal Timing CLKIN (i) 76 CLKIN cycles DRDY (o) CS (i) SDATA (o) Hi-Z (MSB) B15* B19** B14* B18** B1 Hi-Z SCLK (o) (LSB) B0 Hi-Z Hi-Z * CS5501 ** CS5503 Figure 5. Synchronous Self-Clocking (SSC) Mode Timing The eighth output window time overlaps the time in which the serial output port is to be updated. If the CS is recognized as being low when it is polled for the eighth window time, data will be output as normal, but the serial port will not be updated with new data until the next serial port update time. Under these conditions, the serial port will experience an update rate of only 2 kSps 14 14 (CLKIN = 4.096 MHz) instead of the normal 4 kSps serial port update rate. Upon completion of transmission of all the data bits, the SCLK and SDATA outputs will go to a high impedance state even with CS held low. In the event that CS is taken high before all data bits are output, the SDATA and SCLK outputs will DS31F5 DS31F4 CS5501 CS5503 CS5501/CS5503 complete the current data bit output and go to a high impedance state when SCLK goes low. This insures that CS will be recognized and the MSB bit will become stable before the SCLK transitions positive to latch the MSB data bit. Synchronous External Clocking Mode When operated in the SEC mode (MODE pin tied to DGND), the CS5501/CS5503 outputs the data in its serial port at a rate determined by an external clock which is input into the SCLK pin. In this mode the output port will be updated every 1024 CLKIN cycles. DRDY will go low when new data is loaded into the output port. If CS is not active, DRDY will return positive 1020 CLKIN cycles later and remain so for four CLKIN cycles. If CS is taken low it will be recognized immediately unless it occurs while DRDY is high for the four clock cycles. As soon as CS is recognized, the SDATA output will come out of its high-impedance state and present the MSB data bit. The MSB data bit will remain present until a falling edge of SCLK occurs to advance the output to the MSB-1 bit. If the CS and external SCLK are operated asynchronously to CLKIN, errors can result in the output data unless certain precautions are taken. If CS is activated asynchronously, it may occur during the four clock cycles when DRDY is high and therefore not be recognized immediately. To be certain that data misread errors will not result if CS occurs at this time, the SCLK input should not transition high to latch the MSB until four CLKIN cycles plus 160 ns after CS is taken low. When SCLK returns low the serial port will present the MSB-1 data bit on its output. Subsequent cycles of SCLK will advance the data output. When all data bits are clocked out, DRDY will then go high and the SDATA output will go into a high impedance state. If the CS input goes low and all of the data bits are not clocked out of the port, filter cycles will continue to occur but the output serial port will not be updated with new data (DRDY will remain low). If CS is taken high at any time, the SDATA output pin will go to a high impedance state. If any of the data bits in the serial port have not been clocked out, they will remain available until DRDY returns high for four clock cycles. After this DRDY will fall and the port will be updated with a new 16-bit word in the CS5501 or 20-bit word in the CS5503. It is acceptable to clock out less than all possible data bits if CS is returned high to allow the port to be updated. Figure 6 illustrates the serial port timing in the SEC mode. Asynchronous Communication Mode (CS5501 Only) In the CS5501, the AC mode is activated when the MODE pin is tied to VD- (-5 V). When operating in the AC mode the CS5501 is designed to DRDY (o) CS (i) SCLK (i) SDATA (o) Hi-Z (MSB) B15* B19** (LSB) B14* B18** B1 B0 Hi-Z * CS5501 ** CS5503 Figure 6. Synchronous External-Clocking (SEC) Mode Timing DS31F5 DS31F4 15 15 CS5501 CS5503 CS5501/CS5503 provide data output in UART compatible format. The baud rate of the SDATA output will be determined by the rate of the SCLK input. The data which is output of the SDATA pin will be formatted such that it will contain two 11 bit data packets. Each packet includes one start bit, eight data bits, and two stop bits. The packet which carries the most-significant-byte data will be output first, with its lsb being the first data bit output after the start bit. In this mode, DRDY will occur every 1024 clock cycles. If the serial port is not outputting a data byte, DRDY will return high after 1020 clock cycles and remain high for 4 clock cycles. DRDY will then go low to indicate that an update to the serial output port with a new 16 bit word has occurred. To initiate a transmission from the port the CS line must be taken low. Then SCLK, which is an input in this mode, must transition from a high to a low to latch the state of CS internal to the CS5501. Once CS is recognized and latched as a low, the port will begin to output data. Figure 7 details the timing for this output. CS can be returned high before the end of the 11-bit transmission and the transmission will continue until the second stop bit of the first 11-bit packet is output. The SDATA output will go into a high impedance state after the second stop bit is output. To obtain the second 11-bit packet CS must again be brought low before DRDY goes high or the second 11-bit data packet will be overwritten with a serial port update. For the second 11-bit packet, CS need only to go low for 50 ns; it need not be latched by a falling edge of SCLK. Alternately, the CS line can be taken low and held low until both 11-bit data packets are output. This is the preferred method of control as it will prevent losing the second 11-bit data packet if the port is updated. Some serial data rates can be quite slow compared to the rate at which the CS5501 can update its output port. A slow data rate will leave only a short period of time to start the second 11bit packet if CS is returned high momentarily. If CS is held low continuously (CS hard-wired to DGND), the serial port will be updated only after all 22 bits have been clocked out of the port. Upon the completion of a transmission of the two 11-bit data packets the SDATA output will go into a high impedance state. If at any time during transmission the CS is taken back high, the current 11-bit data packet will continue to be output. At the end of the second stop bit of the data packet, the SDATA output will go into a high impedance state. Linearity Performance The CS5501/CS5503 delta-sigma converters are like conventional charge-balance converters in that they have no source of nonmonotonicity. The devices therefore have no missing codes in their transfer functions. See Figure 8 for a plot of the SCLK (i) DRDY (o) CS (i) SDATA (o) Hi-Z Start B8 B9 B14 B15 Stop Stop Start B0 1 2 B1 B6 B7 Stop Stop 1 2 Figure 7. CS5501 Asynchronous (UART) Mode Timing 16 16 DS31F5 DS31F4 CS5501 CS5503 CS5501/CS5503 +1 DNL (LSB) +1/2 0 -1/2 -1 0 32,768 65,535 Codes Figure 8. CS5501 Differential Nonlinearity Plot excellent differential linearity achieved by the CS5501. The CS5501/CS5503 also have excellent integral linearity, which is accomplished with a well-designed charge-balance architecture. Each device also achieves low input drift through the use of chopper-stabilized techniques in its input stage. To assure that the CS5501/CS5503 achieves excellent performance over time and temperature, it uses digital calibration techniques to minimize offset and gain errors to typically within ±1/2 LSB at 16 bits in the CS5501 and ±4 LSB at 20 bits in the CS5503. Calibration The CS5501/CS5503 offer both self-calibration and system level calibration capability. To understand the calibration features, a basic comprehension of the internal workings of the converter are helpful. As mentioned previously in this data sheet, the converter consists of two sections. First is the analog modulator which is a delta-sigma type charge-balance converter. This is followed by a digital filter. The filter circuitry is actually an arithmetic logic unit (ALU) whose architecture and instructions execute the filter function. The modulator (explained in more detail in the applications note "Delta-Sigma Conversion Technique Overview") uses the VREF voltage connected to pin 10 to determine the magnitude of the voltages used in its feedback DAC. The modulator accepts an analog signal at its input and produces a data stream of 1’s and 0’s as its output. This data stream value can change DS31F5 DS31F4 (from 1 to 0 or vice versa) every 256 CLKIN cycles. As the input voltage increases the ratio of 1’s to 0’s out of the modulator increases proportionally. The 1’s density of the data stream out of the modulator therefore provides a digital representation of the analog input signal where the 1’s density is defined as the ratio of the number of 1’s to the number of 0’s out of the modulator for a given period of time. The 1’s density output of the modulator is also a function of the voltage on the VREF pin. If the voltage on the VREF pin increases in value (say, due to temperature drift), and the analog input voltage into the modulator remains constant, the 1’s density output of the modulator will decrease (less 1’s will occur). The analog input into the modulator which is necessary to produce a given binary output code from the converter is ratiometric to the voltage on the VREF pin. This means that if VREF increases by one per cent, the analog signal on AIN must also increase by one per cent to maintain the same binary output code from the converter. For a complete calibration to occur, the calibration microcontroller inside the device needs to record the data stream 1’s density out of the modulator for two different input conditions. First, a "zero scale" point must be presented to the modulator. Then a "full scale" point must be presented to the modulator. In unipolar self-cal mode the zero scale point is AGND and the full scale point is the voltage on the VREF pin. The calibration microcontroller then remembers the 1’s density out of the modulator for each of these points and calculates a slope factor (LSB/µV). This slope factor 17 17 CS5501 CS5503 CS5501/CS5503 represents the gain slope for the input to output transfer function of the converter. In unipolar mode the calibration microcontroller determines the slope factor by dividing the span between the zero point and the full scale point by the total resolution of the converter (216 for the CS5501, resulting in 65,536 segments or 220 for the CS5503, resulting in 1,048,578 segments). In bipolar mode the calibration microcontroller divides the span between the zero point and the full scale point into 524,288 segments for the CS5503 and 32,768 segments for the CS5501. It then extends the measurement range 524,288 segments for the CS5503, 32,768 segments for the CS5501, below the zero scale point to achieve bipolar measurement capability. In either unipolar or bipolar modes the calculated slope factor is saved and later used to calculate the binary output code when an analog signal is present at the AIN pin during measurement conversions. Figure 9). System calibration performs the same slope factor calculations as self cal but uses voltage values presented by the system to the AIN pin for the zero scale point and for the full scale point. Table 2 depicts the calibration modes available. Two system calibration modes are listed. The first mode offers system level calibration for system offset and for system gain. This is a two step calibration. The zero scale point (system offset) must be presented to the converter first. The voltage that represents zero scale point must be input to the converter before the calibration step is initiated and must remain stable until the step is complete. The DRDY output from the converter will signal when the step is complete by going low. After the zero scale point is calibrated, the voltage representing the full scale point is input to the converter and the second calibration step is initiated. Again the voltage must remain stable throughout the calibration step. System calibration allows the A/D converter to compensate for system gain and offset errors (see This two step calibration mode offers another calibration feature. After a two step calibration VREF sys Signal Conditioning Circuitry Analog MUX Transducer SCLK CS5501 CS5503 SDATA CAL SC1 SC2 A0 A1 CLK DATA µC I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 Figure 9. System Calibration CAL SC1 SC2 Cal Type ZS Cal FS Cal Sequence Calibration Time 0 0 Self-Cal AGND VREF One Step 3,145,655/fclk 1 1 AIN - 1st Step 1,052,599/fclk 0 1 System Offset & System Gain - AIN 2nd Step 1,068,813/fclk 1 0 System Offset AIN VREF One Step 2,117,389/fclk * DRDY remains high throughout the calibration sequence. In Self-Cal mode (SC1 and SC2 low) DRDY falls once the CS5501 or CS5503 has settled to the analog input. In all other modes DRDY falls immediately after the calibration term has been determined. Table 2. Calibration Control 18 18 DS31F5 DS31F4 CS5501 CS5503 CS5501/CS5503 sequence (system offset and system gain) has been properly performed, additional offset calibrations can be performed by themselves to reposition the gain slope (the slope factor is not changed) to adjust its zero reference point to the new system zero reference value. A second system calibration mode is available which uses an input voltage for the zero scale calibration point, but uses the VREF voltage as the full scale calibration point. Whenever a system calibration mode is used, there are limits to the amount of offset and to the amount of span which can be accommodated. The range of input span which can be accommodated in either unipolar or bipolar mode is restricted to not less than 80% of the voltage on VREF and not more than 200% of (VREF + 0.1) V. The amount of offset which can be calibrated depends upon whether unipolar or bipolar mode is being used. In unipolar mode the system calibration modes can handle offsets as positive as 20% of VREF (this is restricted by the minimum span requirement of 80% VREF) or as negative as -(VREF + 0.1) V. This capability enables the unipolar mode of the CS5501/CS5503 to be calibrated to mimic bipolar mode operation. In the bipolar mode the system offset calibration range is restricted to a maximum of ±40% of VREF. It should be noted that the span restrictions limit the amount of offset which can be calibrated. The span range of the converter in bipolar mode extends an equidistance (+ and -) from the voltage used for the zero scale point. When the zero scale point is calibrated it must not cause either of the two endpoints of the bipolar transfer function to exceed the positive or the negative input overrange points (+(VREF + 0.1) V or - (VREF + 0.1) V). If the span range is set to a minimum (80% VREF) the offset voltage can move ±40% VREF without causing the end points of the transfer function to exceed the overrange points. Alternatively, if the span range is set to 200% of DS31F5 DS31F4 VREF, the input offset cannot move more than +0.1 or 0.1 V before an endpoint of the transfer function exceeds the input overrange limit. Initiating Calibration Table 2 illustrates the calibration modes available in the CS5501/CS5503. Not shown in the table is the function of the BP/UP pin which determines whether the converter is calibrated to measure bipolar or unipolar signals. A calibration step is initiated by bringing the CAL pin (13) high for at least 4 CLKIN cycles to reset the part and then bringing CAL low. The states of SC1 (pin 4) and SC2 (pin 17) along with the BP/UP (pin 12) will determine the type of calibration to be performed. The SC1 and SC2 inputs are latched when CAL goes low. The BP/UP input is not latched and therefore must remain in a fixed state throughout the calibration and measurement cycles. Any time the state of the BP/UP pin is changed, a new calibration cycle must be performed to enable the CS5501/CS5503 to properly function in the new mode. When a calibration step is initiated, the DRDY signal will go high and remain high until the step is finished. Table 2 illustrates the number of clock cycles each calibration requires. Once a calibration step is initiated it must finish before a new calibration step can be executed. In the two step system calibration mode, the offset calibration step must be initiated before initiating the gain calibration step. When a self-cal is completed DRDY falls and the output port is updated with a data word that represents the analog input signal at the AIN pin. When a system calibration step is completed, DRDY will fall and the output port will be updated with the appropriate data value (zero scale point, or full scale point). In the system calibration mode, the digital filter must settle before the output code will represent the value of the analog input signal. 19 19 CS5501 CS5503 CS5501/CS5503 Cal Mode Zero Scale 1LSB Gain Factor Unipolar Bipolar CS5501 CS5503 CS5501 CS5503 Self-Cal AGND VREF VREF 65,536 VREF 1,048,526 2VREF 65,536 2VREF 1,048,526 System Cal SOFF SGAIN SGAIN−SOFF 65,536 SGAIN−SOFF 1,048,526 2(SGAIN−SOFF) 65,536 2(SGAIN−SOFF) 1,048,526 Table 3. Output Code Size After Calibration Input Voltage, Unipolar Mode System-Cal Self-Cal >(SGAIN - 1.5 LSB) SGAIN - 1.5 LSB Input Voltage, Bipolar Mode Output Codes (Hex) CS5501 CS5503 Self-Cal System Cal >(VREF - 1.5 LSB) FFFF FFFFF >(VREF - 1.5 LSB) >(SGAIN - 1.5 LSB) FFFF FFFFF VREF - 1.5 LSB FFFE FFFFE VREF - 1.5 LSB SGAIN - 1.5 LSB AGND - 0.5 LSB SOFF -0.5 LSB (SGAIN - SOFF)/2 - 0.5 LSB VREF/2 - 0.5 LSB 8000 80000 7FFF 7FFFF 0001 00001 SOFF + 0.5 LSB AGND + 0.5 LSB 0000 00000 -VREF+ 0.5 LSB -SGAIN + 2SOFF + 0.5 LSB