CS5506-BSZ

CS5505/6/7/8 CS5505/6/7/8 Very Low Power, 16-bit & 20-Bit A/D Converters Very Low Power, 16-Bit and20-bit A/D Converters Features l Very Description The CS5505/6/7/8 are a family of low power CMOS A/D converters which are ideal for measuring low-frequency signals representing physical, chemical, and biological processes. The CS5507/8 have single-channel differential analog and reference inputs while the CS5505/6 have four pseudo-differential analog input channels. The CS5505/7 have a 16-bit output word. The CS5506/8 have a 20-bit output word.The CS5505/6/7/8 sample upon command up to 100 Sps. The on-chip digital filter offers superior line rejection at 50 and 60 Hz when the device is operated from a 32.768 kHz clock (output word rate = 20 Sps). The CS5505/6/7/8 include on-chip self-calibration circuitry which can be initiated at any time or temperature to ensure minimum offset and full-scale errors. The CS5505/6/7/8 serial port offers two general-purpose modes for the direct interface to shift registers or synchronous serial ports of industry-standard microcontrollers. ORDERING INFORMATION See page 30. Low Power Consumption - Single supply +5 V operation: 1.7 mW - Dual supply ±5 V operation: 3.2 mW l Offers superior performance to VFCs and multi-slope integrating ADCs l Differential Inputs - Single Channel (CS5507/8) and Four-Channel (CS5505/6) pseudo-differential versions l Either 5 V or 3.3 V Digital Interface l Linearity Error: - ±0.0015% FS (16-bit CS5505/7) - ±0.0007% FS (20-bit CS5506/8) l Output update rates up to 100 Sps l Flexible Serial Port l Pin-Selectable Unipolar/Bipolar Ranges I 9$ 9$ 9' '*1' 95()287 95() 95() $,1 $,1 $,1 $,1 $,1         &DOLEUDWLRQ 65$0    &6 %,7 $1' &6 %,7 6+2:1 $ $ &DOLEUDWLRQ µ& 26&   &219 ;,1 ;287 08; 'LIIHUHQWLDO WK2UGHU 'HOWD6LJPD 0RGXODWRU 'LJLWDO )LOWHU 9ROWDJH 5HIHUHQFH     6HULDO ,QWHUIDFH /RJLF   &6 '5'<  6&/.  6'$7$  06/3  &$/  %383 Cirrus Logic, Inc. Crystal Semiconductor Products Division http://www.cirrus.com P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com Copyright © Cirrus Copyright  Cirrus Logic, Inc. 2009 Logic, Inc. 1997 (All Rights Reserved) (All Rights Reserved) MAR ‘09 AUG ‘95 DS59F4 DS59F6 1 CS5505/6/7/8 CS5505/6/7/8 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ = 3.3V ± 5%; VREF+ = 2.5V(external); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kΩ with a 10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2) CS5505/7-A Parameter* Specified Temperature Range Min Typ -40 to +85 Max Min CS5507-S Typ -55 to +125 Max Units °C 0.003 ±0.5 ±2 ±4 ±2 ±%FS LSB16 LSB16 LSB16 LSB16 LSB16 LSB16 LSB16 LSBrms16 Accuracy Linearity Error Differential Nonlinearity Full Scale Error Full Scale Drift Unipolar Offset Unipolar Offset Drift Bipolar Offset Bipolar Offset Drift Noise (Referred to Output) (Note 3) (Note 4) (Note 3) (Note 4) (Note 3) (Note 4) 0.0015 ±0.25 ±0.25 ±0.5 ±0.5 ±0.5 ±0.25 ±0.25 0.16 0.003 ±0.5 ±2 ±2 ±1 0.0015 ±0.25 ±0.5 ±2 ±1 ±1 ±0.5 ±0.5 0.16 Notes: 1. The AIN pin presents a very high input resistance at dc and a minor dynamic load which scales to the master clock frequency. Both source resistance and shunt capacitance are therefore critical in determining the CS5505/6/7/8’s source impedance requirements. For more information refer to the text section Analog Input Impedance Considerations. 2. Specifications guaranteed by design, characterization and/or test. 3. Applies after calibration at the temperature of interest. 4. Total drift over the specified temperature range since calibration at power-up at 25°C. Recalibration at any temperature will remove these errors. mV 10 19 38 76 152 LSB’s 0.26 0.50 1.00 2.00 4.00 Unipolar Mode % FS 0.0004 0.0008 0.0015 0.0030 0.0061 ppm FS LSB’s 4 0.13 8 0.26 15 0.50 30 1.00 61 2.00 VREF = 2.5V Bipolar Mode % FS 0.0002 0.0004 0.0008 0.0015 0.0030 ppm FS 2 4 8 15 30 CS5505/7; 16-Bit Unit Conversion Factors * Refer to the Specification Definitions immediately following the Pin Description Section. Specifications are subject to change without notice. 2 2 DS59F4 DS59F6 CS5505/6/7/8 CS5505/6/7/8 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ = 3.3V ± 5%; VREF+ = 2.5V (external); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kΩ with a 10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2) CS5506/8-B Parameter* Specified Temperature Range Min Typ -40 to +85 Max Min CS5508-S Typ -55 to +125 Max Units °C 0.003 ±32 ±64 ±32 LSB20 LSB20 LSB20 LSB20 LSB20 LSB20 LSBrms20 ±%FS Bits 20 (Note 3) (Note 4) (Note 3) (Note 4) (Note 3) (Note 4) ±4 ±8 ±8 ±8 ±4 ±4 2.6 ±32 ±32 ±16 20 ±8 ±32 ±16 ±16 ±8 ±8 2.6 Accuracy Linearity Error Differential Nonlinearity (No Missing Codes) Full Scale Error Full Scale Drift Unipolar Offset Unipolar Offset Drift Bipolar Offset Bipolar Offset Drift Noise (Referred to Output) 0.0007 0.0015 0.0015 mV 0.596 1.192 2.384 4.768 9.537 LSB’s 0.25 0.50 1.00 2.00 4.00 Unipolar Mode % FS 0.0000238 0.0000477 0.0000954 0.0001907 0.0003814 ppm FS LSB’s 0.24 0.13 0.47 0.26 0.95 0.50 1.91 1.00 3.81 2.00 VREF = 2.5V Bipolar Mode % FS 0.0000119 0.0000238 0.0000477 0.0000954 0.0001907 ppm FS 0.12 0.24 0.47 0.95 1.91 CS5506/8; 20-Bit Unit Conversion Factors DYNAMIC CHARACTERISTICS Parameter Modulator Sampling Frequency Output Update Rate (CONV = 1) Filter Corner Frequency Settling Time to 1⁄2 LSB (FS Step) Symbol fs fout f-3dB ts Ratio fclk/2 fclk/1622 fclk/1928 1/fout Units Hz Sps Hz s DS59F4 DS59F6 3 CS5505/6/7/8 CS5505/6/7/8 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; CS5505/7 CS5506/8 Parameter* Specified Temperature Range Min Typ -40 to +85 VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ = 3.3V ± 5%; VREF+ = 2.5V (external); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kΩ with a 10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2) CS5507/8-S Max Min Typ -55 to +125 Max Units °C Volts Volts dB dB dB pF nA Analog Input Analog Input Range: (VAIN+)-(VAIN-) Unipolar Bipolar (Note 5) 120 (Note 1) 0 to +2.5 ±2.5 105 120 15 5 120 0 to +2.5 ±2.5 105 120 15 5 Common Mode Rejection: dc 50, 60 Hz (Note 6) Off Channel Isolation Input Capacitance DC Bias Current Voltage Reference (Output) VREFOUT Voltage VREFOUT Voltage Tolerance VREFOUT Voltage Temperature Coefficient VREFOUT Line Regulation VREFOUT Output Voltage Noise 0.1 to 10 Hz VREFOUT: Source Current Sink Current (VA+)-2.5 60 1.5 50 4.0 3 50 (VA+)-2.5 60 1.5 50 4.0 3 50 Volts % ppm/°C mV/Volt µVp-p µA µA µA µA µA mW µW dB dB Power Supplies DC Power Supply Currents: ITotal IAnalog IDigital 340 300 40 3.2 5 80 80 450 4.5 10 340 300 40 3.2 10 80 80 450 4.5 25 - Power Dissipation: (Note 7) SLEEP inactive SLEEP active Power Supply Rejection: Positive Supplies Negative Supplies Notes: 5. Common mode voltage may be at any value as long as AIN+ and AIN- remain within the VA+ and VA- supply voltages. 6. XIN = 32.768 kHz. Guaranteed by design and / or characterization. 7. All outputs unloaded. All inputs CMOS levels. SLEEP mode controlled by M/SLP pin. SLEEP active = M/SLP pin at (VD+)/2 input level. 4 4 DS59F4 DS59F6 CS5505/6/7/8 CS5505/6/7/8 5V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; Parameter High-Level Input Voltage: XIN M/SLP All Pins Except XIN and M/SLP XIN M/SLP All Pins Except XIN and M/SLP (Note 8) (Note 9) Iout = 1.6 mA VA+VD+ = 5V ± 10%; VA-= -5V ± 10%; DGND = 0.) All measurements below are performed under static conditions. (Note 2) Symbol VIH VIH VIH VIL VIL VIL VSLP VOH VOL Iin IOZ Cout Min 3.5 0.9VD+ 2.0 0.45VD+ (VD+)-1.0 Typ 0.5VD+ 1 9 Max 1.5 0.1VD+ 0.8 0.55VD+ 0.4 10 ±10 Units V V V V V V V V V µA µA pF Low-Level Input Voltage: M/SLP SLEEP Active Threshold High-Level Output Voltage Low Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance Notes: 8. Under normal operation this pin should be tied to VD+ or DGND. Anytime the voltage on the M/SLP pin enters the SLEEP active threshold range the device will enter the power down condition. Returning to the active state requires elapse of the power-on reset period, the oscillator to start-up, and elapse of the wake-up period. 9. Iout = -100 µA. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ Iout = -40 µA). 3.3V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; Parameter High-Level Input Voltage: XIN M/SLP All Pins Except XIN and M/SLP XIN M/SLP All Pins Except XIN and M/SLP (Note 8) Iout = -400 µA Iout = 400 µA Symbol VIH VIH VIH VA+ = 5V ± 10%; VD+ = 3.3V ± 5%; VA-= -5V ± 10%; DGND = 0.) All measurements below are performed under static conditions. (Note 2) Min 0.7VD+ 0.9VD+ 0.6VD+ Typ Max 0.3VD+ 0.1VD+ 0.16VD+ Units V V V V V V V V V µA µA pF Low-Level Input Voltage: VIL VIL VIL VSLP VOH VOL Iin IOZ Cout M/SLP SLEEP Active Threshold High-Level Output Voltage Low Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance 0.43VD+ 0.45VD+ 0.47VD+ (VD+)-0.3 1 9 0.3 10 ±10 - DS59F4 DS59F6 5 CS5505/6/7/8 CS5505/6/7/8 5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; Parameter Master Clock Frequency: Internal Oscillator: External Clock: Master Clock Duty Cycle Rise Times: Fall Times: Any Digital Input Any Digital Output Any Digital Input Any Digital Output (Note 10) (Note 10) trise tfall -A,B -S Symbol XIN or fclk VA+, VD+ = 5V ± 10%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2) Min 30.0 30.0 30 40 Typ 32.768 32.768 50 20 Max 53.0 34.0 163 60 1.0 1.0 Units kHz kHz kHz % µs ns µs ns Start-Up Power-On Reset Period Oscillator Start-up Time Wake-up Period XTAL=32.768 kHz (Note 11) (Note 12) (Note 13) tres tosu twup tccw tscl tcal tsac thca tcpw tscn tbus tbuh tcon BP/UP stable prior to DRDY falling BP/UP stable after DRDY falls (Note 15) 10 500 1800/fclk 3246/fclk 1624/fclk ms ms s Calibration CONV Pulse Width (CAL = 1) CONV and CAL High to Start of Calibration Start of Calibration to End of Calibration (Note 14) 100 2/fclk+200 ns ns s Conversion Set Up Time Hold Time CONV Pulse Width CONV High to Start of Conversion Set Up Time Hold Time A0, A1 to CONV High A0, A1 after CONV High 50 100 100 82/fclk 0 2/fclk+200 ns ns ns ns s ns s Start of Conversion to End of Conversion Notes: 10. Specified using 10% and 90% points on waveform of interest. 11. An internal power-on-reset is activated whenever power is applied to the device, or when coming out of a SLEEP state. 12. Oscillator start-up time varies with the crystal parameters. This specification does not apply when using an external clock source. 13. The wake-up period begins once the oscillator starts; or when using an external fclk, after the power-on reset time elapses. 14. Calibration can also be initiated by pulsing CAL high while CONV=1. 15. Conversion time will be 1622/fclk if CONV remains high continuously. 6 6 DS59F4 DS59F6 CS5505/6/7/8 CS5505/6/7/8 VA+ = 5V ± 10%; VD+ = 3.3V ± 5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2) Parameter Master Clock Frequency: Internal Oscillator: External Clock: Master Clock Duty Cycle Rise Times: Fall Times: Any Digital Input Any Digital Output Any Digital Input Any Digital Output (Note 10) (Note 10) trise tfall -A,B -S Symbol XIN or fclk Min 30.0 30.0 30 40 Typ 32.768 32.768 50 20 Max 53.0 34.0 163 60 1.0 1.0 Units kHz kHz kHz % µs ns µs ns 3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX Start-Up Power-On Reset Period Oscillator Start-up Time Wake-up Period XTAL=32.768 kHz (Note 11) (Note 12) (Note 13) tres tosu twup tccw tscl tcal tsac thca tcpw tscn tbus tbuh tcon BP/UP stable prior to DRDY falling BP/UP stable after DRDY falls (Note 15) 10 500 1800/fclk 3246/fclk 1624/fclk ms ms s Calibration CONV Pulse Width (CAL = 1) CONV and CAL High to Start of Calibration Start of Calibration to End of Calibration (Note 14) 100 2/fclk+200 ns ns s Conversion Set Up Time Hold Time CONV Pulse Width CONV High to Start of Conversion Set Up Time Hold Time A0, A1 to CONV High A0, A1 after CONV High 50 100 100 82/fclk 0 2/fclk+200 ns ns ns ns s ns s Start of Conversion to End of Conversion DS59F4 DS59F6 7 CS5505/6/7/8 CS5505/6/7/8 XIN XIN/2 CAL t ccw CONV t scl STATE Standby t cal Calibration Standby Figure 1. Calibration Timing (Not to Scale) XIN XIN/2 A0, A1 t sac CONV DRDY BP/UP t scn STATE Standby t con Conversion t bus t buh Standby t cpw t hca Figure 2. Conversion Timing (Not to Scale) 8 8 DS59F4 DS59F6 CS5505/6/7/8 CS5505/6/7/8 5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; Parameter Symbol VA+, VD+ = 5V ± 10%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2) Min Typ Max Units SSC Mode (M/SLP = VD+) Access Time: SDATA Delay Time: SCLK Delay Time Serial Clock (Out) Output Float Delay: CS Low to SDATA out (DRDY = low) DRDY falling to MSB (CS = low) SCLK falling to next SDATA bit SDATA MSB bit to SCLK rising Pulse Width High Pulse Width Low CS high to output Hi-Z (Note 16) SCLK rising to SDATA Hi-Z tcsd1 tdfd tdd1 tcd1 tph1 tpl1 tfd1 tfd2 fsclk Pulse Width High Pulse Width Low CS Low to data valid (Note 17) (Note 18) SCLK falling to new SDATA bit CS high to output Hi-Z (Note 16) SCLK falling to SDATA Hi-Z tph2 tpl2 tcsd2 tdd2 tfd3 tfd4 2/fclk 80 1/fclk 1/fclk 1/fclk 1/fclk 60 150 60 160 2/fclk 3/fclk 250 2/fclk ns ns ns ns ns ns ns ns SEC Mode (M/SLP = DGND) Serial Clock (In) Serial Clock (In) Access Time: Maximum Delay time: Output Float Delay: 0 200 200 2.5 200 310 150 300 MHz ns ns ns ns ns ns Notes: 16. If CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance. 17. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for 2 clock cycles. The propagation delay time may be as great as 2 f clk cycles plus 200 ns. To guarantee proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high sooner than 2 fclk + 200 ns after CS goes low. 18. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the serial port shifting mechanism before falling edges can be recognized. DS59F4 DS59F6 9 CS5505/6/7/8 CS5505/6/7/8 VA+ = 5V ± 10%; VD+ = 3.3V ± 5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2) Parameter Symbol Min Typ Max Units 3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX SSC Mode (M/SLP = VD+) Access Time: SDATA Delay Time: SCLK Delay Time Serial Clock (Out) Output Float Delay: CS Low to SDATA out (DRDY = low) DRDY falling to MSB (CS = low) SCLK falling to next SDATA bit SDATA MSB bit to SCLK rising Pulse Width High Pulse Width Low CS high to output Hi-Z (Note 16) SCLK rising to SDATA Hi-Z tcsd1 tdfd tdd1 tcd1 tph1 tpl1 tfd1 tfd2 fsclk Pulse Width High Pulse Width Low CS Low to data valid (Note 17) (Note 18) SCLK falling to new SDATA bit CS high to output Hi-Z (Note 16) SCLK falling to SDATA Hi-Z tph2 tpl2 tcsd2 tdd2 tfd3 tfd4 2/fclk 265 1/fclk 1/fclk 1/fclk 1/fclk 100 400 70 320 2/fclk 3/fclk 400 2/fclk ns ns ns ns ns ns ns ns SEC Mode (M/SLP = DGND) Serial Clock (In) Serial Clock (In) Access Time: Maximum Delay time: Output Float Delay: 0 200 200 1.25 200 600 150 500 MHz ns ns ns ns ns ns 10 10 DS59F4 DS59F6 CS5505/6/7/8 CS5505/6/7/8 XIN XIN/2 CONV CS STATE DRDY tph1 SCLK(o) Hi-Z tcd1 SDATA(o) Hi-Z MSB Standby Conversion tcsd1 Standby Conversion Hi-Z tdd1 MSB-1 tpl1 LSB+1 tfd2 LSB Hi-Z STATE (CONV held high) Conversion1 Conversion2 Figure 3. Timing Relationships; SSC Mode (Not to Scale) DRDY CS SDATA(o) Hi-Z SCLK(i) t csd2 t fd3 MSB MSB-1 MSB-2 t dd2 DRDY CS t csd2 SDATA(o) Hi-Z MSB MSB-1 LSB+2 LSB+1 LSB t dd2 SCLK(i) t ph2 t pl2 t fd4 Figure 4. Timing Relationships; SEC Mode (Not to Scale) DS59F4 DS59F6 11 CS5505/6/7/8 CS5505/6/7/8 RECOMMENDED OPERATING CONDITIONS (DGND = 0V) Parameter DC Power Supplies: Positive Digital (VA+)-(VA-) Positive Analog Negative Analog Symbol VD+ Vdiff VA+ VAMin 3.15 4.5 4.5 0 1.0 0 -((VREF+)-(VREF-)) (Note 19) Max 5.5 11 11 -5.5 3.6 (VREF+)-(VREF-) +((VREF+)-(VREF-)) Units V V V V V V V Typ 5.0 10 5.0 -5.0 2.5 - Analog Reference Voltage (Note 20) (VREF+)-(VREF-) Analog Input Voltage: (Note 21) Unipolar Bipolar VAIN VAIN Notes: 19. All voltages with respect to ground. 20. The CS5505/6/7/8 can be operated with a reference voltage as low as 100 mV; but with a corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and VA-. 21. The CS5505/6/7/8 can accept input voltages up to the analog supplies (VA+ and VA-). In unipolar mode the CS5505/6/7/8 will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output all 0’s if the input becomes more negative than 0 Volts. In bipolar mode the CS5505/6/7/8 will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output all 0’s if the input becomes more negative in magnitude than -((VREF+)-(VREF-)). ABSOLUTE MAXIMUM RATINGS* Parameter DC Power Supplies: Digital Ground Positive Digital Positive Analog Negative Analog (VA+)-(VA-) (VA+)-(VD+) (Note 22) (Note 23) Symbol DGND VD+ VA+ VAVdiff1 Vdiff2 Iin VINA VIND TA T stg Min -0.3 -0.3 -0.3 +0.3 -0.3 -0.3 (VA-)-0.3 -0.3 -55 -65 Typ Max (VD+)-0.3 6.0 or VA+ 12.0 -6.0 12.0 12.0 ±10 (VA+)+0.3 (VD+)+0.3 125 150 Units V V V V V V mA V V °C Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature Notes: 22. 23. 24. 25. (Notes 24, 25) AIN and VREF pins °C No pin should go more positive than (VA+)+0.3V. VD+ must always be less than (VA+)+0.3 V,and can never exceed 6.0V. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power supply pin is ± 50 mA. * WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 12 12 DS59F4 DS59F6 CS5505/6/7/8 CS5505/6/7/8 GENERAL DESCRIPTION The CS5505/6/7/8 are very low power monolith ic CM OS A/D co nverters designed specifically for measurement of dc signals. The CS5505/7 are 16-bit converters (a four channel and a single channel version). The CS5506/8 are 20-bit converters (a four channel and a single channel version). Each of the devices includes a delta-sigma charge-balance converter, a voltage reference, a calibration microcontroller with SRAM, a digital filter and a serial interface. The CS5505 and CS5506 include a four channel pseudo-differential (all four channels have the same reference measurement node) multiplexer. The CS5505/6/7/8 include an on-chip reference but can also utilize an off-chip reference for precision applications. The CS5505/6/7/8 can be used to measure either unipolar or bipolar signals. The devices use self-calibration to insure excellent offset and gain accuracy. The CS5505/6/7/8 are optimized to operate from a 32.768 kHz crystal but can be driven by an external clock whose frequency is between 30 kHz and 163 kHz. When the digital filter is operated with a 32.768 kHz clock, the filter has zeros precisely at 50 and 60 Hz line frequencies and multiples thereof. The CS5505/6/7/8 use a "start convert" command to latch the input channel selection and to start a convolution cycle on the digital filter. Once the filter cycle is completed, the output port is updated. When operated with a 32.768 kHz clock the ADC converts and updates its output port at 20 samples/sec. The throughput rate per channel is the output update rate divided by th e number of channels being multiplexed. The output port includes a serial interface with two modes of operation. The CS5505/6/7/8 can operate from dual polarity power supplies (+5 and -5), from a single +5 volt supply, or with +10 volts on the analog and DS59F4 DS59F6 +5 on the digital. They can also operate with dual polarity (+5 and -5), or from a single +5 volt supply on the analog and + 3.3 on the digital. THEORY OF OPERATION FOR THE CS5505/6/7/8 The front page of this data sheet illustrates the block diagram of the CS5505/6. Basic Converter Operation The CS5505/6/7/8 A/D converters have four operating states. These are start-up, calibration, conversion and sleep. When power is first applied, the device enters the start-up state. The first step is a power-on reset delay of about 10 ms which resets all of the logic in the device. To proceed with start-up, the oscillator must then begin oscillating. After the power-on reset the device enters the wake-up period for 1800 clock cycles after clock is present. This allows the delta-sigma modulator and other circuitry (which are operating with very low currents) to reach a stable bias condition prior to entering into either the calibration or conversion states. During the 1800 cycle wake-up period, the device can accept an input command. Execution of this command will not occur until the complete wake-up period elapses. If no command is given, the device enters the standby mode. Calibration After the initial application of power, the CS5505/6/7/8 must enter the calibration state prior to performing accurate conversions. During calibration, the chip executes a two-step process. The device first performs an offset calibration and then follows this with a gain calibration. The two calibration steps determine the zero reference point and the full scale reference point of the converter’s transfer function. From these points it calibrates the zero point and a gain 13 CS5505/6/7/8 CS5505/6/7/8 slope to be used to properly scale the output digital codes when doing conversions. The calibration state is entered whenever the CAL and CONV pins are high at the same time. The state of the CAL and CONV pins at poweron and when coming out of sleep are recognized as commands, but will not be executed until the end of the 1800 clock cycle wake-up period. Note that any time CONV transitions from low to high, the multiplexer inputs A0 and A1 are latched internal to the CS5505 and CS5506 devices. These latched inputs select the analog input channel which will be used once conversion commences. If CAL and CONV become active (high) during the 1800 clock cycle wake-up time, the converter will wait until the wake-up period elapses before executing the calibration. If the wake-up time has elapsed, the converter will be in the standby mode waiting for instruction and will enter the calibration cycle immediately. The calibration lasts for 3246 clock cycles. Calibration coefficients are then retained in the SRAM (static RAM) for use during conversion. At the end of the calibration cycle, the on-chip microcontroller checks the logic state of the CONV signal. If the CONV input is low the device will enter the standby mode where it waits for further instruction. If the CONV signal is high at the end of the calibration cycle, the converter will enter the conversion state and perform a conversion on the input channel which was selected when CONV transitioned from low to high. The CAL signal can be returned low any time after calibration is initiated. CONV can also be returned low, but it should never be taken low and then taken back high until the calibration period has ended and the converter is in the standby state. If CONV is taken low and then high again with CAL high while the converter is calibrating, the device will interrupt the current calibration cycle and start a new one. If CAL is taken low and CONV is taken low and 14 14 then high during calibration, the calibration cycle will continue as the conversion command is disregarded. The states of A0, A1 and BP/UP are not important during calibrations. If an "end of calibration" signal is desired, pulse the CAL signal high while leaving the CONV signal high continuously. Once the calibration is completed, a conversion will be performed. At the end of the conversion, DRDY will fall to indicate the first valid conversion after the calibration has been completed. See Understanding Converter Calibration for details on how the converter calibrates its transfer function. Conversion The conversion state can be entered at the end of the calibration cycle, or whenever the converter is idle in the standby mode. If CONV is taken high to initiate a calibration cycle ( CAL also high), and remains high until the calibration cycle is completed (CAL is taken low after CONV transitions high), the converter will begin a conversion upon completion of the calibration period. The device will perform a conversion on the input channel selected by the A0 and A1 inputs when CONV transitioned high. Table 1 indicates the multiplexer channel selection truth table for A0 and A1. A1 0 0 1 1 A0 0 1 0 1 Channel addressed AIN1 AIN2 AIN3 AIN4 Table 1. Multiplexer Truth Table The A0 and A1 inputs are latched internal to the 4-channel devices (CS5505/6) when CONV rises. A0 and A1 have internal pull-down circuits which default the multiplexer to channel DS59F4 DS59F6 CS5505/6/7/8 CS5505/6/7/8 AIN1. The BP/UP pin is not a latched input. The BP/UP pin controls how the output word from the digital filter is processed. In bipolar mode the output word computed by the digital filter is offset by 8000H in the 16-bit CS5505/7 or 80000H in 20-bit CS5506/8 (see Understanding Converter Calibration). BP/UP can be changed after a conversion is started as long as it is stable for 82 clock cycles of the conversion period prior to DRDY falling. If one wishes to intermix measurement of bipolar and unipolar signals on various input channels, it is best to switch the BP/UP pin immediately after DRDY falls and leave BP/UP stable until DRDY falls again. If the converter is beginning a conversion starting from the standby state, BP/UP can be changed at the same time as A0 and A1. The digital filter in the CS5505/6/7/8 has a Finite Impulse Response and is designed to settle to full accuracy in one conversion time. Therefore, the multiplexer can be changed at the conversion rate. If CONV is left high, the CS5505/6/7/8 will perform continuous conversions on one channel. The conversion time will be 1622 clock cycles. If conversion is initiated from the standby state, there may be up to two XIN clock cycles of uncertainty as to when conversion actually begins. This is because the internal logic operates at one half the external clock rate and the exact phase of the internal clock may be 180° out of phase relative to the XIN clock. When a new conversion is initiated from the standby state, it will take up to two XIN clock cycles to begin. Actual conversion will use 1624 clock cycles before DRDY goes low to indicate that the serial port has been updated. See the Serial Interface Logic section of the data sheet for information on reading data from the serial port. In the event the A/D conversion command (CONV going positive) is issued during the conversion state, the current conversion will be DS59F4 DS59F6 terminated and a new conversion will be initiated. Voltage Reference The CS5505/6/7/8 uses a differential voltage reference input. The positive input is VREF+ and the negative input is VREF-. The voltage between VREF+ and VREF- can range from 1 volt minimum to 3.6 volts maximum. The gain slope will track changes in the reference without recalibration, accommodating ratiometric applications. The CS5505/6/7/8 include an on-chip voltage reference which outputs 2.5 volts on the VREFOUT pin. This voltage is referenced to the VA+ pin and will track changes relative to VA+. The VREFOUT output requires a 0.1 µF capacitor connected between VREFOUT and VA+ for stability. When using the internal reference, the VREFOUT signal should be connected to the VREF- input and the VREF+ pin should be connected to the VA+ supply. The internal voltage reference is capable of sourcing 3 µA maximum and sinking 50 µA maximum. If a more precise reference voltage is required, an external voltage reference should be used. If an external voltage reference is used, the VREFOUT pin of the internal reference should be connected directly to VA-. It cannot be left open unless the 0.1 µF capacitor is in place for stability. CS5505/6/7/8 +VA LT1019, REF43 or LM368 2.5V VA+ VREF+ -VA VREFVREFOUT VA- Figure 5. External Reference Connections 15 CS5505/6/7/8 CS5505/6/7/8 CS5505/6/7/8 +VA VA+ VREF+ 0.1 µF VREFVREFOUT ages for the A/D. The differential input voltage can also have any common mode value as long as the maximum signal magnitude stays within the supply voltages. The A/D converter is intended to measure dc or low frequency inputs. It is designed to yield accurate conversions even with noise exceeding the input voltage range as long as the spectral components of this noise will be filtered out by the digital filter. For example, with a 3.0 volt reference in unipolar mode, the converter will accurately convert an input dc signal up to 3.0 volts with up to 15% overrange for 60 Hz noise. A 3.0 volt dc signal could have a 60 Hz component which is 0.5 volts above the maximum input of 3.0 (3.5 volts peak; 3.0 volts dc plus 0.5 volts peak noise) and still accurately convert the input signal (XIN = 32.768 kHz). This assumes that the signal plus noise amplitude stays within the supply voltages. The CS5505/6/7/8 converters output data in binary format when converting unipolar signals and in offset binary format when converting bipolar signals. Table 2 outlines the output coding for the 16-bit CS5505/7 and the 20-bit CS5506/8 in both unipolar and bipolar measurement modes. -VA VA- Figure 6. Internal Reference Connections External reference voltages can range from 1.0 volt minimum to 3.6 volts maximum. The common mode voltage range of the external reference can allow the reference to lie at any voltage between the VA+ and VA- supply rails. Figures 5 and 6 illustrate how the CS5505/6/7/8 converters are connected for external and for internal voltage reference use, respectively. Analog Input Range The analog input range is set by the magnitude of the voltage between the VREF+ and VREFpins. In unipolar mode the input range will equal the magnitude of the voltage reference. In bipolar mode the input voltage range will equate to plus and minus the magnitude of the voltage reference. While the voltage reference can be as great as 3.6 volts, its common mode voltage can be any value as long as the reference inputs VREF+ and VREF- stay within the supply voltCS5505 and CS5507 (16 Bit) Unipolar Input Voltage >(VREF - 1.5 LSB) VREF - 1.5 LSB VREF/2 - 0.5 LSB +0.5 LSB (VREF - 1.5 LSB) VREF - 1.5 LSB -0.5 LSB -VREF + 0.5 LSB (VREF - 1.5 LSB) VREF - 1.5 LSB VREF/2 - 0.5 LSB +0.5 LSB (VREF - 1.5 LSB) VREF - 1.5 LSB -0.5 LSB -VREF + 0.5 LSB