CS5523-ASZ

CS5521/22/23/24/28 16-bit or 24-bit, 2/4/8-channel ADCs with PGIA Features Low Input Current (100 pA), Chopperstabilized Instrumentation Amplifier Scalable Input Span (Bipolar/Unipolar) - 2.5V VREF: 25 mV, 55 mV, 100 mV, 1 V, 2.5 V, 5 V - External: 10 V, 100 V General Description The CS5521/22/23/24/28 are highly integrated ∆Σ analog-to-digital converters (ADCs) which use chargebalance techniques to achieve 16-bit (CS5521/23) and 24-bit (CS5522/24/28) performance. The ADCs come as either two-channel (CS5521/22), four-channel (CS5523/24), or eight-channel (CS5528) devices and include a low-input-current, chopper-stabilized instrumentation amplifier. To permit selectable input spans of 25 mV, 55 mV, 100 mV, 1 V, 2.5 V, and 5 V, the ADCs include a PGA (programmable gain amplifier). To accommodate ground-based thermocouple applications, the devices include a charge pump drive which provides a negative bias voltage to the on-chip amplifiers. These devices also include a fourth-order ∆Σ modulator followed by a digital filter which provides eight selectable output word rates. The digital filters are designed to settle to full accuracy within one conversion cycle and when operated at word rates below 30 Sps, they reject both 50 Hz and 60 Hz interference. These single-supply products are ideal solutions for measuring isolated and non-isolated, low-level signals in process control applications. Wide VREF Input Range (+1 to +5 V) Fourth Order Delta-Sigma A/D Converter Easy to Use Three-wire Serial Interface Port - Programmable/Auto Channel Sequencer with Conversion Data FIFO - Accessible Calibration Registers per Channel - Compatible with SPI™ and Microwire™ System and Self Calibration Eight Selectable Word Rates - Up to 617 Sps (XIN = 200 kHz) - Single Conversion Settling - 50/60 Hz ±3 Hz Simultaneous Rejection Single +5 V Power Supply Operation - Charge Pump Drive for Negative Supply - +3 to +5 V Digital Supply Operation Low Power Consumption: 6.0 mW VA+ AGND ORDERING INFORMATION See page 52. VREF+ VREFX1 DGND VD+ Programmable Gain AIN1+ AIN1AIN2+ AIN2AIN3+ AIN3AIN4+ AIN4NBV CPD MUX CS5524 Shown X1 + X20 X1 Differential 4th Order Modulator Digital Filter ∆Σ Controller, Setup Registers, & Channel Scan Logic CS Serial Port Interface SCLK SDI SDO Latch Clock Gen. Data FIFO & Calibration Registers A0 A1 XIN XOUT http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved) JUL ‘08 DS317F6 CS5521/22/23/24/28 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5 ANALOG CHARACTERISTICS ................................................................................................ 5 TYPICAL RMS NOISE, CS5521/23.......................................................................................... 7 TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 .................................................... 7 TYPICAL RMS NOISE, CS5522/24/28..................................................................................... 8 TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 ............................................... 8 5 V DIGITAL CHARACTERISTICS........................................................................................... 9 3 V DIGITAL CHARACTERISTICS........................................................................................... 9 DYNAMIC CHARACTERISTICS ............................................................................................ 10 RECOMMENDED OPERATING CONDITIONS ..................................................................... 10 ABSOLUTE MAXIMUM RATINGS ......................................................................................... 10 SWITCHING CHARACTERISTICS ........................................................................................ 11 2. GENERAL DESCRIPTION ..................................................................................................... 13 2.1 Analog Input ..................................................................................................................... 13 2.1.1 Instrumentation Amplifier ......................................................................................... 14 2.1.2 Coarse/Fine Charge Buffers ............................................................................... 14 2.1.3 Analog Input Span Considerations .......................................................................... 15 2.1.4 Measuring Voltages Higher than 5 V .................................................................. 15 2.1.5 Voltage Reference .............................................................................................. 16 2.2 Overview of ADC Register Structure and Operating Modes ............................................ 16 2.2.1 System Initialization ............................................................................................ 18 2.2.2 Command Register Quick Reference ............................................................... 19 2.2.3 Command Register Descriptions ........................................................................ 20 2.2.4 Serial Port Interface ............................................................................................ 25 2.2.5 Reading/Writing the Offset, Gain, and Configuration Registers .......................... 26 2.2.6 Reading/Writing the Channel-Setup Registers ................................................... 26 2.2.6.1 Latch Outputs ...................................................................................... 28 2.2.6.2 Channel Select Bits ............................................................................. 28 2.2.6.3 Output Word Rate Selection ............................................................... 28 2.2.6.4 Gain Bits .............................................................................................. 28 2.2.6.5 Unipolar/Bipolar Bit ............................................................................. 28 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. 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All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. 2 DS317F6 CS5521/22/23/24/28 2.2.7 Configuration Register ........................................................................................ 28 2.2.7.1 Chop Frequency Select ...................................................................... 28 2.2.7.2 Conversion/Calibration Control Bits .................................................... 28 2.2.7.3 Power Consumption Control Bits ........................................................ 28 2.2.7.4 Charge Pump Disable ......................................................................... 29 2.2.7.5 Reset System Control Bits .................................................................. 29 2.2.7.6 Data Conversion Error Flags .............................................................. 29 2.3 Calibration ....................................................................................................................... 31 2.3.1 Self Calibration .................................................................................................... 31 2.3.2 System Calibration .............................................................................................. 32 2.3.3 Calibration Tips ................................................................................................... 34 2.3.4 Limitations in Calibration Range ......................................................................... 34 2.4 Performing Conversions and Reading the Data Conversion FIFO .................................. 34 2.4.1 Conversion Protocol ............................................................................................ 35 2.4.1.1 Single, One-Setup Conversion ........................................................... 35 2.4.1.2 Repeated One-Setup Conversions without Wait ................................ 35 2.4.1.3 Repeated One-Setup Conversions with Wait ..................................... 36 2.4.1.4 Single, Multiple-Setup Conversions .................................................... 36 2.4.1.5 Repeated Multiple-Setup Conversions without Wait ........................... 37 2.4.1.6 Repeated Multiple-Setup Conversions with Wait ................................ 37 2.4.2 Calibration Protocol ............................................................................................. 38 2.4.3 Example of Using the CSRs to Perform Conversions and Calibrations .............. 38 2.5 Conversion Output Coding .............................................................................................. 40 2.5.1 Conversion Data FIFO Descriptions ................................................................... 41 2.6 Digital Filter ..................................................................................................................... 42 2.7 Clock Generator .............................................................................................................. 42 2.8 Power Supply Arrangements ........................................................................................... 43 2.8.1 Charge Pump Drive Circuits ............................................................................... 45 2.9 Digital Gain Scaling ........................................................................................................ 45 2.10 Getting Started .............................................................................................................. 46 2.11 PCB Layout ................................................................................................................... 47 PIN DESCRIPTIONS .............................................................................................................. 48 3.1 Clock Generator .............................................................................................................. 49 3.2 Control Pins and Serial Data I/O ..................................................................................... 49 3.3 Measurement and Reference Inputs ............................................................................... 49 3.4 Power Supply Connections ............................................................................................. 50 SPECIFICATION DEFINITIONS ............................................................................................. 51 ORDERING INFORMATION .................................................................................................. 52 ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ............................ 52 PACKAGE DIMENSION DRAWINGS ................................................................................... 53 3. 4. 5. 6. 7. DS317F6 3 CS5521/22/23/24/28 LIST OF FIGURES Figure 1. Continuous Running SCLK Timing ................................................................................ 12 Figure 2. SDI Write Timing ............................................................................................................ 12 Figure 3. SDO Read Timing .......................................................................................................... 12 Figure 4. Multiplexer Configurations.............................................................................................. 13 Figure 5. Input Models for AIN+ and AIN- pins, ≤100 mV Input Ranges....................................... 14 Figure 6. Input Models for AIN+ and AIN- pins, >100 mV input ranges ........................................ 14 Figure 7. Input Ranges Greater than 5 V ...................................................................................... 16 Figure 8. Input Model for VREF+ and VREF- Pins........................................................................ 16 Figure 9. CS5523/24 Register Diagram ........................................................................................ 17 Figure 10. Command and Data Word Timing................................................................................ 25 Figure 11. Self Calibration of Offset (Low Ranges)....................................................................... 32 Figure 12. Self Calibration of Offset (High Ranges) ...................................................................... 32 Figure 13. Self Calibration of Gain (All Ranges) ........................................................................... 32 Figure 14. System Calibration of Offset (Low Ranges) ................................................................. 32 Figure 15. System Calibration of Offset (High Ranges) ................................................................ 33 Figure 16. System Calibration of Gain (Low Ranges) ................................................................... 33 Figure 17. System Calibration of Gain (High Ranges) .................................................................. 33 Figure 18. Filter Response (Normalized to Output Word Rate = 15 Sps) ..................................... 42 Figure 19. Typical Linearity Error for CS5521/23 .......................................................................... 42 Figure 20. Typical Linearity Error for CS5522/24/28 ..................................................................... 42 Figure 21. CS5522 Configured to use on-chip charge pump to supply NBV ................................ 43 Figure 22. CS5522 Configured for ground-referenced Unipolar Signals....................................... 44 Figure 23. CS5522 Configured for Single Supply Bridge Measurement ....................................... 44 Figure 24. Charge Pump Drive Circuit for VD+ = 3 V.................................................................... 45 Figure 25. Alternate NBV Circuits ................................................................................................. 45 LIST OF TABLES Table 1. Relationship between Full Scale Input, Gain Factors, and Internal Analog Signal Limitations ............................................................................................................. 15 Table 2. Command Register Quick Reference.............................................................................. 19 Table 3. Channel-Setup Registers ................................................................................................ 27 Table 4. Configuration Register..................................................................................................... 30 Table 5. Offset and Gain Registers ............................................................................................... 31 Table 6. Output Coding for 16-bit CS5521/23 and 24-bit CS5522/24/28 ...................................... 40 4 DS317F6 CS5521/22/23/24/28 CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (TA = 25° C; VA+, VD+ = 5 V ±5%; VREF+ = 2.5 V, VREF- = AGND, NBV = -2.1 V, XIN = 32.768 kHz, CFS1-CFS0 = ‘00’, OWR (Output Word Rate) = 15 Sps, Bipolar Mode, Input Range = ±100 mV; See Notes 1 and 2.) CS5521/23 Parameter Accuracy Resolution Linearity Error Bipolar Offset Unipolar Offset Offset Drift Bipolar Gain Error Unipolar Gain Error Gain Drift Power Supplies Power Supply Currents (Normal Mode) IA+ (Note 5)ID+ INBV Power Consumption (Note 6) Normal Mode Low Power Mode Sleep Power Supply Rejection Positive Supplies dc NBV N/A 1.0 90 400 6.0 N/A 500 120 110 1.4 135 570 8.9 N/A 1.5 90 525 9 5.5 500 120 110 1.9 135 700 12 7.5 mA µA µA mW mW µW dB dB (Note 4) (Note 3) (Note 3) (Notes 3 and 4) ±0.0015 ±1 ±2 20 ±8 ±16 1 16 ±0.003 ±2 ±4 ±31 ±62 3 ±16 ±32 20 ±8 ±16 1 24 ±32 ±64 ±31 ±62 3 Bits %FS LSBN LSBN nV/°C ppm ppm ppm/°C ±0.0007 ±0.0015 Min Typ Max Min CS5522/24/28 Typ Max Unit Notes: 1. Applies after system calibration at any temperature within -40° C ~ +85° C. 2. Specifications guaranteed by design, characterization, and/or test. 3. Specification applies to the device only and does not include any effects by external parasitic thermocouples. LSBN: N is 16 for the CS5521/23 and N is 24 for the CS5522/24/28 4. Drift over specified temperature range after calibration at power-up at 25° C. 5. Measured with Charge Pump Drive off. 6. All outputs unloaded. All input CMOS levels and the CS5521/23 do not have a low power mode. DS317F6 5 CS5521/22/23/24/28 ANALOG CHARACTERISTICS (Continued) Parameter Analog Input Common Mode + Signal on AIN+ or AINBipolar/Unipolar Mode NBV = -1.8 to -2.5 V Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V NBV = AGND Range = 25 mV, 55 mV, or 100 mV (Note 7) Range = 1 V, 2.5 V, or 5 V CVF Current on AIN+ or AIN(Note 8) Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V Input Current Drift Range = 25 mV, 55 mV, or 100 mV Input Leakage for Multiplexer when Off Common Mode Rejection Input Capacitance Voltage Reference Input Range VREF+ VREFCVF Current Common Mode Rejection dc 50, 60 Hz Input Capacitance System Calibration Specifications Full Scale Calibration Range (VREF = 2.5V) 25 mV 55 mV 100 mV 1V 2.5 V 5V Offset Calibration Range 25 mV 55 mV 100 mV 1V 2.5 V 5V Bipolar/Unipolar Mode 10 25 40 0.40 1.0 2.0 Bipolar/Unipolar Mode ±12.5 ±27.5 ±50 ±0.5 ±1.25 ±2.50 mV mV mV V V V 32.5 71.5 105 1.30 3.25 VA+ mV mV mV V V V (Note 8) (VREF+) - (VREF-) 1 (VREF-)+1 Min Typ Max Unit -0.150 NBV 1.85 0.0 - 100 10 1 10 120 120 10 2.5 5.0 110 130 16 0.950 VA+ 2.65 VA+ 300 VA+ VA+ (VREF+)-1 V V V V pA nA pA/°C pA dB dB pF V V V nA dB dB pF (Note 8) dc 50, 60 Hz NBV - - (Note 9) Notes: 7. For the CS5528, the 25 mV, 55 mV and 100 mV ranges cannot be used unless NBV is powered at -1.8 to -2.5 V 8. See the section of the data sheet which discusses input models. Chop clock is 256 Hz (XIN/128) for PGIA (programmable gain instrumentation amplifier). XIN = 32.768 kHz. 9. The maximum full scale signal can be limited by saturation of circuitry within the internal signal path. 6 DS317F6 CS5521/22/23/24/28 TYPICAL RMS NOISE, CS5521/23 (Notes 10 and 11) Output Rate -3 dB Filter (Sps) Frequency 1.88 1.64 3.76 3.27 7.51 6.55 15.0 12.7 30.0 25.4 61.6 (Note 12) 50.4 84.5 (Note 12) 70.7 101.1 (Note 12) 84.6 25 mV 90 nV 122 nV 180 nV 280 nV 580 nV 2.6 µV 11 µV 41 µV Input Range, (Bipolar/Unipolar Mode) 55 mV 100 mV 1V 2.5 V 148 nV 220 nV 1.8 µV 3.9 µV 182 nV 310 nV 2.6 µV 5.7 µV 267 nV 435 nV 3.7 µV 8.5 µV 440 nV 810 nV 5.7 µV 14 µV 1.1 µV 2.1 µV 18.2 µV 48 µV 4.9 µV 8.5 µV 92 µV 238 µV 27 µV 43 µV 458 µV 1.1 mV 72 µV 130 µV 1.2 mV 3.4 mV 5V 7.8 µV 11.3 µV 18.1 µV 28 µV 96 µV 390 µV 2.4 mV 6.7 mV Notes: 10. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25° C. 11. To estimate Peak-to-Peak Noise, multiply RMS noise by 6.6 for all ranges and output rates. 12. For input ranges 5 V) measurement. Figure 8 illustrates the input models for the VREF pins. The dynamic input current for each of the pins can be determined from the models shown. 1.2 Overview of ADC Register Structure and Operating Modes The CS5521/22/23/24/28 ADCs have an on-chip controller, which includes a number of user-accessible registers. The registers are used to hold offset and gain calibration results, configure the chip's operating modes, hold conversion instructions, and to store conversion data words. Figure 9 depicts a block diagram of the on-chip controller’s internal registers for the CS5523/24. Each of the converters has 24-bit registers to function as offset and gain calibration registers for each channel. The converters with two channels have two offset and two gain calibration registers, the converters with four channels have four offset and four gain calibration registers, and the eight channel converter has eight offset and eight gain calibration registers. These registers hold calibration results. The contents of these registers can be read or written by the user. This allows calibration data to be off-loaded into an external EEPROM. The user can also manipulate the contents of these registers to modify the offset or the gain slope of the converter. The converters include a 24-bit configuration register of which 17 of the bits are used for setting options such as the conversion mode, operating power options, setting the chop clock rate of the instruφ 1 F in e φ 2 C o ars e C = 10 pF f = 3 2.76 8 kH z 1.1.5 Voltage Reference The CS5521/22/23/24/28 devices are specified for operation with a 2.5 V reference voltage between the VREF+ and VREF- pins of the device. For a single-ended reference voltage, such as the LT1019-2.5, the reference voltage is input into the VREF+ pin of the converter and the VREF- pin is grounded. The differential voltage between the VREF+ and VREF- can be any voltage from 1.0 V up to VA+, however, the VREF+ cannot go above VA+ and the VREF- pin can not go below NBV. 10 Ω +5 V 0.1 µF VA+ 2.5 V VREF+ VREF1 MΩ ±10V Voltage Divider 10 KΩ + PGIA ∆Σ ADC VD+ 0.1 µF PGIA set for + 100 mV chop clock = 256 Hz NBV Charge Pump Regulator CPD V ≈ -2.1 V BAT85 1N4148 10 µF 0.033 µF DGND VREF V os ≤ 2 5 m V i n = fV os C + 1N4148 Charge Pump Circuitry Figure 7. Input Ranges Greater than 5 V Figure 8. Input Model for VREF+ and VREF- Pins 16 DS317F6 CS5521/22/23/24/28 mentation amplifier, and providing a number of flags which indicate converter operation. A group of registers, called Channel Set-up Registers, are also included in the converters. These registers are used to hold pre-loaded conversion instructions. Each channel set-up register is 24 bits wide and holds two 12-bit conversion instructions (Setups). Upon power-up, these registers can be initialized by the user’s microcontroller with conversion instructions. The user can then use bits in the configuration register to choose a conversion mode. Several conversion modes are possible. Using the single conversion mode, an 8-bit command word can be written into the serial port. The command includes pointer bits which ‘point’ to a 12-bit command in one of the Channel Setup Registers which is to be executed. The 12-bit commands can be setup to perform a conversion on any of the input channels of the converter. More than one of the 12bit Setups can be used for the same analog input channel. This allows the user to convert on the same signal with either a different conversion speed, a different gain range, or any of the other options available in the Setup Register. The user can set up the registers to perform conversions using different conversion options on each of the input channels. The ADCs also include multiple-channel conversion capability. User bits in the configuration register of the ADCs can be configured to sequence through the 12-bit command Setups, performing a conversion according to the content of each 12-bit Setup. This channel scanning capability can be configured to run continuously, or to scan through a specified number of Setup Registers and stop until commanded to continue. In the multiple-channel scanning modes, the conversion data words are loaded into an on-chip data FIFO. The converter issues a flag on the SDO pin when a scan cycle is completed so the user can read the FIFO. More details are given in the following pages. Instructions are provided on how to initialize the converter, perform offset and gain calibrations, and to configure the converter for the various conversion modes. Each of the bits of the configuration register and of the Channel Setup Registers is described. A list of examples follows the description section. Table 2 can be used to decode all valid commands (the first 8 bits into the serial port). AIN1 AIN2 AIN3 AIN4 4 (24) Off 1 Off 2 Off 3 Off 4 1 x 24 Configuration 4 (24) Gain 1 Gain 2 Gain 3 Gain 4 4 (12 x 2) Setup 1 Setup 2 Setup 3 Setup 5 Setup 7 Setup 4 Setup 6 Setup 8 8 x 24 DATA FIFO SDO Chop Frequency Multiple Conversions Depth Pointer Loop Read Convert Powerdown Modes Flags Etc. Latch Outputs Channel Select Output Word Rate PGA Selection Unipolar/Bipolar Figure 9. CS5523/24 Register Diagram DS317F6 17 CS5521/22/23/24/28 1.2.1 System Initialization After power is first applied to the CS5521/22/2324/28 devices, the user should wait for the oscillator to start before attempting to communicate with the converter. If a 32.768 kHz crystal is used, this may be 500 milliseconds. The initialization sequence should be as follows: Initialize the serial port by sending the port initialization sequence of 15 bytes of all 1's followed by one byte with the following bit contents '1111 110'. This sequence places the chip in the command mode where it waits for a valid command to be written. The first command should be to perform a system reset. This is accomplished by writing a logic 1 to the RS (Reset System) bit in the configuration register. After a reset the RV bit is set until the configuration register is read. The user must then write a logic 0 to the RS bit to take the part out of reset mode. Any other bits written to the configuration register at this time will be lost. The configuration register must be written again once RS= 0 to set any other bits to their desired settings. After a reset, the on-chip registers are initialized to the following states: configuration register: offset registers: gain registers: channel setup registers: 000040(H) 000000(H) 400000(H) 000000(H) 18 DS317F6 CS5521/22/23/24/28 1.2.2 Command Register Quick Reference D7(MSB) CB BIT D7 D6-D4 D6 CS2 D5 CS1 NAME Command Bit, CB Channel Select Bits, CSB2-CSB0 D4 CS0 D3 R/W VALUE 0 1 000 . . 111 0 1 000 001 010 011 101 D2 RSB2 D1 RSB1 D0 RSB0 FUNCTION Must be logic 0 for these commands. See table below. CS2-CS0 provide the address of one of the eight physical channels. These bits are used to access the calibration registers associated with respective channels. Note: These bits are ignored when reading the data register. Write to selected register. Read from selected register. Reserved Offset Register Gain Register Configuration Register Channel Set-up Registers - register is 48-bits long for CS5521/22 - register is 96-bits long for CS5523/24 - register is 192-bits long for CS5528 Reserved Reserved D2 CC2 D1 CC1 D0 CC0 FUNCTION See table above. Must be logic 1 for these commands. These bits are used as pointers to the Setups. Note: The MC bit, must be logic 0 for these bits to take effect. When MC = 1, these bits are ignored. The LP, MC, and RC bits in the configuration register are ignored during calibration. Normal Conversion Self-Offset Calibration Self-Gain Calibration Reserved Reserved System-Offset Calibration System-Gain Calibration Reserved D3 D2-D0 Read/Write, R/W Register Select Bit, RSB2-RSB0 110 111 D7(MSB) CB BIT D7 D6-D3 D6 CSRP3 D5 CSRP2 NAME Command Bit, CB Channel Pointer Bits, CSRP3-CSRP0 D4 CSRP1 D3 CSRP0 VALUE 0 1 0000 . . . 1111 000 001 010 011 100 101 110 111 D2-D0 Conversion/Calibration Bits, CC2-CC0 Table 2. Command Register Quick Reference DS317F6 19 CS5521/22/23/24/28 1.2.3 Command Register Descriptions READ/WRITE INDIVIDUAL OFFSET CALIBRATION REGISTER D7(MSB) 0 D6 CS2 D5 CS1 D4 CS0 D3 R/W D2 0 D1 0 D0 1 Function: These commands are used to access each offset register separately. CS1 - CS0 decode the registers accessed. Write to selected register. Read from selected register. R/W (Read/Write) 0 1 CS[2:0] (Channel Select Bits) 000 001 010 011 100 101 110 111 Offset Register 1(All devices) Offset Register 2 (All devices) Offset Register 3 (CS5523/24/28 only) Offset Register 4 (CS5523/24/28 only) Offset Register 5 (CS5528 only) Offset Register 6 (CS5528 only) Offset Register 7 (CS5528 only) Offset Register 8 (CS5528 only) READ/WRITE INDIVIDUAL GAIN REGISTER D7(MSB) 0 D6 CS2 D5 CS1 D4 CS0 D3 R/W D2 0 D1 1 D0 0 Function: These commands are used to access each gain register separately. CS1 - CS0 decode the registers accessed. Write to selected register. Read from selected register. R/W (Read/Write) 0 1 CS[2:0] (Channel Select Bits) 000 001 010 011 100 101 110 111 Gain Register 1(All devices) Gain Register 2 (All devices) Gain Register 3 (CS5523/24/28 only) Gain Register 4 (CS5523/24/28 only) Gain Register 5 (CS5528 only) Gain Register 6 (CS5528 only) Gain Register 7 (CS5528 only) Gain Register 8 (CS5528 only) 20 DS317F6 CS5521/22/23/24/28 READ/WRITE CONFIGURATION REGISTER D7(MSB) 0 D6 0 D5 0 D4 0 D3 R/W D2 0 D1 1 D0 1 Function: 0 1 These commands are used to read from or write to the configuration register. Write to selected register. Read from selected register. R/W (Read/Write) READ/WRITE CHANNEL-SETUP REGISTER(S) D7(MSB) 0 D6 0 D5 0 D4 0 D3 R/W D2 1 D1 0 D0 1 Function: These commands are used to access the channel-setup registers (CSRs). The number of CSRs accessed is determined by the device being used and the number of CSRs that are being accessed (i.e. the depth bits in the configuration register determine the number of levels accessed). This register is 48-bits long (4 Setups) for the CS5521/22, 96-bits long (8 Setups) for the CS5523/24, and 192-bits (16 Setups) long for the CS5528. Write to selected register. Read from selected register. R/W (Read/Write) 0 1 DS317F6 21 CS5521/22/23/24/28 PERFORM CONVERSION D7(MSB) 1 D6 CSRP3 D5 CSRP2 D4 CSRP1 D3 CSRP0 D2 0 D1 0 D0 0 Function: These commands instruct the ADC to perform conversions on the physical input channel pointed to by the pointer bits (CSRP2 - CSRP0) in the channel-setup registers. The particular type of conversion performed is determined by the states of the conversion control bits (the multiple conversion bit, the loop bit, read convert bit, and the depth pointer bits) in the configuration register. Setup 1 (All devices) Setup 2 (All devices) Setup 3 (All devices) Setup 4 (All devices) Setup 5 (CS5523/24/28) Setup 6 (CS5523/24/28) Setup 7 (CS5523/24/28) Setup 8 (CS5523/24/28) Setup 9 (CS5528 only) Setup 10 (CS5528 only) Setup 11 (CS5528 only) Setup 12 (CS5528 only) Setup 13 (CS5528 only) Setup 14 (CS5528 only) Setup 15 (CS5528 only) Setup 16 (CS5528 only) CSRP [3:0] (Channel Setup Register Pointer Bits) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 22 DS317F6 CS5521/22/23/24/28 PERFORM CALIBRATION D7(MSB) 1 D6 CSRP3 D5 CSRP2 D4 CSRP1 D3 CSRP0 D2 CC2 D1 CC1 D0 CC0 Function: These commands instruct the ADC to perform a calibration on the physical input channel referenced which is chosen by the command byte pointer bits (CSRP3 - CRSP0). Setup 1 (All devices) Setup 2 (All devices) Setup 3 (All devices) Setup 4 (All devices) Setup 5 (CS5523/24/28 only) Setup 6 (CS5523/24/28 only) Setup 7 (CS5523/24/28 only) Setup 8 (CS5523/24/28 only) Setup 9 (CS5528 only) Setup 10 (CS5528 only) Setup 11 (CS5528 only) Setup 12 (CS5528 only) Setup 13 (CS5528 only) Setup 14 (CS5528 only) Setup 15 (CS5528 only) Setup 16 (CS5528 only) CSRP [3:0] (Channel Setup Register Pointer Bits) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CC [2:0] (Calibration Control Bits) 000 001 010 011 100 101 110 111 Reserved Self-Offset Calibration Self-Gain Calibration Reserved Reserved System-Offset Calibration System-Gain Calibration Reserved DS317F6 23 CS5521/22/23/24/28 SYNC1 D7(MSB) 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 D0 1 Function: SYNC0 D7(MSB) 1 Part of the serial port re-initialization sequence. D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 D0 0 Function: NULL D7(MSB) 0 End of the serial port re-initialization sequence. D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Function: This command is used to clear a port flag and keep the converter in the continuous conversion mode. 24 DS317F6 CS5521/22/23/24/28 1.2.4 Serial Port Interface The CS5521/22/23/24/28’s serial interface consists of four control lines: CS, SCLK, SDI, SDO. Figure 10 illustrates the serial sequence necessary to write to, or read from the serial port’s registers. CS (Chip Select) is the control line which enables access to the serial port. If the CS pin is tied low, the port can function as a three-wire interface. SDI (Serial Data In) is the data signal used to transfer data to the converters. SDO (Serial Data Out) is the data signal used to transfer output data from the converters. The SDO output will be held at high impedance any time CS is at logic 1. SCLK (Serial Clock) is the serial bit clock which controls the shifting of data to or from the ADC’s serial port. The CS pin must be held low (logic 0) before SCLK transitions can be recognized by the port logic. To accommodate opto-isolators SCLK is designed with a Schmitt-trigger input to allow an opto-isolator with slower rise and fall times to directly drive the pin. Additionally, SDO is capable of sinking or sourcing up to 5 mA to directly drive an opto-isolator LED. SDO will have less than a 400 mV loss in the drive voltage when sinking or sourcing 5 mA. CS SCLK SDI Command Time 8 SCLKs MSB LSB Data Time 24 SCLKs Write Cycle CS SCLK SDI Command Time 8 SCLKs SDO MSB LSB Data Time 24 SCLKs Read Cycle SCLK SDI Command Time 8 SCLKs SDO td* XIN/OWR Clock Cycles 8 SCLKs Clear SDO Flag MSB LSB * td = XIN/OWR clock cycles for each conversion except the first conversion which will take XIN/OWR + 7 clock cycles Data Time 24 SCLKs Figure 10. Command and Data Word Timing DS317F6 25 CS5521/22/23/24/28 1.2.5 Reading/Writing the Offset, Gain, and Configuration Registers The CS5521/22/23/24/28’s offset, gain, and configuration registers are accessed individually and can be read from or written to. To write to an offset, a gain, or the configuration register, the user must transmit the appropriate write command which accesses the particular register and then follow that command with 24 bits of data (refer to Figure 10 for details). For example, to write 0x800000 (hexadecimal) to physical channel one’s gain register, the user would transmit the command byte 0x02 (hexadecimal) and then follow that command byte with the data 0x800000 (hexadecimal). Similarly, to read physical channel one’s gain register, the user must first transmit the command byte 0x0A (hexadecimal) and then read the 24 bits of data. Once an offset, a gain, or the configuration register is written to or read from, the serial port returns to the command mode. Once programmed, they are used to determine the mode (e.g. unipolar, 15 Sps, 100 mV range etc.) the ADC will operate in when future conversions or calibrations are performed. To access the CSRs, the user must first initialize the depth pointer bits in the configuration register as these bits determine the number of CSRs to read from or write to. For example, to write CSR1 (Setup1 and Setup2), the user would first program the configuration register’s depth pointer bits with ‘0001’ binary. This notifies the ADC’s serial port that only the first CSR is to be accessed. Then, the user would transmit the write command, 0x05 (hexadecimal) and follow that command with 24 bits of data. Similarly, to read CSR1, the user must transmit the command byte 0x0D (hexadecimal) and then read the 24 bits of data. To write more than one CSR, for instance CSR1 and CSR2 (Setup1, Setup2, Setup3, and Setup4), the user would first set the depth pointer bits in the configuration register to ‘0011’ binary. The user would then transmit the write CSR command 0x05 (hexadecimal) and follow that with the information for Setup1, Setup2, Setup 3, and Setup 4 which is 48 bits of information. Note that while reading/writing CSRs, two Setups are accessed in pairs as a single 24-bit CSR register. Even if one of the Setups isn’t used, it must be written to or read. Further note that the CSRs are accessed as a closed array – the user can not access CSR2 without accessing CSR1. This requirement means that the depth bits in the configuration register can only be set to one of the following states when the CSRs are being read from or written to: 0001, 0011, 0101, 0111, 1001, 1011, 1101, 1111. Examples detailing the power of the CSRs are provided in the Performing Conversions and Reading the Data Conversion FIFO section. Once the CSRs are written to or read from, the serial port returns to the command mode. 1.2.6 Reading/Writing the Channel-Setup Registers The CS5521/22 have two 24-bit channel-setup registers (CSRs). The CS5523/24 have four CSRs, and the CS5528 has eight CSRs (refer to Table 3 for more detail on the CSRs). These registers are accessed in conjunction with the depth pointer bits in the configuration register. Each CSR contains two 12-bit Setups which are programmed by the user to contain data conversion or calibration information such as: 1) state of the output latch pins 2) output word rate 3) gain range 4) polarity 5) the address of a physical input channel to be converted. 26 DS317F6 CS5521/22/23/24/28 CSR (Channel-Setup Register) #1 #2 Setup 1 Bits Setup 3 Bits Setup 2 Bits Setup 4 Bits CSR #1 Setup 1 Setup 2 Bits Bits CSR #1 Setup 1 Setup 2 Bits Bits #4 CS5521/22 Setup 7 Setup 8 Bits Bits CS5523/24 #8 Setup 15 Bits CS5528 Setup 16 Bits D23(MSB) A1 D11 A1 BIT D22 A0 D10 A0 D21 CS2 D9 CS2 NAME D20 CS1 D8 CS1 D19 CS0 D7 CS0 D18 WR2 D6 WR2 D17 WR1 D5 WR1 D16 WR0 D4 WR0 D15 G2 D3 G2 FUNCTION D14 G1 D2 G1 D13 G0 D1 G0 D12 U/B D0 U/B VALUE 00 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 0 1 D23-D22/ Latch Outputs, A1-A0 D11-D10 D21-D19/ Channel Select, CS2D9-D7 CS0 *R Latch Output Pins A1-A0 mimic D23/D11-D22/D10 register bits. R Select physical channel 1 (All devices) Select physical channel 2(All devices) Select physical channel 3 (CS5523/24/28 only) Select physical channel 4 (CS5523/24/28 only) Select physical channel 5 (CS5528 only) Select physical channel 6 (CS5528 only) Select physical channel 7 (CS5528 only) Select physical channel 8 (CS5528 only) R 15.0 Sps (2180 XIN cycles). 30.0 Sps (1092 XIN cycles). 61.6 Sps (532 XIN cycles). 84.5 Sps (388 XIN cycles). 101.1 Sps (324 XIN cycles). 1.88 Sps (17444 XIN cycles). 3.76 Sps (8724 XIN cycles). 7.51 Sps (4364 XIN cycles). R 100 mV (assumes VREF Differential = 2.5 V) 55 mV 25 mV 1.0 V 5.0 V 2.5 V Not used. Not used. R Bipolar measurement mode. Unipolar measurement mode. D18-D16/ Word Rate, WR2-WR0 D6-D4 D15-D13/ Gain Bits, G2-G0 D3-D1 D12/D0 Unipolar/Bipolar, U/B * R indicates the bit value after the part is reset Table 3. Channel-Setup Registers DS317F6 27 CS5521/22/23/24/28 1.2.6.1 Latch Outputs The A1-A0 pins mimic the latch output, D23/D11D22/D10, bits of the channel-setup registers. A1-A0 can be used to control external multiplexers and other logic functions outside the converter. The outputs can sink or source at least 1 mA, but it is recommended to limit drive currents to less than 20 µA to reduce self-heating of the chip. These outputs are powered from VA+, hence their output voltage for a logic 1 will be limited to the VA+ supply voltage. 1.2.7 Configuration Register The configuration register is 24 bits long. The following subsections detail the bits in the configuration register. Table 4 summarizes the configuration register. 1.2.7.1 Chop Frequency Select The chop frequency select (CFS1-CFS0) bits are used to set the rate at which the instrumentation amplifier’s chop switches modulate the input signal. The 256 Hz rate is desirable as it provides the lowest input CVF (sampling) current, (VFS-1.5 LSB) VFS-1.5 LSB Two's Complement 7FFFFF 7FFFFF -----7FFFFE 000000 -----FFFFFF 800001 -----800000 800000 >(VFS-1.5 LSB) FFFFFF VFS/2-0.5 LSB VFS/2-0.5 LSB -0.5 LSB -0.5 LSB +0.5 LSB +0.5 LSB -VFS+0.5 LSB