CS5526-BSZ

CS5525 CS5526 16-bit/20-bit, Multi-range ADC with 4-bit Latch Features Delta-sigma A/D Converter - Linearity Error: 0.0015%FS - Noise-free Resolution: 18-bits General Description The 16-bit CS5525 and the 20-bit CS5526 are highly integrated ∆Σ A/D converters which include an instrumentation amplifier, a PGA (programmable gain amplifier), eight digital filters, and self and system calibration circuitry. The converters are designed to provide their own negative supply which enables their on-chip instrumentation amplifiers to measure bipolar ground-referenced signals ≤±100 mV. By directly supplying NBV with -2.5 V and with VA+ at 5 V, ±2.5 V signals (with respect to ground) can be measured. The digital filters provide programmable output update rates between 3.76 Sps to 202 Sps (XIN = 32.768 kHz). Output word rates can be increased by approximately 3X by using XIN = 100 kHz. Each filter is designed to settle to full accuracy for its output update rate in one conversion cycle. The filters with word rates of 15 Sps or less (XIN = 32.768 kHz) reject both 50 and 60 Hz (±3 Hz) line interference simultaneously. Low power, single conversion settling time, programmable output rates, and the ability to handle negative input signals make these single supply products ideal solutions for isolated and non-isolated applications. ORDERING INFORMATION See page 29. Bipolar/Unipolar Input Ranges - 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V Chopper Stabilized Instrumentation Amplifier On-chip Charge Pump Drive Circuitry 4-bit Output Latch Simple three-wire serial interface - SPI™ and Microwire™ Compatible - Schmitt Trigger on Serial Clock (SCLK) Programmable Output Word Rates - 3.76 Sps to 202 Sps (XIN = 32.768 kHz) - 11.47 Sps to 616 Sps (XIN = 100 kHz) Output Settles in One Conversion Cycle Simultaneous 50/60 Hz Noise Rejection System and Self-calibration with Read/Write Registers Single +5 V Analog Supply +3.0 V or +5 V Digital Supply Low-power Mode Consumption: 4.9 mW - 1.8 mW in 1 V, 2.5 V, and 5 V Input Ranges VA+ AGND VREF+ VREF- DGND VD+ AIN+ AIN- + X20 - Programmable Gain Differential 4th Order Delta-Sigma Modulator Digital Filter Calibration Register CS SCLK NBV A0 A1 A2 A3 Control Register SDI Latch Calibration Memory Calibration µC Clock Gen. Output Register SDO CPD XIN XOUT http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) AUG ‘05 DS202F5 CS5525 CS5526 (TA = 25 °C; VA+, VD+ = 5 V ±5%; VREF+ = 2.5 V, VREF- = AGND, NBV = -2.1 V, FCLK = 32.768 kHz, OWR (Output Word Rate) = 15 Sps, Bipolar Mode, Input Range = ±100 mV; See Notes 1 and 2.) CS5525 Parameter Accuracy Linearity Error No Missing Codes Bipolar Offset Unipolar Offset Offset Drift Bipolar Gain Error Unipolar Gain Error Gain Drift Voltage Reference Input Range Common Mode Rejection Input Capacitance CVF Current (Note 5) (VREF+) - (VREF-) dc 50, 60 Hz 1 2.5 110 130 16 0.6 3.0 1 2.5 110 130 16 0.6 3.0 V dB dB pF µA/V (Note 4) (Note 3) (Note 3) (Notes 3 and 4) 16 ±0.0015 ±0.003 ±1 ±2 20 ±8 ±16 1 ±2 ±4 ±31 ±62 3 20 ±0.0007 ±0.0015 ±16 ±32 20 ±8 ±16 1 ±32 ±64 ±31 ±62 3 %FS Bits LSB LSB nV/°C ppm ppm ppm/°C Min Typ Max Min CS5526 Typ Max Unit ANALOG CHARACTERISTICS Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C. 2. Specifications guaranteed by design, characterization, and/or test. 3. Specification applies to the device only and does not include any effects by external parasitic thermocouples. LSB = LSB16 for the CS5525, and LSB20 for the CS5526. 4. Drift over specified temperature range after calibration at power-up at 25 °C. 5. See the section of the data sheet which discusses input models on page 15. RMS NOISE (Notes 6 and 7) Output Rate -3 dB Filter (Sps) Frequency 3.76 3.27 7.51 6.55 15.0 12.7 30.1 25.4 60.0 50.4 123.2 (Note 8) 103.6 168.9 (Note 8) 141.3 202.3 (Note 8) 169.2 25 mV 90 nV 110 nV 170 nV 250 nV 500 nV 2.0 µV 10 µV 30 µV Input Range, (Bipolar/Unipolar Mode) 55 mV 100 mV 1V 2.5 V 90 nV 130 nV 1.0 µV 2.0 µV 130 nV 190 nV 1.5 µV 3.0 µV 200 nV 250 nV 2.0 µV 5.0 µV 300 nV 500 nV 4.0 µV 10 µV 1.0 µV 1.5 µV 15 µV 45 µV 4.0 µV 8.0 µV 72 µV 190 µV 20.0 µV 30 µV 340 µV 900 µV 55 µV 105 µV 1.1 mV 2.4 mV 5V 4.0 µV 7 µV 10 µV 15 µV 85 µV 350 µV 2.0 mV 5.3 mV Notes: 6. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C. 7. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates. 8. For input ranges 60 Sps, 32.768 kHz chopping frequency is used. Specifications are subject to change without notice. 2 DS202F5 CS5525 CS5526 ANALOG CHARACTERISTICS (Continued) Parameter Analog Input Common Mode + Signal on AIN+ or AINBipolar/Unipolar Mode NBV = -1.8 to -2.5 V Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V NBV = AGND Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V Common Mode Rejection Input Capacitance CVF Current on AIN+ or AIN(Note 5) Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V System Calibration Specifications Full-scale Calibration Range 25 mV 55 mV 100 mV 1V 2.5 V 5V Offset Calibration Range 25 mV 55 mV 100 mV 1V 2.5 V 5V Power Supplies DC Power Supply Currents (Normal Mode) IA+ ID+ INBV Power Consumption Normal Mode Low Power Mode Standby Sleep dc Positive Supplies dc NBV (Note 11) 1.65 15 475 9.4 4.9 1.2 500 95 110 2.2 30 700 12.7 8.5 mA µA µA mW mW mW µW dB dB Bipolar/Unipolar Mode (Note 9) 17.5 38.5 70 0.70 1.75 3.50 Bipolar/Unipolar Mode ±12.5 ±27.5 ±50 ±0.5 ±1.25 ±2.50 mV mV mV V V V 32.5 71.5 105 1.30 3.25 VA+ mV mV mV V V V dc 50, 60 Hz -0.150 NBV 1.85 0.0 120 120 10 100 1.2 0.950 VA+ 2.65 VA+ 300 V V V V dB dB pF pA µA/V Min Typ Max Unit (Note 10) Power Supply Rejection Notes: 9. The minimum Full-scale Calibration Range (FSCR) is limited by the maximum allowed gain register value (with margin). The maximum FSCR is limited by the ∆Σ modulator’s 1’s density range. 10. The maximum full-scale signal can be limited by saturation of circuitry within the internal signal path. 11. All outputs unloaded. All input CMOS levels. DS202F5 3 CS5525 CS5526 5 V DIGITAL CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5 V ±5%; GND = 0; See Notes 2 and 12.)) Parameter High-level Input Voltage All Pins Except XIN and SCLK XIN SCLK All Pins Except XIN and SCLK XIN SCLK Symbol VIH Min 0.6 VD+ 3.5 (VD+) - 0.45 0.0 (VA+) - 1.0 (VD+) - 1.0 (VD+) - 1.0 VOL Iin IOZ Cout ±1 9 0.4 0.4 0.4 ±10 ±10 V V V µA µA pF Typ Max VD+ 0.8 1.5 0.6 Unit V V V V V V V V V Low-level Input Voltage VIL High-level Output Voltage All Pins Except CPD and SDO (Note 13) CPD, Iout = -4.0 mA SDO, Iout = -5.0 mA Low-level Output Voltage All Pins Except CPD and SDO, Iout = 1.6 mA CPD, Iout = 2 mA SDO, Iout = 5.0 mA Input Leakage Current 3-state Leakage Current Digital Output Pin Capacitance Notes: 12. All measurements performed under static conditions. VOH 13. Iout = -100 µA unless stated otherwise. (VOH = 2.4 V @ Iout = -40 µA.) 3.0 V DIGITAL CHARACTERISTICS (TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10%; GND = 0; See Notes 2 and 12.)) Parameter High-level Input Voltage All Pins Except XIN and SCLK XIN SCLK All Pins Except XIN and SCLK XIN SCLK Symbol VIH Min 0.6 VD+ 0.54 VA+ (VD+) - 0.45 0.0 (VA+) - 0.3 (VD+) - 1.0 (VD+) - 1.0 VOL Iin IOZ Cout ±1 9 0.3 0.4 0.4 ±10 ±10 V V V µA µA pF Typ Max VD+ 0.16 VD+ 1.5 0.6 Unit V V V V V V V V V Low-level Input Voltage VIL High-level Output Voltage All Pins Except CPD and SDO, Iout = -400 µA CPD, Iout = -4.0 mA SDO, Iout = -5.0 mA Low-level Output Voltage All Pins Except CPD and SDO, Iout = 400 µA CPD, Iout = 2 mA SDO, Iout = 5.0 mA Input Leakage Current 3-state Leakage Current Digital Output Pin Capacitance VOH 4 DS202F5 CS5525 CS5526 DYNAMIC CHARACTERISTICS Parameter Modulator Sampling Frequency Filter Settling Time to 1/2 LSB (Full Scale Step) Symbol fs ts Ratio XIN/2 1/fout Unit Hz s RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V; See Note 14.)) Parameter DC Power Supplies Analog Reference Voltage Negative Bias Voltage Notes: 14. All voltages with respect to ground. Positive Digital Positive Analog (VREF+) - (VREF-) Symbol VD+ VA+ VRefdiff NBV Min 2.7 4.75 1.0 -1.8 Typ 5.0 5.0 2.5 -2.1 Max 5.25 5.25 3.0 -2.5 Unit V V V V ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; See Note 14.) Parameter DC Power Supplies (Note 15) Positive Digital Positive Analog Negative Potential (Note 16 and 17) (Note 18) VREF pins AIN Pins Symbol VD+ VA+ NBV IIN IOUT PDN VINR VINA VIND TA Tstg Min -0.3 -0.3 +0.3 -0.3 NBV - 0.3 -0.3 -40 -65 Max +6.0 +6.0 -3.0 ±10 ±25 500 (VA+) + 0.3 (VA+) + 0.3 (VD+) + 0.3 85 150 Unit V V V mA mA mW V V V °C °C Negative Bias Voltage Input Current, Any Pin Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature Notes: 15. No pin should go more negative than NBV - 0.3 V. 16. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins. 17. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA. 18. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. DS202F5 5 CS5525 CS5526 SWITCHING CHARACTERISTICS (TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; Input Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50 pF.)) Parameter Master Clock Frequency (Note 19) Internal Clock External Clock (Note 20) Any Digital Input Except SCLK SCLK Any Digital Output (Note 20) Any Digital Input Except SCLK SCLK Any Digital Output XTAL = 32.768 kHz (Note 21) Symbol XIN 30 30 40 trise tfall tost tpor 50 500 1003 1.0 100 µs µs ns ms XIN cycles MHz ns ns ns ns ns ns ns ns ns ns 50 1.0 100 µs µs ns 32.768 32.768 36 100 60 kHz % Min Typ Max Unit Master Clock Duty Cycle Rise Times Fall Times Start-up Oscillator Start-up Time Power-on Reset Period Serial Port Timing Serial Clock Frequency SCLK Falling to CS Falling for continuous running SCLK (Note 22) Serial Clock SDI Write Timing CS Enable to Valid Latch Clock Data Set-up Time prior to SCLK rising Data Hold Time After SCLK Rising SCLK Falling Prior to CS Disable SDO Read Timing CS to Data Valid SCLK Falling to New Data Bit CS Rising to SDO Hi-Z t7 t8 t9 150 150 150 t3 t4 t5 t6 50 50 100 100 Pulse Width High Pulse Width Low SCLK t0 t1 t2 0 100 250 250 2 - Notes: 19. Device parameters are specified with a 32.768 kHz clock; however, clocks up to 100 kHz can be used for increased throughput. 20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. 22. Applicable when SCLK is continuously running. 6 DS202F5 CS5525 CS5526 CS t0 t3 t1 t6 SCLK t2 Continuous Running SCLK Timing (Not to Scale) CS t3 SDI M SB t4 M S B -1 t5 t1 LS B t6 S C LK t2 SDI Write Timing (Not to Scale) CS t7 t9 SDO M SB t8 M S B -1 t2 LS B SCLK t1 SDO Read Timing (Not to Scale) DS202F5 7 CS5525 CS5526 DETAILED DESCRIPTION The CS5525 and CS5526 are 16-bit and 20-bit pin compatible converters which include a chopperstabilized instrumentation amplifier input, and an on-chip programmable gain amplifier. They are both optimized for measuring low-level unipolar or bipolar signals in process control and medical applications. The CS5525/26 also include a fourth order deltasigma modulator, a calibration microcontroller, eight digital filters, a 4-bit analog latch, and a serial port. The digital filters provide any one of eight different output update rates. The CS5525/26 include a CPD (Charge Pump Drive) output (shown in Figure 1). CPD provides a negative bias voltage to the on-chip instrumentation amplifier when used with a combination of external diodes and capacitors. This enables the CS5525/26 to measure negative voltages with respect to ground, making the converters ideal for thermocouple temperature measurements. Theory of Operation The CS5525/26 A/D converters are designed to operate from a single +5 V analog supply and provide several different input ranges. See the Analog Characteristics section on page 3 for details. Figure 1 illustrates the CS5525/26 connected to generate their own negative bias supply using the on-chip CPD (Charge Pump Drive). This enables the CS5525/26 to measure ground referenced signals with magnitudes down to NBV (Negative Bias Voltage, approximately -2.1 V in this example). Figure 2 illustrates a charge pump circuit when the converters are powered from a +3.0 V digital supply. Alternatively, the negative bias supply can be generated from a negative supply voltage or a resistive divider as illustrated in Figure 3. Figure 1. CS5525/26 Configured to use on-chip charge pump to supply NBV. 8 DS202F5 CS5525 CS5526 Figure 4 illustrates the CS5525/26 connected to measure ground referenced unipolar signals of a positive polarity using the 1 V, 2.5 V, and 5 V input voltage ranges on the converter. For the 25 mV, 55 mV, and 100 mV ranges the signal must have a common mode near +2.5 V (NBV = 0V). The CS5525/26 are optimized for the measurement of thermocouple outputs, but they are also well suited for the measurement of ratiometric bridge transducer outputs. Figure 5 illustrates the CS5525/26 connected to measure the output of a ratiometric differential bridge transducer while operating from a single +5 V supply. 2N 5087 o r sim ila r NBV + 10 µ F 3 4 .8 K NBV 3 0 .1 K 2 .0 K + 10 µF 2 .1 K -5 V -5 V Figure 2. Charge Pump Drive Circuit for VD+ = 3 V. Figure 3. Alternate NBV Circuits. Figure 4. CS5525/26 Configured for ground-referenced Unipolar Signals. DS202F5 9 CS5525 CS5526 Figure 5. CS5525/26 Configured for Single Supply Bridge Measurement. System Initialization When power to the CS5525/26 is applied, they are held in a reset condition until their 32.768 kHz oscillators have started and their start-up counter-timer elapses. Due to the high Q of a 32.768 kHz crystal, the oscillators take 400-600 ms to start. The converter’s counter-timer counts no more than 1024 oscillator clock cycles to make sure the oscillator is fully stable. During this time-out period the serial port logic is reset and the RV (Reset Valid) bit in the configuration register is set. A reset can be initiated at any time by writing a logic 1 to the RS (Reset System) bit in the configuration register. This automatically sets the RV bit until the RS bit is written to logic 0, and the configuration register is read. After a reset, the on-chip registers are initialized to the following states and the converters are ready to perform conversions. configuration register: offset register: gain register: 000040(H) 000000(H) 800000(H) Command Operation The CS5525/26 include a microcontroller with five registers used to control the converter. Each register is 24-bits in length except the 8-bit command register (command, configuration, offset, gain, and conversion data). After a system initialization or reset, the serial port is initialized to the command mode and the converter stays in this mode until a valid 8-bit command is received (the first 8-bits into the serial port). Table 1 lists all the valid commands. Once a valid 8-bit command (a read or a write command word) is received and interpreted by the command register, the serial port enters the data mode. In data mode the next 24 serial clock pulses shift data either into or out of the serial port (72 serial clock pulses are needed if set-up register is selected). See Table 2 for configuring the CS5525/26. 10 DS202F5 CS5525 CS5526 Reading/Writing On-Chip Registers The CS5525/26’s offset, gain, and configuration registers are read/writable while the conversion data register is read only. To perform a read from a specific register, the R/W bit of the command word must be a logic 1. The SC, CC, and PS/R bits must be logic 0 and the CB (MSB) bit must be a logic 1. The register to be written is selected with the RSB2-RSB0 bits of the command word. To perform a write to a specific register, the R/W bit of the command word must be a logic 0. The SC, CC, and PS/R bits must be logic 0 and the CB (MSB) bit must be a logic 1. The register to be written is selected with the RSB2-RSB0 bits of the command word. Figure 6 illustrates the serial sequence necessary to write to, or read from the serial port. If the Set-up Registers are chosen with the RSB2RSB0 bits, the registers are read or written in the following sequence: Offset, Gain and Configuration. This is accomplished by following one 8-bit command word with three 24-bit data words for a total of 72 data bits. Command Register D7(MSB) CB BIT D7 D6 SC D5 CC NAME Command Bit, CB D4 R/W D3 RSB2 VALUE 0 1 D6 D5 D4 D3-D1 Single Conversion, SC Continuous Conversions, CC Read/Write, R/W Register Select Bit, RSB2-RSB0 0 1 0 1 0 1 000 001 010 011 100 101 110 111 0 1 D2 RSB1 D1 RSB0 D0 PS/R FUNCTION Null command (no operation). All command bits, including CB must be 0. Logic 1 for executable commands. Single Conversion not active. Perform a conversion. Continuous Conversions not active. Perform conversions continuously. Write to selected register. Read from selected register. Offset Register Gain Register Configuration Register Conversion Data Register (read only) Set-up Registers (Offset, Gain, Configuration) Reserved Reserved Reserved Run Power Save D0 Power Save/Run, PS/R Table 1. Command Set DS202F5 11 CS5525 CS5526 Configuration Register D23(MSB) A3 D11 G2 BIT D23-D20 D19 D18 D17 D16 D15-D13 D22 A2 D10 G1 D21 A1 D9 G0 NAME Latch Outputs, A3-A0 Not Used, NU Chop Frequency Select, CFS Not Used, NU Low Power Mode, LPM Word Rate, WR2-0 Note: For XIN = 32.768kHz D20 A0 D8 PD VALUE 0000 0 0 1 0 0 1 000 001 010 011 100 101 110 111 0 1 000 001 010 011 100 101 110/111 0 1 0 1 0 1 0 1 0 1 0 1 000 001 010 011 100 101 110 111 R Must always be logic 0. R 256 Hz Amplifier chop frequency 32768 Hz Amplifier chop frequency R Must always be logic 0. R Normal Mode Reduced Power mode R 15.0 Sps (2182 XIN cycles) 30.1 Sps (1090 XIN cycles) 60.0 Sps (546 XIN cycles) 123.2 Sps (266 XIN cycles) 168.9 Sps (194 XIN cycles) 202.3 Sps (162 XIN cycles) 3.76 Sps (8722 XIN cycles) 7.51 Sps (4362 XIN cycles) R Bipolar Measurement mode Unipolar Measurement mode R 100 mV (assumes VREF = 2.5V) 55 mV 25 mV 1V 5.0 V 2.5 V Not Used. R Charge Pump Enabled For PD = 1, the CPD pin goes to a Hi-Z output state. R Normal Operation Activate a Reset cycle. To return to Normal Operation write bit to zero. No reset has occurred or bit has been cleared (read only). R Valid Reset has occurred. (Cleared when read.) R Port Flag mode inactive Port Flag mode active R Standby Mode (Oscillator active, allows quick power-up) Sleep Mode (Oscillator inactive) R Done Flag bit is cleared (read only). Calibration or Conversion cycle completed (read only). R Normal Operation (no calibration) Offset -- Self-Calibration Gain -- Self-Calibration Offset Self-Calibration followed by Gain Self-Calibration Not used. Offset -- System Calibration Gain -- System Calibration Not Used. D19 NU D7 RS D18 CFS D6 RV D17 NU D5 PF D16 LPM D4 PSS D15 WR2 D3 DF FUNCTION R* Latch Output Pins A3-A0 mimic the D23-D20 Register bits. D14 WR1 D2 CC2 D13 WR0 D1 CC1 D12 U/B D0 CC0 D12 D11-D9 Unipolar/Bipolar, U/B Gain Bits, G2-G0 D8 D7 D6 D5 D4 D3 D2-D0 Pump Disable, PD Reset System, RS Reset Valid , RV Port Flag, PF Power Save Select, PSS Done Flag, DF Calibration Control Bits, CC2-CC0 * R indicates the bit value after the part is reset Table 2. Configuration Register 12 DS202F5 CS5525 CS5526 CS SCLK SDI C om m a nd T im e 8 SC LKs MSB LSB D a ta T im e 2 4 S C L K s (or 72 S C LK s fo r S e t-u p R e giste rs ) W rite C ycle CS SCLK SDI C om m a nd T im e 8 SC LKs SDO MSB LSB D ata T im e 2 4 S C LK s (or 7 2 S C LK s for S et-u p R e gisters ) Read C ycle SCLK SDI C o m m a n d T im e 8 SC LKs SDO td * X IN /O W R C lo ck C yc le s 8 S C L K s C le ar S D O F la g MSB LS B * td = X IN /O W R clock c ycles for each convers ion except the first conv ersion w hich w ill take X IN /O W R + 7 clock c ycles S DO C on tin u ou s C o nversion R ead (P F b it = 1) D ata T im e 2 4 S C LK s Figure 6. Command and Data Word Timing. DS202F5 13 CS5525 CS5526 Analog Input Figure 7 illustrates a block diagram of the analog input signal path inside the CS5525/26. The front end consists of a chopper-stabilized instrumentation amplifier with 20X gain and a programmable gain section. The instrumentation amplifier is powered from VA+ and from the NBV (Negative Bias Voltage) pin allowing the CS5525/26 to be operated in either of two analog input configurations. The NBV pin can be biased to a negative voltage between -1.8 V and -2.5 V, or tied to AGND. The choice of the operating mode for the NBV voltage depends upon the input signal and its common mode voltage. For the 25 mV, 55 mV, and 100 mV input ranges, the input signals to AIN+ and AIN- are amplified by the 20X instrumentation amplifier. For ground referenced signals with magnitudes less then 100 mV, the NBV pin should be biased with -1.8 V to -2.5 V. If NBV is tied between -1.8 V and -2.5 V, the (Common Mode + Signal) input on AIN+ and AIN- must stay between -0.150 V and 0.950 V to ensure proper operation. Alternatively, NBV can be tied to AGND where the input (Common Mode + Signal) on AIN+ and AIN- must stay between 1.85 V and 2.65 V to ensure that the amplifier operates properly. For the 1 V, 2.5 V, and 5 V input ranges, the instrumentation amplifier is bypassed and the input signals are directly connected to the Programmable Gain block. With NBV tied between -1.8 V and -2.5 V, the (Common Mode + Signal) input on AIN+ and AIN- must stay between NBV and VA+. Alternatively, NBV can be tied to AGND where the input (Common Mode + Signal) on AIN+ and AIN- pins can span the entire range between AGND and VA+. The CS5525/26 can accommodate full scale ranges other than 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V by performing a system calibration within the limits specified. See the Calibration section for more details. Another way to change the full scale range is to increase or to decrease the voltage reference to other than 2.5 V. See the Voltage Reference section for more details. Three factors set the operating limits for the input span. They include: instrumentation amplifier saturation, modulator 1’s density, and a lower reference voltage. When the 25 mV, 55 mV or 100 mV range is selected, the input signal (including the common mode voltage and the amplifier offset voltage) must not cause the 20X amplifier to saturate in either its input stage or output stage. To prevent saturation the absolute voltages on AIN+ and AINmust stay within the limits specified (refer to the ‘Analog Input’ table on page 3). Additionally, the differential output voltage of the amplifier must not exceed 2.8 V. The equation ABS(VIN + VOS) x 20 = 2.8 V defines the differential output limit, where VIN = (AIN+) - (AIN-) is the differential input voltage and VOS is the absolute maximum offset voltage for the instrumentation amplifier (VOS will not exceed 40 mV). If the VREF+ VREF- A IN + A IN NBV X 20 P ro g ra m m ab le G a in D iffere ntial 4 th o rder d e lta sig m a m o d ula to r D ig ita l F ilter Figure 7. Block Diagram of Analog Signal Path 14 DS202F5 CS5525 CS5526 Max. Differential Output 20X Amplifier 2.8 V (2) 2.8 V (2) 2.8 V (2) ∆-Σ Nominal(1) Differential Input ± 0.5 V ± 1.1 V ± 2.0 V ± 1.0 V ± 2.5 V ± 5.0 V ∆-Σ(1) Max. Input ± 0.75 V ± 1.65 V ± 3.0 V ± 1.5 V ± 5.0 V 0V, VA+ Input Range(1) ± 25 mV ± 55 mV ± 100 mV ± 1.0 V ± 2.5 V ± 5.0 V VREF 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V Gain Factor 5 2.272727... 1.25 2.5 1.0 0.5 Note: 1. The converter's actual input range, the delta-sigma's nominal full scale input, and the delta-sigma's maximum full scale input all scale directly with the value of the voltage reference. The values in the table assume a 2.5 V VREF voltage. Table 3. Relationship between Full Scale Input, Gain Factors, and Internal Analog Signal Limitations differential output voltage from the amplifier exceeds 2.8 V, the amplifier may saturate, which will cause a measurement error. The input voltage into the modulator must not cause the modulator to exceed a low of 20 percent or a high of 80 percent 1's density. The nominal full scale input span of the modulator (from 30 percent to 70 percent 1’s density) is determined by the VREF voltage divided by the Gain Factor. See Table 3 to determine if the CS5525/26 are being used properly. For example, in the 55 mV range to determine the nominal input voltage to the modulator, divide VREF (2.5 V) by the Gain Factor (2.2727). When a smaller voltage reference is used, the resulting code widths are smaller causing the converter output codes to exhibit more changing codes for a fixed amount of noise. Table 3 is based upon a VREF = 2.5 V. For other values of VREF, the values in Table 3 must be scaled accordingly. Figure’s 8 and 9 illustrate the input models for the AIN and VREF pins. The dynamic input current for each of the pins can be determined from the models shown and is dependent upon the setting of the CFS (Chop Frequency Select) bit. The effective input impedance for the AIN+ and AIN- pins remains constant for the three low level measurement ranges (25 mV, 55 mV, and 100 mV). The input current is lowest with the CFS bit cleared to logic 0. DS202F5 Note: Residual noise appears in the converter’s baseband for output word rates greater than 60 Sps if CFS is logic 0. By setting CFS to logic 1, the amplifier’s chop frequency chops at 32768 Hz eliminating the residual noise, but increasing the current. Note that C=48pF is for input current modeling only. For physical input capacitance see ‘Input Capacitance’ specification under ‘Analog Characteristics’ on page 3. 25m V , 55m V , and 100m V R anges A IN V os ≤ 2 5 m V i n = fV os C C = 48pF C F S = 0 , f = 256 H z C F S = 1 , f = 32.76 8 kH z 1V , 2 .5 V , and 5V R a nges A IN + A IN C = 32pF i n = [(V A IN + ) - (V A IN - )] fC f = 32.768 kH z Figure 8. Input models for AIN+ and AIN- pins VREF+ VREFC = 16pF i n = [(V R E F + ) - (V R E F -)] fC f = 3 2 .7 6 8 k H z Figure 9. Input model for VREF+ and VREF- pins. 15 CS5525 CS5526 Charge Pump Drive The CPD (Charge Pump Drive) pin of the converters can be used with external components (shown in Figure 1) to develop an appropriate negative bias voltage for the NBV pin. When CPD is used to generate the NBV, the NBV voltage is regulated with an internal regulator loop referenced to VA+. Therefore, any change on VA+ results in a proportional change on NBV. With VA+ = 5 V, NBV’s regulation is set proportional to VA+ at approximately -2.1 V. Figure 3 illustrates a means of supplying NBV voltage from a -5 V supply. For ground based signals with the instrumentation amplifier engaged (when in the 25mV, 55mV, or 100mV ranges), the voltage on the NBV pin should at no time be less negative than -1.8 V or more negative than -2.5 V. To prevent excessive voltage stress to the chip the NBV voltage should not be more negative than -3.0 V. The components in Figure 1 are the preferred components for the CPD filter. However, smaller capacitors can be used with acceptable results. The 10 µF ensures very low ripple on NBV. Intrinsic safety requirements prohibit the use of electrolytic capacitors. In this case, two 0.47 µF ceramic capacitors in parallel can be used. The CPD pin itself is a tri-state output and enters tri-state whenever the converters are placed into the Sleep Mode, Standby Mode, or when the charge pump is disabled (when the Pump Disable bit, bit D8 in the configuration register, is set). Once in tristate, the digital current can increase if this CPD output floats near 1/2 digital supply. To ensure the CPD pin stays near ground and to minimize the digital current, add a 5MΩ resistor between it and DGND (see Figure 1). If the resistor is left out, the digital supply current may increase from 2 µA to 10 µA. Voltage Reference The CS5525/26 are specified for operation with a 2.5 V reference voltage between the VREF+ and VREF- pins of the devices. For a single-ended reference voltage, such as the LT1019-2.5, the reference’s output is connected to the VREF+ pin of the CS5525/26. The ground reference for the LT10192.5 is connected to the VREF- pin. The differential voltage between the VREF+ and VREF- can be any voltage from 1.0 V up to 3.0 V, however, the VREF- pin can not go below analog ground. Calibration The CS5525/26 offer five different calibration functions including self calibration and system calibration. However, after the CS5525/26 are reset, they can perform measurements without being calibrated. In this case, the converters will utilize the initialized values of the on-chip registers (Gain = 1.0, Offset = 0.0) to calculate output words for the ±100 mV range. Any initial offset and gain errors in the internal circuitry of the chips will remain. The gain and offset registers, which are used for both self and system calibration, are used to set the zero and full-scale points of the converter’s transfer function. One LSB in the offset register is 2-24 proportion of the input span (bipolar span is 2 times the unipolar span). The MSB in the offset register determines if the offset to be trimmed is positive or negative (0 positive, 1 negative). The converters can typically trim ±50 percent of the input span. The gain register spans from 0 to (2 - 2-23). The decimal equivalent meaning of the gain register is N D = b0 2 + b1 2 0 –1 + b2 2 –2 + … + bN 2 –N = ∑ bi 2 i=0 –i where the binary numbers have a value of either zero or one (b0 corresponds to the MSB). Refer to Table 4 for details. 16 DS202F5 CS5525 CS5526 Offset Register Register Reset (R) 2-2 0 2-3 0 2-4 0 2-5 0 ≈ MSB Sign 0 LSB 2-20 0 2-21 0 2-22 0 2-23 0 2-24 0 2-6 0 2-19 0 One LSB represents 2-24 proportion of the input span (bipolar span is 2 times unipolar span) Offset and data word bits align by MSB (bit MSB-4 of offset register changes bit MSB-4 of data) Gain Register Register Reset (R) 2 1 0 2 0 -1 2 0 -2 2 0 -3 2 0 -4 ≈ MSB LSB 2 -19 2 0 -5 2 -18 2 -20 2 -21 2 -22 0 0 0 0 0 2-23 0 The gain register span is from 0 to (2-2-23). After Reset the MSB = 1, all other bits are 0. Table 3. Table 4. Offset and Gain Registers The offset and gain calibration steps each take one conversion cycle to complete. At the end of the calibration step, the calibration control bits will be set back to logic 0, and the DF (Done Flag) bit will be set to a logic 1. For the combination self-calibration (CC2-CC0= 011; offset followed by gain), the calibration will take two conversion cycles to complete and will set the DF bit after the gain calibration is completed. The DF bit will be cleared any time the data register, the offset register, the gain register, or the setup register is read. Reading the configuration register alone will not clear the DF bit. of the modulator are connected together and then routed to the VREF- pin as shown in Figure 11. For self-calibration of gain, the differential inputs of the modulator are connected to VREF+ and S1 OPEN AIN+ S2 CLOSED AIN+ X20 + Self Calibration The CS5525/26 offer both self offset and self gain calibrations. For the self-calibration of offset in the 25 mV, 55 mV, and 100 mv ranges, the converter internally ties the inputs of the instrumentation amplifier together and routes them to the AIN- pin as shown in Figure 10. For proper self-calibration of offset to occur in the 25 mV, 55 mV, and 100 mV ranges, the AIN- pin must be at the proper common-mode-voltage (i.e. AIN- = 0V, NBV must be between -1.8 V to -2.5 V). For self-calibration of offset in the 1.0 V, 2.5 V, and 5 V ranges, the inputs DS202F5 Figure 10. Self Calibration of Offset (Low Ranges). S1 OPEN AIN+ + X20 S3 CLOSED S2 OPEN S4 CLOSED + AINVREF- - - Figure 11. Self Calibration of Offset (High Ranges). 17 CS5525 CS5526 OPEN A IN+ + X20 AINVREF+ Reference + VREFCLOSED CLOSED OPEN + External Connections + AIN+ 0V + CM + AINX20 + Figure 12. Self Calibration of Gain (All Ranges). Figure 13. System Calibration of Offset (Low Ranges). VREF- as shown in Figure 12. For any input range other than the 2.5 V range, the modulator gain error can not be completely calibrated out. This is due to the lack of an accurate full scale voltage internal to the chips. The 2.5 V range is an exception because the external reference voltage is 2.5 V nominal and is used as the full scale voltage. In addition, when self-calibration of gain is performed in the 25 mV, 55 mV, and 100 mV input ranges, the instrumentation amplifier’s gain is not calibrated. These two factors can leave the converters with a gain error of up to ±20% after self-calibration of gain. Therefore, a system gain is required to get better accuracy, except for the 2.5 V range. External Connections + AIN+ 0V + AINX20 + CM + - Figure 14. System Calibration of Offset (High Ranges). External Connections + + X20 CM + AINAIN+ Full Scale + - System Calibration For the system calibration functions, the user must supply the converters calibration signals which represent ground and full scale. When a system offset calibration is performed, a ground reference signal must be applied to the converter. See Figures 13 and 14. As shown in Figures 15 and 16, the user must input a signal representing the positive full scale point to perform a system gain calibration. In either case, the calibration signals must be within the specified calibration limits for each specific calibration step (refer to the System Calibration Specifications). Figure 15. System Calibration of Gain (Low Ranges) External Connections + AIN+ Full Scale + CM + AINX20 + Figure 16. System Calibration of Gain (High Ranges). 18 DS202F5 CS5525 CS5526 Assuming a system can provide two known voltages, equations can allow the user to manually compute the calibration register’s values based on two uncalibrated conversions. The offset and gain calibration registers are used to adjust a typical conversion as follows: Rc = (Ru + Co>>4) * Cg / 223. Calibration can be performed using the following equations: Co = (Rc0/G - Ru0) > >2 is x shifted right 2 bits) = The shift left operator (e.g. x(VFS-1.5 LSB) VFS-1.5 LSB Two's Complement 7FFF 7FFF ----7FFE 0000 ----FFFF 8001 ----8000 8000 CS5526 20-Bit Output Coding Unipolar Input Offset Voltage Binary >(VFS-1.5 LSB) FFFFF VFS-1.5 LSB FFFFF ----FFFFE 80000 ----7FFFF 00001 ----00000 00000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 LSB Two's Complement 7FFFF 7FFFF ----7FFFE 00000 ----FFFFF 80001 ----80000 80000 VFS/2-0.5 LSB -0.5 LSB VFS/2-0.5 LSB -0.5 LSB +0.5 LSB