CS61583

CS61583 Dual T1/E1 Line Interface Features General Description The CS61583 is a dual line interface for T1/E1 applications, designed for high-volume cards where low power and high density are required. Each channel features individual control and status pins which eliminates the need for external microprocessor support. The matched impedance drivers reduce power consumption and provide substantial return loss to insure superior T1/E1 pulse quality. hance system testability and reliability. The CS61583 is a 5 volt device and is a hardware mode derivative of the CS61584. ORDERING INFORMATION CS61583-IL5: 68-pin PLCC, -40 to +85 °C CS61583-IQ5: 64-pin TQFP, -40 to +85 °C • • • • • • • Dual T1/E1 Line Interface Low Power Consumption (Typically 220mW per Line Interface) Matched Impedance Transmit Drivers Common Transmit and Receive TransformThe CS61583 provides JTAG boundary scan to eners for all Modes Selectable Jitter Attenuation for Transmit or Receive Paths Supports JTAG Boundary Scan Hardware Mode Derivative of the CS61584 RESET CLKE ATTEN2 CON11 TAOS1 RLOOP1 CON12 TAOS2 RLOOP2 AMI1 AMI2 ATTEN1 CODER1 CON01 CON21 LLOOP1 CODER2 CON02 CON22 LLOOP2 CONTROL E N C O D E R D E C O D E R E N C O D E R D E C O D E R R E M O T E L O O P B A C K R E M O T E L O O P B A C K TCLK1 TPOS1/ TDATA1 TNEG1/ AIS1 RCLK1 RPOS1/ RDATA1 RNEG1/ BPV1 L O C A L TAOS PULSE SHAPING CIRCUITRY TTIP1 DRIVER TRING1 JITTER ATTENUATOR L O O P B A C K LOS DETECT CLOCK & DATA RECOVERY RTIP1 RECEIVER RRING1 TCLK2 TPOS2/ TDATA2 TNEG2/ AIS2 RCLK2 RPOS2/ RDATA2 RNEG2/ BPV2 L O C A L TAOS PULSE SHAPING CIRCUITRY TTIP2 DRIVER TRING2 JITTER ATTENUATOR L O O P B A C K LOS DETECT CLOCK & DATA RECOVERY RTIP2 RECEIVER RRING2 JTAG 4 CLOCK GENERATOR 2 REFCLK 1XCLK LOS1 LOS2 2 2 2 3 2 TV+ TGND RV+ RGND DV+ DGND AV+ AGND BGREF Crystal Semiconductor Corporation P. O. Box 17847, Austin, Texas, 78760 (512) 445 7222 FAX:(512) 445 7581 Copyright © Crystal Semiconductor Corporation 1996 (All Rights Reserved) JULY ’96 DS172PP5 1 CS61583 Table of Contents Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Specifications Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . 3 Digital Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Analog Specifications Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Switching Characteristics T1 Clock/Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 E1 Clock/Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 General Description Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Line Control and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . 13 Line Code Encoder/Decoder. . . . . . . . . . . . . . . . . . . 13 Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . 14 Bipolar Violation Detection . . . . . . . . . . . . . . . . . . . 14 Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Transmit All Ones . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Local Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Remote Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 JTAG Boundary Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2 DS172PP5 CS61583 ABSOLUTE MAXIMUM RATINGS Parameter DC Supply (TV+1, TV+2, RV+1, RV+2, AV+, DV+) (Note 1) Input Voltage (Any Pin) Input Current (Any Pin) Ambient Operating Temperature Storage Temperature (Note 2) Vin Iin TA Tstg Symbol Min RGND - 0.3 -10 -40 -65 Max 6.0 (RV+) + 0.3 10 85 150 Units V V mA °C °C WARNING: Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Referenced to RGND1, RGND2, TGND1, TGND2, AGND, DGND at 0V. 2. Transient currents of up to 100 mA will not cause SCR latch-up. RECOMMENDED OPERATING CONDITIONS Parameter DC Supply (TV+1, TV+2, RV+1, RV+2, AV+, DV+) (Note 3) Ambient Operating Temperature Power Consumption (Each Channel) T1 T1 E1, 75Ω E1, 120Ω T1 T1 E1 E1 (Notes (Notes (Notes (Notes 4 4 4 4 and and and and 5) 6) 5) 5) TA PC Symbol Min 4.75 -40 1.544 100 ppm 12.352 100 ppm 2.048 100 ppm Typ 5.0 25 310 220 275 275 1.544 12.352 2.048 Max 5.25 85 1.544 + 100 ppm 12.352 + 100 ppm 2.048 + 100 ppm Units V °C mW mW mW mW MHz MHz MHz REFCLK Frequency 1XCLK = 1 1XCLK = 0 1XCLK = 1 1XCLK = 0 Notes: 3. 4. 5. 6. 16.384 16.384 + 16.384 MHz 100 ppm 100 ppm TV+1, TV+2, AV+, DV+, RV+1, RV+2 should be connected together. TGND1, TGND2, RGND1, RGND2, DGND1, DGND2, DGND3 should be connected together. Power consumption while driving line load over operating temperature range. Includes IC and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. Assumes 100% ones density and maximum line length at 5.25V. Assumes 50% ones density and 300ft. line length at 5.0V. DS172PP5 3 CS61583 DIGITAL CHARACTERISTICS (TA = -40 to 85 °C; power supply pins within ±5% of nominal) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Digital pins) Low-Level Output Voltage (Digital pins) IOUT = -40 µA (Note 8) IOUT = 1.6 mA (Note 7) (Note 7) (Note 8) Symbol VIH VIL VOH VOL Min (DV+)-0.5 (DV+)-0.3 Typ Max 0.5 0.3 ±10 Units V V V V µA Input Leakage Current (Digital pins except J-TMS, and J-TDI) Notes: 7. Digital inputs are designed for CMOS logic levels. 8. Digital outputs are TTL compatible and drive CMOS levels into a CMOS load. ANALOG SPECIFICATIONS (TA = -40 to 85 °C; Parameter power supply pins within ±5% of nominal) Min -13.6 (Note 9) (Note 10) (Note 11) (Note 12) (Note 13) 60 55 45 40 160 300 6.0 0.4 12 18 14 Typ 20k 0.3 65 50 175 4 5.5 60 Max 70 75 55 60 190 Units Ω dB V % of Peak bits UI UI UI dB dB dB Hz Hz dB UIpk-pk Receiver RTIP/RRING Differential Input Impedance Sensitivity Below DSX-1 (0 dB = 2.4 V) Loss of Signal Threshold Data Decision Threshold T1, DSX-1 E1 Allowable Consecutive Zeros before LOS Receiver Input Jitter Tolerance (DSX-1, E1) Receiver Return Loss 10 Hz and below 2 kHz 10 kHz - 100 kHz 51 kHz - 102 kHz 102 kHz - 2.048 MHz 2.048 MHz - 3.072 MHz T1 E1 (Notes 14, 21, and 22) Jitter Attenuator Jitter Attenuation Curve Corner Frequency (Notes 14 and 15) (Notes 14 and 15) Attenuation at 10 kHz Jitter Frequency Attenuator Input Jitter Tolerance (Note 14) 28 43 (Before Onset of FIFO Overflow or Underflow Protection) Notes: 9. For input amplitude of 1.2 Vpk to 4.14 Vpk 10. For input amplitude of 0.5 Vpk to 1.2 Vpk, and 4.14 Vpk to 5.0 Vpk 11. For input amplitude of 1.07 Vpk to 4.14 Vpk, 12. For input amplitude of 4.14 Vpk to 5.0 Vpk, 13. Jitter tolerance increases at lower frequencies. Refer to the Receiver section. 14. Not production tested. Parameters guaranteed by design and characterization. 15. Attenuation measured with sinusoidal input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates jitter at 20 dB/decade above the corner frequency. Output jitter can increase significantly when more than 28 UI’s are input to the attenuator. Refer to the Jitter Attenuator section. 4 DS172PP5 CS61583 ANALOG SPECIFICATIONS (TA = -40 to 85 °C; power supply pins within ±5% of nominal) Parameter Min (Note (Note (Note (Note 16) 17) 18) 19) Typ Max Units Transmitter AMI Output Pulse Amplitudes E1, 75Ω E1, 120Ω T1, DSX-1 Recommended Transmitter Output Load T1 E1, 75Ω E1, 120Ω Jitter Added During Remote Loopback 10 Hz - 8 kHz 8 kHz - 40 kHz 10 Hz - 40 kHz Broad Band 2.14 2.7 2.4 12.6 -29 -5 -5 18 14 10 2.37 3.0 3.0 76.6 57.4 90.6 0.005 0.008 0.010 0.015 15 -38 0.2 25 18 12 25 244 2.6 3.3 3.6 17.9 0.5 +5 +5 50 V V V Ω Ω Ω UI UI UI UI dBm dB dB % % dB dB dB mArms ns ns (Note 16) (Note 20) (Notes 14 and 21) (DSX-1 only) (Notes 14 and 21)) (DSX-1 only) Power in 2 kHz band about 772 kHz Power in 2 kHz band about 1.544 MHz (referenced to power in 2 kHz band at 772 kHz) Positive to Negative Pulse Imbalance (Notes 14 and 21) T1, DSX-1 E1, amplitude at center of pulse interval E1, width at 50% of nominal amplitude Transmitter Return Loss (Notes 14, 21, and 22) 51 kHz - 102 kHz 102 kHz - 2.048 MHz 2.048 MHz - 3.072 MHz (Note 23) (Note 24) E1 Short Circuit Current E1 and DSX-1 Output Pulse Rise/Fall Times E1 Pulse Width (at 50% of peak amplitude) E1 Pulse Amplitude E1, 75Ω -0.237 0.237 V -0.3 0.3 V for a space E1, 120Ω Notes: 16. Using a transformer that meets the specifications in the Applications section. 17. Measured across 75 Ω at the output of the transmit transformer for CON2/1/0 = 0/0/0. 18. Measured across 120 Ω at the output of the transmit transformer for CON2/1/0 = 0/0/1. 19. Measured at the DSX-1 cross-connect for line length settings CON2/1/0 = 0/1/0, 0/1/1, 1/0/0, 1/0/1, and 1/1/0 after the appropriate length of #22 ABAM cable specified in Table 1. 20. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK. 21. Typical performance using the line interface circuitry recommended in the Applications section. 22. Return loss = 20 log 10 ABS((z1+z0)/(z1-z0)) where z1=impedance of the transmitter or receiver, and z0=cable impedance. 23. Transformer secondary shorted with 0.5 Ω resistor during the transmission of 100% ones. 24. At transformer secondary and measured from 10% to 90% of amplitude. DS172PP5 5 CS61583 SWITCHING CHARACTERISTICS - T1 CLOCK/DATA (TA = -40 to 85 °C; power supply pins within ±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3) Parameter TCLK Frequency TCLK Duty Cycle RCLK Duty Cycle Rise Time (All Digital Outputs) Fall Time (All Digital Outputs) RCLK Rising to RPOS/RNEG (RDATA) Hold Time TPOS/TNEG (TDATA) to TCLK Falling Setup Time TCLK Falling to TPOS/TNEG (TDATA) Hold Time (Note 27) (Note 27) (Note 25) Symbol ftclk tpwh2/tpw2 (Note 26) tpwh1/tpw1 tr tf tsu1 th1 tsu2 th2 Min 30 45 25 25 Typ 1.544 50 50 274 274 Max 70 55 65 65 Units MHz % % ns ns ns ns ns ns RPOS/RNEG (RDATA) to RCLK Rising Setup Time Notes: 25. The maximum burst rate of a gapped TCLK input clock is 8.192 MHz. For the gapped clock to be tolerated by the CS61583, the jitter attenuator must be switched to the transmit path of the line interface. The maximum gap size that can be tolerated on TCLK is 28 UIp-p. 26. RCLK duty cycle may be outside the specified limits when the jitter attenuator is in the receive path, and when the jitter attenuator is employing the overflow/underflow protection mechanism. 27. At max load of 50 pF. SWITCHING CHARACTERISTICS - E1 CLOCK/DATA (TA = -40 to 85 °C; power supply pins within ±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3) Parameter TCLK Frequency TCLK Duty Cycle RCLK Duty Cycle Rise Time (All Digital Outputs) Fall Time (All Digital Outputs) RCLK Rising to RPOS/RNEG (RDATA) Hold Time TPOS/TNEG (TDATA) to TCLK Falling Setup Time TCLK Falling to TPOS/TNEG (TDATA) Hold Time (Note 27) (Note 27) (Note 25) Symbol ftclk tpwh2/tpw2 (Note 26) tpwh1/tpw1 tr tf tsu1 th1 tsu2 th2 Min 30 45 25 25 Typ 2.048 50 50 194 194 Max 70 55 65 65 Units MHz % % ns ns ns ns ns ns RPOS/RNEG (RDATA) to RCLK Rising Setup Time 6 DS172PP5 CS61583 tr Any Digital Output 90% 10% 90% tf 10% Figure 1. Signal Rise and Fall Characteristics t pw1 RCLK (CLKE = 1) t pwl1 t pwh1 RPOS RNEG RDATA BPV RCLK (CLKE =0) t su1 t h1 Figure 2. Recovered Clock and Data Switching Characteristics t pw2 t pwh2 TCLK t su2 TPOS TNEG TDATA t h2 Figure 3. Transmit Clock and Data Switching Characteristics DS172PP5 7 CS61583 SWITCHING CHARACTERISTICS - JTAG Parameter Cycle Time J-TMS/J-TDI to J-TCK rising setup time J-TCK rising to J-TMS/J-TDI hold time J-TCK falling to J-TDO valid (TA = - 40 ° to 85 ° C; TV+, RV+ = nominal ±0.3V; Inputs: Logic 0 = 0V, Logic 1 = RV+) (See Figure 4) Symbol tcyc tsu th tdv Min 200 50 50 Typ Max 50 Units ns ns ns ns t cyc J-TCK t su J-TMS J-TDI th t dv J-TDO Figure 4. JAG Switching Characteristics 8 DS172PP5 CS61583 OVERVIEW The CS61583 is a dual line interface for T1/E1 applications, designed for high-volume cards where low power and high density are required. One board design can support all T1/E1 shorthaul modes by only changing component values in the receive and transmit paths (if REFCLK and TCLK are externally tied together). Figure 5 illustrates applications of the CS61583 in various environments. All control of the device is achieved via external pins, eliminating the need for microprocessor support. The following pin control options are available on a per channel basis: line length selection, coder mode, jitter attenuator location, transmit all ones, local loopback, and remote loopback. The line driver generates waveforms compatible with E1 (CCITT G.703), T1 short haul (DSX-1), and T1 FCC Part 68 Option A (DS1). A single transformer turns ratio is used for all waveform types. The driver internally matches the impedance of the load, providing excellent return loss to insure superior T1/E1 pulse quality. An addi- L O O P T IM ED AP PL IC A TIO N R EF C LK C S 61583 T T IP LIN E D R IV ER TR IN G TPOS TNEG TC LK C S 62180B FR A M E R R C LK RPOS R N EG T R A N SM IT C IR C U IT R Y JIT TE R A T TE N U A T O R R T IP LIN E R E C E IV E R R R IN G R E C E IVE C IR C U IT R Y ASYNCHRO NOUS MUX APPLICATIO N (i.e., VT1.5 card for SO NET or SDH mux) R E F C LK TD A TA JIT T ER AT T E N U A T O R M UX TC LK (ga pped ) R C LK R D A TA AMI B8ZS , H D B 3, CODER AIS DETECT LIN E R E C E IV E R C S 61583 T T IP LIN E D R IV ER T R IN G T R A N SM IT C IR C U IT R Y R TIP R R IN G R E C E IVE C IR C U IT R Y SYNCHRO NOUS APPLICATIO N (Including 62411 systems w ith multiple T1 lines) R E F C LK T C LK T T IP TPOS TNEG C S 62180B FR A M E R R C LK RPOS C S 61583 LIN E D R IV ER T R IN G T R A N SM IT C IR C U IT R Y R N EG JIT TE R A T TE N U A T O R R T IP LIN E R E C E IV ER R R IN G R E C E IVE C IR C U IT R Y Figure 5. Examples of CS61583 Applications DS172PP5 9 CS61583 tional benefit of the internal impedance matching is a 50 percent reduction in power consumption compared to implementing return loss using external resistors that causes the transmitter to drive the equivalent of two line loads. The line receiver contains all the necessary clock and data recovery circuits. The jitter attenuator meets AT&T 62411 requirements when using a 1X or 8X reference clock supplied by either a crystal oscillator or external reference at the REFCLK input pin. AT&T 62411 Customer Premises Application The AT&T 62411 specification applies to the T1 interface between the customer premises and the carrier, and must be implemented by the customer premises equipment in order to connect to the AT&T network. In 62411 applications, the management of jitter is a very important design consideration. Typically, the jitter attenuator is placed in the receive path of the CS61583 to reduce the jitter input to the system synchronizer. The jitter attenuated recovered clock is used as the input to the transmit clock to implement a loop-timed system. A Stratum 4 (±32 ppm) quality clock or better should be input to REFCLK. Note that any jitter present on the reference clock will not be filtered by the jitter attenuator. Asynchronous Multiplexer Application Asynchronous multiplexers accept multiple T1/E1 lines (which are asynchronous to each other), and combine them into a higher speed transmission rate (e.g. M13 muxes and SONET muxes). In these systems, the jitter attenuator is placed in the transmit path of the CS61583 to remove the gapped clock jitter input by the multiplexer to TCLK. Because the transmit clock is jittered, the reference clock to the CS61583 is provided by an external source operating at 1X or 8X the data rate. Because T1/E1 framers are 10 not usually required in asynchronous multiplexers, the B8ZS/AMI/HDB3 coders in the CS61583 are activated to provide data interfaces on TDATA and RDATA. Synchronous Application A typical example of a synchronous application is a T1 card in a central office switch or a 0/1 digital cross-connect system. These systems place the jitter attenuator in the receive path to reduce the jitter presented to the system. A Stratum 3 or better system clock is input to the CS61583 transmit and reference clocks. TRANSMITTER The transmitter accepts data from a T1 or E1 system and outputs pulses of appropriate shape to the line. The transmit clock (TCLK) and transmit data (TPOS & TNEG, or TDATA) are supplied synchronously. Data is sampled on the falling edge of the TCLK input. The configuration pins CON[2:0] control transmitted pulse shapes, transmitter source impedance, and receiver slicing level as shown in Table 1. Typical output pulses are shown in Figures 6 and 7. These pulse shapes are fully pre-defined by circuitry in the CS61583, and are fully compliant with appropriate standards when used with our application guidelines in standard installations. Both channels must be operated at the same line rate (both T1 or both E1). Note that the pulse width for Part 68 Option A (324 ns) is narrower than the optimal pulse width for DSX-1 (350 ns). The CS61583 automatically adjusts the pulse width based on the configuration selection. The transmitter impedance changes with the line length options in order to match the load impedance (75Ω for E1 coax, 100Ω for T1, 120Ω for E1 shielded twisted pair), providing a minimum of 14 dB return loss for T1 and E1 frequencies DS172PP5 CS61583 Percent nominal peak voltage 120 110 ANSI T1.102 SPECIFICATION 0.5 NORMALIZED AMPLITUDE 1.0 of 269 ns 244 ns 194 ns G.703 Specification 100 90 80 0 CS61583 OUTPUT PULSE SHAPE -0.5 0 250 500 750 1000 50 10 Nominal Pulse 0 -10 -20 219 ns 488 ns TIME (nanoseconds) Figure 6. Typical Pulse Shape at DSX-1 Cross Connect d uring the transmission of both marks and spaces. This improves signal quality by minimizing reflections from the transmitter. Impedance matching also reduces load power consumption by a factor of two when compared to the return loss achieved by using external resistors. The CS61583 driver will automatically detect an inactive TLCK input (i.e., no valid data is being clocked to the driver). When this condition is detected, the driver is forced low (except during remote loopback) to output spaces and prevent TTIP and TRING from entering a constant transmit-mark state. C O N 2 0 0 0 0 1 1 1 1 C O N 1 0 0 1 1 0 0 1 1 C O N 0 0 1 0 1 0 1 0 1 Transmit Pulse Width at 50% Transmit Pulse Shape Amplitude 244 244 350 350 350 350 350 324 ns ns ns ns ns ns ns ns (50%) (50%) (54%) (54%) (54%) (54%) (54%) (50%) Figure 7. Pulse Mask at the 2048 kbps Interface When any transmit configuration established by CON[2:0], TAOS, or LLOOP changed states, the transmitter stabilizes within 22 TCLK bit periods. The transmitter takes longer to stabilize when RLOOP1 or RLOOP2 is selected because the timing circuitry must adjust to the new frequency from RCLK. When the transmitter transformer secondaries are shorted through a 0.5 ohm resistor, the transmitReceiver Slicing Level 50% 50% 65% 65% 65% 65% 65% 65% E1: square, 2.37 Volts into 75 Ω E1: square, 3.00 Volts into 120 Ω DSX-1: 0-133 ft. / or DS1 FCC Part 68 Option A with undershoot DSX-1: 133-266 ft. DSX-1: 266-399 ft. DSX-1: 399-533 ft. DSX-1: 533-655 ft. DS1: FCC Part 68 Option A (0 dB) Table 1. Configuration Selection DS172PP5 11 CS61583 ter will output a maximum of 50 mA-rms, as required by European specification BS6450. RECEIVER The receiver extracts data and clock from the T1/E1 signal on the line interface and outputs clock and synchronized data to the system. The signal is detected differentially across the receive transformer and can be recovered over the entire range of short haul cable lengths. The transmit and receive transfomer specifications are identical and are presented in the Applications section. As shown in Table 1, the receiver slicing level is set at 65% for DS1/DSX-1 short-haul and at 50% for all other applications. The clock recovery circuit is a second-order phase locked loop that can tolerate up to 0.4 UI of jitter from 10 kHz to 100 kHz without generating errors (Figure 8). The clock and data recovery circuit is tolerant of long strings of consecutive zeros and will successfully recover a 1-in-175 jitter-free line input signal. Reco vered data at RPOS and RNEG (or RDATA) is stable and may be sampled using the recovered clock RCLK. The CLKE input determines the clock polarity for which output data is stable and valid as shown in Table 2. When CS61583 Performance CLKE is low, RPOS and RNEG (or RDATA) are valid on the rising edge of RCLK. When CLKE is high, RPOS and RNEG (or RDATA) are valid on the falling edge of RCLK. CLKE LOW HIGH DATA RPOS, RNEG or RDATA RPOS, RNEG or RDATA CLOCK RCLK RCLK RCLK RCLK Clock Edge for Valid Data Rising Rising Falling Falling Table 2. Recovered Data/Clock Options JITTER ATTENUATOR The jitter attenuator can be switched into either the receive or transmit paths. Alternatively, it can also be removed from both paths to reduce the propagation delay. The location of the attenuators for both channels is controlled by the ATTEN0 and ATTEN1 pins. Table 3 shows how these pins are decoded. ATTEN1 0 0 1 1 ATTEN0 0 1 0 1 Location of Jitter Attenuator Receiver Disabled Transmitter Reserved Table 3. Jitter Attenuation Control 300 138 100 AT&T 62411 (1990 Version) 28 PEAK-TO-PEAK JITTER 10 (unit intervals) 1 .4 .1 1 10 100 300 700 1k JITTER FREQUENCY (Hz) 10k 100k Figure 8. Minimum Input Jitter Tolerance of Receiver (Clock Recovery Circuit and Jitter Attenuator) 12 The attenuator consists of a 64-bit FIFO, a narrow-band monolithic PLL, and control logic. Signal jitter is absorbed in the FIFO which is designed to neither overflow nor underflow. If overflow or underflow is imminent, the jitter transfer function is altered to insure that no biterrors occur. Under this condition, jitter gain may occur and jitter should be attenuated externally in a frame buffer. The jitter attenuator will typically tolerate 43 UIs before the overflow/underflow mechanism occurs. If the jitter attenuator has not had time to "lock" to the averDS172PP5 CS61583 age incoming frequency (e.g. following a device reset) the attenuator will tolerate a minimum of 22 UIs before the overflow/underflow mechanism occurs. For T1/E1 line cards used in high-speed mutiplexers (e.g., SONET and SDH), the jitter attenuator is typically used in the transmit path. The attenuator can accept a transmit clock with gaps ≤ 28 UIs and a transmit clock burst rate of ≤ 8 MHz. When the jitter attenuator is in the receive path and loss of signal occurs, the frequency of the last recovered signal is held. When the jitter attenuator is not in the receive path, the last recovered frequency is not held and the output frequency becomes the frequency of the reference clock. A typical jitter attenuation curve is shown in Figure 9. 0 a) Minimum Attenuation Limit 10 20 30 40 50 60 CS61583 Performance 1 10 100 1k 10 k b) Maximum Attenuation Limit 62411 (1990 Version) Requirements jittered transmit clock, the reference clock should not be tied to the transmit clock and a separate external oscillator should drive the reference clock input. Any jitter present on the reference clock will not be filtered by the jitter attenuator. POWER-UP RESET On power-up, the device is held in a static state until the power supply achieves approximately 60% of the power supply voltage. When this threshold is crossed, the device waits another 10 ms to allow the power supply to reach operating voltage and then calibrates the transmit and receive circuitry. This initial calibration takes less than 20 ms but can occur only if REFCLK and TCLK are present. The power-up reset performs the same functions as the RESET pin. LINE CONTROL AND MONITORING Line control and monitoring of the CS61583 is achieved using the control pins. The controls and indications available on the CS61583 are detailed below. Line Code Encoder/Decoder Coding may be transparent, AMI, B8ZS, or HDB3 and is selected using the CODER1, CODER2, AMI1, and AMI2 pins. In the coder mode, AMI, B8ZS, and HDB3 line codes are available. The input data to the encoder is on TDATA and the output data from the decoder is in NRZ format on RDATA. See Table 4. CODER[2:1]=0 CODER[2:1]=1 AMI[2:1]=0 B8ZS/HDB3 Encoder/Decoder Enabled AMI[2:1]=1 AMI Encoder/Decoder Enabled Attenuation in dB Frequency in Hz Figure 9. Typical Jitter Transfer Function REFERENCE CLOCK The CS61583 requires a reference clock with a minimum accuracy of ±100 ppm for T1 and E1 applications. This clock can be either a 1X clock (i.e., 1.544 MHz or 2.048 MHz), or can be a 8X clock (i.e., 12.352 MHz or 16.384 MHz) as selected by the 1XCLK pin. In systems with a DS172PP5 Transparent Mode Enabled and AMI[2:1] Pin(s) Disabled Table 4. Coder Mode Options 13 CS61583 Alarm Indication Signal In coder mode, the TNEG pin becomes the alarm indication signal (AIS) output controlled by the receiver. The receiver detects the AIS condition on observation of 99.9% ones density in a 5.3 ms period (< 9 zeros in 8192 bits) and sets the AIS pin high. The AIS condition is exited when ≥ 9 zeros are detected in 8192 bits. Bipolar Violation Detection In coder mode, the RNEG pin becomes the bipolar violation (BPV) strobe output controlled by the receiver. The BPV pin goes high for one RCLK period when a bipolar violation is detected in the received signal. Note that B8ZS or HDB3 zero substitutions are not flagged as bipolar violations when the decoder is enabled. Loss of Signal The loss of signal (LOS) indication is detected by the receiver and reported when the LOS pin is high. Loss of signal is indicated when 175±15 consecutive zeros are received. The LOS conditio n is exited according to the ANSI T1.231-1993 criteria that requires 12.5% ones density over 175±75 bit periods with no more than 100 consecutive zeros. Note that bit errors may occur at RPOS and RNEG (or RDATA) prior to the LOS indication if the analog input level falls below the receiver sensitivity. The LOS pin is set high when the device is reset or in powered up and returns low when data is recovered by the receiver. Transmit All Ones Transmit all ones is selected by setting the TAOS pin high. Selecting TAOS causes continuous ones to be transmitted to the line interface on TTIP and TRING at the frequency of REFCLK. In this mode, the transmit data inputs TPOS and TNEG (or TDATA) are ignored. A TAOS overrides the data transmitted to the line interface during local and remote loopbacks. 14 Local Loopback A local loopback is selected by setting the LLOOP pin high. Selecting LLOOP causes the TCLK, TPOS, and TNEG (or TDATA) inputs to be looped back through the jitter attenuator (if enabled) to the RCLK, RPOS, and RNEG (or RDATA) outputs. Data received at the line interface is ignored, but data at TPOS and TNEG (or TDATA) continues to be transmitted to the line interface at TTIP and TRING. A TAOS request overrides the data transmitted to the line interface during local loopback. Note that simultaneous selection of local and remote loopback modes is not valid. Remote Loopback A remote loopback is selected by setting the RLOOP pin high. Selecting RLOOP causes the data received from the line interface at RTIP and RRING to be looped back through the jitter attenuator (if enabled) and retransmitted on TTIP and TRING. Data transmitted at TPOS and TNEG (or TDATA) is ignored, but data recovered from RTIP and RRING continues to be transmitted on RPOS and RNEG (or RDATA). Remote loopback is functional if TCLK is absent. A TAOS request overrides the data transmitted to the line interface during a remote loopback. Note that simultaneous selection of local and remote loopback modes is not valid. Reset Pin The CS61583 is continuously calibrated during operation to insure the performance of the device over power supply and temperature. The continuous calibration function eliminates the need to reset the line interface during operation. A device reset may be selected by setting the RESET pin high for a minimum of 200 ns. The reset function initiates on the falling edge of RESET and takes less than 20 ms to complete. The control logic is initialized and the transmit and DS172PP5 CS61583 receive circuitry is calibrated if REFCLK and TCLK are present. JTAG BOUNDARY SCAN Board testing is supported through JTAG boundary scan. Using boundary scan, the integrity of the digital paths between devices on a circuit board can be verified. This verification is supported by the ability to externally set the signals on the digital output pins of the CS61583, and to externally read the signals present on the input pins of the CS61583. Additionally, the manufacturer ID, part number and revision of the CS61583 can be read during board test using JTAG boundary scan. As shown in Figure 10, the JTAG hardware consists of data and instruction registers plus a Test Access Port (TAP) controller. Control of the TAP is achieved through signals applied to the Test Mode Select (J-TMS) and Test Clock ( J-TCK) input pins. Data is shifted into the registers via the Test Data Input (J-TDI) pin, and shifted out of the registers via the Test Data Output (J-TDO) pin. Both J-TDI and J-TDO are clocked at a rate determined by J-TCK. The Instruction register defines which data register is accessed in the Digital output pins shift operation. Note that if J-TDI is floating, an internal pull-up resistor forces the pin high. JTAG Data Registers (DR) The test data registers are the Boundary-Scan Register (BSR), the Device Identification Register (DIR), and the Bypass Register (BR). Boundary Scan Register: The BSR is connected in parallel to all the digital I/O pins, and provides the mechanism for applying/reading test patterns to/from the board traces. The BSR is 67 bits long and is initialized and read using the instruction SAMPLE/PRELOAD. The bit ordering for the BSR is the same as the top-view package pin out, beginning with the LOS1 pin and moving counter-clockwise to end with the CODER1 pin as shown in Table 5. Note that the analog, oscillator, power, ground, CLKE, and ATTEN0 pins are not included as part of the boundaryscan register. The input pins require one bit in the BSR and only one J-TCK cycle is required to load test data for each input pin. The output pins have two bits in the BSR to define output high, output low, or high impedance. Digital input pins JTAG Block parallel latched output Boundary Scan Data Register Device ID Data Register J-TDI Bypass Data Register Instruction (shift) Register parallel latched output J-TMS TAP Controller MUX J-TDO J-TCK Figure 10. Block Diagram of JTAG Circuitry DS172PP5 15 CS61583 The first bit (shifted in first) selects between an output-enabled state (bit set to 1) or high-impedance state (bit set to 0). The second bit shifted in contains the test data that may be output on the pin. Therefore, two J-TCK cycles are required to load test data for each output pin. BSR bits 0-2 3-5 6 7 8-9 10-11 12-13 14-16 17-19 20 21-23 24-26 27-29 30-32 33-35 36-38 39-41 42-44 45 46-48 49-50 51-52 53-54 55 56 57-59 60-62 63 64 65 66 Pin Name LOS1 TNEG1/AIS1 TPOS1/TDATA1 TCLK1 RNEG1/BPV1 RPOS1/RDATA1 RCLK1 ATTEN1 RLOOP1 LLOOP1 LLOOP2 TAOS1 TAOS2 CON01 CON02 CON11 CON12 CON21 CON22 AMI1 RCLK2 RPOS2/RDATA2 RNEG2/BPV2 TCLK2 TPOS2/TDATA2 TNEG2/AIS2 LOS2 AMI2 CODER2 RLOOP2 CODER1 Pad Type bi-directional2 bi-directional input input output output output bi-directional1 bi-directional input bi-directional1 bi-directional1 bi-directional1 bi-directional1 bi-directional1 bi-directional1 bi-directional1 bi-directional1 input bi-directional1 output output output input input bi-directional bi-directional2 input input input input 1 The bi-directional pins have three bits in the BSR to define input, output high, output low, or high impedance. The first bit shifted into the BSR configures the output driver as high-impedance (bit set to 0) or active (bit set to 1). The second bit shifted into the BSR sets the output value when the first bit is 1. The third bit captures the value of the pin. This pin may have its value set externally as an input (if the first bit is 0) or set internally as an output (if the first bit is 1). To configure a pad as an input, the J-TDI pattern is 0X0. To configure a pad as an output, the J-TDI pattern is 1X1. Therefore, three J-TCK cycles are required to load test data for each bidirectional pin. Device Identification Register: The DIR provides the manufacturer, part number, and version of the CS61583. This information can be used to verify that the proper version or revision number has been used in the system under test. The DIR is 32 bits long and is partitioned as shown in figure 11. MSB LSB 31 28 27 12 11 10 00000000000000000011000011001001 (4 bits) (16 bits) (11 bits) BIT #(s) 31-28 27-12 11-1 0 FUNCTION Version number Part Number Manufacturer Number Constant Logic ’1’ Total Bits 4 16 11 1 Figure 11. Device Identification Register Data from the DIR is shifted out to J-TDO LSB first. Bypass Register: The Bypass register consists of a single bit, and provides a serial path between J-TDI and J-TDO, bypassing the BSR. This allows bypassing specific devices during certain board-level tests. This also reduces test access times by reducing the total number of shifts required from J-TDI to J-TDO. 1. Configure pad as an input. 2. Configure pad as an output. Table 5. Boundary Scan Register 16 DS172PP5 CS61583 JTAG Instructions and Instruction Register (IR) The instruction register (2 bits) allows the instruction to be shifted into the JTAG circuit. The instruction selects the test to be performed or the data register to be accessed or both. The valid instructions are shifted in LSB first and are listed below: IR CODE 00 01 10 11 INSTRUCTION EXTEST SAMPLE/PRELOAD IDCODE BYPASS Internal Testing Considerations Note that the INTEST instruction is not supported because of the difficulty in performing significant internal tests using JTAG. The one test that could be easily performed using an arbitrary clock rate on TCLK and REFCLK is a local loopback with jitter attenuator disabled. However, this test provides limited fault coverage and is only useful in determining if the device had been catastrophically destroyed. Alternatively, catastrophic destruction of the device and/or surrounding board traces can be detected using EXTEST. Therefore, the INTEST instruction provides limited testing capability and was not included in the CS61583. JTAG TAP Controller Figure 12 shows the state diagram for the TAP state machine. A description of each state follows. Note that the figure contains two main branches to access either the data or instruction registers. The value shown next to each state transition in this figure is the value present at J-TMS at each rising edge of J-TCK. Test-Logic-Reset State In this state, the test logic is disabled to continue normal operation of the device. During initialization, the CS61583 initializes the instruction register with the IDCODE instruction. Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the J-TMS input is held high for at least five rising edges of J-TCK. The controller remains in this state while J-TMS is high. The CS61583 processor automatically enters this state at power-up. Run-Test/Idle State This is a controller state between scan operations. Once in this state, the controller remains in the state as long as J-TMS is held low. The 17 EXTEST Instruction: The EXTEST instruction allows testing of off-chip circuitry and boardlevel interconnect. EXTEST connects the BSR to the J-TDI and J-TDO pins. The normal path between the CS61583 logic and I/O pins is broken. The signals on the output pins are loaded from the BSR and the signals on the input pins are loaded into the BSR. SAMPLE/PRELOAD Instruction: The SAMPLE/PRELOAD instructions allows scanning of the boundary-scan register without interfering with the operation of the CS61583. This instruction connects the BSR to the J-TDI and J-TDO pins. The normal path between the CS61583 logic and its I/O pins is maintained. The signals on the I/O pins are loaded into the BSR. Additionally, this instruction can be used to latch values into the digital output pins. IDCODE Instruction: The IDCODE instruction connects the device identification register to the J-TDO pin. The IDCODE instruction is forced into the instruction register during the TestLog ic-Reset co ntroller state. The default instruction is IDCODE after a device reset. BYPASS Instruction: The BYPASS instruction connects the minimum length bypass register between the J-TDI and J-TDO pins and allows data to be shifted in the Shift-DR controller state. DS172PP5 CS61583 instruction register and all test data registers retain their previous state. When J-TMS is high and a rising edge is applied to J-TCK, the controller moves to the Select-DR state. Select-DR-Scan State This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If J-TMS is held low and a rising edge is applied to J-TCK when in this state, the controller moves into the CaptureDR state and a scan sequence for the selected test data register is initiated. If J-TMS is held high and a rising edge applied to J-TCK, the controller moves to the Select-IR-Scan state. The instruction does not change in this state. Capture-DR State In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD. The other test data registers, which do not have parallel input, are not changed. The instruction does not change in this state. When the TAP controller is in this state and a rising edge is applied to J-TCK, the controller enters the Exit1-DR state if J-TMS is high or the Shift-DR state if J-TMS is low. Shift-DR State In this controller state, the test data register connected between J-TDI and J-TDO as a result of the current instruction shifts data on stage toward its serial output on each rising edge of J-TCK. The instruction does not change in this state. When the TAP controller is in this state and a rising edge is applied to J-TCK, the controller enters the Exit1-DR state if J-TMS is high or remains in the Shift-DR state if J-TMS is low. Exit1-DR State This is a temporary state. While in this state, if J-TMS is held high, a rising edge applied to JTCK causes the controller to enter the Update-DR state, which terminates the scanning process. If J-TMS is held low and a rising edge is applied to J-TCK, the controller enters the Pause-DR state. 1 Test-Logic-Reset 0 1 1 1 1 0 Run-Test/Idle 1 Select-DR-Scan 0 Capture-DR 0 Select-IR-Scan 0 Capture-IR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 0 1 Exit2-DR 1 Update-DR 1 0 1 0 Shift-IR 1 Exit1-IR 0 1 0 0 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 Figure 12. TAP Controller State Diagram 18 DS172PP5 CS61583 The test data register selected by the current instruction retains its previous value during this state. The instruction does not change in this state. Pause-DR State The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between J-TDI and J-TDO. For example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test sequence. The test data register selected by the current instruction retains its previous value during this state. The instruction does not change in this state. The controller remains in this state as long as J-TMS is low. When J-TMS goes high and a rising edge is applied to J-TCK, the controller moves to the Exit2-DR state. Exit2-DR State This is a temporary state. While in this state, if J-TMS is held high, a rising edge applied to JTCK cau ses th e con troller to enter the Update-DR state, which terminates the scanning process. If J-TMS is held low and a rising edge is applied to J-TCK, the controller enters the Shift-DR state. The test data register selected by the current instruction retains its previous value during this state. The instruction does not change in this state. Update-DR State The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in response to the EXTEST and SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan Register is selected, data is latched into the DS172PP5 parallel output of this register from the shift-register path on the falling edge of J-TCK. The data held at the latched parallel output changes only in this state. All shift-register stages in the test data register selected by the current instruction retains their previous value during this state. The instructions does not change in this state. Select-IR-Scan State This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If J-TMS is held low and a rising edge is applied to J-TCK when in this state, the controller moves into the CaptureIR state, and a scan sequence for the instruction register is initiated. If J-TMS is held high and a rising edge is applied to J-TCK, the controller moves to the Test-Logic-Reset state. The instruction does not change in this state. Capture-IR State In this controller state, the shift register contained in the instruction register loads a fixed value of "01" on the rising edge of J-TCK. This supports fault-isolation of the board-level serial test data path. Data registers selected by the current instruction retain their value during this state. The instructions does not change in this state. When the controller is in this state and a rising edge is applied to J-TCK, the controller enters the Exit1-IR state if J-TMS is held high, or the Shift-IR state if J-TMS is held low. Shift-IR State In this state, the shift register contained in the instruction register is connected between J-TDI and J-TDO and shifts data one stage towards its serial output on each rising edge of J-TCK. 19 CS61583 The test data register selected by the current instruction retains its previous value during this state. The instruction does not change in this state. When the controller is in this state and a rising edge is applied to J-TCK, the controller enters the Exit1-IR state if J-TMS is held high, or remains in the Shift-IR state if J-TMS is held low. Exit1-IR State This is a temporary state. While in this state, if J-TMS is held high, a rising edge applied to JTCK causes the controller to enter the Update-IR state, which terminates the scanning process. If J-TMS is held low and a rising edge is applied to J-TCK, the controller enters the Pause-IR state. The test data register selected by the current instruction retains its previous value during this state. The instruction does not change in this state. Pause-IR State The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test data register selected by the current instruction retains its previous value during this state. The instruction does not change in this state. The controller remains in this state as long as J-TMS is low. When J-TMS goes high and a rising edge is applied to J-TCK, the controller moves to the Exit2-IR state. Exit2-IR State This is a temporary state. While in this state, if J-TMS is held high, a rising edge applied to JTCK causes the controller to enter the Update-IR state, which terminates the scanning process. If J-TMS is held low and a rising edge is applied to J-TCK, the controller enters the Shift-IR state. The test data register selected by the current instruction retains its previous value during this state. The instruction does not change in this state. Update-IR State The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of J-TCK. When the new instruction has been latched, it becomes the current instruction. Test data registers selected by the current instruction retain their previous value. JTAG Application Examples Figures 13 and 14 illustrate examples of updating the instruction and data registers during JTAG operation. 20 DS172PP5 CS61583 TCK TMS Test-Logic-Reset Select-DR-Scan Select-IR-Scan Run-Test/Idle Controller state TDI Parallel Input to IR IR shift-register Parallel output of IR Parallel Input to TDR Parallel output of TDR TDR shift-register Register selected TDO enable TDO = Don't care or undefined Inactive Act Instruction register Inactive Active Inactive Old data IDCODE New Instruction Figure 13. JTAG Instruction Register Update DS172PP5 Run-Test/Idle Capture-IR Update-IR Pouse-IR Exit1-IR Exit2-IR Exit1-IR Shift-IR Shift-IR 21 CS61583 TCK TMS Controller state TDI Parallel Input to IR IR shift-register Parallel output of IR Parallel Input to TDR TDR shift-register Parallel output of TDR Register Selected TDO enable TDO = Don't care or undefined Inactive Active Old data Test data register Inactive Active Inactive New data Instruction IDCODE Figure 14. JTAG Data Register Update 22 DS172PP5 Test-Logic-Reset Select-DR-Scan Select-DR-Scan Select-IR-Scan Run-Test/Idle Run-Test/Idle Capture-DR Update-DR Pouse-DR Exit1-DR Exit2-DR Exit1-DR Shift-DR Shift-DR CS61583 PIN DESCRIPTIONS DGND1 CON01 TAOS2 TAOS1 LLOOP2 LLOOP1 RLOOP1 ATTEN1 not used RCLK1 RPOS1/RDATA1 RNEG1/BPV1 TCLK1 TPOS1/TDATA1 TNEG1/AIS1 LOS1 J-TDO DGND2 J-TDI TTIP1 TV+1 TGND1 TRING1 CODER1 ATTEN0 not used RTIP1 RRING1 RV+1 RGND1 AGND1 BGREF AGND2 AV+ 25 19 21 23 13 15 17 68-Pin PLCC Top View CS61583 53 51 49 47 45 11 9 7 5 3 1 67 65 63 61 59 57 55 DV+ DGND3 CON02 CON11 CON12 CON21 CON22 AMI1 not used RCLK2 RPOS2/RDATA2 RNEG2/BPV2 TCLK2 TPOS2/TDATA2 TNEG2/AIS2 LOS2 AMI2 J-TCK J-TMS TTIP2 TV+2 TGND2 TRING2 CODER2 CLKE not used RTIP2 RRING2 RV+2 RGND2 1XCLK RLOOP2 REFCLK RESET 27 29 31 33 35 37 39 41 43 Note: Pins labeled as "not used" should be tied to ground. DS172PP5 23 CS61583 DGND1 CON01 TAOS2 TAOS1 LLOOP2 LLOOP1 RLOOP1 ATTEN1 RCLK1 RPOS1/RDATA1 RNEG1/BPV1 TCLK1 TPOS1/TDATA1 TNEG1/AIS1 LOS1 J-TDO DGND2 J-TDI TTIP1 TV+1 TGND1 TRING1 CODER1 ATTEN0 RTIP1 RRING1 RV+1 RGND1 AGND1 BGREF AGND2 AV+ 64 1 2 4 6 8 10 62 60 58 56 54 52 50 48 46 44 CS61583 42 64-Pin TQFP Top View 40 38 36 34 18 20 22 24 26 28 30 32 12 14 16 DV+ DGND3 CON02 CON11 CON12 CON21 CON22 AMI1 RCLK2 RPOS2/RDATA2 RNEG2/BPV2 TCLK2 TPOS2/TDATA2 TNEG2/AIS2 LOS2 AMI2 J-TCK J-TMS TTIP2 TV+2 TGND2 TRING2 CODER2 CLKE RTIP2 RRING2 RV+2 RGND2 1XCLK RLOOP2 REFCLK RESET 24 DS172PP5 CS61583 Power Supplies AGND1, AGND2 : Analog Ground (PLCC pins 31, 33; TQFP pins 21, 23) Analog supply ground pins. AV+ : Analog Power Supply (PLCC pin 34; TQFP pin 24) Analog supply pin for the internal bandgap reference and timing generation circuits. BGREF : Bandgap Reference (PLCC pin 32; TQFP pin 22) This pin is used by the internal bandgap reference and must be connected to ground by a 4.99kΩ ±1% resistor to provide an internal current reference. DGND1, DGND2, DGND3 : Digital Ground (PLCC pins 1, 18, 67; TQFP pins 57, 9, 55) Power supply ground pins for the digital circuitry of both channels. DV+ : Power Supply (PLCC pin 68; TQFP pin 56) Power supply pin for the digital circuitry of both channels. RGND1, RGND2 : Receiver Ground (PLCC pins 30, 39; TQFP pins 20, 29) Power supply ground pins for the receiver circuitry. RV+1, RV+2 : Receiver Power Supply (PLCC pins 29, 40; TQFP pins 19, 30) Power supply pins for the analog receiver circuitry. TGND1, TGND2 : Transmit Ground (PLCC pins 22, 47; TQFP pins 13, 36) Power supply ground pins for the transmitter circuitry. TV+1, TV+2 : Transmit Power Supply (PLCC pins 21, 48; TQFP pins 12, 37) Power supply pins for the analog transmitter circuitry. T1/E1 Data RCLK1, RCLK2 : Receive Clock (PLCC pins 10, 59; TQFP pins 1, 48) RPOS1, RPOS2 : Receive Positive Data (PLCC pins 11, 58; TQFP pins 2, 47) RNEG1, RNEG2 : Receive Negative Data (PLCC pins 12, 57; TQFP pins 3, 46) The receiver recovered clock and NRZ digital data from RTIP and RRING is output on these pins. The CLKE pin determines the clock edge on which RPOS and RNEG are stable and valid. A positive pulse (with respect to ground) received on RTIP generates a logic 1 on RPOS, and a positive pulse received on RRING generates a logic 1 on RNEG. RDATA1, RDATA2 : Receive Data (PLCC pins 11, 58; TQFP pins 2, 47) In coder mode (CODER = 1), the decoded digital data stream from RTIP and RRING is output on RDATA in NRZ format. The CLKE pin determines the clock edge on which RDATA is stable and valid. RTIP1, RTIP2 : Receive Tip (PLCC pins 27, 42; TQFP pins 17, 32) RRING1, RRING2 : Receive Ring (PLCC pins 28, 41; TQFP pins 18, 31) The receive AMI signal from the line interface is input on these pins. The recovered clock and data are output on RCLK, RPOS, and RNEG (or RDATA). DS172PP5 25 CS61583 TCLK1, TCLK2 : Transmit Clock (PLCC pins 13, 56; TQFP pins 4, 45) TPOS1, TPOS2 : Transmit Positive Data (PLCC pins 14, 55; TQFP pins 5, 44) TNEG1, TNEG2 : Transmit Negative Data (PLCC pins 15, 54; TQFP pins 6, 43) The transmit clock and data are input to these pins. The signal is driven to the line interface at TTIP and TRING. Data at TPOS and TNEG are sampled on the falling edge of TCLK. An input at TPOS causes a positive pulse to be transmitted at TTIP and TRING, while an input at TNEG causes a negative pulse to be transmitted at TTIP and TRING. TDATA1, TDATA2 : Transmit Positive Data (PLCC pins 14, 55; TQFP pins 5, 44) In coder mode (CODER = 1), the un-encoded digital data stream is input on TDATA in NRZ format. Data at TDATA is sampled on the falling edge of TCLK. TTIP1, TTIP2 : Transmit Tip (PLCC pins 20, 49; TQFP pins 11, 38) TRING1, TRING2 : Transmit Ring (PLCC pins 23, 46; TQFP pins 14, 35) The transmit AMI signal to the line interface is output on these pins. The transmit clock and data are input from TCLK, TPOS, and TNEG (or TDATA). Oscillator 1XCLK : One-times Clock Frequency Select (PLCC pin 38; TQFP pin 28) When 1XCLK is set high, REFCLK must be a 1X clock (i.e., 1.544 MHz for T1 or 2.048 MHz for E1 applications). When 1XCLK is set low, REFCLK must be an 8X clock (i.e., 12.352 MHz for T1 or 16.384 MHz for E1 applications). REFCLK : External Reference Clock Input (PLCC pin 36, TQFP pin 26) Input reference clock for the receive and jitter attenuator circuits. When 1XCLK is high, REFCLK must be a 1X clock (i.e., 1.544 MHz ±100 ppm for T1 applications or 2.048 MHz ±100 ppm for E1 applications). When 1XCLK is set low, REFCLK must be an 8X clock (i.e., 12.352 MHz ±100 ppm for T1 applications or 16.384 MHz ±100 ppm for E1 applications). The REFCLK input also determines the transmission rate when TAOS is asserted. Control AMI1, AMI2 : Encoder/Decoder Select (PLCC pins 61, 52; TQFP pins 49, 41) Setting AMI low enables the B8ZS or HDB3 zero substitution in the transmitter encoders and receiver decoders. Setting AMI high enables AMI encoders and decoders. The AMI pins are enabled by setting the corresponding CODER pin high. ATTEN0, ATTEN1 : Jitter Attenuator Select (PLCC pins 25, 8; TQFP pins 16, 64) Selects the jitter attenuation path for both channels (transmit/receive/neither). CLKE : Clock Edge (PLCC pin 44; TQFP pin 33) Controls the polarity of the recovered clock RCLK. When CLKE is high, RPOS and RNEG are valid on the falling edge of RCLK. When CLKE is low, RPOS and RNEG are valid on the rising edge of RCLK. 26 DS172PP5 CS61583 CODER1, CODER2 : Coder Mode Configuration (PLCC pins 24, 45; TQFP pins 15, 34) Setting CODER high causes the Coder Mode to be enabled. In Coder Mode, the transmit and receive data appears in NRZ format on TDATA and RDATA, respectively. These pins also enable the corresponding AMI pin. CON01, CON11, CON21, : Configuration Selection CON02, CON12, CON22 : (PLCC pins 2, 65, 63, 66, 64, 62; TQFP pins 58, 53, 51, 54, 52, 50) These pins configure the transmitter (pulse shape, pulse width, pulse amplitude, and driver impedance) receiver (slicing level), and coder (HDB3 vs B8ZS). The CONx1 pins control channel 1 and the CONx2 pins control channel 2. Both channels must be configured to operate at the same data rate on the line interface (both T1 or both E1). LLOOP1, LLOOP2 : Local Loopback (PLCC pins 6, 5; TQFP pins 62, 61) A local loopback is enabled when LLOOP is high. During local loopback, the TCLK, TPOS/TNEG (or TDATA) inputs are looped back through the jitter attenuator (if enabled) to the RCLK, RPOS/RNEG (or RDATA) outputs. The data at TPOS/TNEG continues to be transmitted to the line interface unless overridden by a TAOS request. The inputs at RTIP and RRING are ignored. RESET : Reset (PLCC pin 35; TQFP pin 25) A device reset is selected by setting the RESET pin high for a minimum of 200 ns. The reset function initiates on the falling edge of RESET and requires less than 20 ms to complete. The control logic is initialized and LOS is set high. RLOOP1, RLOOP2 : Remote Loopback (PLCC pins 7, 37; TQFP pins 63, 27) A remote loopback is selected when RLOOP is high. The data received from the line interface at RTIP and RRING is looped back through the jitter attenuator (if enabled) and retransmitted on TTIP and TRING. Data recovered from RTIP and RRING continues to be transmitted on RPOS/RNEG (or RDATA). Data input on TPOS/TNEG (or TDATA) is ignored. A TAOS request overrides the data transmitted at TTIP and TRING. TAOS1, TAOS2 : Transmit All Ones Select (PLCC pins 4, 3; TQFP pins 60, 59) Setting TAOS high causes continuous ones to be transmitted at the line interface on TTIP and TRING at the frequency determined by REFCLK. Status AIS1, AIS2 : Alarm Indication Signal (PLCC pins 15, 54; TQFP pins 6, 43) The AIS indication goes high when the receiver detects 99.9% ones density in a 5.3 ms period (< 9 zeros in 8192 bits). The AIS indication returns low when the receiver detects ≥ 9 zeros in 8192 bits. BPV1, BPV2 : Bipolar Violation (PLCC pins 12, 57; TQFP pins 3, 46) The BPV indication goes high for one RCLK bit period when a bipolar violation is detected in the received signal. Bipolar violations caused by B8ZS (or HDB3) zero substitutions are not flagged by the BPV pin if the coder mode is enabled. DS172PP5 27 CS61583 LOS1, LOS2 : Loss of Signal (PLCC pins 16, 53; TQFP pins 7, 42) The LOS indication goes high when 175 ± 15 consecutive zeros are received on the line interface. The LOS indication returns low when a minimum 12.5% ones density signal over 175 ± 75 bit periods with no more than 100 consecutive zeros is received. Test J-TCK : JTAG Test Clock (PLCC pin 51; TQFP pin 40) Data on pins J-TDI and J-TDO is valid on the rising edge of J-TCK. When J-TCK is stopped low, all JTAG registers remain unchanged. J-TMS : JTAG Test Mode Select (PLCC pin 50; TQFP pin 39) An active high signal on J-TMS enables the JTAG serial port. This pin has an internal pull-up resistor. J-TDI : JTAG Test Data In (PLCC pin 19; TQFP pin 10) JTAG data is shifted into the device on this pin. This pin has an internal pull-up resistor. Data must be stable on the rising edge of J-TCK. J-TDO : JTAG Test Data Out (PLCC pin 17; TQFP pin 8) JTAG data is shifted out of the device on this pin. This pin is active only when JTAG testing is in progress. J-TDO will be updated on the falling edge of J-TCK. 28 DS172PP5 CS61583 PHYSICAL DIMENSIONS DIM A A1 B D D1 E E1 e u x y z 68 pin PLCC MILLIMETERS INCHES MIN MAX MIN MAX 4.20 5.08 .165 .200 2.29 0.38 24.79 24.13 24.79 24.13 1.27 23.37 1.067 23.62 1.219 .51 .51 x 45° x 3 3.30 0.53 25.30 24.38 25.30 24.38 .090 .015 .976 .950 .976 .950 .050 .920 .042 .930 .048 .020 .02 x 45° x 3 A y A1 z D1 D x .130 .021 .996 .960 .996 .960 68 pin PLCC E1 E e u B DS172PP5 29 CS61583 D D1 64-Pin TQFP MILLIMETERS DIM A A1 B C D D1 E E1 MIN 0.00 0.14 0.077 11.70 10.00 11.70 10.00 0.40 0.35 0° MAX 1.66 0.26 0.177 12.30 10.00 12.30 10.00 0.60 0.70 12° INCHES MIN 0.00 0.006 0.003 0.461 0.394 0.461 0.394 0.016 0.014 0° MAX 0.068 0.010 0.007 0.484 0.394 0.484 0.394 0.024 0.028 12° E E1 64 1 e L ∝ A1 B e A C Terminal Detail 1 L ∝ 30 DS172PP5 CS61583 APPLICATIONS CLKE ATTEN2 AMI1 CON11 TAOS1 RLOOP1 AMI2 CON12 TAOS2 RLOOP2 REFCLK 1XCLK RESET Clock Generator TCLK1 TPOS1 (TDATA1) TNEG1 (AIS1) RCLK1 RPOS1 (RDATA1) RNEG1 (BPV1) TCLK2 TPOS2 (TDATA2) TNEG2 (AIS2) RCLK2 RPOS2 (RDATA2) RNEG2 (BPV2) ATTEN1 CODER1 CON01 CON21 LLOOP1 CODER2 CON02 CON22 LLOOP2 Hardware Control TTIP1 TRING1 Channel 1 RTIP1 0.47µF R1 T1 1:1.15 C1 T2 1:1.15 transmit Framer 0.47µF receive RRING1 TTIP2 TRING2 Channel 2 RTIP2 R2 0.47µF R3 T3 1:1.15 C2 T4 1:1.15 transmit Framer 0.47µF receive RRING2 R4 Power Supply AV+ AGND1:2 BGREF TGND2 TV+2 TV+1 TGND1 RGND2 RV+2 RV+1 RGND1 DV+ DGND1:3 0.1 µF 2 3 R3 0.1 µF 4.99kΩ 0.1 µF 0.1 µF 0.1 µF 0.01 µF + + 1 µF 22 µF VCC Figure A1. Typical Connection Diagram Data Rate (MHz) REFCLK Frequency (MHz) 1XCLK = 1 1XCLK = 0 Cable (Ω) R1-R4 (Ω) C1-C2 (pF) 1.544 2.048 1.544 2.048 12.352 16.384 100 75 120 38.3 28.7 45.3 220 470 220 Table A1. CS61583 External Components Line Interface Figure A1 illustrates a typical connection diagram and Table A1 lists the external components that are required in T1 and E1 applications. In the transmit line interface circuitry, capacitors C1 and C2 provide transmitter return loss. The 0.47 µF capacitor in series with the transformer primary prevents output stage imbalances from producing a DC current through the transformer that might saturate the transformer and result in an output level offset. In the receive line interface circuitry, resistors R1R4 provide receive impedance matching and receiver return loss. The 0.47 µF capacitor to ground provides the necessary differential input voltage reference for the receiver. Power Supply As shown in Figure A1, the CS61583 operates from a 5.0 Volt supply. Separate analog and digital power supply and ground pins provide internal isolation. The TGND, RGND, and DGND ground pins must not be more negative than AGND. It is recommended that all of the supply pins be connected together at the device. A 4.99kΩ ±1% 31 DS172PP5 CS61583 r esistor must be connected from BGREF to ground to provide an internal current reference. De-coupling and filtering of the power supplies is crucial for the proper operation of the analog circuits. A capacitor should be connected between each supply and its respective ground. For capacitors smaller than 1 µF, use mylar or ceramic capacitors and place them as close as possible to their respective power supply pins. Wire-wrap bread boarding of the line interface is not recommended because lead resistance and inductance defeat the function of the de-coupling capacitors. Crystal Oscillator Specifications Turns Ratio Primary inductance Primary leakage inductance Secondary leakage inductance Interwinding capacitance ET-constant 1:1.15 step-up transmit 1:1.15 step-down receive 1.5 mH min at 772 kHz 0.3 µH max at 772 kHz with secondary shorted 0.4 µH max at 772 kHz 18 pF max, primary to secondary 16 V-µs min Table A3. Transformer Specifications Designing for AT&T 62411 When a reference clock signal is not available, a CMOS crystal oscillator operating at either the 1X or 8X rate can be connected at the REFCLK pin. The oscillator must have a minimum symmetry of 40-60% and minimum stability of ±100 ppm for T1 and E1 applications. Based on these specifications, some suggested crystal oscillators for use with the CS61583 are shown in Table A2. Manufacturer Part Number Contact Number For additional information on the requirements of AT&T 62411 and the design of an appropriate system synchronizer, refer to the Crystal Semiconductor Application Notes "AT&T 62411 Design Considerations - Jitter and Synchronization" and "Jitter Testing Procedures for Compliance with AT&T 62411." Line Protection Secondary protection components can be added to the line interface circuitry to provide lightning surge and AC power-cross immunity. For additional information on the different electrical safety standards and specific application circuit recommendations, refer to the Crystal Semiconductor Application Note "Secondary Line Protection for T1 and E1 Line Cards." Comclok CTS M-tron SaRonix CT31CH CXO-65HG-5-I MH26TAD NTH250A (800) 333-9825 (815) 786-8411 (800) 762-8800 (800) 227-8974 Notes: Frequency tolerances are ±32 ppm with a -40 to +85 °C operating temperature range. All are 8-pin DIP packages and can be tristated. Table A2. Suggested Crystal Oscillators Transformers Recommended transformer specifications are shown in Table A3. Based on these specifications, the transformers recommended for use with the CS61583 are listed in Table A4. 32 DS172PP5 CS61583 Turns Ratio Manufacturer Part Number Package Type PE-65388 PE-65770 PE-65838 1:1.15 Pulse Engineering PE-68674 PE-65870 67124840 ST5112 Schott Valor 1.5 kV through-hole, single 1.5 kV through-hole, single extended temperature 3.0 kV through-hole, single extended temperature 1.5 kV surface-mount, dual extended temperature 1.5 kV surface-mount, dual 1.5 kV through-hole, single extended temperature 2.0 kV surface mount, dual Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering. Call: (512) 445-7222 DS172PP5 33 CDB61583 Dual Line Interface Evaluation Board Features General Description The evaluation board includes a socketed CS61583 dual line interface device and all support components necessary for evaluation. The board is powered by an external +5 Volt supply. The board may be configured for 100Ω twisted-pair T1, 75Ω coax E1, or 120Ω twisted-pair E1 operation. Binding posts and bantam jacks are provided for line interface connections. Several BNC connectors provide clock and data I/O at the system interface. Reference timing may be derived from a crystal oscillator or an external reference clock. Four LED indicators monitor device alarm conditions. ORDERING INFORMATION: CDB61583 +5V 0V • Socketed CS61583 Dual Line Interface • All Required Components for CS61583 Evaluation • Locations to Evaluate Protection Circuitry • LED Status Indications for Alarm Conditions • Control of Enhanced Hardware Options CHANNEL 1 { { TCLK1 TTIP1 TPOS1 (TDATA1) TNEG1 RCLK1 TRING1 RTIP1 RPOS1 (RDATA1) RNEG1 (BPV1) RRING1 } } CHANNEL 1 +5V Hardware Control and Mode Circuit LED Status Indicators RESET CIRCUIT REFCLK CS61583 Oscillator Circuit TCLK2 TTIP2 TPOS2 (TDATA2) TNEG2 RCLK2 TRING2 RTIP2 CHANNEL 2 CHANNEL 2 RPOS2 (RDATA2) RNEG2 (BPV2) RRING2 Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445 7581 Copyright © Crystal Semiconductor Corporation 1995 (All Rights Reserved) DEC ’95 DB172PP1 34 CDB61583 POWER SUPPLY As shown on the evaluation board schematic in Figures 1-5, power is supplied to the board from an external +5 Volt supply connected to the two binding posts labeled V+ and GND. Zener diode Z1 protects the components on the board from reversed supply connections and over-voltage damage. Capacitor C16 provides power supply decoupling and ferrite bead L1 isolates the CS61583 and buffer supplies. Both sides of the evaluation board contain extensive areas of ground plane to insure optimum performance. Capacitors C3, C5-C8, C13, C18, and C38 provide power supply decoupling for the CS61583. The BGREF pin is pulled down through resistor R10 to provide an internal current reference. The buffers are decoupled using capacitors C9, C15, and C19. Ferrite beads L2-L4 help reduce the power supply noise that is coupled from the buffers to the power supply. BOARD CONFIGURATION The evaluation board is based on the CDB61584 used to evaluate the CS61584 dual LIU optimized for Host mode applications. Because the CS61583 is optimized for Hardware mode applications, slide switch SW6 must be placed in the "HW" position to set the AGND1 pin of the CS61583 to a logic 0. In addition, the host processor interface appearing at J26 is not used on the CDB61583. The evaluation board is configured using DIP switches SW2, SW3, and SW4. Because the evaluation board is based on the CDB61584 design, switches SW2, SW3, and SW4 are relabeled with white stickers. These switches establish the digital control inputs for both line interface channels. Closing a DIP switch towards the label sets the CS61583 control pin of the same name to a logic 1. All switch inputs are pulled-down using resistor networks RP2-RP5. The CDB61583 switch functions are listed below: • TAOS1, TAOS2: transmit all ones; • LLOOP1, LLOOP2: local loopback; • RLOOP1, RLOOP2: remote loopback; • CODER1, CODER2: encoder/decoder control; • ATTEN0, ATTEN1: jitter attenuator selection; • CLKE: RCLK edge polarity; • 1XCLK: clock frequency selection; • AMI1, AMI2: encoder/decoder control; • CONx1, CONx2: line configuration settings. A jumper must be installed on header J10 to enable RLOOP2 functionality. Alarm Indications The LOS1 and LOS2 LED indicators illuminate when the line interface receiver has detected a loss of signal. Headers J7 and J13 must be jumpered in the "TNEG" position to provide connectivity to the BNC input when the coder mode is disabled (CODER(1,2) = 0). The AIS alarm condition is provided when the coder mode is enabled (CODER(1,2) = 1) and headers J7 and J13 are jumpered in the "AIS" position. The AIS1 and AIS2 LED indicators illuminate when the line interface receiver has detected the all-ones receive input signal. Resistors R26 and R27 pull-down the TNEG(1,2) inputs when coder mode is disabled but headers J7 and J13 are jumpered in the "AIS" position. Manual Reset A momentary contact switch SW1 provides a manual reset by forcing the RESET pin of the CS61583 to a logic 1. Although the transmit and receive circuitry are continuously calibrated, the DB172PP1 35 CDB61583 reset can be used to initialize the control logic. Both channels are powered up after exiting reset. TRANSMIT CIRCUIT The transmit clock and data signals are supplied on BNC inputs labeled TCLK(1,2), TPOS(1,2), and TNEG(1,2). When the coder mode is disabled, data is supplied on the TPOS(1,2) and TNEG(1,2) BNC inputs in RZ format. When the coder mode enabled, data is supplied on the TDATA(1,2) BNC input in NRZ format and the TNEG(1,2) BNC input may be used to indicate the AIS alarm condition as described in the Board Configuration section. The transmitter output is transformer coupled to the line interface through 1:1.15 step-up transformers T1 and T4. The signal is available at either the TTIP(1,2) and TRING(1,2) binding posts or the TX(1,2) bantam jacks. Capacitors C2 and C11 prevent output stage imbalances from producing a DC current that may saturate the transformer and result in an output level offset. Capacitors C1 and C12 provide transmitter return loss and are socketed so the value may be changed according to the application. A 220 pF capacitor is required for 100Ω twisted-pair T1 or 120Ω twisted-pair E1 applications. A 470 pF capacitor is required for 75Ω coax E1 applications. These capacitors are included with the evaluation board. Optional diode locations D6-D9 and D10-D13 and optional resistor locations R8-R9 and R18-R19 provide test locations to evaluate transmit line interface protection circuitry. RECEIVE CIRCUIT The receive signal is input at either the RTIP(1,2) and RRING(1,2) binding posts or the RX(1,2) bantam jacks. The receive signal is transformer coupled to the CS61583 through 1:1.15 step-down transformers T2 and T3. The receive line is terminated by resistors R3-R4 and R14-R15 to provide impedance matching and receiver return loss. They are socketed so the values may be changed according to the application. The evaluation board is supplied from the factory with 38.3Ω resistors for terminating 100Ω twisted-pair T1 lines, 45.3Ω resistors for terminating 120Ω twisted-pair E1 lines, and 28.7Ω resistors for terminating 75Ω coaxial E1 lines. Capacitors C4 and C10 provide a differential input voltage reference. Optional resistor locations R1-R2, R12-R13, R16-R17, and R24-R25 provide test locations to evaluate receive line interface protection circuitry. The recovered clock and data signals are available on BNC outputs labeled RCLK(1,2), RPOS(1,2), and RNEG(1,2). When the coder mode is disabled, data is available on the RPOS(1,2) and RNEG(1,2) BNC outputs in RZ format. When the coder mode is enabled, data is available on the RDATA(1,2) BNC output in NRZ format and bipolar violations are reported on BPV(1,2). REFERENCE CLOCK The CDB61583 requires a T1 or E1 reference clock for operation. This clock may operate at either a 1-X rate (1.544 MHz or 2.048 MHz) or an 8-X rate (12.352 MHz or 16.384 MHz) and can be supplied by either a crystal oscillator or an external reference. The evaluation board is supplied from the factory with two crystal oscillators for T1 and E1 operation. 36 DB172PP1 CDB61583 Crystal Oscillator A crystal oscillator may be inserted at socket U4 in the orientation indicated by the silkscreen. Header J14 must be jumpered in the "OSC" position to provide connectivity to the REFCLK pin of the CS61583. The SW2 switch position labeled "1XCLK" must be open (logic 0) for 8-X clock operation or closed (logic 1) for 1-X clock operation. External Reference An external reference may be provided at the REFCLK BNC input. Header J14 must be jumpered in the "REFCLK" position to provide connectivity to the REFCLK pin of the CS61583. The SW2 switch position labeled "1XCLK" must be open (logic 0) for 8-X clock operation or closed (logic 1) for 1-X clock operation. BUFFERING Buffers U2 and U3 provide additional drive capability for the BNC inputs and outputs. The buffer outputs are filtered with an RC network to reduce the transients caused by buffer switching. JTAG ACCESS The CS61583 implements JTAG boundary scan to support board-level testing. Interface port J56 provides access to the four JTAG pins on the CS61583. The J-TMS pin of the CS61583 is pulled-down by resistor R28 to disable boundary scan unless the pin is externally pulled high using the interface port. TRANSFORMER SELECTION The evaluation board is supplied from the factory with Pulse Engineering PE-65388 transformers installed at locations T1-T4. They are socketed to permit the evaluation of other transformers. LINE PROTECTION EVALUATION Several optional resistor and diode locations on the transmit and receive line interface allow for the installation and evaluation of various types of protection circuitry. Each location is drilled with 60 mil vias to permit the installation of sockets. These sockets can be obtained from McKenzie at (510) 651-2700 by requesting part #PPC-SIP-1X32-620C and are identical to the socket type installed at various resistor locations on the board. They allow the line protection circuitry to be easily changed during testing. Note that the traces forming shorts between the socket locations on the line interface may need to be cut prior to protection circuitry installation. PROTOTYPING AREA Four prototyping areas with power supply and ground connections are provided on the evaluation board. These areas can be used to develop and test a variety of additional circuits such as framer devices, system synchronizer PLLs, or specialized interface logic. EVALUATION HINTS 1. The orientation of pin 1 for the CS61583 is labeled "1" on the left side of the socket U7. 2. A jumper must be placed on header J10 when using the CDB61583. 3. Component locations R3-R4, R14-R15, C1, and C12 must have the correct values installed according to the application. All the necessary components are included with the evaluation board. DB172PP1 37 CDB61583 4. Closing a DIP switch on SW2, SW3, and SW4 towards the label sets the CS61583 control pin of the same name to logic 1. 5. When performing a manual loopback of the recovered signal to the transmit signal at the BNC connectors, the recovered data must be valid on the falling edge of RCLK to properly latch the data in the transmit direction. To accomplish this, the SW2 switch position labeled "CLKE" must be closed (logic 1). 6. Jumpers can be placed on headers J9 and J12 to provide a ground reference on TRING for 75Ω coax E1 applications. 7. Properly terminate TTIP/TRING when evaluating the transmit output pulse shape. For more information concerning pulse shape evaluation, refer to the Crystal application note entitled "Measurement and Evaluation of Pulse Shapes in T1/E1 Transmission Systems." 38 DB172PP1 CDB61583 VA+ J1 R29 R C LK 1 5 1 .1 J2 RPOS1 (R D A T A 1 ) J3 R 31 RNEG1 (B P V 1 ) J4 T C LK 1 J5 TPOS (T D A T A 1) J6 TNEG 8 6 4 5 1 .1 7 R30 5 1 .1 5 U2 C27 1 0 0p F U2 C28 1 00 p F 16 U2 C 29 10 0 p F 14 U2 C30 100pF 12 C31 1 00 p F VA+ 3 2 Q1 U2 1 3 LOS1 D2 LED R7 470 VD+ T T IP 1 R8 R9 T1 D10 2 VD+ D 12 D13 R T IP 1 J3 3 T R R R IN G 1 J3 4 J8B 6 9 R24 T2 R1 D 11 C1 Q2 1 VA+ 2 R5 5 1.1 1 3 J7 VD+ R 26 47 K C3 .1 µF CODER1 ATTEN0 2 4 J-T D O J-T D I 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 13 3 U2 C 26 1 0 0 pF 15 17 L4 C9 .1 µF 20 10 VCC 1 U2 19 GND ENA ENA U7 CS61583 CHANNEL 1 RCLK1 RPOS1 RNEG1 TCLK1 TPOS1 TNEG1 LOS1 J -T D O DGND2 J -T D I T T IP 1 TV+1 TG ND1 T R IN G 1 CO DER1 ATTEN0 N /C -1 R38 R39 5 1 .1 5 1 .1 A IS 1 D1 LED R6 470 J3 1 T R J8A 1 4 1 3 27 R T IP 1 28 R R IN G 1 T R IN G 1 J32 J9 6 1.15 :1 P E -6 5 3 88 5 TV+1 C2 .4 7 µF 1 3 2 R25 6 1 .1 5 :1 P E -6 5 3 8 8 5 R2 R4 R3 C4 .4 7 µF N otes: C om pon ents R 3, R 4, and C 1 are soc keted to perm it v alue change s to the ap plicatio n. C om po nent loc ations R 1, R 2, R 8, R 9 , R 24, R 25, an d D 10-D 13 provide areas for eva luatin g protection circu itry. Figure 1. Channel 1 Circuitry DB172PP1 39 CDB61583 VA+ 11 L2 U3 9 C 32 1 00pF 7 U3 C 15 .1 µF 15 5 U3 C 34 100pF 14 U7 C S 61583 C HANN EL 2 100pF N /C -3 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 16 6 C 33 100pF J16 R 41 R C LK 2 51.1 J1 7 R 42 5 1.1 J18 R 43 51 .1 J19 U3 C 35 T C LK 2 J20 U3 C 36 1 00pF 4 TPOS2 (T D A T A 2) J21 2 TNEG2 RNEG2 (B P V 2) RPOS2 (R D A T A 2) ENA VCC 1 20 E N A 19 U 3 10 GND 13 RCLK2 RPOS2 RNEG2 TCLK2 TPOS2 TNEG 2 LO S 2 A M I2 J-T C K J-T M S T T IP 2 TV+2 TGND2 T R IN G 2 CODER2 C LK E 41 R R IN G 2 42 R T IP 2 43 N /C -2 R 50 R 51 51 .1 51 .1 1 3 A M I2 J-T C K J-T M S R 28 J13 VD+ C 13 .1 µF CODER2 C LK E VD+ D6 2 VD+ D7 D8 6 2 R 27 47K 2 R 22 4 5 1.1 18 U3 C 37 10 0pF VA+ 3 2 Q3 1 R 20 470 3 Q4 LO S 2 D4 LE D R 21 470 A IS 2 D3 LE D 10K VA+ 1 T4 1 3 R 18 R 19 6 J11B 9 J27 T R J28 T T IP 2 C 12 T V +1 C 38 22 µF C 11 .47 µF 5 1:1.15 P E -65388 T R IN G 2 J12 R T IP 2 D9 R 12 2 T3 1 3 R 13 R 14 R 15 6 5 R17 4 R R R IN G 2 R16 1 J11A J29 T 1:1.15 P E -65388 J30 C 10 .47 µF N otes: C om po nents R 14, R 15, an d C 12 a re socketed to perm it value changes accordin g to th e application. C om ponent locations R 12, R 13, R 16-R 1 9, and D 6-D 9 provide area s for evaluatin g p rotection circuitry. Figure 2. Channel 2 Circuitry 40 DB172PP1 CDB61583 VD+ J2 4 R 55 3 .9 2 k CS SD1 SCLK SD 0 25 IN T 2 3 21 19 17 15 13 11 9 7 5 3 1 J26 26 24 22 20 18 16 14 12 10 8 6 4 2 R56 5 1 .1 R 40 5 1 .1 100 pF C25 9 U6 GND 11 RP2 6 543 2 1 47k SW 3 1 8 2 7 3 6 4 5 VD+ 100 pF 7 C 39 U6 13 GND J -T D 0 J -T D 1 J -T M S T -T C K 1 3 5 7 J5 6 2 4 6 8 VD+ SW 2 24 23 22 21 20 19 18 17 16 15 14 13 TAOS2 TAOS1 L LO O P 2 L LO O P 1 RLO OP1 CO DER1 CO DER2 ATTEN0 ATTEN1 CLKE 1 X C LK RLO OP2 8 7 6 5 4 32 1 2 3 4 5 6 7 8 9 10 11 12 C O N 01 C O N 11 C O N 21 A M I1 CODER1 CODER2 ATTEN0 C LKE 1 X C LK R LO O P 2 1 RP5 47 k 65432 GND RP3 6 U6 100pF C20 R57 5 1 .1 14 2 U6 4 U6 C24 100pF VD+ .0 1 µF C 18 A M I2 SW 4 C O N02 1 8 C O N12 2 7 C O N22 3 6 A M I2 4 5 8 7 6 5 4 32 1 RP4 47 k GND 1 47 k N ote: T he H ost interface at J26 is not used on the C D B 61583. Figure 3. Control Circuitry DB172PP1 ATTEN1 RLOO P1 LL O O P 1 LL O O P 2 TAO S1 TAO S2 CO N01 DGND1 DV+ DGND3 CO N02 CO N11 CO N12 CO N21 CO N22 A M I1 U7 CS61584 C ON TRO L C IR CU ITR Y N /C -4 9 8 7 6 5 4 3 5 1.1 R 5 9 2 1 68 67 66 65 64 63 62 61 18 100 16 pF C 23 5 1 .1 R 58 41 CDB61583 U7 CS61583 TIMING CIRCUITRY 29 R V +1 30 RGND1 31 AGND1 32 R 10 BGREF 4.99k 3 3 AGND2 34 AV+ 35 RESET 36 R E F C LK 37 R LO O P 2 1X C L K 38 1X C LK 39 RGND2 40 R V +2 C8 Y1 C6 C7 .1 µF 1 .0 µF .1 µF VD+ J 10 (m ust be jum pe red) VD+ SW 6 SW 1 2 R23 47 K VD+ VD+ VA+ U4 C 14 .1 µF VCC GND 8 J15 J14 1 3 REFCLK 2 4 1 R 11 10 K RLOO P2 C5 .1 µF VD+ N otes: A crystal o scillator at U 4 o r e xtern al refere nce sup plied a t J15 m ust be p rovided . A qu artz crystal cann ot b e use d w ith the C S 6 158 3 Figure 4. Timing Circuitry 42 DB172PP1 CDB61583 V+ J22 VA+ C 16 4 7 µF Z1 GND J23 VD+ L1 VD+ P rototyping A rea Figure 5. Common Circuitry DB172PP1 43 Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation