CS6422-CSZR

CS6422 CS6422 Enhanced Enhanced Full-Duplex Full-duplex Speakerphone Speakerphone IC IC Features General Description l Single-chip, Most modern speakerphones use half-duplex operation, which alternates transmission between the far-end talker and the speakerphone user. This is done to ensure stability because the acoustic coupling between the speaker and microphone is much higher in speakerphones than in handsets where the coupling is mechanically suppressed. full-duplex, hands-free operation l Optional Tx Noise Guard l Programmable attenuation during double-talk l Optional 34 dB microphone preamplifier l Dual channel AGC’ed volume controls with mute l Dual integrated 80 dB IDR codecs l Speech-trained Network and Acoustic Echo Cancellers l Rx and Tx supplementary echo suppression l Configurable half-duplex training mode l Powerdown mode l Microcontroller Interface NC1 NC2 NC3 9 10 11 RGain NI 17 ADC + + NC4 12 RVol ORDERING INFORMATION See page 48. CS6422-IS -40o to 85oC 20-pin SOIC CDB6422 Evaluation Board AVDD 16 1 Rx Suppression Σ 14 Pre-emphasis Filter NO Acoustic ASdt Sidetone (none, -24, -18, -12 dB) - TVol Σ + + 6 Preliminary Product Information P.O. Box 17847, Austin, Texas 78760 http://www.cirrus.com (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com CLKO 20 API TGain 18 ADC APO (0, 6, 9.5, 12 dB) Voltage Reference Microcontroller Interface 7 CLKI 34 dB (Mute, -12 to +30 dB) 8 Mic 13 AO 1 kΩ Tx Suppression DAC Clock Generation Acoustic Echo Canceller Pre-emphasis Filter 4 3 DAC - Network Echo Canceller Network Sidetone (none, -24, NSdt -18, -12 dB) The CS6422 consists of telephone & audio interfaces, two codecs and an echo-cancelling DSP. DVDD (Mute, -12 to +30 dB) (0, 6, 9.5, 12 dB) The CS6422 enables full-duplex conversation using echo cancellation and suppression in a single-chip solution. The CS6422 can easily replace existing half-duplex speakerphone ICs with a huge increase in conversation quality. 5 15 2 19 This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright  Cirrus Copyright © Cirrus Logic, Inc. 2005Logic, Inc. 2001 (All Rights Reserved) (All Rights Reserved) JUL ‘01 SEP ‘05 DS295PP4 DS295F1 1 CS6422 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5 RECOMMENDED OPERATING CONDITIONS ....................................................................... 5 POWER CONSUMPTION ........................................................................................................ 5 ANALOG CHARACTERISTICS ................................................................................................ 5 ANALOG TRANSMISSION CHARACTERISTICS.................................................................... 6 MICROPHONE AMPLIFIER ..................................................................................................... 6 DIGITAL CHARACTERISTICS ................................................................................................. 6 SWITCHING CHARACTERISTICS .......................................................................................... 7 2. OVERVIEW ............................................................................................................................... 9 3. FUNCTIONAL DESCRIPTION ................................................................................................. 9 3.1 Analog Interface ................................................................................................................. 9 3.1.1 Acoustic Interface ................................................................................................ 10 3.1.2 Network Interface ................................................................................................ 11 3.2 Microcontroller Interface .................................................................................................. 11 3.2.1 Description .......................................................................................................... 11 3.2.2 Register Definitions ............................................................................................. 12 3.3 Register 0 ......................................................................................................................... 13 3.3.1 Mic - Microphone Preamplifier Enable .................................................................... 14 3.3.2 HDD - Half-Duplex Disable...................................................................................... 14 3.3.3 GB - Graded Beta.................................................................................................... 14 3.3.4 RVol - Receive Volume Control............................................................................... 14 3.3.5 TSD - Transmit Suppression Disable ...................................................................... 14 3.3.6 ACC - Acoustic Coefficient Control ......................................................................... 15 3.3.7 TSMde - Transmit Suppression Mode..................................................................... 15 3.4 Register 1 ......................................................................................................................... 16 3.4.1 THDet - Transmit Half-Duplex Detection Threshold ................................................ 17 3.4.2 Taps - AEC/NEC Tap Allocation ............................................................................. 17 3.4.3 TVol - Transmit Volume Control .............................................................................. 17 3.4.4 RSD - Receive Suppression Disable....................................................................... 17 3.4.5 NCC - Network Coefficient Control.......................................................................... 17 3.4.6 AuNECD - Auto re-engage NEC Disable ................................................................ 17 3.5 Register 2 ......................................................................................................................... 18 3.5.1 RHDet - Receive Half-Duplex Detection Threshold ................................................ 19 3.5.2 RSThd - Receive Suppression Threshold ............................................................... 19 3.5.3 NseRmp - Noise estimator Ramp rate .................................................................... 19 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 DS295F1 CS6422 3.5.4 HDly - Half-Duplex Holdover Delay......................................................................... 19 3.5.5 HHold - Hold in Half-Duplex on Howl ...................................................................... 19 3.5.6 TDSRmp - Tx Double-talk Suppression Ramp rate ................................................ 19 3.5.7 RDSRmp - Rx Double-talk Suppression Ramp rate ............................................... 20 3.5.8 IdlTx - half-duplex Idle return-to-Transmit ............................................................... 20 3.6 Register 3 ......................................................................................................................... 21 3.6.1 TSAtt - Transmit Suppression Attenuation.............................................................. 22 3.6.2 PCSen- Path Change Sensitivity ............................................................................ 22 3.6.3 TDbtS - Tx Double-talk Suppression attenuation.................................................... 22 3.6.4 RDbtS - Rx Double-talk Suppression attenuation ................................................... 22 3.6.5 TSThd - Transmit Suppression Threshold .............................................................. 22 3.6.6 TSBias - Transmit Suppression Bias ...................................................................... 22 3.7 Register 4 ......................................................................................................................... 23 3.7.1 AErle - AEC Erle threshold...................................................................................... 24 3.7.2 AFNse - AEC Full-duplex Noise threshold .............................................................. 24 3.7.3 NErle - NEC Erle threshold ..................................................................................... 24 3.7.4 NFNse - NEC Full-duplex Noise threshold.............................................................. 24 3.7.5 RGain - Receive Analog Gain ................................................................................. 24 3.7.6 TGain - Transmit Analog Gain ................................................................................ 24 3.8 Register 5 ......................................................................................................................... 25 3.8.1 HwlD - Howl detector Disable ................................................................................. 26 3.8.2 TD - Tone detector Disable ..................................................................................... 26 3.8.3 APCD - Acoustic Path Change detector Disable .................................................... 26 3.8.4 NPCD - Network Path Change detector Disable..................................................... 26 3.8.5 APFD/NPFD - Acoustic Pre-emphasis Filter Disable/Network Pre-emphasis Filter Disable..................................................................................... 26 3.8.6 AECD - Acoustic Echo Canceller Disable ............................................................... 27 3.8.7 NECD - Network Echo Canceller Disable ............................................................... 27 3.8.8 ASdt - Acoustic Sidetone level ................................................................................ 27 3.8.9 NSdt - Network Sidetone level ................................................................................ 27 3.9 Reset ............................................................................................................................... 28 3.9.1 Cold Reset .......................................................................................................... 28 3.9.2 Warm Reset ........................................................................................................ 28 3.9.3 Reset Timer ........................................................................................................ 28 3.10 Clocking ......................................................................................................................... 28 3.11 Power Supply ................................................................................................................ 29 3.11.1 Power Down Mode ............................................................................................ 29 3.11.2 Noise and Grounding ........................................................................................ 29 4. DESIGN CONSIDERATIONS ................................................................................................. 31 4.1 Algorithmic Considerations .............................................................................................. 31 4.1.1 Full-Duplex Mode ................................................................................................ 31 4.1.1.1 Theory of Operation ........................................................................... 31 4.1.1.2 Adaptive Filter ..................................................................................... 32 4.1.1.2.1 Pre-Emphasis ............................................................................ 32 4.1.1.2.2 Graded Beta .............................................................................. 33 4.1.1.3 Update Control .................................................................................... 33 4.1.1.4 Speech Detection ................................................................................ 33 4.1.2 Half-Duplex Mode ............................................................................................... 34 4.1.2.1 Idle Return to Transmit ....................................................................... 34 4.1.3 AGC .................................................................................................................... 34 4.1.4 Suppression ........................................................................................................ 35 4.1.4.1 Transmit Suppression ......................................................................... 36 4.1.4.2 Receive Suppression .......................................................................... 36 DS295F1 3 CS6422 4.1.4.3 Double-talk Attenuation ....................................................................... 36 4.1.4.4 Noise Guard ........................................................................................ 37 4.2 Circuit Design ................................................................................................................... 37 4.2.1 Interface Considerations ..................................................................................... 37 4.2.1.1 Analog Interface .................................................................................. 37 4.2.1.2 Microcontroller Interface ...................................................................... 37 4.2.2 Grounding Considerations .................................................................................. 38 4.2.3 Layout Considerations ........................................................................................ 38 4.3 System Design ................................................................................................................. 38 4.3.1 Gain Structure ..................................................................................................... 38 4.3.2 Testing Issues ..................................................................................................... 39 4.3.2.1 ERLE ................................................................................................... 39 4.3.2.2 Convergence Time .............................................................................. 40 4.3.2.3 Half-Duplex Switching ......................................................................... 40 5. PIN DESCRIPTIONS .............................................................................................................. 41 6. GLOSSARY ............................................................................................................................ 44 7. PACKAGE DIMENSIONS ....................................................................................................... 46 LIST OF FIGURES Figure 1. CLKI Timing ................................................................................................................... 7 Figure 2. Reset Timing .................................................................................................................. 7 Figure 3. Microcontroller Interface Timing ..................................................................................... 7 Figure 4. Typical Connection Diagram (Microphone Preamplifier Enabled) ................................. 8 Figure 5. Typical Connection Diagram (Microphone Preamplifier Disabled) ................................ 8 Figure 6. Analog Interface ........................................................................................................... 10 Figure 7. Microcontroller Interface .............................................................................................. 12 Figure 8. Suggested Layout ........................................................................................................ 29 Figure 9. Ground Planes ............................................................................................................. 30 Figure 10. Simplified Acoustic Echo Canceller Block Diagram ................................................... 31 Figure 11. How the AGC works (TVol = +30 dB) ........................................................................ 35 LIST OF TABLES Table 1. Full scale voltages for each gain stage ........................................................................... 11 Table 2. MCR Control Register Mapping ...................................................................................... 12 Table 3. Register 0 Bit Definitions................................................................................................. 13 Table 4. Register 1 Bit Definitions................................................................................................. 16 Table 5. Register 2 Bit Definitions................................................................................................. 18 Table 6. Register 3 Bit Definitions................................................................................................. 21 Table 7. Register 4 Bit Definitions................................................................................................. 23 Table 8. Register 5 Bit Definitions................................................................................................. 25 4 DS295F1 CS6422 1. CHARACTERISTICS AND SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Units -0.3 6.0 V Iin -10 +10 mA Vina Vind -0.3 -0.3 AVDD+0.3 DVDD+0.3 V Ambient Operating Temperature TA -40 85 °C Storage Temperature Tstg -65 150 °C DC Supply (AVDD, DVDD) Input Current (Except supply pins) Input Voltage Analog Digital WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS Parameter Symbol DC Supply (AVDD, DVDD) Ambient Operating Temperature Commercial Industrial TAOp Min Typ Max Units 4.5 5.0 5.5 V 0 -40 25 25 70 85 °C POWER CONSUMPTION (TA = 25°C, DVDD = AVDD = 5 V, fXTAL = 20.480 MHz) (Note 1) Parameter Symbol Power Supply Current, Analog (RST=0) PDA0 Power Supply Current, Analog (RST=1) PDA Power Supply Current, Digital (RST=0) PDD0 Power Supply Current, Digital (RST=1) PDD Min Typ 10 50 Max Units 1 mA 20 mA 1 mA 80 mA Notes: 1. AO and NO outputs are not loaded. ANALOG CHARACTERISTICS (TA = 25°C, DVDD = AVDD = 5 V, fXTAL = 20.480 MHz) Parameter Symbol Min Typ Max Units Input Offset Voltage (APO, NI) 2.12 V Output Offset Voltage (AO, NO) 2.12 V Transmit Group Delay (Note 2) Receive Group Delay (Note 2) 6 6 Input Impedance (APO, NI) Zin Load Impedance (AO, NO) Zload 1.5 10 Power Supply Rejection (1 kHz) ms ms MΩ kΩ 40 dB Notes: 2. These parameters are guaranteed by design or by characterization. DS295F1 5 CS6422 ANALOG TRANSMISSION CHARACTERISTICS (TA = 25°C, DVDD = AVDD = 5 V, f XTAL = 20.480 MHz, RVol=TVol=RGain=TGain= 0 dB, HDD=TSD=RSD=1, analog inputs and outputs loaded with resistors and capacitors as shown in the typical connection diagram, Figure 4) Parameter Idle Channel Noise (Inputs grounded through a capacitor) Symbol Min Typ Max Units -80 11 -78 -73 dBV dBrnC0 dBm0p C-Message weighted (0-4 kHz) C-Message weighted (0-4 kHz) Psophometrically weighted (0-4 kHz) Signal-to-Noise Ratio C-Message weighted (0-4 kHz) (1.0 Vrms, 1 kHz sine wave input) SNR Total Harmonic Distortion C-Message weighted (0-4 kHz) (1.0 Vrms, 1 kHz sine wave input) THD Programmable Analog Gain 73 80 0.030 RGain/TGain = 00 RGain/TGain = 01 RGain/TGain = 10 RGain/TGain = 11 Volume Control Stepsize (TVol/RVol) ADC Full-scale Voltage Input dB 0.9 0.1 % 0 6 9.5 12 dB 3 dB 1.0 Vrms DAC Full-scale Voltage Output 1.0 ADC Noise Floor C-Message weighted (0-4 kHz) -83 1.2 Vrms dBV DAC Noise Floor, DAC muted C-Message weighted (0-4 kHz) -83 dBV MICROPHONE AMPLIFIER (TA = 25°C, DVDD = AVDD = 5 V, fXTAL = 20.480 MHz) Parameter Gain (Zsource = 50Ω) Symbol Min Typ Max Units Amic 34 dB SNRm 70 dB Input Impedance Zinm 8 kΩ Input Offset Voltage Voffm 2.12 V Signal-to-Noise Ratio C-Message weighted (0-4 kHz) DIGITAL CHARACTERISTICS (TA = 25°C, DVDD = AVDD = 5 V,fXTAL = 20.480 MHz) Parameter Symbol Min High-Level Input Voltage VIH DVDD-1.0 Low-Level Input Voltage Max Units VIL 1.0 V Input Leakage Current Ileak 10 µA Input Capacitance CIN 6 Typ V 5 pF DS295F1 CS6422 ANALOG TRANSMISSION CHARACTERISTICS (TA = -40°C to 85oC, DVDD = AVDD = 5 V, f XTAL =20.480 MHz, RVol=TVol=RGain=TGain= 0 dB, HDD=TSD=RSD=1, analog inputs and outputs loaded with resistors and capacitors as shown in the typical connection diagram, Figure 4) Parameter Idle Channel Noise (Inputs grounded through a capacitor) Symbol Min Typ Max Units -80 11 -78 -72 dBV dBrnC0 dBm0p C-Message weighted (0-4 kHz) C-Message weighted (0-4 kHz) Psophometrically weighted (0-4 kHz) Signal-to-Noise Ratio C-Message weighted (0-4 kHz) (1.0 Vrms, 1 kHz sine wave input) SNR Total Harmonic Distortion C-Message weighted (0-4 kHz) (1.0 Vrms, 1 kHz sine wave input) THD Programmable Analog Gain 72 80 dB 0.030 0.1 % dB 0 6 9.5 12 RGain/TGain = 00 RGain/TGain = 01 RGain/TGain = 10 RGain/TGain = 11 Volume Control Stepsize (TVol/RVol) ADC Full-scale Voltage Input 0.9 3 dB 1.0 Vrms DAC Full-scale Voltage Output 1.0 1.2 Vrms ADC Noise Floor C-Message weighted (0-4 kHz) -83 dBV DAC Noise Floor, DAC muted C-Message weighted (0-4 kHz) -83 dBV MICROPHONE AMPLIFIER (TA = 25°C, DVDD = AVDD = 5 V, fXTAL = 20.480 MHz) Parameter Gain (Zsource = 50Ω) Signal-to-Noise Ratio C-Message weighted (0-4 kHz) Symbol Min Typ Amic 34 Max Units dB SNRm 70 dB Input Impedance Zinm 8 kΩ Input Offset Voltage Voffm 2.12 V DIGITAL CHARACTERISTICS (TA = 25°C, DVDD = AVDD = 5 V,fXTAL = 20.480 MHz) Parameter High-Level Input Voltage Symbol Min VIH DVDD-1.0 Typ Max Units V Low-Level Input Voltage VIL 1.0 V Input Leakage Current Ileak 10 µA Input Capacitance CIN DS295F1 5 pF 7 CS6422 SWITCHING CHARACTERISTICS Parameter Symbol Digital input rise time Min Typ trise tRSTL RST low time Units 1.0 µs 1.0 µs 20.480 CLKI frequency fCLKI CLKI duty cycle tLCLKI 40 CLKI high or low time tHLCLKI 19.5 Min DRDY falling to DRDY falling (CLKI = 20.480 MHz) tDRDY STROBE high or low time Max 50 MHz 60 % ns 125 µs tHLSTROBE 55 ns DRDY falling to STROBE rising setup time tsDRDY 30 ns DATA valid to STROBE rising setup time tsDATA 30 ns STROBE rising to DATA valid hold time thDATA 30 ns STROBE rising to DRDY rising hold time thDRDY 30 ns Min RST rising to 4th extra STROBE pulse (cold reset) tcRST 110 ms Max RST rising to 4th extra STROBE pulse (warm reset) twRST 100 ms 1 f CLKI t HLCKI t HLCKI Figure 1. CLKI Timing t cRST t wRST t RSTL RST four extra strobe pulses 1 2 3 4 STROBE DATA Bit15 Bit14 Bit2 Bit1 Bit0 DRDY Figure 2. Reset Timing t DRDY DRDY t sDRDY t hDRDY STROBE t sDATA t hDATA t HLSTROBE DATA Bit15 Bit14 Bit0 Bit15 Bit14 Figure 3. Microcontroller Interface Timing 8 DS295F1 CS6422 ferrite bead +5V Analog 10 µF + 0.1 µF 16 DVDD AVDD 15 DGND AGND 1 0.1 µ F + 2 10 µF CS6422 19 MB 0.1 µF +10 µ F 12.1 kΩ Network Line Out 4 Mic Bias NO APO 18 3300 pF 0.022 µ F 0.47 µF 6.04 kΩ Network Line In 17 NI 3300 pF 20 API 8 7 6 5 From Microcontroller DATA STROBE 0.47 µF 12.1 kΩ 3 AO DRDY RST 3300pF NC4 NC3 NC2 NC1 12 11 10 CLKI 9 14 CLKO 20.480 MHz 13 22pF Speaker Driver 22pF Figure 4. Typical Connection Diagram (Microphone Preamplifier Enabled) ferrite bead +5V Analog 10 µF + 0.1 µF 16 DVDD AVDD 15 DGND AGND CS6422 API 1 0.1 µF + 2 10 µ F 20 0.47 µF 12.1 kΩ Network Line Out 4 6.04 kΩ 0.47 µF NO APO 18 3300 pF 3300 pF 0.47 µF Network Line In 6.04 kΩ 17 NI 3300 pF MB 8 From Microprocessor 7 6 5 DATA STROBE DRDY RST AO 0.1 µF +10 µ F 12.1 kΩ 3 3300pF NC4 NC3 NC2 NC1 12 External Mic Preamp 19 11 10 9 CLKI 14 22pF CLKO 20.480 MHz 13 22pF Speaker Driver Figure 5. Typical Connection Diagram (Microphone Preamplifier Disabled) DS295F1 9 CS6422 2. OVERVIEW The CS6422 is a full-duplex speakerphone chip for use in hands-free communications with telephony quality audio. Common applications include speakerphones, inexpensive video-conferencing, and hands-free cellular phone car kits. The CS6422 requires very few external components and allows system control through a microcontroller interface. Hands-free communication through a microphone and speaker typically results in acoustic feedback or howling because the loop gain of the system exceeds unity by the time audio amplitudes are adjusted to a reasonable level. The solution to the howling problem has typically been half-duplex, where either the transmit or the receive channel is active, never both at the same time. This prevents instability, but diminishes the overall communication quality by clipping words and forcing each talker to speak in turn. Full-duplex conversation, where both transmit and receive channels are active simultaneously, is the conversation quality we enjoy when using handsets. Full-duplex for hands-free communications is achieved in the CS6422 using a digital signal processing technique called “Echo Cancellation.” The end result is a more natural conversation than halfduplex, with no awkward breaks and pauses, allowing both parties to speak simultaneously. Echo Cancellation reduces overall loop gain and the acoustic coupling between speaker and microphone. This coupling reduction prevents the annoying effect of hearing one’s own delayed speech, which is worsened when there is delay in the system, such as vocoder delay in digital cellular phones. The CS6422 is a complete system implementation of a Digital Signal Processor with RAM and program ROM, running Echo Cancellation algorithms developed at Crystal Semiconductor using customer input, integrated with two delta-sigma codecs. The CS6422 is intended to provide a full-duplex 10 speakerphone solution with a minimum of design effort while displacing existing half-duplex speakerphone chips. 3. FUNCTIONAL DESCRIPTION The CS6422 is divided into four external interface blocks. The analog interfaces connect the device to the transmit and receive paths. Control functions are accessible through the microcontroller interface. Two pins accommodate either a crystal or an externally applied digital clock signal. Analog and digital power and ground are provided through four pins. 3.1 Analog Interface In a speakerphone application, one input of the CS6422 connects to the signal from the microphone, called the near-end or transmit input, and one output connects to the speaker. The output that leads to the speaker is called the near-end or receive output. Together, the input and output that connect to the microphone and speaker form the Acoustic Interface. The signal received at the near-end input is passed to the far-end or transmit output after acoustic echo cancellation. This signal is sent to the telephone line. The signal from the telephone line is received at the far-end input, also called the receive input, and this signal is passed to the receive output after network echo cancellation. The far-end input and output form the Network Interface. The analog interfaces are physically implemented using delta sigma converters running at an output word rate of 8 kHz, resulting in a passband from DC to 4 kHz. Because the inputs are analog to digital converters (ADCs), anti-aliasing and full-scale input voltage must be kept in mind. The ADCs expect a single-pole RC filter with a corner at 8 kHz, and they are post-compensated internally to prevent any resulting passband droop. The ADCs also expect a maximum of 0.9 Vrms (2.5 Vpp) at their inputs (which are biased around 2.12 VDC). A signal DS295F1 CS6422 Receive Path NI FAR-END NO 17 RGain ADC D S P (0,6,9.5,12 dB) 4 3 DAC DAC AO NEAR-END ADC 34 dB TGain Mic 20 API 1kΩ (0,6,9.5,12 dB) Voltage Reference CS6422 18 APO 19 MB Transmit Path Figure 6. Analog Interface of higher amplitude will clip the ADC input and will result in poor echo canceller performance. See Section 4., “Design Considerations” for more details. The outputs are delta-sigma digital to analog converters (DACs) and have similar requirements to the ADCs. The DACs are pre-compensated to expect a single-pole RC filter with a corner frequency at 4 kHz. The full scale voltage output from a DAC is 1.1 Vrms (3.1 Vpp) maximum, 1 Vrms typical, biased around 2.12 VDC. 3.1.1 Acoustic Interface The pins API (pin 20), APO (pin 18), AO (pin 3), and MB (pin 19) form the Acoustic Interface. A block diagram of the Acoustic Interface is shown in Figure 6. API and APO are, respectively, the input and output of the built-in microphone pre-amplifier. The pre-amplifier is an inverting amplifier with a fixed DS295F1 gain of 34 dB biased around an input offset voltage of 2.12 V. APO is the output of the pre-amplifier after a 1 kΩ (typical) resistor. The circuitry connected to the amplifier input must present low source impedance (