CS7410-CM

CS7410 CD/MP3/WMA Audio Controller Features l Super on-chip Integration for low cost and low count bill of materials l 32-Bit RISC Processor performs audio decode and system management functions l 16-bit DSP for audio special effects l 80 Kbytes internal SRAM, and 256 Kbytes internal ROM l Interfaces to external SDRAM or EDO DRAM (for shock protection), and to external ROM/FLASH (for custom program storage) l CD serial interface with advanced pattern matching and software error handling l Integrated DAC functionality l Simultaneous 4 channels PCM audio output and IEC-958 output. l Large number of GPIO pins for servo control, key scan, LCD control, etc. l Three serial control/status ports l Sophisticated clock management and low power consumption l Supports ISO9660 and multi-session write methods l Low power 0.18 micron technology l 100-pin MQFP package l 100-pin LQFP package Description The CS7410 is a true system-on-a-chip for the CDbased digital audio market. With a powerful RISC processor, one DSP, integrated audio ∆Σ modulator, large internal SRAM and program ROM, and glueless interface to popular CD chip sets, the CS7410 is a complete single chip low-power programmable audio decoder. This powerful architecture is easily capable of MP3, WMA, and other future audio formats. The CS7410’s flexible architecture and low power consumption make it an ideal low-cost solution for a wide range of player applications. For portable audio systems, the memory interface can be used to add DRAM or SRAM for Electronic Shock Protection (ESP). A flexible set of interfaces are available for end-user I/O such as a keypad and LCD control for use in mass market CD players, boom boxes, and shelf-top systems. ORDERING INFORMATION CS7410-CM 0° to 70° C 100-pin MQFP CS7410-CQ 0° to 70° C 100-pin LQFP RISC-32 Instruction Cache CPU Data Cache MAC DSP-16 Instruction Cache X,Y Data memory Audio Interface ∆Σ Modulator PCM Out IEC-958 CPU / MAC CD Interface Control FIFO System Miscellaneous PLL Clock Control Timers Register Bank Get Bits 80 KB Internal SRAM External Interface 2-Wire Debug Interface Memory Controller ROM/SRAM Control Flash Control Mini DMA DRAM Control 3/4 Wire Serial Programmable I/O PWM Out 256 KB Internal ROM Preliminary Product Information Cirrus Logic, Inc. P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2002 (All Rights Reserved) JUL ‘02 DS553PP1 1 CS7410 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5 1.1 AC and DC Parametric Specifications ............................................................................... 5 1.1.1 Absolute Maximum Rating .................................................................................... 5 1.1.2 Recommended Operating Conditions ................................................................... 5 1.1.3 Electrical Specifications ........................................................................................ 5 1.1.4 DC Characteristics ................................................................................................ 7 1.1.4.1 SDRAM Interface .................................................................................. 7 1.1.4.2 Serial Interface .................................................................................... 11 1.1.4.3 EDO DRAM interface .......................................................................... 12 1.1.4.4 FLASH / ROM Interface ...................................................................... 15 1.1.4.5 Audio Output Interface ........................................................................ 17 1.1.4.6 CD Interface ........................................................................................ 18 1.1.4.7 Miscellaneous Timings ........................................................................ 20 2. CS7410 SUMMARY ................................................................................................................ 21 2.1 CS7410 Typical Application ............................................................................................. 21 2.2 CS7410 Block Summaries .............................................................................................. 21 2.2.1 RISC-32 .............................................................................................................. 21 2.2.2 DSP-16 ................................................................................................................ 21 2.2.3 System Controls .................................................................................................. 21 2.2.4 Memory System .................................................................................................. 22 2.2.5 CD Interface ........................................................................................................ 22 2.2.6 Audio Interface .................................................................................................... 22 2.2.7 External Interface ................................................................................................ 22 2.2.8 System Functions ................................................................................................ 22 3. FUNCTIONAL DESCRIPTION ............................................................................................... 23 3.1 RISC-32 Processor .......................................................................................................... 23 3.2 DSP-16 Processor ........................................................................................................... 23 3.3 Memory Control ............................................................................................................... 23 3.4 CD Interface ..................................................................................................................... 23 3.5 System Control Functions ................................................................................................ 23 3.6 Audio Output .................................................................................................................... 24 4. PIN DESCRIPTION ................................................................................................................. 25 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. “Advance” product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the “Foreign Exchange and Foreign Trade Law” is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 2 DS553PP1 CS7410 4.1 Pin Identification .............................................................................................................. 25 4.2 Miscellaneous Pins .......................................................................................................... 30 4.3 Serial Interface Pins ........................................................................................................ 30 4.4 SDRAM / DRAM Interface ............................................................................................... 31 4.5 ROM/NVRAM Interface ................................................................................................... 32 4.6 Digital Audio Output Interface .......................................................................................... 33 4.7 ∆Σ Modulator Interface .................................................................................................... 33 4.8 CD Interface .................................................................................................................... 34 4.9 General Purpose Input/Output (GPIO) ............................................................................ 35 4.10 Power and Ground ........................................................................................................ 36 5. 100-PIN MQFP PACKAGE SPECIFICATIONS (20X14X2.85MM) ....................................... 38 6. 100-PIN LQFP PACKAGE SPECIFICATIONS (14X14X1.4MM) ........................................... 39 LIST OF FIGURES Figure 1. SDRAM Timing ................................................................................................................ 7 Figure 2. SDRAM Load Mode ......................................................................................................... 8 Figure 3. SDRAM Burst Write ......................................................................................................... 9 Figure 4. SDRAM Burst Read ......................................................................................................... 9 Figure 5. SDRAM Refresh ............................................................................................................ 10 Figure 6. Serial Interface Timing Diagram .................................................................................... 11 Figure 7. EDO Page Write Timing Diagram .................................................................................. 13 Figure 8. EDO Page Read Timing Diagram.................................................................................. 13 Figure 9. EDO Refresh Timing Diagram ....................................................................................... 14 Figure 10. FLASH/ROM Read ...................................................................................................... 15 Figure 11. FLASH/ROM Write....................................................................................................... 16 Figure 12. Audio Output Timing .................................................................................................... 17 Figure 13. CD Interface Timing ..................................................................................................... 18 Figure 14. CD Interface Timing Diagrams..................................................................................... 19 Figure 15. Miscellaneous Timings................................................................................................. 20 Figure 16. CS7410 Application ..................................................................................................... 21 Figure 17. CS7410 Pin Identification............................................................................................. 25 Figure 18. 100-Pin MQFP Package (20x14x2.85mm) .................................................................. 38 Figure 19. 100-Pin LQFP Package (14X14X1.4mm) .................................................................... 39 LIST OF TABLES Table 1. SDRAM Characterization Data ......................................................................................... 7 Table 2. Serial Interface Characterization Data ............................................................................ 11 Table 3. EDO DRAM Characterization Data ................................................................................. 12 Table 4. FLASH/ROM Read Characterization Data...................................................................... 15 Table 5. Audio Output Interface Symbols and Characterization Data........................................... 17 Table 6. Pin Type and Direction Legend....................................................................................... 25 Table 7. Pin Assignments ............................................................................................................. 26 Table 8. Miscellaneous Interface Pins .......................................................................................... 30 Table 9. Serial Interface Pins ........................................................................................................ 30 Table 10. SDRAM Interface .......................................................................................................... 31 Table 11. EDO DRAM Interface.................................................................................................... 31 Table 12. ROM/NVRAM Interface................................................................................................. 32 Table 13. Audio Output Interface .................................................................................................. 33 Table 14. ∆Σ Output Interface ....................................................................................................... 33 Table 15. CD Interface .................................................................................................................. 34 DS553PP1 3 CS7410 Table 16. Dedicated General Purpose I/O Pins ............................................................................ 35 Table 17. Redefined General Purpose Pins.................................................................................. 35 Table 18. Power and Ground ........................................................................................................ 36 4 DS553PP1 CS7410 1. CHARACTERISTICS AND SPECIFICATIONS 1.1 1.1.1 AC AND DC PARAMETRIC SPECIFICATIONS Absolute Maximum Rating Description Power Supply Voltage on I/O ring Power Supply Voltage on core logic and PLL Digital Input Applied Voltage (power applied) Digital Input Forced Current Digital Output Forced Current Lead Soldering Temperature Vapor Phase Soldering Temperature Storage Temperature (no power applied) Ambient Temperature (power applied) Power consumption -40 0 Min. -0.5 -0.5 -0.5 -10 -50 Max. 4.6 2.5 5.5 10 50 260 235 125 70 1 Unit Volts Volts Volts mA mA oC oC oC o (AGND, DGND=0V, all voltages with respect to 0V) Symbol VDDIO VDDCORE VI II IO TSOL TVSOL TSTOR TAMB PTOT C W CAUTION: Operating beyond these Minimum and Maximum limits can result in permanent damage to the device. Cirrus Logic recommends that CS7410 devices operate at the settings described in the next table. 1.1.2 RECOMMENDED OPERATING CONDITIONS Parameter Symbol VDD VDD TAMB Min 3.0 1.62 0 Typ 3.3 1.8V 25 Max 3.6 1.98 70 Units Volts Volts o Supply Voltage, IO Supply Voltage, core and PLL Ambient Temperature (power applied) C 1.1.3 Electrical Specifications (TA = 0 to 70 oC) Parameter Power Supply Supply Current, IO Supply Current, core and PLL IDD IDD Normal Operating Normal Operating 13 70 mA mA Symbol Conditions Min Typ Max Units DS553PP1 5 CS7410 Parameter Digital Pins Input Voltage, High Input Voltage, Low Input Current Input Pull up/down resistor Output Voltage, High Output Voltage, Low High-Z-state Leakage VIH VIL IIN RI VOH VOL IOZ @ buffer rating @ buffer rating VOUT = VSS or VDD -1 2.4 0.4 +1 VIN = VDD or VSS -1 75 2.0 0.8 +1 Volts Volts µA KΩ Volts Volts µA Symbol Conditions Min Typ Max Units 6 DS553PP1 CS7410 1.1.4 1.1.4.1 DC CHARACTERISTICS SDRAM Interface (TA= 25°C; VDD_PLL=VDD_CORE=1.8V±10%, VDD_IO=3.3V±10%) Symbol t t t t t t Description DR_CKO Period Output Delay from DR_CKO active edge M_D[15:0] delay from DR_CKO M_D[15:0] valid time after DR_CKO M_D[15:0] setup to DR_CKO M_D[15:0] hold time after DR_CKO 5 Min 22 Typ Max 19 19 Unit ns ns ns ns ns ns mper mco mdow mhw msur 13 0 mhr Table 1. SDRAM Characterization Data t mper DR_CKO M_WE_L M_A DR_RAS_L DR_CAS_L t mco t mdow M_D (write) t mhw t msur M_D (read) t mhr Figure 1. SDRAM Timing DS553PP1 7 CS7410 DR_CKO DR_RAS_L DR_CAS_L M_A M_D M_WE_L Figure 2. SDRAM Load Mode 8 DS553PP1 CS7410 DR_CKO DR_RAS_L DR_CAS_L M_A ADRAS ADCAS M_D D0 D1 ... Dn M_WE_L Figure 3. SDRAM Burst Write DR_CKO DR_RAS_L DR_CAS_L M_A ADRAS ADCAS M_D D1 D2 ... Dn M_WE_L Figure 4. SDRAM Burst Read DS553PP1 9 CS7410 DR_CKO DR_RAS_L DR_CAS_L M_A M_D M_WE_L Figure 5. SDRAM Refresh 10 DS553PP1 CS7410 1.1.4.2 Serial Interface Symbol t t t t t t Description Clock period Master-mode data setup Master-mode data hold Slave-mode data setup Master chip select to clock setup Slave mode data hold Min 66 28 28 15 28 0 Typ Max Unit ns ns ns ns ns ns clk_per DMs DMh DSs CMs DSh Table 2. Serial Interface Characterization Data tclk_per SER2_CLK (CPOL=0) tCMs SER2_CLK (CPOL=1) tDMs SER2_DO (master) MSB tDMh LSB tDSs SER2_DI (slave) SER2_CS MSB tDSh LSB Figure 6. Serial Interface Timing Diagram DS553PP1 11 CS7410 1.1.4.3 EDO DRAM interface Symbol t t t t t t t t t Description RAS low time RAS high pulse time RAS fall to CAS fall CAS low time CAS high time CAS fall to address row Address row to RAS fall RAS fall to address column Min 72 40 38 30 15 29 10 18 Typ Max Unit ns ns ns ns ns ns ns ns ns RAS RP RCL CAS CPN CAH ASR RAH ASC second address column (burst) to CAS fall 10 Column address to data setup CAS fall to data setup CAS fall to RAS fall RAS fall to CAS rise CAS rise to RAS rise Write data setup to CAS fall Write data hold to CAS fall Write enable setup to CAS fall Write enable hold to CAS fall RAS fall to OE fall RAS rise to OE rise Read data hold to CAS rise 19 18 6 12 29 13 20 -5 -5 0 5 5 35 17 tAA tCAC t t ns ns ns ns ns ns ns ns ns ns ns ns CSR CHR tCRH tWDS tWDH t WS tWH tROE tOER t DCH Table 3. EDO DRAM Characterization Data Note:Values shown are for minimum internal clock period (11ns) and all programmed wait states enabled. 12 DS553PP1 CS7410 t RAS DR_RAS_L t RCL DR_CAS_L t RP t CAS tCRH t CPN t CAH ADCAS t WDS t WDH DATA tW H t ASR M_A t RAH ADRAS t ASC ADCAS M_D DATA tW S M_AP_WE Figure 7. EDO Page Write Timing Diagram M_AP_OE tROE t RAS t OER DR_RAS_L t RCL DR_CAS_L tCRH t CAS t RP t ASR M_A t RAH ADRAS t CPN ADCAS tASC ADCAS tAA t CAC DATA t CAH t DCH M_D DATA Figure 8. EDO Page Read Timing Diagram DS553PP1 13 CS7410 t RAS DR_RAS_L t CSR DR_CAS_L t CHR Figure 9. EDO Refresh Timing Diagram 14 DS553PP1 CS7410 1.1.4.4 FLASH / ROM Interface Symbol t t t t t t t t Description CE low period CE fall to output enable fall CE rise to output enable rise Address setup to CE fall Data setup after address1 All outputs setup before WE WE pulse width All outputs hold after WE 5 -5 Min 135 Typ Max Unit ns ns CSpw RDd1 RDd2 5 10 28 ns ns ns ns ns ns ADs -10 DAs WRSU 95 170 95 WRPW WRH Table 4. FLASH/ROM Read Characterization Data 1.Value shown for 3 programmed wait states. Note:Values shown are for minimum internal clock period (11ns) and no programmed wait states. NVM_CE_L tCSpw M_WE_L tRDd1 M_AP_OE tADs M_A tDAS M_D tRDd2 Figure 10. FLASH/ROM Read DS553PP1 15 CS7410 NVM_CE_L M_A M_D tWRPW M_WE_L tWRSU tWRH M_AP_OE Figure 11. FLASH/ROM Write 16 DS553PP1 CS7410 1.1.4.5 Symbol t t t t t Audio Output Interface Description PCM_XCLK High Time (PCM_XCLK is Input/Output) PCM_XCLK Low Time (PCM_XCLK is Input/Output PCM_XCLK period (Input/Output) PCM_BCK period (Output) PCM_BCK delay from PCM_XCLK output transition1 PCM_BCK delay from PCM_XCLK input transition1 PCM_LRCK delay from PCM_BCK transition PCM_D[3:0] delay from PCM_BCK transition 1 1 axch axcl axper aoper sdmo sdmi lrds adsm Min 42 42 55 440 Typ 50 50 Max Units % % ns ns 5 15 5 5 ns ns ns ns t t t Table 5. Audio Output Interface Symbols and Characterization Data 1. Active clock edge is programmable. Timing is referenced from the active edge. t PCM_XCK(Input/Output) t PCM_BCK(Output) t sdmi sdmo axch axper t axcl t aoper PCM_BCK(Output) t PCM_LRCK(Output) t adsm PCM_DO[1:0] (Output) lrds Figure 12. Audio Output Timing DS553PP1 17 CS7410 1.1.4.6 Symbol t t t CD Interface Description CD_LRCK setup to CD_BCK active edge CD_DATA and CD_C2P0 setup to CD_BCK active edge CD_DATA and CD_C2P0 hold time after CD_BCK active edge Min 7 7 3 Typ Max Units ns ns ns slri sdi hsdi Note:Active edge of CD_BCLK is programmable CD_BCK(Input)* tslri CD_LRCK(Input) CD_DO (Input) tsdi thsdi CD_C2PO (Input) Figure 13. CD Interface Timing 18 DS553PP1 CS7410 CD_BCK CD_LRCK DATA C2P0 0 Invalid Lower (Left Channel) Left Channel MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Upper (Left Channel) Invalid Lower (Right Channel) Right Channel MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Upper (Right Channel) 32-bit BCK, MSB First, Right Channel Low, C2P0 LSB First, Data latch timing high CD_BCK CD_LRCK DATA C2P0 0 Invalid Upper (Right Channel) Right Channel MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lower (Right Channel) Invalid Upper (Left Channel) Left Channel MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lower (Left Channel) 32-bit BCK, MSB First, Left Channel Low, C2P0 MSB First, Data latch timing low CD_BCK CD_LRCK DATA C2P0 0 Invalid Left Channel MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lower (Left Channel) Invalid Right Channel MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lower (Right Channel) Invalid Left Channel MSB 15 14 13 12 11 10 9 8 7 6 5 Upper (Left Channel) Upper (Right Channel) Upper (Left Channel) 24-bit BCK, MSB First, Right Channel Low, C2P0 MSB First, Data latch timing high CD_BCK CD_LRCK DATA C2P0 0 Invalid Left Channel LSB MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lower (Left Channel) Invalid Right Channel LSB MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lower (Right Channel) Invalid Left Channel LSB 0 1 2 3 4 5 6 7 8 9 10 Upper (Left Channel) Upper (Right Channel) Upper (Left Channel) 24-bit BCK, LSB First, Right Channel Low, C2P0 MSB First, Data latch timing low CD_BCK CD_LRCK DATA 0 Invalid Left Channel MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Invalid Right Channel MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Invalid Left Channel MSB 15 14 13 12 11 10 9 8 7 6 5 24-bit BCK, MSB First, Right Channel Low, Data latch timing high (Note: no C2P0 for this format) CD_BCK CD_LRCK DATA C2P0 Right Channel Left Channel Right Channel Left Channel MSB LSBMSB LSB MSB LSB MSB LSB MSB 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 Lower (Right Channel) Upper (Right Channel) Lower (Left Channel) Upper (Left Channel) Lower (Right Channel) Upper (Right Channel) Lower (Left Channel) Upper (Left Channel) 16-bit BCK, MSB First, Left Channel Low, C2P0 LSB First, Data latch timing high Figure 14. CD Interface Timing Diagrams DS553PP1 19 CS7410 1.1.4.7 Miscellaneous Timings Symbol t Description XTLCLK period RST_N Low Pulse Width GPIO PW High GPIO PW Low Min 1000 50 50 Typ 59.05 Max Unit ns ns ns ns xclper1 rstl gph gpl t t t 1.Value represents typical application with 16.934 MHz crystal t xccper XTLCLOCK t rst l RESET-N t gp l GPIO t gph Figure 15. Miscellaneous Timings 20 DS553PP1 CS7410 2. CS7410 SUMMARY 2.1 CS7410 Typical Application Figure 16 shows an example of a complete audio player using the CS7410. Speakers/Headphones (2 or 4 channel) IEC-958 4 Chan. Optical Driver PCM DACs 2 Chan. OP-AMPs Servo DSP/Rd Channel Digital Audio Out DAC Out CD Interface Debug Serial Interface CS7410 Memory Interface GPIO ROM/FLASH (optional) 0-2 MB For new code DRAM EDO/SDRAM (optional) 0-8 MB For shock protection Serial EEPROM (optional) Keypad Matrix LCD Controller/ Display IR receiver Figure 16. CS7410 Application 2.2 2.2.1 • • • • • • CS7410 Block Summaries RISC-32 Powerful 32-bit RISC processor Comprehensive development tool support Big or little endian data formats supported 32x32 (64-bit result) MAC, 2 cycles / multiply with C support 4 Kbyte instruction cache, 2 Kbyte data cache Single cycle instructions, runs up to 90 MHz • • • • • 16-bit fixed point logic, with 36 bit accumulator. Single-cycle throughput, 2-cycle latency multiply accumulate, 16-bit simple integer logic 512 byte instruction cache, 8 Kbyte program visible local memory Single cycle instructions, runs up to 90 MHz DSP MAC is pipelined, 1 cycle / multiply 2.2.3 • System Controls 2.2.2 • DSP-16 • Powerful 16-bit DSP processor Includes 32 hardware lockable semaphore registers Two general-purpose registers for inter-proces21 DS553PP1 CS7410 sor communication Three 32-bit timers for I/O and other uses, with programmable interval rates “Getbits” module accelerates peripheral stream parsing Both hardware and software interrupts on data or debug • Integrated sigma-delta (∆Σ) stereo audio modulator • • • 2.2.7 • • • External Interface 2.2.4 • • • • Memory System • Large internal SRAM (80 Kbyte) and internal program ROM (256 Kbyte) Supports both Synchronous and EDO DRAM (256 KBytes to 8 MBytes) for ESP Supports one bank of FLASH and ROM (up to 2 MBytes) for nonvolatile storage 4-, 8-, or16-bit data bus for DRAM, 8-bit data bus for ROM • • 2-wire serial slave port, used for debug 3- or 4-wire synchronous serial master/slave port for external controller or slave peripheral Separate synchronous serial master port optimized for receiving CD sub-codes Up to 29 programmable bi-directional I/O (GPIO) and up to 9 output only (GPO) pins (some multiplexed with other peripherals) All pins defined as GPIOs can be used to receive edge or level detection interrupts. Pulse-width modulated (PWM) output pin can be used to create simple ADC using low-cost comparator (i.e., for battery voltage monitor) 2.2.5 • • CD Interface 2.2.8 • • • • • • • System Functions Glueless interfaces to CD servo chip set, supporting all standard CD formats Includes pattern matching hardware to support fast ESP recovery 2.2.6 • • • Audio Interface Supports 4 channels PCM, I2S connectivity at up to 24 bits Flexible audio clocking scheme using internal PLL and dividers, or external pins Simultaneous IEC-958 output with programmable channel status and user data Internal oscillator uses external crystal, or receives clock (i.e. 16.9 MHz) from CD servo Internal PLL generates any system clock frequency, chip can run up to 90 MHz Includes clock divider and clock shutoff circuits for low power/sleep modes Advanced 0.18 micron CMOS technology, runs off 1.8 V and 3.3 V All I/O pins are 3.3 V, with 5 V tolerance 100-pin MQFP package 100-pin LQFP package 22 DS553PP1 CS7410 3. FUNCTIONAL DESCRIPTION 3.1 RISC-32 Processor The CS7410 includes a powerful, proprietary 32bit RISC processor backed by powerful software development tools. The RISC-32 has a MAC engine which performs multiply/accumulate in 2 cycles with C support, effectively achieving single cycle throughput. There are other instructions that are designed to help with performing audio decoding. The RISC processor coordinates on-chip multi-threaded tasks, as well as supervises system activities such as keypad and front panel display control. memory. This arbitration and scheduling guarantees the allocation of sufficient bandwidth to the various clients. An optimal application will use only internal ROM and SRAM for code and data storage, which results in the best timing and lowest power consumption. External DRAM may be used for runtime code storage or for ESP RAM. In both of these applications, the data throughput requirement is low, and the Memory Controller acts as a DMA engine to move data between external and internal memory with minimal power consumption. The internal ROM contains most of the code required for audio decoding and system functions. Additional code can be stored in external ROM (managed by the Memory Controller) or a small serial ROM (controlled by GPIOs). The CS7410 also supports code storage in external FLASH with insystem write capability for customer code updates. Future firmware releases will provide a complete solution requiring no external ROM. 3.2 DSP-16 Processor The CS7410 contains a proprietary digital signal processor (DSP) called DSP-16, which is optimized for audio and sound applications. In the CS7410, the DSP-16 assists with audio decoding and provides added functions such as surround sound and equalization. The DSP performs 16-bit simple integer operations, and has a 16-bit fixed point logic unit with a 32-bit accumulator. There are 24 general-purpose registers, and eight independent address generation registers, featuring: post-increment ALU, linear and circular buffer operations, bit reverse ALU operations, and dual operand read from memory. The multiply-accumulator has single-cycle throughput, with two cycle latency. The DSP is optimized for bit packing and unpacking operations. The interface to main memory is designed for bursting flexible block sizes and skip counts. 3.4 CD Interface The CD Interface receives compressed or uncompressed (direct audio) data from the CD servo/read channel chip, performs descrambling and CRC checking, and writes the data to an internal FIFO. Additional C3 error decoding is done in software. The CD interface is compatible with all commonly used CD formats. The CS7410 contains a hardware pattern matching circuit to scan the incoming CD data for a pattern of up to 64 bytes. This circuit is used to assist the Electronic Shock Protection function by quickly locating and matching the incoming data with data stored in the ESP RAM. 3.3 Memory Control The Memory Controller performs the arbitration functions for all the other modules in the CS7410, allowing access to internal ROM and SRAM, and to external ROM and DRAM. The Memory Controller services and arbitrates a number of clients and stores their code and/or data within the local DS553PP1 3.5 System Control Functions The system control functions are used to coordinate the activities of the multiple processors, and to provide the supporting system operations. Two 32-bit communication registers are available for inter23 CS7410 processor communication, and 32 semaphore registers are used for resource locking. Three timers are available for general-purpose functions, as well as more specialized functions, such as watchdog timers and performance monitoring. The large number of general purpose I/Os offers flexibility in system configurations. Three separate synchronous serial interfaces, conforming to industry-standard protocols, are available for a variety of system interface functions. Four general purpose software interrupts and twelve hardware interrupts help reduce peripheral overhead and improve UI responsiveness. Power-down control of the internal clocks is also possible. An internal PLL is used to generate the internal system and memory clocks as well as audio clocks for all supported sample rates. channels of PCM data to external audio DACs, plus an independent IEC-958 encoded output. The IEC958 output has fully programmable channel status (commercial), and provides a flexible solution to support all IEC-958 modes for user data. The audio output circuit contains an auto-mute detect circuit, which can generate internal or external mute controls PCM FIFO data up to 18 bits can also be output by the on-board sigma-delta stereo modulator. The sigma-delta modulator yields a typical 85 dB signal-to-noise ratio with few external components required, resulting in a low-cost, low parts count analog front end. The modulator has a 32x upsampling filter, followed by a 32x interpolator, and finally a 5th-order Sigma-Delta modulator. The auto-mute circuit also works on the modulator output, and there are separate programmable attenuators for the modulator output and both PCM outputs. 3.6 Audio Output Decoded audio data is written into an output FIFO in 16-, 18-, 20- or 24-bit PCM format. A flexible audio output stage can simultaneously output 4 24 DS553PP1 CS7410 4. 4.1 PIN DESCRIPTION Pin Identification Figure 17 shows the CS7410 pins grouped by function, also showing the number of pins in each group. Figure 17. CS7410 Pin Identification Table 6 lists the conventions used to identify the pin type and direction.pin assignments. I: Input S: Schmitt trigger on input U: Pull up resistor O: Output O4: Output – 4mA drive T4: High Z output – 4mA drive B: Bi-direction B4: Bi-direction – 4mA drive D4: Bi-direction with 4mA open drain output Table 6. Pin Type and Direction Legend DS553PP1 25 CS7410 Pwr: +2.5V or +3.3V power supply voltage Gnd: Power supply ground Name_N: Low active Name_L: Low active Table 6. Pin Type and Direction Legend (Continued) Table 7 lists the pin number, pin name, and pin type for the 100-pin CS7410 package. For signal pins, the pin direction after reset is shown. The primary function and pin direction is shown for all signal pins. For some signal pins, a secondary function and direction are also shown. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Name PLL_GND PLL_1V8 M_D_15 M_D_14 M_D_13 M_D_12 M_D_11 M_D_10 M_D_9 M_D_8 M_D_7 CORE_1V8 M_D_6 CORE_GND M_D_5 IO_3V3 XTLCLK_O Type Gnd Pwr B4 B4 B4 B4 B4 B4 B4 B4 B4 Pwr B4 Gnd B4 Pwr O O I I I I I I I I I I I Reset Function #1 PLL Ground PLL Power DRAM Data[15] DRAM Data[14] DRAM Data[13] DRAM Data[12] DRAM Data[11] DRAM Data[10] DRAM Data[9] DRAM Data[8] DRAM Data[7] Core Power DRAM Data[6] Core Ground DRAM Data[5] I/O Power Oscillator Out Table 7. Pin Assignments O B NVMem Data[5] B B NVMem Data[6] B B B B B B B B B B NVMem Address[19] NVMem Address[18] NVMem Address[17] NVMem Address[16] NVMem Address[15] NVMem Address[14] NVMem Address[13] NVMem Address[12] NVMem Data[7] O O O O O O O O B Dir Function #2 Dir Note 26 DS553PP1 CS7410 Pin 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Name XTLCLK_I IO_GND M_D_4 M_D_3 M_D_2 M_D_1 M_D_0 M_A_11 M_A_10 M_A_9 M_A_8 M_A_7 M_A_6 M_A_5 M_A_4 M_A_3 M_A_2 M_A_1 M_A_0 DR_RAS_L CORE_1V8 DR_CAS_L Type I Gnd B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 T4 T4 T4 T4 Pwr T4 I I I I I I I I I I I I I I I I I I I Reset I Function #1 Oscillator In I/O Ground DRAM Data[4] DRAM Data[3] DRAM Data[2] DRAM Data[1] DRAM Data[0] DRAM Address[11] DRAM Address[10] DRAM Address[19] DRAM Address[8] DRAM Address[7] DRAM Address[6] DRAM Address[5] DRAM Address[4] DRAM Address[3] DRAM Address[2] DRAM Address[1] DRAM Address[0] DRAM RAS_L Core Power DRAM CAS_L O B B B B B O O O O O O O O O O O O O NVMem Data[4] NVMem Data[3] NVMem Data[2] NVMem Data[1] NVMem Data[0] NVMem Address[11] NVMem Address[10] NVMem Address[9] NVMem Address[8] NVMem Address[7] NVMem Address[6] NVMem Address[5] NVMem Address[4] NVMem Address[3] NVMem Address[2] NVMem Address[1] NVMem Address[0] B B B B B O O O O O O O O O O O O 1 1 1 1 1, 3 1, 3 1, 3 1, 3 1, 3 3 3 3 Dir I Function #2 Dir Note Table 7. Pin Assignments (Continued) DS553PP1 27 CS7410 Pin 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Name CORE_GND M_WE_L IO_GND DR_CKO IO_3V3 DR_CKE DR_BS_L M_AP_OE NVM_CE_L KP_IN_0 KP_IN_1 KP_IN_2 KP_IN_3 KP_IN_4 KP_OUT_0 KP_OUT_1 KP_OUT_2 KP_OUT_3 KP_OUT_4 IR_IN SER1_CLK SER1_DAT SER4_CLK SER4_DAT IO_GND SER2_CLK SER2_DI SER2_DO Type Gnd T4 Gnd T4 Pwr T4 B4 B4 T4 B4U B4U B4U B4U B4U B4 B4 B4 B4 B4 B4S D4S D4S B4S B4S Gnd B4 B4 B4 I I I I I I I I I I I I I I I I I I I I I I I I Reset Function #1 Core Ground DRAM WE_L I/O Ground SDRAM CKO I/O Power SDRAM CKE SDRAM BS_L SDRAM AP, EDO DRAM OE_L NVM_CE_L GPIO[19] GPIO[20] GPIO[21] GPIO[22] GPIO[23] GPIO[24] GPIO[25] GPIO[26] GPIO[27] GPIO[28] GPIO[4] Debug Port Clock Debug Port Data GPIO[5] GPIO[6] I/O Ground Serial2 Clock Serial2 Data In Serial2 Data Out B B B GPIO[7] GPIO[8] GPIO[9] B B B O O O O B B B B B B B B B B B B B B B NVMem Address[20] NVM_ OE_L 1 1 O O NVM_WE_L Dir Function #2 Dir Note Table 7. Pin Assignments (Continued) 28 DS553PP1 CS7410 Pin 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 Name SER2_CS SER3_CLK SER3_DO CORE_1V8 SER3_DI CORE_GND SER3_SS0 IO_3V3 SER3_SS1 SERVOCK PCM_XCK PCM_MUTE CD_C2P0 CD_BCLK CD_LRCK CD_DATA DAC_LP DAC_LN IO_GND DAC_RP DAC_3V3 DAC_RP RST_N TEST PCM_BCK PCM_LRCK PCM_DO_0 PCM_DO_1 IEC958_O GPIO_0 Type B4 B4 B4 Pwr B4 Gnd B4 Pwr B4 B4 B4 B4 B4 IS I I O4 O4 Gnd O4 Pwr O4 IS I B4 B4 B4 B4 B4 B4 O I I O O O O I I O I I I I I I I I O O I I Reset I I I Function #1 Serial2 Chip Select Serial3 Clock Serial3 Data Out Core Power Serial3 Data In Core Ground Serial3 Chip Select0 I/O Power Serial3 Chip Select1 Servo Clock In PCM_XCK PCM_MUTE CD_C2P0 CD_BCLK CD_LRCK CD_DATA ∆Σ DAC Left Positive Out ∆Σ DAC Left Negative Out I/O Ground ∆Σ DAC Right Positive Out ∆Σ DAC I/O Power ∆Σ DAC Right Negative Out Reset_L Manufacturing Test PCM_BCK PCM_LRCK PCM_Dout[0] PCM_Dout[1] IEC-958 Out GPIO[0] O I I O O O O O B GPO[0] GPO[1] GPO[2] GPO[3] GPIO[18] O O O O B 1 1 2 1 GPO[8] O O GPO[7] O O I B O I I I I O O GPO[5] GPO[6] O O GPO[4] GPIO[16] O B 1 GPIO[15] GPIO[17] B B O GPIO[14] B I GPIO[13] B Dir B O O Function #2 GPIO[10] GPIO[11] GPIO[12] Dir B B B Note Table 7. Pin Assignments (Continued) DS553PP1 29 CS7410 Pin 98 99 100 Name GPIO_1 GPIO_2 GPIO_3 Type B4 B4 B4 Reset I I I GPIO[1] GPIO[2] GPIO[3] Function #1 Dir B B B Function #2 PWM_Out Dir O Note Table 7. Pin Assignments (Continued) 1. Optional pull up or pull down resistor may be connected to configure internal ROM program 2. Required external resistor required to select processor boot from internal ROM (pull down) or external ROM (pull up). 3. Drives for a short time after reset, then reverts to high impedance 4.2 Miscellaneous Pins These pins described in Table 8 are used for used for basic functions such as clocking, reset and infrared receiver interface. The main system clock can be derived from an external crystal connected between the XTLCLK_I and XTLCLK_O pins, or can be received from the CD servo chip via the XTLCLK_I pin. The CS7410 can accommodate a variety of input frequencies, such as 44.1 KHz x 256, x 384, or x 512. Pin 17 18 90 91 Signal Name XTLCLK_O XTLCLK_I RST_N TEST Type O I I I Crystal output Crystal input, or oscillator input Asynchronous reset input, active low Manufacturing test, tie to ground Description Table 8. Miscellaneous Interface Pins 4.3 Serial Interface Pins The CS7410 Serial Interface pins are described in Table 9. CS7410 has three dedicated serial ports, each with different protocols. The 2-wire serial port (SER1) supports industry standard protocols. This port is typically used for debug, with the CS7410 as the slave. The slave chip select address is programmable, and defaults to a 7-bit value of 0x1B. A second serial controller (SER2) supports industry standard 3-wire and 4-wire protocols. In master mode, this interface can control a front panel or a small non-volatile memory. In slave mode, it can operate under control of an external processor, for example, in a combination unit. The third serial port (SER3) is a 5-wire master device optimized for reading CD subcodes from the servo chip, and can also be used a general-purpose serial port. Pin 60 61 65 66 67 Signal Name SER1_CLK SER1_DAT SER2_CLK SER2_DI SER2_DO Type B B B I B Description Debug port serial clock Debug port serial data Clock for 4-wire serial port (output for master mode, input for slave mode) Input data for 4-wire serial port Output data for 4-wire serial port – may function as bidirectional data in 3-wire mode. Table 9. Serial Interface Pins 30 DS553PP1 CS7410 68 69 70 72 74 76 SER2_CS SER3_CLK SER3_DO SER3_DI SER3_SS0 SER3_SS1 B O O I O O Chip select for 4-wire serial port (output if master, input if slave mode). Can also be used as bidirectional ready line. Clock output Data output – up to 32 bits per transfer. Data input – up to 96 bits per transfer. Slave select for first peripheral (programmable polarity) Slave select for second peripheral (programmable polarity) Table 9. Serial Interface Pins (Continued) 4.4 SDRAM / DRAM Interface These pins are used to interface the CS7410 with external synchronous or EDO DRAMs. Data widths of 4 to 16 bits are supported. The CS7410 supports word or block transfers (partial word transfers are not required). Table 10 gives instructions on how to interface to any particular configuration of SDRAM. Table 11 gives pin definitions for interfacing to EDO DRAM. Pin Signal Name DRAM Data[15..0] DRAM Address[11..0] DR_RAS_L DR_CAS_L M_WE_L DR_CKO DR_CKE DR_BS_L M_AP_OE O Type B Memory Data Bus. Description 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 20, 21, 22, 23, 24 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 37 39 41 43 45 46 47 Memory Address Bus. Connect in order starting with DR_Addr[0] to all RAM address pins not already connected to DR_BS_L or DR_AP. Memory Row Address Strobe Memory Column Address Strobe Memory Write Enable SDRAM Clock SDRAM Clock Enable Bank Selection. Always connect to RAM BS or BS0 pin. Memory Auto Pre-charge. Always connect to RAM AP pin. O O O O O O O Table 10. SDRAM Interface Pin 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 20, 21, 22, 23, 24 Signal Name DRAM Data[15..0] Type B Memory Data Bus. Description Table 11. EDO DRAM Interface DS553PP1 31 CS7410 Pin 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 37 39 41 47 Signal Name DRAM Address[11..0] DR_RAS_L DR_CAS_L M_WE_L M_AP_OE Type O Memory Address Bus. Description O O O O Memory Row Address Strobe Memory Column Address Strobe Memory Write Enable Memory Output Enable Table 11. EDO DRAM Interface (Continued) 4.5 ROM/NVRAM Interface The ROM/NVRAM Interface pins are described in Table 12. This interface connects to the non-volatile memory that contains the firmware. The memory could be ROM, NVRAM (FLASH), EEPROM, or any combination of these memory types. This interface can also connect to SRAM that would emulate a ROM on a development system. The bus width is always 8 bits. Most of these pins are shared with the DRAM interface, which operates simultaneously with the ROM/NVRAM interface. A number of pins are defined to accept configuration input at power-up (see Table 7), allowing different branches to be taken in the firmware. A configuration resistor is required on pin PCM_DO_0 to select whether the processor will boot from internal or external ROM. Pin Signal Name NVMem Data[7..0] NVM_Addr[11..0] Type B O Description Memory Data Bus (shared with bits [7:0] of DRAM data bus). Memory Address Bus[11..0] (shared with DRAM address bus) Memory Address Bus[19..12] (shared with bits [15..8] of DRAM data bus). Memory Address Bus[20] (DRAM BS_L pin). NVRAM Write Enable (shared with DRAM WE_L pin) NVRAM Write Enable (shared with DRAM WE_L pin) ROM/NVRAM Chip Enable. 11, 13, 15, 20, 21, 22, 23, 24 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 3, 4, 5, 6, 7, 8, 9, 10 46 41 47 48 NVM_Addr[19..12] NVM_Addr[20] NVM_WE_L NVM_OE_L NVM_CE_L O O O O O Table 12. ROM/NVRAM Interface 32 DS553PP1 CS7410 4.6 Digital Audio Output Interface The Digital Audio Output Interface pins are described in Table 13. This is the audio PCM interface that connects to an audio PCM DAC. The sample rate and the size of the samples are programmable to accommodate any commercially available DAC. The CS7410 has two data output pins, for up to 4 channels of PCM output, and a separate output pin to simultaneously output IEC-958 encoded data (either compressed or uncompressed). Pin 78 77 Signal Name PCM_XCK SERVOCK Type B I Description Audio 256x/384x/512x Clock input or output to Serial DAC. When output, it’s generated from CS7410 internal PLL. Optional source of Audio 256x/384x/512x Audio Clock. May be used for CD direct audio to match input and output clocks. Audio Mute control to external DAC. Polarity is programmable and is three-stated at power up. Audio Bit Clock output to serial DAC. Polarity is programmable. Audio Out Left/Right Clock to serial DAC. Audio Serial PCM Data Out[0]. Audio Serial PCM Data Out[1]. IEC-958 Output 79 92 93 94 95 96 PCM_MUTE PCM_BCK PCM_LRCK PCM_DO_0 PCM_DO_1 IEC958_O O O O O O O Table 13. Audio Output Interface 4.7 ∆Σ Modulator Interface The ∆Σ Interface pins are described in Table 14. The CS7410 contains a stereo Delta-Sigma (∆Σ) modulator, which outputs two differential digital signals on four pins. These outputs are design to drive an external op-amp based integrator circuit (contact Cirrus Logic Applications Engineering for details). Pin 84 85 87 89 Signal Name DAC_LP DAC_LN DAC_RP DAC_RN Type O O O O Description ∆Σ left channel, positive output ∆Σ left channel, negative output ∆Σ right channel, positive output ∆Σ right channel, positive output Table 14. ∆Σ Output Interface DS553PP1 33 CS7410 4.8 CD Interface The CD Interface pins are described in Table 15. This interface is used to read serial CD data from a CD servo/read channel chip. The interface supports all standard formats, including 16 MHz, 24 MHz and 32 MHz clocks per container. Control of the CD servo chip is done by the RISC processor using GPIOs, and CD subcode data is read using the dedicated serial interface (SER3). Pin 81 82 83 80 Signal Name CD_BCLK CD_LRCK CD_DATA CD_C2P0 Type I I I I Description CD clock input – polarity is programmable CD left-right clock input CD serial data input CD error signaling input Table 15. CD Interface 34 DS553PP1 CS7410 4.9 General Purpose Input/Output (GPIO) The CS7410 provides a number of General Purpose Input/Output (GPIO) pins, each with individual output three-state controls, and a number of General Purpose Output (GPO) pins. Table 16 shows the 17 dedicated GPIO pins. A naming scheme for these pins was chosen to encourage system designers to adhere to standardized pin usage. Table 17 shows the GPIO and GPO pins that can be redefined from other functions. For redefined pins, mode control register bits select the normal function or GPIO/GPO function for the pins. Table 17 also indicates which mode bit controls each pin. Pin 100, 99, 98, 97 53, 52, 51, 50, 49 58, 57, 56, 55, 54 59 62 63 Signal Name GPIO[3:0] KP_IN[4:0] KP_OUT[4:0] IR_IN SER4_CLK SER4_DAT Type B B B B B B Description 4 General purpose I/O on dedicated pins 5 General purpose I/O on dedicated pins 5 General purpose I/O on dedicated pins General purpose I/O on dedicated pin General purpose I/O on dedicated pin General purpose I/O on dedicated pin Table 16. Dedicated General Purpose I/O Pins Pin 65 67 68 66 69 70 72 74 76 80 77 92 93 94 95 79 84 Signal Name SER2_CLK SER2_DO SER2_CS SER2_DI SER3_CLK SER3_DO SER3_DI SER3_SS0 SER3_SS1 CD_C2P0 SERVOCK PCM_BCK PCM_LRCK PCM_DO_0 PCM_DO_1 PCM_MUTE DAC_LP Type B B B B B B B B B B B O O O O O O Description GPIO controlled by Mode bit 2 GPIO controlled by Mode bit 2 GPIO controlled by Mode bit 2 GPIO controlled by Mode bit 3 GPIO controlled by Mode bit 4 GPIO controlled by Mode bit 4 GPIO controlled by Mode bit 4 GPIO controlled by Mode bit 4 GPIO controlled by Mode bit 5 GPIO controlled by Mode bit 6 GPIO controlled by Mode bit 7 GPO controlled by Mode bit 8 GPO controlled by Mode bit 9 GPO controlled by Mode bit 10 GPO controlled by Mode bit 11 GPO controlled by Mode bit 12 GPO controlled by Mode bit 13 Table 17. Redefined General Purpose Pins DS553PP1 35 CS7410 Pin 85 87 89 96 Signal Name DAC_LN DAC_RP DAC_RN IEC958_O Type O O O B Description GPO controlled by Mode bit 13 GPO controlled by Mode bit 13 GPO controlled by Mode bit 13 GPIO controlled by Mode bit 14 Table 17. Redefined General Purpose Pins (Continued) 4.10 Power and Ground Table 18 describes the power and ground pins. The CS7410 requires 3 different types of power supplies for the PLLs, internal logic, and IO pins. The PLLs and internal logic use 1.8 V supply voltage. The IO pins use 3.3 V supply voltage. An optional separate supply can be used to provide clean 3.3 V to the Sigma-Delta DACs digital output pads. It is recommended that you use good layout techniques to provide isolation between the supply types on the board. Contact Cirrus Logic applications engineering for layout guidelines. Pin Signal Name PLL_GND PLL_1V8 CORE_GND CORE_1V8 IO_GND IO_3V3 DAC_3V3 Type Description Ground for internal PLLs 1.8V for internal PLLs Ground for internal core logic 1.8V for internal core logic Ground for Digital I/Os 3.3V for Digital I/Os 3.3V for Sigma Delta DAC Digital I/Os Table 18. Power and Ground 1 2 14, 40, 73 12, 38, 71 19, 42, 64, 86 16, 44, 75 88 36 DS553PP1 CS7410 DS553PP1 37 CS7410 5. 100-PIN MQFP PACKAGE SPECIFICATIONS (20X14X2.85mm) 23.200 ± 0.250 20.000 ± 0.100 51 50 81 80 100 30 31 1 A 1.35 ± 0.05 0.150±0.008 0.200 (MIN) 0 .310 ± 0.050 0.650 ± 0.150 Note: Measurement Units = mm DETAIL A 1.600 ± 0.150 Figure 18. 100-Pin MQFP Package (20x14x2.85mm) 38 2.85 ± 0.127 3.300 (MAX) 0~8 ° 0.800 ± 0.150 17.200 ± 0.250 14.000 ± 0.100 DS553PP1 CS7410 6. 100-PIN LQFP PACKAGE SPECIFICATIONS (14X14X1.4mm) Figure 19. 100-Pin LQFP Package (14X14X1.4mm) DS553PP1 39