CS8130

CS8130 11/6/97 CS8130 Revision G Addendum Multi-Standard Infrared Transceiver (DS134F1, SEP ‘05) The following items represent permanent changes to the specification of the CS8130 IR transceiver. 1) The Silicon Revision Register (Register 28) reads 0010, indicating rev G silicon. 2) The default receive sensitivity setting is changed to 00011 (Register 6 resets to 0011). 3) Oscillator low power mode is now the default condition after reset (Register 21 resets to 0100). 4) The BLKR bit (Register 4, bit D2) blocks the RXD output data during those periods when the transmit LEDs are on. This prevents the UART/system reading the transmitted data. The re-enable signal for the receiver is delayed by 8 µs from when the LEDs are turned off. Set to 1 to block RXD data, set to 0 to allow RXD data through during transmission. This bit goes to 0 upon RESET. 5) An additional control bit was added which causes the CS8130 receiver to ignore the falling edge of the IR pulse. This bit is called ENPOS, and it is bit D2 of Register #7. ENPOS is normally 1, which causes the falling edge to be ignored. This results in greater range in IrDA and high-frequency ASK (Sharp 500 kHz) modes. ENPOS should be set to 0 for low-frequency amplitude modulated modes. 6) For IrDA/HP-SIR pulse width modes, two additional control bits have been added: a. The THIN bit (Register 7, bit D1) allows the minimum acceptable pulse width to be reduced from 1 µs to 0.5 µs when set to 1. This bit has effect only when the receiver is programmed to mode 1a (fixed 1.6 µs pulses only) or 1c (receive 1.6 µs to 3/16 of a bit cell pulses). This bit resets to 0. b. The WIDE bit (Register 1, Bit D2) expands the maximum allowable pulse width to 9/16 of a bit cell when set to 1. This bit has effect only when the receiver is set to mode 1a (fixed 1.6 µs pulses only). For normal IrDA operation, it is recommended that THIN be set to 0 and WIDE be set to 1. Under these conditions, the qualification boundaries for receiver mode 1c (receive 1.6 µs to 3/16 of a bit cell pulses) are identical to the qualification boundaries for receiver mode 1a (fixed 1.6 µs pulses only). This bit resets to 1. 7) A TV remote receive mode hesitate bit has been added (Register 1, Bit D3). When this bit is set to 0, the RXD pin will remain high until the first valid IR signal is detected. At that time, the RXD pin will output serial data at the specified baud rate until the receiver is disabled (Register 0, bit D1). If this bit is set to 1, the RXD pin will immediately and continuously output data. This bit resets to 0. 8) The ASK transmit carrier frequency formula has changed: MD=(3.6864E6/FR)-2 , where MD is the Modulator Divider Value and FR is the desired modulation frequency (Registers 10 & 11). The RESET default value for MD is now 5, yielding a default carrier Cirrus Logic, Inc. P.O. Box 17847, Austin, Texas 78760 http://www.cirrus.com (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com Copyright © Cirrus Logic, irrus2005 Inc. 1997 Copyright © C Inc. Logic, Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) Reserved) (All Rights Reserved) (All Rights MAR ‘05 SEP ‘06 DS134PP2-B DS134F1-B1 DS134F1-B NOV ‘97 1 CS8130 frequency of 527 kHz. 9) ASK Receive Choices - valid incoming frequency range (with RATS = 0 and MD = 5) is 431 kHz to 609 kHz. 10) RATS register control of receive data frequency window period is now: T(min) ~= [(2*MD)+3+RATS]*135ns T(max) ~= [(2*MD)+3+(6*(RATS+1))]*135ns 11) Clarification: the IrDA/HP-SIR baud rate can be as low as 1200 bps. 12) Specifications in the following tables replace those found in the SEP ’05 CS8130 data sheet (DS134F1). POWER SUPPLY SPECIFICATIONS (TA = 25 °C; V+ = 3.0 V, Digital Input Levels: Logic 0 = 0 V, Logic 1 = V+, Note 1) Parameter Power Supply Voltage Power Supply Current - All functions enabled Power Supply Current - All functions disabled Power Supply Current - Receiver only enabled Power Supply Current - Transmit only enabled Oscillator Power Supply Current Data & State Retention Supply Voltage (Note 2) (Note 3) (Note 2) (Note 4) Symbol Min 2.7 2 Typ 3.0 2.7 0.3 2.0 0.7 0.45 1.3 Max 5.5 3.3 1 2.8 1.5 1.3 2.2 Unit V mA µA mA mA mA mA V low power mode: normal power mode: Notes: 1. Power supply current specifications are with the supply at 3.0 V. For approximate consumption at +5.0 V, multiply the above currents by 1.667. 2. Oscillator in low power mode; does not include LED current. Subtract oscillator current if using an external clock to run the CS8130. 3. Floating digital inputs will not cause the power supply to increase beyond the specification. 4. Does not include LED current, does include oscillator current in low power mode. 2 2 DS134F1-B1 DS134F1-B DS134PP2-B CS8130 RECEIVER CHARACTERISTICS (TA = 25 °C; V+ = 3.0 V, Digital Input Levels: Logic 0 = 0 V, Logic 1 = V+; unless otherwise specified) Parameter Input capacitance Input noise current Maximum signal input current from detector Maximum DC input current (typically sunlight) Input current detection thresholds (Programmable with a 5 bit value) (Note 6) RS4-0 = 00010 RS4-0 = 00011 RS4-0 = 00101 RS4-0 = 00111 RS4-0 = 11111 High Pass -3dB Low Pass -3dB With high (100 µA) dc ambient With normal (2 µA) dc ambient (Note 7) (Note 5) Symbol Min Typ 10 98 114 156 197 724 200 900 5 0.3 5 Max 11 2 100 10 1 10 Unit pF pA/rtHz mA µA nA nA nA nA nA kHz kHz ms ms ms Bandpass filter response Receiver power-up time Turn-around time, with receiver on continuously Notes: 5. Typical PIN diode junction capacitance is 70 pF. 6. The temperature coefficient of the receiver threshold setting is low. Current detection thresholds are above the DC ambient condition. Settings of RS4-0 of less than 00010 are not practical because of noise. RX threshold settings are roughly linear following the formula: Threshold (nA) = (RX setting + 1) * 20 + 36. 7. Turn-around time is the time taken for the PIN diode receiver to recover from the IR energy from the local transmitter. The remote end of the link must wait for this time after receiving data before transmitting a reply. This time may be reduced to