CS8415A-CS

CS8415A 96 kHz Digital Audio Interface Receiver Features ! Complete EIAJ CP1201, IEC-60958, AES3, General Description The CS8415A is a monolithic CMOS device which receives and decodes one of 7 channels of audio data according to the IEC60958, S/PDIF, EIAJ CP1201, or AES3. The CS8415A has a serial digital audio output port and comprehensive control ability through a 4-wire microcontroller port. Channel status and user data are assembled in block-sized buffers, making read access easy. A low-jitter clock recovery mechanism yields a very clean recovered clock from the incoming AES3 stream. Stand-alone operation allows systems with no microcontroller to operate the CS8415A with dedicated output pins for channel status data. The CS8415A is available in a 28-pin TSSOP and SOIC package in both Commerical (-10 to +70°C) and Industrial grades (-40 to +85° C). The CDB8415A Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to page 2 for ordering information. Target applications include A/V receivers, CD-R, DVD receivers, multimedia speakers, digital mixing consoles, effects processors, set-top boxes, and computer and automotive audio systems. S/PDIF-compatible Receiver ! +5.0 V Analog Supply (VA+) ! +3.3 V or +5.0 V Digital Interface (VL+) ! 7:1 S/PDIF Input MUX ! Flexible 3-wire Serial Digital Output Port ! 8-kHz to 96-kHz Sample Frequency Range ! Low-jitter Clock Recovery ! Pin and Microcontroller Read Access to Channel Status and User Data ! Microcontroller and Standalone Modes ! Differential Cable Receiver ! On-chip Channel Status and User Data Buffer Memories ! Auto-detection of Compressed Audio Input Streams ! Decodes CD Q Sub-Code ! OMCK System Clock Mode VA+ AGND FILT RERR RMCK VL+ DGND OMCK RXN0 Receiver Clock & Data Recovery 7:1 MUX AES3 S/PDIF Decoder C & U bit Data Buffer Serial Audio Output RXP6 RXP5 RXP4 RXP3 RXP2 RXP1 RXP0 OLRCK OSCLK SDOUT Misc. Control Control Port & Registers H/S RST EMPH U SDA/ SCL/ AD1/ AD0/ INT CDOUT CCLK CDIN CS http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) AUGUST '05 DS470F4 CS8415A ORDERING INFORMATION Product Description Package Grade Temp Range Pb-Free YES 28TSSOP CS8415A Container Rail Rail Tape and Reel Rail Tape and Reel Rail Rail Tape and Reel - Order Number CS8415A-CZZ CS8415A-CZ CS8415A-CZR CS8415A-IZZ CS8415A-IZZR CS8415A-CSZ CS8415A-CS CS8415A-CSR CDB8415A DS470F4 Commercial -10 to +70°C NO Industrial -40 to +85°C YES YES Tape and Reel CS8415A-CZZR 96 kHz Digital Audio Interface Receiver 28-SOIC Commercial -10 to +70°C NO CDB8415A CS8415A Evaluation Board Tape and Reel CS8415A-CSZR - - - 2 CS8415A TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 6 SPECIFIED OPERATING CONDITIONS .............................................................................................. 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 DC ELECTRICAL CHARACTERISTICS ............................................................................................... 6 DIGITAL INPUT CHARACTERISTICS .................................................................................................. 7 DIGITAL INTERFACE SPECIFICATIONS ............................................................................................ 7 SWITCHING CHARACTERISTICS ....................................................................................................... 7 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS ............................................................. 8 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE................................................... 9 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE.................................................. 10 2. TYPICAL CONNECTION DIAGRAM .................................................................................................. 11 3. GENERAL DESCRIPTION .................................................................................................................. 12 3.1 AES3 and S/PDIF Standards Documents .................................................................................... 12 4. SERIAL AUDIO OUTPUT PORT ......................................................................................................... 13 5. AES3 RECEIVER ................................................................................................................................ 15 5.1 7:1 S/PDIF Input Multiplexer ......................................................................................................... 15 5.2 OMCK System Clock Mode .......................................................................................................... 15 5.3 PLL, Jitter Attenuation, and Varispeed ......................................................................................... 15 5.4 Error Reporting and Hold Function ............................................................................................... 15 5.5 Channel Status Data Handling ..................................................................................................... 16 5.6 User Data Handling ...................................................................................................................... 16 5.7 Non-Audio Auto-Detection ............................................................................................................ 16 5.8 Mono Mode Operation .................................................................................................................. 17 6. CONTROL PORT DESCRIPTION AND TIMING ................................................................................ 18 6.1 SPITM Mode ................................................................................................................................. 18 6.2 I²C Mode ....................................................................................................................................... 19 6.3 Interrupts ...................................................................................................................................... 19 7. CONTROL PORT REGISTER SUMMARY ......................................................................................... 20 7.1 Memory Address Pointer (MAP) ................................................................................................... 20 8. CONTROL PORT REGISTER BIT DEFINITIONS .............................................................................. 21 8.1 Control 1 (01h) ............................................................................................................................ 21 8.2 Control 2 (02h) .............................................................................................................................. 21 8.3 Clock Source Control (04h) .......................................................................................................... 22 8.4 Serial Audio Output Port Data Format (06h) ................................................................................. 22 8.5 Interrupt 1 Status (07h) (Read Only) ............................................................................................ 23 8.6 Interrupt 2 Status (08h) (Read Only) ............................................................................................ 24 8.7 Interrupt 1 Mask (09h) .................................................................................................................. 24 8.8 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh) ..................................................... 24 8.9 Interrupt 2 Mask (0Ch) .................................................................................................................. 24 8.10 Interrupt 2 Mode MSB (0Dh) and Interrupt 2 Mode LSB (0Eh) ................................................... 25 8.11 Receiver Channel Status (0Fh) (Read Only) .............................................................................. 25 8.12 Receiver Error (10h) (Read Only) ............................................................................................... 26 8.13 Receiver Error Mask (11h) .......................................................................................................... 26 8.14 Channel Status Data Buffer Control (12h) .................................................................................. 27 8.15 User Data Buffer Control (13h) ................................................................................................... 27 8.16 Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only) ........................................................ 28 8.17 OMCK/RMCK Ratio (1Eh) (Read Only) ...................................................................................... 28 8.18 C-bit or U-bit Data Buffer (20h - 37h) .......................................................................................... 28 8.19 CS8415A I.D. and Version Register (7Fh) (Read Only) ............................................................. 28 9. PIN DESCRIPTION - SOFTWARE MODE .......................................................................................... 29 10. HARDWARE MODE .......................................................................................................................... 31 10.1 Serial Audio Port Formats .......................................................................................................... 31 11. PIN DESCRIPTION - HARDWARE MODE ....................................................................................... 32 12. APPLICATIONS ............................................................................................................................... 34 12.1 Reset, Power Down and Start-Up .............................................................................................. 34 12.2 ID Code and Revision Code ....................................................................................................... 34 12.3 Power Supply, Grounding, and PCB Layout .............................................................................. 34 DS470F4 3 CS8415A 13. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS .......................... 35 13.1 AES3 Receiver External Components ........................................................................................ 35 13.2 Isolating Transformer Requirements .......................................................................................... 36 14. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........................ 37 14.1 AES3 Channel Status (C) Bit Management ................................................................................ 37 14.2 Accessing the E Buffer ............................................................................................................... 37 14.2.1 Reserving the First 5 Bytes in the E Buffer .................................................................... 38 14.2.2 Serial Copy Management System (SCMS) .................................................................... 38 14.2.3 Channel Status Data E Buffer Access ........................................................................... 38 14.2.3.1 One-Byte Mode .................................................................................................. 38 14.2.3.2 Two-Byte Mode .................................................................................................. 39 14.3 AES3 User (U) Bit Management ................................................................................................. 39 15. APPENDIX C: PLL FILTER ............................................................................................................... 40 15.1 General ....................................................................................................................................... 40 15.2 External Filter Components ........................................................................................................ 41 15.2.1 General .......................................................................................................................... 41 15.2.2 Capacitor Selection ........................................................................................................ 41 15.2.3 Circuit Board Layout ...................................................................................................... 41 15.3 Component Value Selection ....................................................................................................... 42 15.3.1 Identifying the Part Revision .......................................................................................... 42 15.3.2 External Components .................................................................................................... 42 15.3.3 Jitter Tolerance .............................................................................................................. 43 15.3.4 Jitter Attenuation ............................................................................................................ 44 16. REVISION HISTORY ........................................................................................................................ 45 4 DS470F4 CS8415A LIST OF FIGURES Figure 1. Audio Port Master Mode Timing ................................................................................................... 8 Figure 2. Audio Port Slave Mode and Data Input Timing............................................................................. 8 Figure 3. SPI Mode Timing .......................................................................................................................... 9 Figure 4. I²C Mode Timing ......................................................................................................................... 10 Figure 5. Recommended Connection Diagram for Software Mode ........................................................... 11 Figure 6. Serial Audio Output Example Formats........................................................................................ 14 Figure 7. AES3 ReceiverTiming for C & U Pin Output Data ...................................................................... 17 Figure 8. Control Port Timing in SPI Mode ................................................................................................ 18 Figure 9. Control Port Timing in I²C Mode ................................................................................................. 19 Figure 10. Hardware Mode ........................................................................................................................ 31 Figure 11. Professional Input Circuit .......................................................................................................... 36 Figure 12. Transformerless Professional Input Circuit ............................................................................... 36 Figure 13. Consumer Input Circuit ............................................................................................................. 36 Figure 14. S/PDIF MUX Input Circuit ......................................................................................................... 36 Figure 15. TTL/CMOS Input Circuit............................................................................................................ 36 Figure 16. Channel Status Data Buffer Structure....................................................................................... 37 Figure 17. Flowchart for Reading the E Buffer........................................................................................... 38 Figure 18. PLL Block Diagram ................................................................................................................... 40 Figure 19. Recommended Layout Example............................................................................................... 41 Figure 20. Jitter Tolerance Template ......................................................................................................... 43 Figure 21. Revision A................................................................................................................................. 44 Figure 22. Revision A1............................................................................................................................... 44 Figure 23. Revision A2 using A1 Values.................................................................................................... 44 Figure 24. Revision A2 using A2* Values .................................................................................................. 44 LIST OF TABLES Table 1. Control Register Map Summary................................................................................................... 20 Table 2. Equivalent Software Mode Bit Definitions .................................................................................... 31 Table 3. Hardware Mode Start-Up Options................................................................................................ 31 Table 4. Second Line Part Marking............................................................................................................ 42 Table 5. Fs = 8 to 96 kHz ........................................................................................................................... 42 Table 6. Fs = 32 to 96 kHz ......................................................................................................................... 42 Table 7. Revision History ........................................................................................................................... 45 DS470F4 5 CS8415A 1. CHARACTERISTICS AND SPECIFICATIONS All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C. SPECIFIED OPERATING CONDITIONS AGND, DGND = 0 V, all voltages with respect to 0 V. Parameter Power Supply Voltage Symbol (Note 1) VA+ VL+ TA Min 4.5 2.85 -10 -40 Typ 5.0 3.3 or 5.0 - Max 5.5 5.5 +70 +85 Units V V °C Ambient Operating Temperature: Commercial Grade Industrial Grade Notes: 1. I²C protocol is supported only in VL+ = 5.0 V mode. ABSOLUTE MAXIMUM RATINGS AGND, DGND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Power Supply Voltage Input Current, Any Pin Except Supplies Input Voltage Ambient Operating Temperature (power applied) Storage Temperature Symbol VL+,VA+ (Note 2) Iin Vin TA Tstg Min -0.3 -55 -65 Max 6.0 ±10 (VL+) + 0.3 125 150 Units V mA V °C °C 2. Transient currents of up to 100 mA will not cause SCR latch-up. DC ELECTRICAL CHARACTERISTICS AGND = DGND = 0 V; all voltages with respect to 0 V. Parameters Power-down Mode (Note 3) Supply Current in power down VA+ VL+ = 3.3 V VL+ = 5.0 V Symbol Min - Typ 20 60 60 6.3 30.1 46.5 6.6 44.8 76.6 Max - Units µA µA µA mA mA mA mA mA mA Normal Operation (Note 4) Supply Current at 48 kHz frame rate VA+ VL+ = 3.3 V VL+ = 5.0 V VA+ VL+ = 3.3 V VL+ = 5.0 V Supply Current at 96 kHz frame rate 3. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 4. Normal operation is defined as RST = HI. 6 DS470F4 CS8415A DIGITAL INPUT CHARACTERISTICS Parameters Input Leakage Current Differential Input Voltage, RXP0 to RXN0 Symbol Iin VTH Min - Typ ±1 200 Max ±10 - Units µA mV DIGITAL INTERFACE SPECIFICATIONS AGND = DGND = 0 V; all voltages with respect to 0 V. Parameters High-Level Output Voltage (IOH = -3.2 mA) Low-Level Output Voltage (IOH = 3.2 mA) High-Level Input Voltage, except RXn Low-Level Input Voltage, except RXn Symbol VOH VOL VIH (Note 5) VIL Min (VL+) - 1.0 2.0 -0.3 Max 0.4 (VL+) + 0.3 0.4/0.8 Units V V V V 5. At 5.0 V mode, VIL = 0.8 V (Max), at 3.3 V mode, VIL =0.4 V (Max). SWITCHING CHARACTERISTICS Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF. Parameter RST pin Low Pulse Width PLL Clock Recovery Sample Rate Range RMCK output jitter RMCK output duty cycle Symbol Min 200 8.0 Typ 200 50 Max 108.0 60 Units µs kHz ps RMS % (Note 6) 40 6. Cycle-to-cycle using 32 to 96 kHz external PLL filter components. DS470F4 7 CS8415A SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF. Parameter OSCLK Active Edge to SDOUT Output Valid Symbol (Note 7) (Note 7) (Note 8) tdpd tsmd tlmd Min 0 0 - Typ 50 - Max 20 10 10 - Units ns ns ns % ns ns ns ns ns Master Mode RMCK to OSCLK active edge delay RMCK to OLRCK delay OSCLK and OLRCK Duty Cycle Slave Mode OSCLK Period OSCLK Input Low Width OSCLK Input High Width OSCLK Active Edge to OLRCK Edge OLRCK Edge Setup Before OSCLK Active Edge (Note 7, 8, 10) (Note 9) tsckw tsckl tsckh tlrckd tlrcks 36 14 14 20 20 Notes 7, 8, 11 7. The active edges of OSCLK are programmable. 8. The polarity OLRCK is programmable. 9. No more than 128 SCLK per frame. 10. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK has changed. 11. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed. O SC LK (o u tp u t) OLRCK (input) O LR C K (o u tp u t) t sm d t RMCK (o u tp u t) H a rd w a re M o d e RMCK (o u tp u t) S o ftw a re M o d e lm d t lrckd OSCLK (input) t lrcks t sckh t sckl t sckw t dpd SDOUT Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing 8 DS470F4 CS8415A SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF. Parameter CCLK Clock Frequency CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN Symbol (Note 12) fsck tcsh tcss tscl tsch tdsu (Note 13) tdh tpd tr1 tf1 (Note 14) (Note 14) tr2 tf2 Min 0 1.0 20 66 66 40 15 - Typ - Max 6.0 50 25 25 100 100 Units MHz µs ns ns ns ns ns ns ns ns ns ns 12. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is dictated by the timing requirements necessary to access the Channel Status and User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should be safe for all possible conditions. 13. Data must be held for sufficient time to bridge the transition time of CCLK. 14. For fsck 3 63 /64, ORR will saturate at the value FFh. Also, there is no hysteresis on ORR. Therefore a small amount of jitter on either clock can cause the LSB ORR[0] to oscillate. ORR7:6 - Integer part of the ratio (Integer value=Integer(SRR[7:6])) ORR5:0 - Fractional part of the ratio (Fraction value=Integer(SRR[5:0])/64) 8.18 C-bit or U-bit Data Buffer (20h - 37h) Either channel status data buffer E or user data buffer E is accessible through these register addresses. 28 DS470F4 CS8415A 8.19 7 ID3 CS8415A I.D. and Version Register (7Fh) (Read Only) 6 ID2 5 ID1 4 ID0 3 VER3 2 VER2 1 VER1 0 VER0 ID3:0 - ID code for the CS8415A. Permanently set to 0100 VER3:0 - CS8415A revision level. Revision A is coded as 0001 DS470F4 29 CS8415A 9. PIN DESCRIPTION - SOFTWARE MODE SDA/CDOUT AD0/CS EMPH RXP0 RXN0 VA+ AGND FILT RST RMCK RERR RXP1 RXP2 RXP3 1 2 3*+ 4* 5* 6* 7* 8* 9* 10* 11* 12 13 14 28 27 26 25 *24 *23 *22 *21 20 19 *18 *17 *16 15 SCL/CCLK AD1/CDIN RXP6 RXP5 H/S VL+ DGND OMCK U INT SDOUT OLRCK OSCLK RXP4 * Pins which remain the same function in all modes. + Pins which require a pull up or pull down resistor to select the desired startup option. Pin Name SDA/CDOUT # 1 Pin Description Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C mode, SDA is the control I/O data line. SDA is open drain and requires an external pull-up resistor to VL+. In SPI mode, CDOUT is the output data from the control port interface on the CS8415A Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8415A into SPI control port mode. With no falling edge, the CS8415A defaults to I²C mode. In I²C mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the CS8415A AD0/CS 2 EMPH 3 Pre-Emphasis (Output) - EMPH is low when the incoming Channel Status data indicates 50/15 ms pre-emphasis. EMPH is high when the Channel Status data indicates no pre-emphasis or indicates preemphasis other than 50/15 ms. This is also a start-up option pin, and requires a 47 kΩ resistor to either VL+ or DGND, which determines the AD2 address bit for the control port in I²C mode AES3/SPDIF Receiver Port (Input) - Differential line receiver inputs carrying AES3 data. RXP0 may be used as a single-ended input as part of 7:1 S/PDIF Input MUX. If RXP0 is used in MUX, RXN0 must be ac coupled to ground. Additional AES3/SPDIF Receiver Port (Input) - Single-ended receiver inputs carrying AES3 or S/PDIF digital data. These inputs, along with RXP0, comprise the 7:1 S/PDIF Input Multiplexer and select line control is accessed using the MUX2:0 bits in the Control 2 register. Please note that any unused inputs should be tied to ground. See Appendix A for recommended input circuits. Positive Analog Power (Input) - Positive supply for the analog section. Nominally +5.0 V. This supply should be as quiet as possible since noise on this pin will directly affect the jitter performance of the recovered clock RXP0 RXN0 4 5 12 13 14 15 25 26 6 RXP1 RXP2 RXP4 RXP6 RXP3 RXP5 VA+ 30 DS470F4 CS8415A Pin Name AGND FILT # 7 8 Pin Description Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be connected to a common ground area under the chip. PLL Loop Filter (Output) - An RC network should be connected between this pin and ground. See “Appendix C: PLL Filter” on page 41 for recommended schematic and component values. Reset (Input) - When RST is low, the CS8415A enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in hardware mode with multiple CS8415A devices where synchronization between devices is important Input Section Recovered Master Clock (Output) - Input section recovered master clock output when PLL is used. Frequency defaults to 256x the sample rate (Fs) and may be set to 128x. Receiver Error (Output) - When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that can cause RERR to go high are: validity, parity error, bi-phase coding error, confidence, QCRC and CCRC errors, as well as loss of lock in the PLL. Each condition may be optionally masked from affecting the RERR pin using the Receiver Error Mask Register. The RERR pin tracks the status of the unmasked errors: the pin goes high as soon as an unmasked error occurs and goes low immediately when all unmasked errors go away. RST 9 RMCK 10 RERR 11 OSCLK OLRCK SDOUT 16 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin 17 Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin. Frequency will be the output sample rate (Fs) 18 Serial Audio Output Data (Output) - Audio data serial output pin Interrupt (Output) - Indicates errors and key events during the operation of the CS8415A. All bits affecting INT may be unmasked through bits in the control registers. The condition(s) that initiated interrupt 19 are readable through a control register. The polarity of the INT output, as well as selection of a standard or open drain output, is set through a control register. Once set true, the INT pin goes false only after the interrupt status registers have been read and the interrupt status bits have returned to zero INT U OMCK 20 User Data (Output) - Outputs User data from the AES3 receiver, see Figure 7 for timing information System Clock (Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the 21 Control 1 register, the clock signal input on this pin is output through RMCK. OMCK serves as reference signal for OMCK/RMCK ratio expressed in register 1Eh DGND VL+ 22 Digital Ground (Input) - Ground for the digital circuitry in the chip. DGND and AGND should be connected to a common ground area under the chip. 23 Positive Digital Power (Input) - Positive supply for the digital section. Typically +3.3 V or +5.0 V. Hardware/Software Mode Control (Input) - Determines the method of controlling the operation of the CS8415A, and the method of accessing CS and U data. In software mode, device control and CS and U 24 data access is primarily through the control port, using a microcontroller. Hardware mode provides an alternate mode of operation and access to the CS and U data through dedicated pins. This pin should be permanently tied to VL+ or DGND H/S AD1/CDIN SCL/CCLK 27 28 Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input) - In I²C mode, AD1 is a chip address pin. In SPI mode, CDIN is the input data line for the control port interface Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and out of the CS8415A. In I²C mode, SCL requires an external pull-up resistor to VL+ DS470F4 31 CS8415A 10.HARDWARE MODE The CS8415A has a hardware mode which allows using the device without a microcontroller. Hardware mode is selected by connecting the H/S pin to VL+. Various pins change function in hardware mode, described in the hardware mode pin definition section. Hardware mode data flow is shown in Figure 10. Audio data is input through the AES3 receiver, and routed to the serial audio output port. The PRO, COPY, ORIG, EMPH, and AUDIO channel status bits are output on pins. The decoded C and U bits are also output, clocked at both edges of OLRCK (master mode only, see Figure 7).The current audio sample is passed unmodified to the serial audio output port if the validity bit is high, or a parity, bi-phase, or PLL lock error occurs. 10.1 Serial Audio Port Formats In hardware mode, only a limited number of alternative serial audio port formats are available. Table 2 defines the equivalent software mode bit settings for each format. Start-up options are shown in Table 3, and allow choice of the serial audio output port as a master or slave, and the serial audio port format. SOSF SORES1/0 00 00 00 11 SOJUST 0 0 1 0 SODEL 0 1 0 0 SOSPOL SOLRPOL 0 0 0 0 0 1 0 0 OF1 - Left Justified OF2 - I²S 24-bit data OF3 - Right Justified, master mode only OF4 - Direct AES3 data 0 0 0 0 Table 2. Equivalent Software Mode Bit Definitions SDOUT LO HI - ORIG LO LO HI HI EMPH LO HI LO HI Function Serial Output Port is Slave Serial Output Port is Master Left Justified I²S 24-bit data Right Justified Direct AES3 data Table 3. Hardware Mode Start-Up Options VL+ H/S RXP RXN AES3 Rx & Decoder Serial Audio Output OLRCK OSCLK SDOUT C & U bit Data Buffer C U RM CK RERR NVERR CHS COPY ORIG EM PH PRO AUDIO RCBL Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT) are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details. Figure 10. Hardware Mode 32 DS470F4 CS8415A 11.PIN DESCRIPTION - HARDWARE MODE Pin Name COPY VL2+ VL+ VL3+ # Pin Description COPY Channel Status Bit (Output) - Reflects the state of the Copyright Channel Status bit in the incoming 1 AES3 data stream. If the category code is set to General, copyright will be indicated whatever the state of the Copyright bit. 2 23 Positive Digital Power (Input) - Typically +3.3 V or +5.0 V. 27 Pre-Emphasis (Output) - EMPH is low when the incoming Channel Status data indicates 50/15 ms preemphasis. EMPH is high when the Channel Status data indicates no pre-emphasis or indicates pre-empha3 sis other than 50/15 ms. This pin is also a start-up option which, along with ORIG, determines the serial port format. A 47 kΩ resistor to either VL+ or DGND is required. EMPH RXP0 RXN0 VA+ AGND FILT 4 AES3/SPDIF Receiver Port (Input) - Differential line receiver inputs for the AES3 biphase encoded data. 5 See Appendix A for recommended circuits. 6 7 8 Positive Analog Power (Input) - Nominally +5.0 V. This supply should be as quiet as possible since noise on this pin will directly affect the jitter performance of the recovered clock. Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be connected to a common ground area under the chip. PLL Loop Filter (Output) - An RC network should be connected between this pin and ground. See “Appen- dix C: PLL Filter” on page 41 for recommended schematic and component values. RST Reset (Input) - When RST is low, the CS8415A enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in 9 frequency and phase. This is particularly true in hardware mode with multiple CS8415A devices where synchronization between devices is important. DS470F4 33 CS8415A Pin Name RMCK # Pin Description 10 Recovered Master Clock (Output) - Recovered master clock output when PLL is locked to the incoming AES3 stream. Frequency is 256x the sample rate (Fs). Receiver Error (Output) - When high, indicates an error condition in the AES3 receiver. The status of this RERR 11 pin is updated once per sub-frame of incoming AES3 data. Conditions that can cause RERR to go high are: validity bit high, parity error, bi-phase coding error, and loss of lock by the PLL. Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status block. RCBL goes high two frames after the reception of a Z preamble, remains high for 16 frames while COPY, 12 ORIG, AUDIO, EMPH and PRO are updated, and returns low for the remainder of the block. RCBL changes on rising edges of RMCK. RCBL PRO 13 PRO Channel Status Bit (Output) - Reflects the state of the Professional/Consumer Channel Status bit in the incoming AES3 data stream. Low indicates Consumer and high indicates Professional. CHS Channel Select (Input) - Selects which sub-frame’s channel status data is output on the EMPH, COPY, 14 ORIG, PRO and AUDIO pins. Channel A is selected when CHS is low, channel B is selected when CHS is high. No Validity Receiver Error Indicator (Output) - A high output indicates a problem with the operation of the NVERR OSCLK OLRCK SDOUT AUDIO DGND3 DGND2 DGND 15 AES3 receiver. The status of this pin is updated once per frame of incoming AES3 data. Conditions that cause NVERR to go high are: parity error, and bi-phase coding error, and loss of lock by the PLL. 16 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin. 17 18 Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin. Frequency will be the output sample rate (Fs). Serial Audio Output Data (Output) - Audio data serial output pin. This pin is also a start-up option which determines if the serial audio port is master or slave. A 47 kΩ resistor to either VL+ or DGND is required. 19 Audio Channel Status Bit (Output) - Reflects the state of the audio/non audio Channel Status bit in the incoming AES3 data stream. When this bit is low a valid audio stream is indicated. 20 Digital Ground (Input) - Ground for the digital circuitry in the chip. DGND and AGND should be connected 21 to a common ground area under the chip. 22 Hardware/Software Mode Control (Input) - Determines the method of controlling the operation of the CS8415A, and the method of accessing CS and U data. In software mode, device control and CS and U 24 data access is primarily through the control port, using a microcontroller. Hardware mode provides an alternate mode of operation and access to the CS and U data through dedicated pins. This pin should be permanently tied to VL+ or DGND. H/S U C 25 26 User Data (Output) - Outputs user data from the AES3 receiver, clocked by the rising and falling edges of OLRCK. Channel Status Data (Output) - Outputs channel status data from the AES3 receiver, clocked by the rising and falling edges of OLRCK. ORIG Original Channel Status (Output) - SCMS generation indicator. This is decoded from the incoming category code and the L bit in the Channel Status bits. A low output indicates that the source of the audio data 28 stream is a copy not an original. A high indicates that the audio data stream is original. This pin is also a start-up option which, along with EMPH, determines the serial audio port format. A 47 kΩ resistor to either VL+ or DGND is required. 34 DS470F4 CS8415A 12. APPLICATIONS 12.1 Reset, Power Down and Start-Up When RST is low, the CS8415A enters a low-power mode and all internal states are reset, including the control port and registers, and the outputs are muted. When RST is high, the control port becomes operational and the desired settings should be loaded into the control registers. Writing a 1 to the RUN bit will then cause the part to leave the low-power state and begin operation. After the PLL has settled, the serial audio outputs will be enabled. Some options within the CS8415A are controlled by a start-up mechanism. During the reset state, some of the output pins are reconfigured internally to be inputs. Immediately upon exiting the reset state, the level of these pins is sensed. The pins are then switched to be outputs. This mechanism allows output pins to be used to set alternative modes in the CS8415A by connecting a 47 kΩ resistor to between the pin and either VL+ (HI) or DGND (LO). For each mode, every start-up option select pin MUST have an external pull-up or pull-down resistor. In software mode, the only start-up option pin is EMPH, which is used to set a chip address bit for the control port in I²C mode. The hardware mode uses many start-up options, which are detailed in the hardware definition section at the end of this data sheet. 12.2 ID Code and Revision Code The CS8415A has a register that contains a 4-bit code to indicate that the addressed device is a CS8415A. This is useful when other CS84xx family members are resident in the same system, allowing common software modules. The CS8415A 4-bit revision code is also available. This allows the software driver for the CS8415A to identify which revision of the device is in a particular system, and modify its behavior accordingly. To allow for future revisions, it is strongly recommend that the revision code is read into a variable area within the microcontroller, and used wherever appropriate as revision details become known. 12.3 Power Supply, Grounding, and PCB Layout For most applications, the CS8415A can be operated from a single +5.0 V supply, following normal supply decoupling practices. See Figure 5. Note that the I²C protocol is supported only in VL+ = 5.0 V mode. For applications where the recovered input clock, output on the RMCK pin, is required to be low-jitter, then use a separate, quiet, analog +5.0 V supply for VA+, decoupled to AGND. In addition, a separate region of analog ground plane around the FILT, AGND, VA+, RXP[0:6] and RXN0 pins is recommended. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be mounted on the same side of the board as the CS8415A to minimize inductance effects, and all decoupling capacitors should be as close to the CS8415A as possible. DS470F4 35 CS8415A 13.APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS 13.1 AES3 Receiver External Components The CS8415A AES3 receiver is designed to accept both the professional and consumer interfaces. The digital audio specifications for professional use call for a balanced receiver, using XLR connectors, with 110 Ω ±20% impedance. The XLR connector on the receiver should have female pins with a male shell. Since the receiver has a very high input impedance, a 110 Ω resistor should be placed across the receiver terminals to match the line impedance, as shown in Figure 11. Although transformers are not required by the AES, they are strongly recommended. If some isolation is desired without the use of transformers, a 0.01 µF capacitor should be placed in series with each input pin (RXP0 and RXN0) as shown in Figure 12. However, if a transformer is not used, highfrequency energy could be coupled into the receiver, causing degradation in analog performance. Figures 11 and 12 show an optional DC blocking capacitor (0.1 µF to 0.47 µF) in series with the cable input. This improves the robustness of the receiver, preventing the saturation of the transformer, or any DC current flow, if a DC voltage is present on the cable. In the configuration of systems, it is important to avoid ground loops and DC current flowing down the shield of the cable that could result when boxes with different ground potentials are connected. Generally, it is good practice to ground the shield to the chassis of the transmitting unit, and connect the shield through a capacitor to chassis ground at the receiver. However, in some cases it is advantageous to have the ground of two boxes held to the same potential, and the cable shield might be depended upon to make that electrical connection. Generally, it may be a good idea to provide the option of grounding or capacitively coupling the shield to the chassis. In the case of the consumer interface, the standards call for an unbalanced circuit having a receiver impedance of 75 Ω ±5%. The connector for the consumer interface is an RCA phono socket. The receiver circuit for the consumer interface is shown in Figure 13. Figure 14 shows an implementation of the input S/PDIF multiplexer using the consumer interface. The circuit shown in Figure 15 may be used when external RS422 receivers, optical receivers or other TTL/CMOS logic outputs drive the CS8415A receiver section. 36 DS470F4 CS8415A 13.2 Isolating Transformer Requirements Please refer to the application note AN134: AES and SPDIF Recommended Transformers for resources on transformer selection. XLR 110 Ω Twisted Pair 1 * See Text 110 Ω CS8415A RXP0 XLR 110 Ω Twisted * See Text 110 Ω 0.01 µF 0.01 µF CS8415A RXP0 RXN0 Pair 1 RXN0 Figure 11. Professional Input Circuit Figure 12. Transformerless Professional Input Circuit .01µF RCA Phono 75 Ω Coax 75 Ω 0.01 µF CS8415A RXP0 75 Ω Coax 75 Ω Coax 75 Ω Coax 75 Ω .01µF 75 Ω .01µF 75 Ω RXP6 RXP5 . . . RXN0 0.01 µF RXP0 RXN0 .01µF Figure 13. Consumer Input Circuit Figure 14. S/PDIF MUX Input Circuit TTL/CMOS Gate 0.01 µF CS8415A RXP0 0.01 µF RXN0 Figure 15. TTL/CMOS Input Circuit DS470F4 37 CS8415A 14.APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT 14.1 AES3 Channel Status (C) Bit Management The CS8415A contains sufficient RAM to store a full block of C data for both A and B channels (192 x 2 = 384 bits), and also 384 bits of U information. The user may read from these buffer RAMs through the control port. The buffering scheme involves 2 block-sized buffers, named D and E, as shown in Figure 16. The MSB of each byte represents the first bit in the serial C data stream. For example, the MSB of byte 0 (which is at control port address 20h) is the consumer/professional bit for channel status block A. A 8-bits From AES3 Receiver B 8-bits D Received Data Buffer E 24 words Control Port Figure 16. Channel Status Data Buffer Structure The first buffer (D) accepts incoming C data from the AES receiver. The 2nd buffer (E) accepts entire blocks of data from the D buffer. The E buffer is also accessible from the control port, allowing reading of the C data. 14.2 Accessing the E Buffer The user can monitor the incoming data by reading the E buffer, which is mapped into the register space of the CS8415A, through the control port. The user can configure the interrupt enable register to cause interrupts to occur whenever D-to-E buffer transfers occur. This allows determination of the allowable time periods to interact with the E buffer. Also provided is a D-to-E inhibit bit. This may be used whenever “long” control port interactions are occurring. 38 DS470F4 CS8415A A flowchart for reading the E buffer is shown in Figure 17. Since a D-to-E interrupt just occurred after reading, there is a substantial time interval until the next D-to-E transfer (approximately 24 frames worth of time). This is usually plenty of time to access the E data without having to inhibit the next transfer. D to E interrupt occurs Optionally set D to E inhibit Read E data If set, clear D to E inhibit Return Figure 17. Flowchart for Reading the E Buffer 14.2.1 Reserving the First 5 Bytes in the E Buffer D-to-E buffer transfers periodically overwrite the data stored in the E buffer. The CS8415A has the capability of reserving the first 5 bytes of the E buffer for user writes only. When this capability is in use, internal D-to-E buffer transfers will NOT affect the first 5 bytes of the E buffer. Therefore, the user can set values in these first 5 E bytes once, and the settings will persist until the next user change. This mode is enabled using the Channel Status Data Buffer Control register. 14.2.2 Serial Copy Management System (SCMS) In software mode, the CS8415A allows read access to all the channel status bits. For consumer mode SCMS compliance, the host microcontroller needs to read and interpret the Category Code, Copy bit and L bit appropriately. In hardware mode, the SCMS protocol can be followed by either using the COPY and ORIG output pins, or by using the C bit serial output pin. These options are documented in the hardware mode section of this data sheet. 14.2.3 Channel Status Data E Buffer Access The E buffer is organized as 24 x 16-bit words. For each word the MS Byte is the A channel data, and the LS Byte is the B channel data (see Figure 16). There are two methods of accessing this memory, known as one byte mode and two byte mode. The desired mode is selected by setting a control register bit. 14.2.3.1 One-Byte Mode In many applications, the channel status blocks for the A and B channels will be identical. In this situation, if the user reads a byte from one of the channel's blocks, the corresponding byte for the other channel will be the same. One byte mode takes advantage of the often identical nature of A and B channel status data. When reading data in one byte mode, a single byte is returned, which can be from channel A or B data, depending on a register control bit. DS470F4 39 CS8415A One-byte mode saves the user substantial control port access time, as it effectively accesses 2 bytes worth of information in 1 byte's worth of access time. If the control port's autoincrement addressing is used in combination with this mode, multi-byte accesses such as full-block reads can be done especially efficiently. 14.2.3.2 Two-Byte Mode There are those applications in which the A and B channel status blocks will not be the same, and the user is interested in accessing both blocks. In these situations, two-byte mode should be used to access the E buffer. In this mode, a read will cause the CS8415A to output two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data. 14.3 AES3 User (U) Bit Management Entire blocks of U data are buffered using a cascade of 2 block-sized RAMs to perform the buffering. The user has access to the second of these buffers, denoted the E buffer, through the control port. The U buffer access only operates in two-byte mode, since there is no concept of A and B blocks for user data. The arrangement of the data is as followings: Bit15[A7]Bit14[B7]Bit13[A6]Bit12[B6]...Bit1[A0]Bit0[B0]. The arrangement of the data in the each byte is that the MSB is the first received bit and is the first transmitted bit. The first byte read is the first byte received, and the first byte sent is the first byte transmitted. If you read two bytes from the E buffer, you will get the following arrangement: A[7]B[7]A[6]B[6]....A[0]B[0]. 40 DS470F4 CS8415A 15.APPENDIX C: PLL FILTER 15.1 General An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure 18 is a simplified diagram of the PLL in these parts. When the PLL is locked to an AES3 input stream, it is updated at each preamble in the AES3 stream. This occurs at twice the sampling frequency, FS. When the PLL is locked to ILRCK, it is updated at FS so that the duty cycle of the input doesn’t affect jitter. There are some applications where low-jitter in the recovered clock, presented on the RMCK pin, is important. For this reason, the PLL has been designed to have good jitter attenuation characteristics, as shown in Figure 21, Figure 22, Figure 23, and Figure 24. In addition, the PLL has been designed to only use the preambles of the AES3 stream to provide lock update information to the PLL. This results in the PLL being immune to data-dependent jitter affects because the AES3 preambles do not vary with the data. The PLL has the ability to lock onto a wide range of input sample rates with no external component changes. If the sample rate of the input subsequently changes, for example in a varispeed application, the PLL will only track up to ±12.5% from the nominal center sample rate. The nominal center sample rate is the sample rate that the PLL first locks onto upon application of an AES3 data stream or after enabling the CS8415A clocks by setting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will return to its wide lock range mode and re-acquire a new nominal center sample rate. INPUT Phase Comparator and Charge Pump VCO RFLT CFLT CRIP RMCK ÷N Figure 18. PLL Block Diagram DS470F4 41 CS8415A 15.2 External Filter Components 15.2.1 General The PLL behavior is affected by the external filter component values. Figure 5 on page 11 shows the recommended configuration of the two capacitors and one resistor that comprise the PLL filter. In Table 6, the component values shown have the highest corner frequency jitter attenuation curve, takes the shortest time to lock, and offers the best output jitter performance. The component values shown in Table 5 allows the lowest input sample rate to be 8 kHz, and increases the lock time of the PLL. Lock times are worst case for an Fsi transition of 96 kHz. 15.2.2 Capacitor Selection The type of capacitors used for the PLL filter can have a significant effect on receiver performance. Large or exotic film capacitors are not necessary as their leads and the required longer circuit board traces add undesirable inductance to the circuit. Surface mount ceramic capacitors are a good choice because their own inductance is low, and they can be mounted close to the FILT pin to minimize trace inductance. For CRIP, a C0G or NPO dielectric is recommended, and for CFILT, an X7R dielectric is preferred. Avoid capacitors with large temperature coefficients, or capacitors with high dielectric constants, that are sensitive to shock and vibration. These include the Z5U and Y5V dielectrics. 15.2.3 Circuit Board Layout Board layout and capacitor choice affect each other and determine the performance of the PLL. Figure 19 contains a suggested layout for the PLL filter components and for bypassing the analog supply voltage. The 0.1 µF bypass capacitor is in a 1206 form factor. RFILT and the other three capacitors are in an 0805 form factor. The traces are on the top surface of the board with the IC so that there is no via inductance. The traces themselves are short to minimize the inductance in the filter path. The VA+ and AGND traces extend back to their origin and are shown only in truncated form in the drawing. AGND 1000 pF CRIP RFLT .1µF CFLT Figure 19. Recommended Layout Example 42 FILT VA DS470F4 CS8415A 15.3 Component Value Selection When transitioning from one revision of the part another, component values may need to be changed. While it is mandatory for customers to change the external PLL component values when transitioning from revision A to revision A1 or from revision A to revision A2, customers do not need to change external PLL component values when transitioning from revision A1 to revision A2, unless the part is used in an application that is required to pass the AES3 or IEC60958-4 specification for receiver jitter tolerance (see Table 6). 15.3.1 Identifying the Part Revision The first line of the part marking on the package indicates the part number and package type (CS8415Axx). Table 4 shows a list of part revisions and their corresponding second line part marking, which indicates what revision the part is. Pre-October 2002 Revision SOIC & TSSOP (10-Digit) A A1 A2 Zxxxxxxxxx Rxxxxxxxxx N/A New SOIC (12-Digit) ZFBAAXxxxxxx RFBAA1xxxxxx RFBAA2xxxxxx New TSSOP (10-Digit) NAAXxxxxxx NAA1xxxxxx NAA2xxxxxx Table 4. Second Line Part Marking 15.3.2 External Components Shown in Table 5 and Table 6 are the external PLL component values for each revision. Values listed for the 32 to 96 kHz Fs range will have the highest corner frequency jitter attenuation curve, take the shortest time to lock, and offer the best output jitter performance. Revision A A1 A2 RFILT (kΩ) 0.909 0.4 0.4 CFILT (µF) 1.8 0.47 0.47 CRIP (nF) 33 47 47 PLL Lock Time (ms) 56 60 60 Table 5. Fs = 8 to 96 kHz Revision A* A1* A2 A2* RFILT (kΩ) 3.0 1.2 1.2 1.6 CFILT (µF) 0.047 0.1 0.1 0.33 CRIP (nF) 2.2 4.7 4.7 4.7 PLL Lock Time (ms) 35 35 35 35 Table 6. Fs = 32 to 96 kHz * Parts used in applications that are required to pass the AES3 or IEC60958-4 specification for receiver jitter tolerance should use these component values. Please note that the AES3 and IEC60958 specifications do not have allowances for locking to sample rates less than 32 kHz. Also note that many factors can affect jitter performance in a system. Please follow the circuit and layout recommendations outlined previously DS470F4 43 CS8415A 15.3.3 Jitter Tolerance Shown in Figure 20 is the Receiver Jitter Tolerance template as illustrated in the AES3 and IEC60958-4 specification. CS8415A parts used with the appropriate external PLL component values (as noted in Table 6) have been tested to pass this template. Figure 20. Jitter Tolerance Template 44 DS470F4 CS8415A 15.3.4 Jitter Attenuation Shown in Figure 21, Figure 22, Figure 23, and Figure 24 are jitter attenuation plots for the various revisions of the CS8415A when used with the appropriate external PLL component values (as noted in Table 6). The AES3 and IEC60958-4 specifications do not have allowances for locking to sample rates less than 32 kHz. These specifications state a maximum of 2 dB jitter gain or peaking. 5 5 0 0 Jitter Attenuation (dB) Jitter Attenuation (dB) −5 −5 −10 −10 −15 −15 −20 −1 10 10 0 10 1 10 Jitter Frequency (Hz) 2 10 3 10 4 10 5 −20 −1 10 10 0 10 1 10 Jitter Frequency (Hz) 2 10 3 10 4 10 5 Figure 21. Revision A Figure 22. Revision A1 5 5 0 0 −5 Jitter Attenuation (dB) −5 Jitter Attenuation (dB) −10 −10 −15 −15 −20 −20 −25 −1 10 10 0 10 1 10 Jitter Frequency (Hz) 2 10 3 10 4 10 5 −25 −1 10 10 0 10 1 10 Jitter Frequency (Hz) 2 10 3 10 4 10 5 Figure 23. Revision A2 using A1 Values Figure 24. Revision A2 using A2* Values DS470F4 45 CS8415A 16.REVISION HISTORY Release PP1 PP2 PP3 PP4 F1 Date November 1999 November 2000 May 2001 January 2003 January 2004 1st Preliminary Release 2nd Preliminary Release 3rd Preliminary Release 4th Preliminary Release Final Release Updated “Appendix C: PLL Filter” on page 41 to include information from errata ER470E2 -Added lead-free device ordering information. -Changed format of Figure 6 on page 14. -Corrected AES3 Direct (Out) format in Figure 6 on page 14 and text reference to AES3 Direct on page 13. -Corrected bit 0 of regitster 04h to default to 0 on page 22. -Changed description of DETC and DETU bits in “Control Port Register Bit Definitions” on page 21. -Removed reference to Block Mode from DETU and DETUI on page 24 and page 27. -Updated “Ordering Information” on page 2. Changes F2 F3 August 2004 December 2004 F4 August 2005 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. 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