CS8416-CZZ

CS8416 192 kHz Digital Audio Interface Receiver Features Complete EIAJ CP1201, IEC-60958, AES3, S/PDIF-Compatible Receiver +3.3 V Analog Supply (VA) +3.3 V Digital Supply (VD) +3.3 V or +5.0 V Digital Interface Supply (VL) 8:2 S/PDIF Input MUX AES/SPDIF Input Pins Selectable in Hardware Mode Three General Purpose Outputs (GPO) Allow Signal Routing Selectable Signal Routing to GPO Pins S/PDIF-to-TX Inputs Selectable in Hardware Mode Flexible 3-wire Serial Digital Output Port 32 kHz to 192 kHz Sample Frequency Range Low-Jitter Clock Recovery Pin and Microcontroller Read Access to Channel Status and User Data SPI™ or I²C® Control Port Software Mode and Stand-Alone Hardware Mode Differential Cable Receiver On-Chip Channel Status Data Buffer Memories Auto-Detection of Compressed Audio Input Streams Decodes CD Q Sub-Code OMCK System Clock Mode See the General Description and Ordering Information on page 2. VA AGND FILT RMCK VD VL DGND OMCK RXN RXP0 RXP1 RXP2 RXP3 RXP4 RXP5 RXP6 RXP7 Receiver Clock & Data Recovery 8:2 MUX TX Passthrough Misc. Control Format Detect AES3 S/PDIF Decoder De-emphasis Filter C & U bit Data Buffer Control Port & Registers Serial Audio Output OLRCK OSCLK SDOUT GPO0 GPO1 AD2/GPO2 n:3 MUX RST SDA/ SCL/ AD1/ AD0/ CDOUT CCLK CDIN CS http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) AUGUST '07 DS578F3 CS8416 General Description The CS8416 is a monolithic CMOS device that receives and decodes one of eight stereo pairs of digital audio data according to the IEC60958, S/PDIF, EIAJ CP1201, or AES3 interface standards. The CS8416 has a serial digital audio output port and comprehensive control ability through a selectable control port in Software Mode or through selectable pins in Hardware Mode. Channel status data are assembled in buffers, making read access easy. GPO pins may be assigned to route a variety of signals to output pins. A low-jitter clock recovery mechanism yields a very clean recovered clock from the incoming AES3 stream. Stand-alone operation allows systems with no microcontroller to operate the CS8416 with dedicated output pins for channel status data. The CS8416 is available in 28-pin TSSOP, SOIC, and QFN packages in Commercial grade (-10° to +70° C) and Automotive grade (-40° to +85° C). The CDB8416 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 59 for complete ordering information. Target applications include A/V receivers, CD-R, DVD receivers, multimedia speakers, digital mixing consoles, effects processors, set-top boxes, and computer and automotive audio systems. 2 DS578F3 CS8416 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 6 SPECIFIED OPERATING CONDITIONS ............................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 6 DC ELECTRICAL CHARACTERISTICS................................................................................................. 7 DIGITAL INPUT CHARACTERISTICS ................................................................................................... 7 DIGITAL INTERFACE SPECIFICATIONS.............................................................................................. 7 SWITCHING CHARACTERISTICS ........................................................................................................ 8 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS............................................................... 9 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE .................................................. 10 SWITCHING CHARACTERISTICS - CONTROL PORT- I²C FORMAT ............................................... 11 2. PIN DESCRIPTION - SOFTWARE MODE .......................................................................................... 12 2.1 TSSOP Pin Description ................................................................................................................. 12 2.2 QFN Pin Description ...................................................................................................................... 14 3. PIN DESCRIPTION - HARDWARE MODE ......................................................................................... 16 3.1 TSSOP Pin Description ................................................................................................................. 16 3.2 QFN Pin Description ...................................................................................................................... 18 4. TYPICAL CONNECTION DIAGRAMS ................................................................................................ 20 5. APPLICATIONS .................................................................................................................................. 22 5.1 Reset, Power-Down and Start-Up ................................................................................................. 22 5.2 ID Code and Revision Code .......................................................................................................... 22 5.3 Power Supply, Grounding, and PCB Layout ................................................................................. 22 6. GENERAL DESCRIPTION .................................................................................................................. 23 6.1 AES3 and S/PDIF Standards Documents ..................................................................................... 23 7. SERIAL AUDIO OUTPUT PORT ......................................................................................................... 23 7.1 Slip/Repeat Behavior ..................................................................................................................... 25 7.2 AES11 Behavior ............................................................................................................................ 26 8. S/PDIF RECEIVER .............................................................................................................................. 27 8.1 8:2 S/PDIF Input Multiplexer ......................................................................................................... 27 8.1.1 General ............................................................................................................................... 27 8.1.2 Software Mode ................................................................................................................... 27 8.1.3 Hardware Mode .................................................................................................................. 28 8.2 OMCK System Clock Mode ........................................................................................................... 28 8.3 Clock Recovery and PLL Filter ...................................................................................................... 28 9. GENERAL PURPOSE OUTPUTS ....................................................................................................... 29 10. ERROR AND STATUS REPORTING ................................................................................................ 30 10.1 General ........................................................................................................................................ 30 10.1.1 Software Mode ................................................................................................................. 30 10.1.2 Hardware Mode ................................................................................................................ 30 10.2 Non-Audio Detection ................................................................................................................... 31 10.2.1 Format Detection .............................................................................................................. 31 10.3 Interrupts ..................................................................................................................................... 31 11. CHANNEL STATUS AND USER-DATA HANDLING ....................................................................... 32 11.1 Software Mode ............................................................................................................................ 32 11.2 Hardware Mode ........................................................................................................................... 32 12. CONTROL PORT DESCRIPTION ..................................................................................................... 33 12.1 SPI Mode ..................................................................................................................................... 33 12.2 I²C Mode ...................................................................................................................................... 34 13. CONTROL PORT REGISTER QUICK REFERENCE ....................................................................... 35 14. CONTROL PORT REGISTER DESCRIPTIONS .............................................................................. 36 14.1 Memory Address Pointer (MAP) .................................................................................................. 36 14.2 Control0 (00h) ............................................................................................................................. 36 14.3 Control1 (01h) ............................................................................................................................. 37 DS578F3 3 CS8416 14.4 Control2 (02h) ............................................................................................................................. 38 14.5 Control3 (03h) ............................................................................................................................. 39 14.6 Control4 (04h) ............................................................................................................................. 39 14.7 Serial Audio Data Format (05h) ................................................................................................... 40 14.8 Receiver Error Mask (06h) ......................................................................................................... 41 14.9 Interrupt Mask (07h) .................................................................................................................... 41 14.10 Interrupt Mode MSB (08h) and Interrupt Mode LSB(09h) ......................................................... 41 14.11 Receiver Channel Status (0Ah) ................................................................................................ 42 14.12 Format Detect Status (0Bh) ....................................................................................................... 42 14.13 Receiver Error (0Ch) ................................................................................................................ 43 14.14 Interrupt 1 Status (0Dh) ............................................................................................................ 44 14.15 Q-Channel Subcode (0Eh - 17h) ............................................................................................... 44 14.16 OMCK/RMCK Ratio (18h) ....................................................................................................... 45 14.17 Channel Status Registers (19h - 22h) ....................................................................................... 45 14.18 IEC61937 PC/PD Burst Preamble (23h - 26h) .......................................................................... 45 14.19 CS8416 I.D. and Version Register (7Fh) ................................................................................... 45 15. HARDWARE MODE .......................................................................................................................... 46 15.1 Serial Audio Port Formats ........................................................................................................... 46 15.2 Hardware Mode Function Selection ............................................................................................ 46 15.3 Hardware Mode Equivalent Register Settings ............................................................................. 47 16. EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS ................................................... 49 16.1 AES3 Receiver External Components ........................................................................................ 49 16.2 Isolating Transformer Requirements ........................................................................................... 49 17. CHANNEL STATUS BUFFER MANAGEMENT ............................................................................... 51 17.1 AES3 Channel Status (C) Bit Management ................................................................................ 51 17.2 Accessing the E Buffer ................................................................................................................ 51 17.2.1 Serial Copy Management System (SCMS) ...................................................................... 51 18. PLL FILTER ....................................................................................................................................... 53 18.1 General ........................................................................................................................................ 53 18.2 External Filter Components ......................................................................................................... 53 18.2.1 General ............................................................................................................................. 53 18.2.2 Capacitor Selection .......................................................................................................... 54 18.2.3 Circuit Board Layout ......................................................................................................... 54 18.2.4 Component Value Selection ............................................................................................. 54 18.2.5 Jitter Attenuation ............................................................................................................... 55 19. PACKAGE DIMENSIONS ................................................................................................................. 56 TSSOP THERMAL CHARACTERISTICS............................................................................................. 57 QFN THERMAL CHARACTERISTICS ................................................................................................. 58 20. ORDERING INFORMATION ............................................................................................................. 59 21. REVISION HISTORY ......................................................................................................................... 60 4 DS578F3 CS8416 LIST OF FIGURES Figure 1. Audio Port Master Mode Timing ................................................................................................... 9 Figure 2. Audio Port Slave Mode and Data Input Timing............................................................................. 9 Figure 3. SPI Mode Timing ........................................................................................................................ 10 Figure 4. I²C Mode Timing ......................................................................................................................... 11 Figure 5. Typical Connection Diagram - Software Mode ........................................................................... 20 Figure 6. Typical Connection Diagram - Hardware Mode .......................................................................... 21 Figure 7. Serial Audio Output Example Formats........................................................................................ 24 Figure 8. AES3 Data Format...................................................................................................................... 25 Figure 9. Receiver Input Structure ............................................................................................................. 27 Figure 10. C/U Data Outputs...................................................................................................................... 32 Figure 11. Control Port Timing in SPI Mode .............................................................................................. 33 Figure 12. Control Port Timing, I²C Slave Mode Write............................................................................... 34 Figure 13. Control Port Timing, I²C Slave Mode Read............................................................................... 34 Figure 14. De-Emphasis Filter Response .................................................................................................. 39 Figure 15. Hardware Mode Data Flow ....................................................................................................... 46 Figure 16. Professional Input Circuit .......................................................................................................... 49 Figure 17. Transformerless Professional Input Circuit ............................................................................... 49 Figure 18. Consumer Input Circuit ............................................................................................................. 50 Figure 19. S/PDIF MUX Input Circuit ......................................................................................................... 50 Figure 20. TTL/CMOS Input Circuit............................................................................................................ 50 Figure 21. Channel Status Data Buffer Structure....................................................................................... 52 Figure 22. Flowchart for Reading the E Buffer........................................................................................... 52 Figure 23. PLL Block Diagram ................................................................................................................... 53 Figure 24. Recommended Layout Example............................................................................................... 54 Figure 25. Jitter Attenuation Characteristics of PLL................................................................................... 55 LIST OF TABLES Table 1. Typical Delays by Frequency Values ........................................................................................... 26 Table 2. Clock Switching Output Clock Rates............................................................................................ 28 Table 3. GPO Pin Configurations............................................................................................................... 29 Table 4. Hardware Mode Start-Up Pin Conditions ..................................................................................... 47 Table 5. Hardware Mode Serial Audio Format Select................................................................................ 48 Table 6. External PLL Component Values ................................................................................................. 54 DS578F3 5 CS8416 1. CHARACTERISTICS AND SPECIFICATIONS All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C. SPECIFIED OPERATING CONDITIONS (AGND, DGND = 0 V, all voltages with respect to 0 V) Parameter Symbol Min Typ Max Units Power Supply Voltage Ambient Operating Temperature: Commercial Grade Automotive Grade VA VD VL TA 3.13 3.13 3.13 -10 -40 3.3 3.3 3.3 or 5.0 - 3.46 3.46 5.25 +70 +85 V V V °C ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.) Parameter Symbol Min Max Units Power Supply Voltage Input Current, Any Pin Except Supplies Input Voltage Ambient Operating Temperature (power applied) Storage Temperature Notes: (Note 1) VA, VD,VL Iin Vin TA Tstg -0.3 -55 -65 6.0 ±10 (VL) + 0.3 125 150 V mA V °C °C 1. Transient currents of up to 100 mA will not cause SCR latch-up. 6 DS578F3 CS8416 DC ELECTRICAL CHARACTERISTICS (AGND = DGND = 0 V; all voltages with respect to 0 V.) Parameters Power-Down Mode (Notes 2, 4) Symbol Min Typ Max Units μA μA μA μA Supply Current in power-down VA VD VL = 3.3 V VL = 5.0 V VA VD VL = 3.3 V VL = 5.0 V VA VD VL = 3.3 V VL = 5.0 V IA ID IL IL IA ID IL IL IA ID IL IL - 10 70 10 12 5.7 5.9 2.8 4.2 9.4 23 7.8 11.8 - Normal Operation (Notes 3, 4) Supply Current at 48 kHz frame rate Supply Current at 192 kHz frame rate mA mA mA mA mA mA mA mA Notes: 2. Power-Down Mode is defined as RST = LO with all clocks and data lines held static. 3. Normal operation is defined as RST = HI. 4. Assumes that no inputs are floating. It is recommended that all inputs be driven high or low at all times. DIGITAL INPUT CHARACTERISTICS (AGND = DGND = 0 V; all voltages with respect to 0 V.) Parameters Symbol Min Typ Max Units μA Input Leakage Current Differential Input Sensitivity, RXP[7:0] to RXN Input Hysteresis IIN VTH VH 0.15 150 - ±0.5 200 1.0 mVpp V DIGITAL INTERFACE SPECIFICATIONS (AGND = DGND = 0 V; all voltages with respect to 0 V.) Parameters Symbol Min Max Units High-Level Output Voltage (IOH = -3.2 mA) Low-Level Output Voltage (IOL = 3.2 mA) High-Level Input Voltage, except RXP[7:0], RXN Low-Level Input Voltage, except RXP[7:0], RXN VOH VOL VIH VIL (VL) - 1.0 2.0 -0.3 0.5 (VL) + 0.3 0.8 V V V V DS578F3 7 CS8416 SWITCHING CHARACTERISTICS (Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Parameter Symbol Min Typ Max Units μS RST Pin Low Pulse Width PLL Clock Recovery Sample Rate Range RMCK Output Jitter RMCK Output Duty-Cycle RMCK/OMCK Maximum Frequency Notes: 200 30 45 50 - 200 50 55 - 200 55 65 50 kHz ps RMS % % MHz (Note 5) (Note 6) (Note 7) 5. Typical RMS cycle-to-cycle jitter. 6. Duty cycle when clock is recovered from biphase encoded input. 7. Duty cycle when OMCK is switched over for output on RMCK. 8 DS578F3 CS8416 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS (Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Parameter Symbol Min Typ Max Units OSCLK/OLRCK Active Edge to SDOUT Output Valid (Note 8) Master Mode RMCK to OSCLK active edge delay (Note 8) RMCK to OLRCK delay (Note 9) OSCLK and OLRCK Duty Cycle Slave Mode OSCLK Period OSCLK Input Low Width OSCLK Input High Width OSCLK Active Edge to OLRCK Edge (Notes 8,9,10) OSCLK Edge Setup Before OSCLK Active-Edge (Notes 8,9,11) Notes: tdpd tsmd tlmd 0 0 36 14 14 10 10 50 - 23 12 12 - ns ns ns % ns ns ns ns ns tsckw tsckl tsckh tlrckd tlrcks 8. In Software Mode the active edges of OSCLK are programmable. 9. In Software Mode the polarity of OLRCK is programmable. 10. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK has changed. 11. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed. O SCLK (o utp ut) OLRCK (input) t lrckd t lrcks t sckh t sckl OLRCK (o utp ut) t sm d RMCK (o utp ut) t OSCLK (input) t sckw lm d SDOUT t dpd Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input DS578F3 9 CS8416 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Parameter Symbol Min Max Unit CCLK Clock Frequency CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN Notes: (Note 12) fsck tcsh tcss tscl tsch tdsu tdh tpd tr1 tf1 tr2 tr2 0 1.0 20 66 66 40 15 - 6.0 50 25 25 100 100 MHz µs ns ns ns ns ns ns ns ns ns ns (Note 13) (Note 14) (Note 14) 12. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is dictated by the timing requirements necessary to access the Channel Status memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate is 32 kHz, so choosing CCLK to be less than or equal to 4.1 MHz should be safe for all possible conditions. 13. Data must be held for sufficient time to bridge the transition time of CCLK. 14. For fsck