EP9315 Data Sheet
FEATURES
•
•
•
•
•
Linux®, Microsoft® Windows® CE-enabled MMU
100-MHz System Bus
MaverickCrunch™ Math Engine
• Floating Point, Integer, and Signal Processing
Instructions
• Optimized for digital music compression and
decompression algorithms.
• Hardware interlocks allow in-line coding.
IrDA Interface
PCMCIA Interface
Touchscreen Interface with ADC
8 x 8 Keypad Scanner
•
One Serial Peripheral Interface (SPI™) Port
•
Peripheral Bus
12-channel DMA
(3) UARTs
w/
IrDA
Clocks &
Timers
MaverickCrunchTM
Interrupts
& GPIO
ARM920T
MaverickKeyTM
(3) USB
Hosts
D-Cache
16KB
Boot
ROM
I-Cache
16KB
Bus
Bridge
MMU
Keypad &
Touch
Screen I/F
USER INTERFACE
Serial
Audio
Interface
•
•
•
•
• 6-channel or 2-channel Serial Audio Interface (I2S)
• 2-channel, Low-cost Serial Audio Interface (AC'97)
• 2 High-resolution PWMs (16 bits each)
Internal Peripherals
• 12 Direct Memory Access (DMA) Channels
• Real-time Clock with Software Trim
• Dual PLL controls all clock domains.
• Watchdog Timer
• Two General-purpose 16-bit Timers
• One General-purpose 32-bit Timer
• One 40-bit Debug Timer
• Interrupt Controller
• Boot ROM
Package
• 352-pin PBGA
•
MaverickKey™ IDs
• 32-bit Unique ID can be used for DRM-compliant
128-bit random ID.
Integrated Peripheral Interfaces
• 32-bit SDRAM Interface (up to 4 Banks)
• 32/16-bit SRAM / FLASH / ROM
• Serial EEPROM Interface
• EIDE (up to 2 devices)
• 1/10/100-Mbps Ethernet MAC
• Three UARTs
• Three-port USB 2.0 Full-speed Host (OHCI)
(12 Mbits per second)
• LCD and Raster Interface with Graphics
Accelerator
COMMUNICATIONS PORTS
•
Enhanced Universal Platform
System-on-Chip Processor
200-MHz ARM920T Processor
• 16-kbyte Instruction Cache
• 16-kbyte Data Cache
Processor Bus
Ethernet
MAC
EIDE
I/F
SRAM & Flash I/F
PCMCIA
Unified
SDRAM I/F
Video/LCD
Controller
Graphics
Accelerator
MEMORY AND STORAGE
Copyright 2010 Cirrus Logic (All Rights Reserved)
http://www.cirrus.com
Mar ‘10
DS638F2
1
EP9315
Enhanced Universal Platform SOC Processor
OVERVIEW
The EP9315 is an ARM920T-based system-on-a-chip
design with a large peripheral set targeted to a variety of
applications:
•
•
•
•
•
•
•
Thin Client Computers for Business and Home
Internet Radio
Internet Access Devices
Industrial Computers
Specialized Terminals
Point-of-sale Terminals
Test and Measurement Equipment
The ARM920T microprocessor core with separate
16-kbyte, 64-way set-associative instruction and data
caches is augmented by the MaverickCrunch™ coprocessor,
enabling
high-speed
floating
point
calculations.
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
A high-performance 1/10/100-Mbps Ethernet media
access controller (EMAC) is included along with external
interfaces to SPI, I2S audio, Raster/LCD, IDE storage
peripherals, keypad, and touchscreen. A three-port USB
2.0 Full Speed Host (OHCI) (12 Mbits per second) and
three UARTs are included as well.
The EP9315 is a high-performance, low-power, RISCbased, single-chip computer built around an ARM920T
microprocessor core with a maximum operating clock
rate of 200 MHz (184 MHz for industrial conditions). The
ARM core operates from a 1.8 V supply, while the I/O
operates at 3.3 V with power usage between 100 mW
and 750 mW (dependent on speed).
MaverickKey™ unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
Table A. Revision History
2
Revision
Date
PP1
January 2004
PP2
July 2004
PP3
Febuary 2005
Changes
Initial Release.
Update AC data.
Add ADC data.
Update electrical characteristics based upon more complete characterization data.
PP4
March 2005
PP5
October 2007
Minor correction to block diagram on page 1..
Updated PCMCIA timing descriptions on pages 30 and 31.
F1
February 2010
Removed “Preliminary Data” statement from legal disclaimer. Removed lead-containing device part numbers.
Increased minimum CVDD & VDD_PLL voltages from 1.65 V min. to 1.71 V min. Changed operating
temperatures to 0 to 60°C commercial, -40 to 70°C industrial.
F2
March 2010
Added note restricting power dissipationat temperature. Increased commercial/industrial temperatures to
70/85 deg. C max.
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Table of Contents
FEATURES .........................................................................................................1
OVERVIEW .........................................................................................................2
Processor Core - ARM920T ......................................................................................... 6
MaverickCrunch™ Math Engine .................................................................................. 6
MaverickKey™ Unique ID ............................................................................................ 6
General Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH) ........................ 6
IDE Interface ................................................................................................................ 7
Ethernet Media Access Controller (MAC) .................................................................... 7
Serial Interfaces (SPI, I2S and AC ’97) ........................................................................ 7
Raster / LCD Interface ................................................................................................. 7
Graphics Accelerator ................................................................................................... 8
Touch Screen Interface with 12-bit Analog-to-digital Converter (ADC) ........................ 8
64-Key Keypad Interface ............................................................................................. 8
Universal Asynchronous Receiver/Transmitters (UARTs) ............................................ 9
Triple Port USB Host .................................................................................................... 9
Two-wire Interface With EEPROM Support ................................................................. 9
Real-Time Clock with Software Trim .......................................................................... 10
PLL and Clocking ....................................................................................................... 10
Timers ........................................................................................................................ 10
Interrupt Controller ..................................................................................................... 10
Dual LED Drivers ....................................................................................................... 10
General Purpose Input/Output (GPIO) ....................................................................... 10
Reset and Power Management ..................................................................................11
Hardware Debug Interface ..........................................................................................11
Internal Boot ROM ......................................................................................................11
12-channel DMA Controller .........................................................................................11
PCMCIA Interface .......................................................................................................11
Electrical Specifications .................................................................................12
Absolute Maximum Ratings ....................................................................................... 12
Recommended Operating Conditions ........................................................................ 12
DC Characteristics ..................................................................................................... 13
Timings .............................................................................................................14
Memory Interface ....................................................................................................... 15
PCMCIA Interface ...................................................................................................... 30
IDE Interface .............................................................................................................. 32
Ethernet MAC Interface ............................................................................................ 45
Audio Interface ........................................................................................................... 47
AC’97 ........................................................................................................................ 51
LCD Interface ............................................................................................................ 52
ADC ........................................................................................................................... 53
JTAG .......................................................................................................................... 54
352 Pin BGA Package Outline .......................................................................55
352-Ball PBGA Diagram ........................................................................................... 55
352 Pin BGA Pinout (Bottom View) ........................................................................... 56
Acronyms and Abbreviations ........................................................................63
Units of Measurement .....................................................................................63
ORDERING INFORMATION ............................................................................64
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
3
EP9315
Enhanced Universal Platform SOC Processor
List of Figures
Figure 1. Timing Diagram Drawing Key ................................................................................. 14
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement ..................................... 15
Figure 3. SDRAM Burst Read Cycle Timing Measurement ................................................... 16
Figure 4. SDRAM Burst Write Cycle Timing Measurement ................................................... 17
Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................ 18
Figure 6. Static Memory Single Word Read Cycle Timing Measurement .............................. 19
Figure 7. Static Memory Single Word Write Cycle Timing Measurement .............................. 20
Figure 8. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement .................... 21
Figure 9. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement .................... 22
Figure 10. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement ................ 23
Figure 11. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement ................ 24
Figure 12. Static Memory Burst Read Cycle Timing Measurement ....................................... 25
Figure 13. Static Memory Burst Write Cycle Timing Measurement ....................................... 26
Figure 14. Static Memory Single Read Wait Cycle Timing Measurement ............................. 27
Figure 15. Static Memory Single Write Wait Cycle Timing Measurement .............................. 28
Figure 16. Static Memory Turnaround Cycle Timing Measurement ....................................... 29
Figure 17. PCMCIA Read Cycle Timing Measurement .......................................................... 30
Figure 18. PCMCIA Write Cycle Timing Measurement .......................................................... 31
Figure 19. Register Transfer to/from Device .......................................................................... 33
Figure 20. PIO Data Transfer to/from Device ......................................................................... 35
Figure 21. Initiating an Ultra DMA data-in Burst ..................................................................... 37
Figure 22. Sustained Ultra DMA data-in Burst ....................................................................... 38
Figure 23. Host Pausing an Ultra DMA data-in Burst ............................................................. 38
Figure 24. Device Terminating an Ultra DMA data-in Burst ................................................... 39
Figure 25. Host Terminating an Ultra DMA data-in Burst ....................................................... 40
Figure 26. Initiating an Ultra DMA data-out Burst .................................................................. 41
Figure 27. Sustained Ultra DMA data-out Burst ..................................................................... 42
Figure 28. Device Pausing an Ultra DMA data-out Burst ....................................................... 42
Figure 29. Host Terminating an Ultra DMA data-out Burst .................................................... 43
Figure 30. Device Terminating an Ultra DMA data-out Burst ................................................. 44
Figure 31. Ethernet MAC Timing Measurement ..................................................................... 46
Figure 32. TI Single Transfer Timing Measurement ............................................................... 48
Figure 33. Microwire Frame Format, Single Transfer ............................................................ 48
Figure 34. SPI Format with SPH=1 Timing Measurement ..................................................... 49
Figure 35. Inter-IC Sound (I2S) Timing Measurement ........................................................... 50
Figure 36. AC ‘97 Configuration Timing Measurement .......................................................... 51
Figure 37. LCD Timing Measurement .................................................................................... 52
Figure 38. ADC Transfer Function ......................................................................................... 53
Figure 39. JTAG Timing Measurement .................................................................................. 54
Figure 40. 352 Pin PBGA Pin Diagram .................................................................................. 55
Figure 40. 352 PIN BGA PINOUT ......................................................................................... 57
4
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
List of Tables
Table A. Change History .......................................................................................................... 2
Table B. General Purpose Memory Interface Pin Assignments .............................................. 6
Table C. IDE Interface Pin Assignments .................................................................................. 7
Table D. Ethernet Media Access Controller Pin Assignments ................................................. 7
Table E. Audio Interfaces Pin Assignment .............................................................................. 7
Table F. LCD Interface Pin Assignments ................................................................................ 8
Table G. Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments ... 8
Table H. 64-Key Keypad Interface Pin Assignments ............................................................... 8
Table I. Universal Asynchronous Receiver/Transmitters Pin Assignments ............................ 9
Table J. Triple Port USB Host Pin Assignments ..................................................................... 9
Table K. Two-Wire Port with EEPROM Support Pin Assignments .......................................... 9
Table L. Real-Time Clock with Pin Assignments ................................................................... 10
Table M.PLL and Clocking Pin Assignments ........................................................................ 10
Table N. Interrupt Controller Pin Assignment ........................................................................ 10
Table O. Dual LED Pin Assignments ..................................................................................... 10
Table P. General Purpose Input/Output Pin Assignment ...................................................... 11
Table Q. Reset and Power Management Pin Assignments ................................................... 11
Table R. Hardware Debug Interface ...................................................................................... 11
Table S. PCMCIA Interface ................................................................................................... 11
Table R. 352 Pin Diagram Dimensions .................................................................................. 56
Table S. Pin Descriptions ..................................................................................................... 60
Table T. Pin Multiplex Usage Information ............................................................................. 62
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
5
EP9315
Enhanced Universal Platform SOC Processor
Processor Core - ARM920T
The ARM920T is a Harvard architecture processor with
separate 16-kbyte instruction and data caches with an 8word line length but a unified memory. The processor
utilizes a five-stage pipeline consisting of fetch, decode,
execute, memory, and write stages. Key features include:
•
•
•
•
•
•
•
•
ARM (32-bit) and Thumb (16-bit compressed)
Instruction Sets
32-bit Advanced Micro-Controller Bus Architecture
(AMBA)
16-kbyte Instruction Cache with Lockdown
16-kbyte Data Cache (programmable write-through or
write-back) with Lockdown
MMU for Linux®, Microsoft® Windows® CE and Other
Operating Systems
Translation Look Aside Buffers with 64 Data and 64
Instruction Entries
Programmable Page Sizes of 1 Mbyte, 64 kbyte,
4 kbyte, and 1 kbyte
Independent Lockdown of TLB Entries
MaverickCrunch™ Math Engine
The MaverickCrunch Engine is a mixed-mode
coprocessor designed primarily to accelerate the math
processing required to rapidly encode digital audio
formats. It accelerates single and double precision
integer and floating point operations plus an integer
multiply-accumulate
(MAC)
instruction
that
is
considerably faster than the ARM920T's native MAC
instruction. The ARM920T coprocessor interface is
utilized thereby sharing its memory interface and
instruction stream. Hardware forwarding and interlock
allows the ARM to handle looping and addressing while
MaverickCrunch handles computation. Features include:
•
•
•
•
•
•
•
•
IEEE-754 single and double precision floating point
32 / 64-bit integer
Add / multiply / compare
Integer MAC 32-bit input with 72-bit accumulate
Integer Shifts
Floating point to/from integer conversion
Sixteen 64-bit register files
Four 72-bit accumulators
MaverickKey
™
Unique ID
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
6
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP9315 through the use of laser
probing technology. These IDs can then be used to
match secure copyrighted content with the ID of the
target device the EP9315 is powering, and then deliver
the copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today’s
Internet appliances.
General Purpose Memory Interface (SDRAM,
SRAM, ROM, FLASH)
The EP9315 features a unified memory address model
where all memory devices are accessed over a common
address/data bus. A separate internal port is dedicated to
the read-only Raster/LCD refresh engine, while the rest
of the memory accesses are performed via the Processor
bus. The SRAM memory controller supports 8, 16 and
32-bit devices and accommodates an internal boot ROM
concurrently with 32-bit SDRAM memory.
•
•
•
•
1-4 banks of 32-bit 66 or 100 MHz SDRAM
One internal port dedicated to the Raster/LCD
Refresh Engine (Read Only)
Address and data bus shared between SDRAM,
SRAM, ROM, and FLASH memory
NOR FLASH memory supported
Table B. General Purpose Memory Interface Pin Assignments
Pin Mnemonic
Pin Description
SDCLK
SDRAM Clock
SDCLKEN
SDRAM Clock Enable
SDCSn[3:0]
SDRAM Chip Selects 3-0
RASn
SDRAM RAS
CASn
SDRAM CAS
SDWEn
SDRAM Write Enable
CSn[7:6] and CSn[3:0]
Chip Selects 7, 6, 3, 2, 1, 0
AD[25:0]
Address Bus 25-0
DA[31:0]
Data Bus 31-0
DQMn[3:0]
SDRAM Output Enables / Data Masks
WRn
SRAM Write Strobe
RDn
SRAM Read / OE Strobe
WAITn
SRAM Wait Input
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
IDE Interface
Serial Interfaces (SPI, I2S and AC ’97)
The IDE Interface provides an industry-standard
connection to two AT Advanced Packet Interface (ATAPI)
compliant devices. The IDE port will attach to a master
and a slave device. The internal DMA controller performs
all data transfers using the Ultra DMA modes. The
interface supports the following operating modes:
The SPI port can be configured as a master or a slave,
supporting the National Semiconductor®, Motorola® and
Texas Instruments® signaling protocols.
•
•
PIO Mode 0 thru 4
Ultra DMA Modes 0 thru 3
Table C. IDE Interface Pin Assignments
Pin Mnemonic
Pin Description
The AC'97 port supports multiple codecs for multichannel
audio output with a single stereo input. Three I2S ports
can be configured to support six channel 24-bit audio.
These ports are multiplexed so that I2S port 0 will take
over either the AC'97 pins or the SPI pins. The second
and third I2S ports' serial input and serial output pins are
multiplexed with EGPIO[4,5,6,13]. The clocks supplied in
the first I2S port are also used for the second and third
I2S ports.
DD[15-0]
IDE Data bus
IDEDA[2-0]
IDE Device address
•
Normal Mode: One SPI Port and one AC’97 Port
IDECSn[0,1]
IDE Chip Select 0 and 1
•
I2S on SSP Mode: One AC’97 Port and up to three I2S
Ports
•
I2S on AC’97 Mode: One SPI Port and up to three I2S
Ports
DIORn
IDE Read Strobe
DIOWn
IDE Write Strobe
DMACKn
IDE DMA acknowledge
Ethernet Media Access Controller (MAC)
The MAC subsystem is compliant with the ISO/TEC
802.3 topology for a single shared medium with several
stations. Multiple MII-compliant PHYs are supported.
Features include:
•
•
Supports 1/10/100 Mbps transfer rates for home /
small-business / large-business applications
Interfaces to an off-chip PHY through industry
standard Media Independent Interface (MII)
Table E. Audio Interfaces Pin Assignment
Pin
Name
Normal Mode
I2S on SSP
Mode
I2S on AC'97
Mode
Pin
Description
Pin Description
Pin Description
SCLK1
SPI Bit Clock
SFRM1
SPI Frame Clock I2S Frame Clock
SSPRX1 SPI Serial Input
SSPTX1
SPI Serial
Output
Pin Description
MDC
Management Data Clock
MDIO
Management Data I/O
RXCLK
Receive Clock
MIIRXD[3:0]
Receive Data
RXDVAL
Receive Data Valid
RXERR
Receive Data Error
TXCLK
Transmit Clock
SPI Frame Clock
I2S Serial Input
SPI Serial Input
I2S Serial Output
SPI Serial Output
ARSTn
AC'97 Reset
ABITCLK AC'97 Bit Clock
AC'97 Reset
I2S Master Clock
AC'97 Bit Clock
I2S Serial Clock
ASYNC
AC'97 Frame
Clock
AC'97 Frame
Clock
I2S Frame Clock
ASDI
AC'97 Serial
Input
AC'97 Serial Input
I2S Serial Input
ASDO
AC'97 Serial
Output
AC'97 Serial
Output
I2S Serial Output
Raster / LCD Interface
MIITXD[3:0]
Transmit Data
TXEN
Transmit Enable
TXERR
Transmit Error
CRS
Carrier Sense
CLD
Collision Detect
DS638F2
SPI Bit Clock
(No I2S Master
Clock)
Table D. Ethernet Media Access Controller Pin Assignments
Pin Mnemonic
I2S Serial Clock
The Raster / LCD interface provides data and interface
signals for a variety of display types. It features fully
programmable video interface timing for non-interlaced
flat panel or dual scan displays. Resolutions up to
1024 x 768 are supported from a unified SDRAM based
frame buffer. A 16-bit PWM provides control for LCD
panel contrast. LCD specific features include:
Copyright 2010 Cirrus Logic (All Rights Reserved)
7
EP9315
Enhanced Universal Platform SOC Processor
•
•
•
•
•
•
•
•
Timing and interface signals for digital LCD and TFT
displays
Full programmability for either non-interlaced or dualscan color and grayscale flat panel displays
Dedicated data path to SDRAM controller for
improved system performance
Pixel depths of 4, 8, 16, or 24 bits per pixel or 256
levels of grayscale
Hardware Cursor up to 64 x 64 pixels
256 x 18 Color Lookup Table
Hardware Blinking
8-bit interface to low-end panel
only interrupts the processor when a meaningful change
occurs. The touch screen hardware may be disabled and
the switch matrix and ADC controlled directly if desired.
Features include:
•
•
•
Support for 4-, 5-, 7-, or 8-wire analog resistive touch
screens.
Flexibility - unused lines may be used for temperature
sensing or other functions.
Touch screen interrupt function.
Table G. Touch Screen Interface with 12-bit Analog-to-Digital
Converter Pin Assignments
Pin Mnemonic
Table F. LCD Interface Pin Assignments
Pin Mnemonic
Pin Description
SPCLK
Pixel Clock
P[17:0]
Pixel Data Bus [17:0]
HSYNC / LP
Horizontal
Synchronization / Line Pulse
VCSYNC / FP
Vertical or Composite
Synchronization / Frame Pulse
BLANK
Composite Blank
BRIGHT
Pulse Width Modulated Brightness
Graphics Accelerator
The EP9315 contains a hardware graphics acceleration
engine that improves graphic performance by handling
block copy, block fill and hardware line draw operations.
The Graphics Accelerator is used in the system to offload graphics operations from the processor.
Pixel depths supported by the Graphics Accelerator are
4, 8, 16, or 24 bits per pixel. The 24 bits per pixel mode
can be operated as packed (4 pixels every 3 words) or
unpacked (1 pixel per word with the high byte unused.)
The block copy operations of the Graphics Accelerator
are similar to a DMA (Direct Memory Access) transfer
that understands pixel organization, block width,
transparency, and transformation from 1bpp to higher 4,
8, 16, or 24bpp.
The line draw operations also allow for solid lines or
dashed lines. The colors for line drawing can be either
foreground color and background color or foreground
color with the background being transparent.
Xp, Xm
Pin Description
Touch screen ADC X Axis
Yp, Ym
Touch screen ADC Y Axis
SXp, SXm
Touch screen ADC X Axis
Voltage Feedback
SYp, SYm
Touch screen ADC Y Axis
Voltage Feedback
64-Key Keypad Interface
The keypad circuitry scans an 8 x 8 array of 64 normally
open, single-pole switches. Any one or two keys
depressed will be de-bounced and decoded. An interrupt
is generated whenever a stable set of depressed keys is
detected. If the keypad is not utilized, the 16 column/row
pins may be used as general purpose I/O. The Keypad
interface:
•
•
•
•
•
Provides scanning, debounce, and decoding for a 64key switch array.
Scans an 8-row by 8-column matrix.
May decode 2 keys at once.
Generates an interrupt when a new stable key is
determined.
Also generates a 3-key reset interrupt.
Table H. 64-Key Keypad Interface Pin Assignments
Pin Mnemonic
Pin
Description
Alternative Usage
COL[7:0]
Key Matrix Column
Inputs
General Purpose I/O
ROW[7:0]
Key Matrix Row
Inputs
General Purpose I/O
Touch Screen Interface with 12-bit Analogto-digital Converter (ADC)
The touch screen interface performs all sampling,
averaging, ADC range checking, and control for a wide
variety of analog resistive touch screens. This controller
8
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Universal Asynchronous
Receiver/Transmitters (UARTs)
Three 16550-compatible UARTs are supplied. Two
provide asynchronous HDLC (High-level Data Link
Control) protocol support for full-duplex transmit and
receive. The HDLC receiver handles framing, address
matching, CRC checking, control-octet transparency, and
optionally passes the CRC to the host at the end of the
packet. The HDLC transmitter handles framing, CRC
generation, and control-octet transparency. The host
must assemble the frame in memory before
transmission. The HDLC receiver and transmitter use the
UART FIFOs to buffer the data streams. A third IrDA®compatible UART is also supplied.
•
•
•
UART1 supports modem bit rates up to 115.2 Kbps,
supports HDLC and includes a 16-byte FIFO for
receive and a 16-byte FIFO for transmit. Interrupts are
generated on Rx, Tx, and modem status change.
UART2 contains an IrDA encoder operating at either
the slow (up to 115 Kbps), medium (0.576 or 1.152
Mbps), or fast (4 Mbps) IR data rates. It also has a 16byte FIFO for receive and a 16-byte FIFO for transmit.
UART3 supports HDLC and includes a 16-byte FIFO
for receive and a 16-byte FIFO for transmit. Interrupts
are generated on Rx and Tx.
Triple Port USB Host
The USB Open Host Controller Interface (Open HCI)
provides full speed serial communications ports at a
baud rate of 12 Mbits/sec. Up to 127 USB devices
(printer, mouse, camera, keyboard, etc.) and USB hubs
can be connected to the USB host in the USB “tieredstart” topology.
This includes the following features:
•
•
•
Compliance with the USB 2.0 specification
Compliance with the Open HCI Rev 1.0 specification
Supports both low speed (1.5 Mbps) and full speed
(12 Mbps) USB device connections
• Root HUB integrated with 3 downstream USB ports
• Transceiver buffers integrated, over-current protection
on ports
• Supports power management
• Operates as a master on the bus
The Open HCI host controller initializes the master DMA
transfer with the AHB bus:
•
•
•
•
Fetches endpoint descriptors and transfer descriptors
Accesses endpoint data from system memory
Accesses the HC communication area
Writes status and retire transfer descriptor
Table I. Universal Asynchronous Receiver/Transmitters Pin
Assignments
Pin Mnemonic
Pin Name - Description
TXD0
UART1 Transmit
RXD0
UART1 Receive
CTSn
UART1 Clear To Send /
Transmit Enable
DSRn / DCDn
UART1 Data Set Ready /
Data Carrier Detect
DTRn
UART1 Data Terminal Ready
RTSn
UART1 Ready To Send
EGPIO[0] / RI
UART1 Ring Indicator
TXD1 / SIROUT
UART2 Transmit /
IrDA Output
RXD1 / SIRIN
UART2 Receive / IrDA Input
TXD2
UART3 Transmit
RXD2
UART3 Receive
EGPIO[3] / TENn
HDLC3 Transmit Enable
DS638F2
Table J. Triple Port USB Host Pin Assignments
Pin Mnemonic
Pin Name - Description
USBp[2:0]
USB Positive signals
USBm[2:0]
USB Negative Signals
Two-wire Interface
The two-wire interface provides communication and
control for synchronous-serial-driven devices.
Table K. Two-Wire Port with EEPROM Support Pin Assignments
Pin Mnemonic
Pin Name - Description
Alternative
Usage
EECLK
Two-Wire Interface Clock
General
Purpose I/O
EEDATA
Two-Wire Interface Data
General
Purpose I/O
Copyright 2010 Cirrus Logic (All Rights Reserved)
9
EP9315
Enhanced Universal Platform SOC Processor
Real-Time Clock with Software Trim
The software trim feature on the real time clock (RTC)
provides software controlled digital compensation of the
32.768 kHz input clock. This compensation is accurate to
±1.24 sec/month.
Note:
A real time clock must be connected to RTCXTALI or
the EP9315 device will not boot.
Table L. Real-Time Clock with Pin Assignments
Pin Mnemonic
low, level-sensitive inputs. GPIO may be programmed as
active-high level-sensitive, active-low level-sensitive,
rising-edge-triggered, falling-edge-triggered, or combined
rising/falling-edge-triggered.
•
•
•
Pin Name - Description
RTCXTALI
Real-Time Clock Oscillator Input
RTCXTALO
Real-Time Clock Oscillator Output
•
•
PLL and Clocking
Supports 64 interrupts from a variety of sources (such
as UARTs, GPIO, and key matrix)
Routes interrupt sources to either the ARM920T’s
IRQ or FIQ (Fast IRQ) inputs
Four dedicated off-chip interrupt lines INT[3:0]
operate as active-high, level-sensitive interrupts
Any of the 16 GPIO lines maybe configured to
generate interrupts
Software supported priority mask for all FIQs and
IRQs
The processor and the peripheral clocks operate from a
single 14.7456 MHz crystal.
Table N. External Interrupt Pin Assignment
Pin Mnemonic
The real time clock operates from a 32.768 kHz external
oscillator.
Table M. PLL and Clocking Pin Assignments
Pin Mnemonic
Pin Name - Description
XTALI
Main Oscillator Input
XTALO
Main Oscillator Output
VDD_PLL
Main Oscillator Power
GND_PLL
Main Oscillator Ground
Timers
The Watchdog Timer insures proper operation by
requiring periodic attention to prevent a reset-on-timeout.
Two 16-bit timers operate as free running down-counters
or as periodic timers for fixed interval interrupts and have
a range of 0.03 ms to 4.27 seconds.
One 32-bit timer, plus a 6-bit prescale counter, has a
range of 0.03 μs to 73.3 hours.
One 40-bit debug timer, plus 6-bit prescale counter, has a
range of 1.0 μs to 12.7 days.
Interrupt Controller
The interrupt controller allows up to 64 interrupts to
generate an Interrupt Request (IRQ) or Fast Interrupt
Request (FIQ) signal to the processor core. Thirty-two
hardware priority assignments are provided for assisting
IRQ vectoring, and two levels are provided for FIQ
vectoring. This allows time critical interrupts to be
processed in the shortest time possible. Internal
interrupts may be programmed as active-high or active10
INT[3:0]
Pin Name - Description
External Interrupt 3-0
Dual LED Drivers
Two pins are assigned specifically to drive external
LEDs.
Table O. Dual LED Pin Assignments
Pin Mnemonic
Pin Name Description
GRLED
Green LED
General Purpose I/O
REDLED
Red LED
General Purpose I/O
Alternative Usage
General Purpose Input/Output (GPIO)
The 16 EGPIO pins may each be configured individually
as an output, an input, or an interrupt input. Port F may
be configured as GPIO. Each Port F pin may be
configured individually as an output, input or an interrupt
input.
There are 23 pins that may be used as alternate inputs or
outputs, but do not support interrupts. These pins are:
• Key Matrix ROW[7:0], COL[7:0]
• Ethernet MDIO
• Both LED Outputs
• Two-wire Clock and Data
• SLA [1:0]
6 pins may alternatively be used as inputs only:
• CTSn, DSRn / DCDn
• 4 Interrupt Lines
2 pins may alternatively be used as outputs only:
• RTSn
• ARSTn
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Table P. General Purpose Input/Output Pin Assignment
Pin Mnemonic
Pin Name - Description
EGPIO[15:0]
Expanded General Purpose Input / Output
Pins with Interrupts
FGPIO[7:0]
Expanded General Purpose Input / Output
Pins with Interrupts
Note:
Port F defaults as PCMCIA pins. Port F must be
configured by software to be used as GPIO.
Reset and Power Management
The chip may be reset through the PRSTn pin or through
the open drain common reset pin, RSTOn.
Clocks are managed on a peripheral-by-peripheral basis
and may be turned off to conserve power.
The processor clock is dynamically adjustable from 0 to
200 MHz (184 MHz for industrial conditions).
12-channel DMA Controller
The DMA module contains 12 separate DMA channels.
Ten of these may be used for peripheral-to-memory or
memory-to-peripheral access. Two of these are
dedicated to memory-to-memory transfers. Each DMA
channel is connected to the 16-bit DMA request bus.
The request bus is a collection of requests, Serial Audio,
and UARTs. Each DMA channel can be used
independently or dedicated to any request signal. For
each DMA channel, source and destination addressing
can be independently programmed to increment,
decrement, or stay at the same value. All DMA
addresses are physical, not virtual addresses.
PCMCIA Interface
The EP9315 has a single PCMCIA port which can be
used to access either 8 or 16-bit devices.
Table S. PCMCIA Interface
Table Q. Reset and Power Management Pin Assignments
Pin Mnemonic
Pin Name - Description
Pin Mnemonic
Pin Name - Description
VS1
Voltage sense
Voltage sense
PRSTn
Power On Reset
VS2
User Reset In/Out – Open Drain –
Preserves Real Time Clock value
MCD1
Card detect
RSTOn
MCD2
Card detect
MCBVD1
Voltage detection / status change
Hardware Debug Interface
MCBVD2
Voltage detection
The JTAG interface allows use of ARM’s Multi-ICE or
other in-circuit emulators.
MCDIR
Data transceiver direction control
MCDAENn
Data bus transceiver enable
MCADENn
Address bus transceiver enable
MCREGn
Memory card register
MCEHn
Memory card high byte select
MCELn
Memory card low byte select
Note:
The JTAG interface does not support boundary scan.
Table R. Hardware Debug Interface
Pin Mnemonic
Pin Name - Description
IORDn
I/O card read
I/O card write
TCK
JTAG Clock
IOWRn
TDI
JTAG Data In
MCRDn
Memory card read
TDO
JTAG Data Out
MCWRn
Memory card write
TMS
JTAG Test Mode Select
READY
Ready / interrupt
JTAG Port Reset
WP
Write protect
TRSTn
Internal Boot ROM
MCWAITn
Wait Input
MCRESETn
Card reset
The Internal 16-kbyte ROM allows booting from FLASH
memory, SPI or UART. Consult the EP93xx User’s
Manual for operational details
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
11
EP9315
Enhanced Universal Platform SOC Processor
Electrical Specifications
Absolute Maximum Ratings
(All grounds = 0 V, all voltages with respect to 0 V)
Parameter
Power Supplies
Total Power Dissipation
Symbol
Min
Max
Unit
RVDD
CVDD
VDD_PLL
VDD_ADC
-
3.96
2.16
2.16
3.96
V
V
V
V
-
2
W
(Note 1)
Input Current per Pin, DC (Except supply pins)
-
±10
mA
Output current per pin, DC
-
±50
mA
-0.3
RVDD+0.3
V
-40
+125
°C
Digital Input voltage
(Note 2)
Storage temperature
Note:
1. Includes all power generated due to AC and/or DC output loading.
2. The power supply pins are at recommended maximum values.
Caution:
Operation beyond these limits may result in permanent damage to the device. Normal operation is not
guaranteed at these extremes.
Recommended Operating Conditions
(All grounds = 0 V, all voltages with respect to 0 V)
Parameter
Power Supplies
Symbol
Min
Typ
Max
Unit
RVDD
CVDD
VDD_PLL
VDD_ADC
3.0
1.71
1.71
3.0
3.3
1.80
1.80
3.3
3.6
1.94
1.94
3.6
V
V
V
V
Operating Ambient Temperature - Commercial
(Note 3)
TA
0
+25
+70
°C
Operating Ambient Temperature - Industrial
(Note 4)
TA
-40
+25
+85
°C
Processor Clock Speed - Commercial
FCLK
-
-
200
MHz
Processor Clock Speed - Industrial
FCLK
-
-
184
MHz
System Clock Speed - Commercial
HCLK
-
-
100
MHz
System Clock Speed - Industrial
HCLK
-
-
92
MHz
Note:
3. The device is capable of operating up to 70° C ambient under typical operating conditions with power consumption less than 1.5W.
4. The device is capable of operating up to 85° C ambient under typical operating conditions with power consumption less than 1.5W.
12
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
DC Characteristics
(TA = 0 to 70° C; CVDD = VDD_PLL = 1.8; RVDD = 3.3 V;
All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted)
Parameter
High level output voltage
Iout = -4 mA
Low level output voltage
Iout = 4 mA
(Note 5)
Symbol
Min
Max
Unit
Voh
0.85 × RVDD
-
V
Vol
-
0.15 × RVDD
V
High level input voltage
(Note 6)
Vih
0.65 × RVDD
VDD + 0.3
V
Low level input voltage
(Note 6)
Vil
-0.3
0.35 × RVDD
V
High level leakage current
Vin = 3.3 V
(Note 6)
Iih
-
10
µA
Low level leakage current
Vin = 0
(Note 6)
Iil
-
-10
µA
Min
Typ
Max
Unit
Parameter
Power Supply Pins (Outputs Unloaded), 25° C
Power Supply Current:
CVDD / VDD_PLL Total
RVDD
-
190
45
240
80
mA
mA
Low-Power Mode Supply Current
CVDD / VDD_PLL Total
RVDD
-
2
1
3.5
2
mA
mA
Note:
DS638F2
5. For open drain pins, high level output voltage is dependent on the external load.
6. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation (See Table S on
page 60). If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not
driven and programmed as an input, it should be tied to power or ground through its own resistor.
Copyright 2010 Cirrus Logic (All Rights Reserved)
13
EP9315
Enhanced Universal Platform SOC Processor
Timings
Timing Diagram Conventions
This data sheet contains one or more timing diagrams. The following key explains the components used in these
diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached
unless specifically stated.
Clock
High to Low
High/Low to High
Bus Change
Bus Valid
Undefined/Invalid
Valid Bus to Tristate
Bus/Signal Omission
Figure 1. Timing Diagram Drawing Key
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements.
• TA = 0 to 70° C
• CVDD = VDD_PLL = 1.8V
• RVDD = 3.3 V
• All grounds = 0 V
• Logic 0 = 0 V, Logic 1 = 3.3 V
• Output loading = 50 pF
• Timing reference levels = 1.5 V
• The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between
33 MHz and 100 MHz (92 MHz for industrial conditions).
14
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Memory Interface
Figure 2 through Figure 5 define the timings associated with all phases of the SDRAM. The following table contains the
values for the timings of each of the SDRAM modes.
Parameter
Symbol
Min
Typ
Max
Unit
SDCLK high time
tclk_high
-
(tHCLK) / 2
-
ns
SDCLK low time
tclk_low
-
(tHCLK) / 2
-
ns
tclkrf
-
2
4
ns
SDCLK rise/fall time
Signal delay from SDCLK rising edge time
td
-
-
8
ns
Signal hold from SDCLK rising edge time
th
1
-
-
ns
DQMn delay from SDCLK rising edge time
tDQd
-
-
8
ns
DQMn hold from SDCLK rising edge time
tDQh
1
-
-
ns
DA valid setup to SDCLK rising edge time
tDAs
2
-
-
ns
DA valid hold from SDCLK rising edge time
tDAh
3
-
-
ns
SDRAM Load Mode Register Cycle
tclk_low
tclkrf
tclk_high
SDCLK
td
th
SDCSn
RASn
CASn
SDWEn
DQMn
AD
OP-Code
DA
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
15
EP9315
Enhanced Universal Platform SOC Processor
SDRAM Burst Read Cycle
tclk_low
tclk_high
SDCLK
tclkrf
td
th
SDCSn
RASn
CASn
SDWEn
tDQh
tDQd
DQMn
CL = 2
tDQh
DQMn
CL = 3
AD
td
tDAs
DA
tDAh
n
n+1
n+2
n+3
CL = 2
tDAs
DA
CL = 3
tDAh
n
n+1
n+2
n+3
Figure 3. SDRAM Burst Read Cycle Timing Measurement
16
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
SDRAM Burst Write Cycle
tclk_high
tclk_low
SDCLK
tclkrf
td
th
th
SDCSn
RASn
CASn
SDWEn
DQMn
AD
DA
n
n +1
n+2
n+3
Figure 4. SDRAM Burst Write Cycle Timing Measurement
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
17
EP9315
Enhanced Universal Platform SOC Processor
SDRAM Auto Refresh Cycle
tclk_high
tclk_low
SDCLK
tclkrf
td
SDCSn
th
7
b
d
e
RASn
CASn
SDWEn
Note:
Chip select shown as bus to illustrate multiple devices being put into auto refresh in one access
Figure 5. SDRAM Auto Refresh Cycle Timing Measurement
18
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Static Memory Single Word Read Cycle
Parameter
Symbol
Min
Typ
Max
Unit
AD setup to CSn assert time
tADs
0
-
-
ns
AD hold from CSn deassert time
tADh
tHCLK
-
-
ns
RDn assert time
tRDpw
-
tHCLK × (WST1 + 2)
-
ns
CSn to RDn delay time
tRDd
-
-
3
ns
tDQMd
-
-
1
ns
DA setup to RDn deassert time
tDAs
tHCLK + 12
-
-
ns
DA hold from RDn deassert time
tDAh
0
-
-
ns
CSn assert to DQMn assert delay time
See “Timing Conditions” on page 14 for definition of HCLK.
tADs
tADh
AD
CSn
WRn
tRDd
tRDd
RDn
DQMn
tDQMd
tDAs
tDAh
DA
WAIT
Figure 6. Static Memory Single Word Read Cycle Timing Measurement
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
19
EP9315
Enhanced Universal Platform SOC Processor
Static Memory Single Word Write Cycle
Parameter
Symbol
Min
Typ
Max
Unit
AD setup to WRn assert time
tADs
tHCLK
-3
-
-
ns
AD hold from WRn deassert time
tADh
tHCLK × 2
-
-
ns
WRn deassert to CSn deassert time
tCSh
7
-
-
ns
CSn to WRn assert delay time
tWRd
-
-
2
ns
WRn assert time
tWRpw
-
tHCLK × (WST1 + 1)
-
ns
CSn to DQMn assert delay time
tDQMd
-
-
1
ns
WRn deassert to DA transition time
tDAh
tHCLK
-
-
ns
WRn assert to DA valid
tDAV
-
-
8
ns
tADs
tADh
AD
tCSh
CSn
tWRd
tWRpw
WRn
RDn
DQMn
tDQMd
tDAV
tDAh
DA
WAIT
Figure 7. Static Memory Single Word Write Cycle Timing Measurement
20
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Static Memory 32-bit Read on 8-bit External Bus
Parameter
Symbol
Min
Typ
Max
Unit
AD setup to CSn assert time
tADs
tHCLK
-
-
ns
CSn assert to Address transition time
tAD1
-
tHCLK × (WST1 + 1)
-
ns
Address assert time
tAD2
-
tHCLK × (WST1 + 1)
-
ns
AD transition to CSn deassert time
tAD3
-
tHCLK × (WST1 + 2)
-
ns
tADh
-
ns
tHCLK
-
tRDpwL
-
tHCLK × (4 × WST1 + 5)
-
ns
tRDd
-
-
3
ns
CSn assert to DQMn assert delay time
tDQMd
-
-
1
ns
DA setup to AD transition time
tDAs1
15
-
-
ns
DA setup to RDn deassert time
tDAs2
tHCLK + 12
-
-
ns
DA hold from AD transition time
tDAh1
0
-
-
ns
DA hold from RDn deassert time
tDAh2
0
-
-
ns
AD hold from CSn deassert time
RDn assert time
CSn to RDn delay time
tADs
tAD1
tAD2
tAD2
tADh
tAD3
AD
CSn
WRn
tRDd
tRDd
RDn
tDQMd
DQMn
tDAh1
tDAh1
tDAh11
tDAh2
DA
tDAs1
tDAs1
tDAs1
tDAs2
WAIT
Figure 8. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
21
EP9315
Enhanced Universal Platform SOC Processor
Static Memory 32-bit Write on 8-bit External Bus
Parameter
Symbol
Min
Typ
Max
Unit
AD setup to WRn assert time
tADs
tHCLK − 3
-
-
ns
WRn/DQMn deassert to AD transition time
tADd
-
-
tHCLK + 6
ns
AD hold from WRn deassert time
tADh
tHCLK × 2
-
-
ns
CSn hold from WRn deassert time
tCSh
7
-
-
ns
tWRd
2
ns
CSn to WRn assert delay time
-
-
WRn assert time
tWRpwL
-
tHCLK × (WST1 + 1)
-
ns
WRn deassert time
tWRpwH
-
tHCLK × 2
(tHCLK × 2) + 14
ns
tDQMd
-
-
1
ns
DQMn assert time
tDQMpwL
-
tHCLK × (WST1 + 1)
-
ns
DQMn deassert time
tDQMpwH
-
-
(tHCLK × 2) + 7
ns
WRn / DQMn deassert to DA transition time
tDAh
tHCLK
-
-
ns
WRn / DQMn assert to DA valid time
tDAV
-
-
8
ns
CSn to DQMn assert delay time
tADs
tADd
tADd
tADd
tADh
AD
CSn
tWRd
tWRpwL
tWRpwL
tCSh
tWRpwL
WRn
tWRpwH
tWRpwH
tWRpwH
RDn
tDQMd
tDQMpwL
tDQMpwL
tDQMpwL
DQMn
tDQMpwH
tDAV
tDQMpwH
tDAV
tDQMpwH
tDAV
tDAV
DA
tDAh
tDAh
tDAh
tDAh
WAIT
Figure 9. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement
22
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Static Memory 32-bit Read on 16-bit External Bus
Parameter
Symbol
Min
Typ
Max
Unit
AD setup to CSn assert time
tADs
tHCLK
-
-
ns
CSn assert to AD transition time
tADd1
-
tHCLK × (WST1 + 1)
-
ns
AD transition to CSn deassert time
tADd2
-
tHCLK × (WST1 + 2)
-
ns
AD hold from CSn deassert time
tADh
tHCLK
-
-
ns
tRDpwL
-
tHCLK × ((2 × WST1) + 3)
-
ns
tRDd
-
-
3
ns
CSn assert to DQMn assert delay time
tDQMd
-
-
1
ns
DA setup to AD transition time
tDAs1
15
-
-
ns
DA to RDn deassert time
tDAs2
tHCLK + 12
-
-
ns
DA hold from AD transition time
tDAh1
0
-
-
ns
DA hold from RDn deassert time
tDAh2
0
-
-
ns
RDn assert time
CSn to RDn delay time
tADs
tADd1
tADd2
tADh
AD
CSn
WRn
tRDd
tRDh
tRDpwl
RDn
DQMn
tDQMh
tDQMd
tDAs1
tDAh1
tDAs2
tDAh2
DA
WAIT
Figure 10. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
23
EP9315
Enhanced Universal Platform SOC Processor
Static Memory 32-bit Write on 16-bit External Bus
Parameter
Symbol
Min
Typ
Max
Unit
AD setup to WRn assert time
tADs
tHCLK – 3
-
-
ns
WRn/DQMn deassert to AD transition time
tADd
-
-
tHCLK + 6
ns
AD hold from WRn deassert time
tADh
tHCLK × 2
-
-
ns
CSn hold from WRn deassert time
tCSh
7
-
-
ns
tWRd
CSn to WRn assert delay time
-
-
2
ns
WRn assert time
tWRpwL
-
tHCLK × (WST1 + 1)
-
ns
WRn deassert time
tWRpwH
-
-
(tHCLK × 2) + 14
ns
tDQMd
-
-
1
ns
DQMn assert time
tDQMpwL
-
tHCLK × (WST1 + 1)
-
ns
DQMn deassert time
tDQMpwH
-
-
(tHCLK × 2) + 7
ns
WRn / DQMn deassert to DA transition time
tDAh1
tHCLK
-
-
ns
WRn / DQMn assert to DA valid time
tDAV
-
-
8
ns
CSn to DQMn assert delay time
tADs
tADd
tADh
AD
CSn
tWRd
tWRpwL
WRn
tWRpwL
tCSh
tWRpwH
RDn
tDQMd
tDQpwL
DQMn
tDQpwL
tDQpwH
tDAV
tDAh
tDAV
tDAh
DA
WAIT
Figure 11. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement
24
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Static Memory Burst Read Cycle
Parameter
Symbol
Min
Typ
Max
Unit
CSn assert to Address 1 transition time
tADd1
-
tHCLK × (WST1 + 1)
-
ns
Address assert time
tADd2
-
tHCLK × (WST2 + 1)
-
ns
AD transition to CSn deassert time
tADd3
-
tHCLK × (WST1 + 2)
-
ns
AD hold from CSn deassert time
tADh
tHCLK
-
-
ns
tRDd
-
-
3
ns
CSn to RDn delay time
CSn to DQMn assert delay time
tDQMd
-
-
1
ns
DA setup to AD transition time
tDAs1
15
-
-
ns
DA setup to CSn deassert time
tDAs2
tHCLK + 12
-
-
ns
DA hold from AD transition time
tDAh1
0
-
-
ns
DA hold from RDn deassert time
tDAh2
0
-
-
ns
Note:
These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
tADs
tADd1
tADd2
tADd2
tADh
tADd3
AD
CSn
WRn
tRDd
RDn
DQMn
tDQMd
tDAh1
tDAh1
tDAh1
tDAh2
DA
tDAs1
tDAs1
tDAs1
tDAs2
WAIT
Figure 12. Static Memory Burst Read Cycle Timing Measurement
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
25
EP9315
Enhanced Universal Platform SOC Processor
Static Memory Burst Write Cycle
Parameter
Symbol
Min
AD setup to WRn assert time
tADs
tHCLK − 3
ns
AD hold from WRn deassert time
tADh
tHCLK × 2
ns
WRN/DQMn deassert to AD transition time
tADd
CSn hold from WRn deassert time
tCSh
CSn to WRn assert delay time
tWRd
CSn to DQMn assert delay time
tDQMd
DQMn assert time
tDQpwL
DQMn deassert time
tDQpwH
WRn assert time
tWRpwL
WRn deassert time
tWRpwH
WRn/DQMn deassert to DA transition time
tDAh
WRn/DQMn assert to DA valid time
tDAv
Note:
Typ
Max
Unit
tHCLK + 6
ns
7
ns
2
ns
1
ns
tHCLK × (WST1 + 1)
ns
(tHCLK × 2) + 14
ns
tHCLK × (WST1 + 11)
ns
(tHCLK × 2) + 7
ns
tHCLK
ns
8
ns
These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
tADs
tADd
tADh
AD
CSn
tWRpwL
WRn
tCSh
tWRpwH
tWRd
RD
tDQMd
tDQpwL
DQMn
tDQpwH
tDAv
tDAh
DA
WAIT
Figure 13. Static Memory Burst Write Cycle Timing Measurement
26
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Static Memory Single Read Wait Cycle
Parameter
Symbol
Min
Typ
Max
Unit
CSn assert to WAIT time
tWAITd
-
-
tHCLK × (WST1-2)
ns
WAIT assert time
tWAITpw
tHCLK × 2
-
tHCLK × 510
ns
tCSnd
tHCLK × 3
-
tHCLK × 5
ns
WAIT to CSn deassert delay time
AD
CSn
WRn
RDn
DQMn
DA
WAIT
tWAITd
tWAITpw
tCSnd
Figure 14. Static Memory Single Read Wait Cycle Timing Measurement
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
27
EP9315
Enhanced Universal Platform SOC Processor
Static Memory Single Write Wait Cycle
Parameter
Symbol
Min
Typ
Max
Unit
tWRd
tHCLK × 2
-
tHCLK × 4
ns
CSn assert to WAIT time
tWAITd
-
-
tHCLK × (WST1-2)
ns
WAIT assert time
tWAITpw
tHCLK × 2
-
tHCLK × 510
ns
tCSnd
tHCLK × 3
-
tHCLK × 5
ns
WAIT to WRn deassert delay time
WAIT to CSn deassert delay time
AD
CSn
tWRd
WRn
RDn
DQMn
DA
tWAITd
tWAITpw
tCSnd
WAIT
Figure 15. Static Memory Single Write Wait Cycle Timing Measurement
28
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Static Memory Turnaround Cycle
Parameter
CSnX deassert to CSnY assert time
Symbol
Min
Typ
Max
Unit
tBTcyc
-
tHCLK × (IDCY+1)
-
ns
Notes: 1. X and Y represent any two chip select numbers.
2. IDCY occurs on read-to-write and write-to-read.
3. IDCY is honored when going from a asynchronous device (CSx) to a synchronous device (/SDCSy).
tBTcyc
AD
CSnX
CSnY
WRn
RDn
DQMn
DA
WAIT
Figure 16. Static Memory Turnaround Cycle Timing Measurement
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
29
EP9315
Enhanced Universal Platform SOC Processor
PCMCIA Interface
PCMCIA Read Cycle
Parameter
Symbol
Min
Typ
Max
Unit
tADs
0
-
-
ns
DA setup to MCRDn / IORDn rising edge
ts
10
-
-
ns
DA hold from MCRDn / IORDn rising edge
th
0
-
-
ns
MCDIR hold time
tMCDh
0
-
-
ns
MCADENn/MCDAENn hold time
tMCAh
0
-
-
ns
MCEHn/MCELn/MCREGn hold time
tMCEh
0
-
-
ns
AD setup to signal transition time
Wait Time1
tA-[2 × tHCLK]
tW
-
-
Attribute access time
tA
[(AA + 1) × tHCLK] - 14
(AA + 1) × tHCLK
-
ns
Attribute hold time
tH
[(HA + 1) × tHCLK] - 3
(HA + 1) × tHCLK
-
ns
Attribute space pre-charge delay time
tp
(PA + 1) × tHCLK
(PA + 1) × tHCLK
-
ns
Common access time
tA
[(AC + 1) × tHCLK] - 14
(AC + 1) × tHCLK
-
ns
Common hold time
tH
[(HC + 1) × tHCLK] - 3
(HC + 1) × tHCLK
-
ns
Common space pre-charge delay time
tp
(PC + 1) × tHCLK
(PC + 1) × tHCLK
-
ns
I/O access time
tA
[(AI + 1) × tHCLK] - 14
(AI + 1) × tHCLK
-
ns
I/O hold time
tH
[(HI + 1) × tHCLK] - 3
(HI + 1) × tHCLK
-
ns
I/O space pre-charge delay time
tp
(PI + 1) × tHCLK
(PI + 1) × tHCLK
-
ns
ns
Attribute Mode Timing
Common Mode Timing
I/O Mode Timing
tADs
AD
tMCAh
MCADENn/
MCDAENn
tMCEh
MCEHn/
MCELn/
MCREGn
tp
tA
tH
MCRDn/
IORDn
tMCDh
MCDIR
ts
th
DA
(in)
MCWAITn
tW
Figure 17. PCMCIA Read Cycle Timing Measurement
Note:
30
MCWAITn asserted will extend the MCRD / IORD strobe time.
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
PCMCIA Write Cycle
Parameter
Symbol
Min
Typ
Max
Unit
tADs
0
-
-
ns
MCDIR hold time
tMCDh
0
-
-
ns
MCEHn/MCELn/MCREGn hold time
tMCEh
0
-
-
ns
DATA invalid delay time
tDAfo
0
-
-
ns
tW
-
-
tA-[2 × tHCLK]
ns
Attribute access time
tA
[(AA + 1) × tHCLK] - 14
(AA + 1) × tHCLK
-
ns
Attribute hold time
tH
[(HA + 1) × tHCLK] - 3
(HA + 1) × tHCLK
-
ns
Attribute space pre-charge delay time
tp
(PA + 1) × tHCLK
(PA + 1) × tHCLK
-
ns
Common access time
tA
[(AC + 1) × tHCLK] - 14
(AC + 1) × tHCLK
-
ns
Common hold time
tH
[(HC + 1) × tHCLK] - 3
(HC + 1) × tHCLK
-
ns
Common space pre-charge delay time
tp
(PC + 1) × tHCLK
(PC + 1) × tHCLK
-
ns
I/O access time
tA
[(AI + 1) × tHCLK] - 14
(AI + 1) × tHCLK
-
ns
I/O hold time
tH
[(HI + 1) × tHCLK] - 3
(HI + 1) × tHCLK
-
ns
I/O space pre-charge delay time
tp
(PI + 1) × tHCLK
(PI + 1) × tHCLK
-
ns
AD setup to signal transition time
Wait
Time1
Attribute Mode Timing
Common Mode Timing
I/O Mode Timing
tADs
AD
tMCEh
MCEHn/
MCELn/
MCREGn
tp
tA
tH
MCWRn/
IOWRn
tMCDh
MCDIR
tDAfo
DA
(out)
MCWAITn
tW
Figure 18. PCMCIA Write Cycle Timing Measurement
Note:
DS638F2
MCWAITn asserted will extend the MCWR / IOWR strobe time.
Copyright 2010 Cirrus Logic (All Rights Reserved)
31
EP9315
Enhanced Universal Platform SOC Processor
IDE Interface
Register Transfers
Parameter
Symbol
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
(in ns) (in ns) (in ns) (in ns) (in ns)
Cycle time
(min)
(Notes 1, 4, 5)
t0
600
383
330
180
120
Address valid to DIORn / DIOWn setup
(min)
(Note 4)
t1
70
50
30
30
25
DIORn / DIOWn pulse width 8-bit
(min)
(Note 1, 4)
t2
290
290
290
80
70
DIORn / DIOWn recovery time
(min)
(Note 1, 4)
t2i
-
-
-
70
25
DIOWn data setup
(min)
(Note 4)
t3
60
45
30
30
20
DIOWn data hold
(min)
t4
0
0
0
0
0
DIORn data setup
(min)
t5
20
20
20
20
20
DIORn data hold
(min)
t6
0
0
0
0
0
DIORn data high impedance state
(max)
(Note 2, 4)
t6z
30
30
30
30
30
DIORn / DIOWn to address valid hold
(min)
(Note 4)
t9
20
15
10
10
10
Read Data Valid to IORDY
active (if IORDY initially low after tA)
(min)
(Note 4)
tRD
0
0
0
0
0
(Note 3, 4)
tA
35
35
35
35
35
(Note 4)
tB
1250
1250
1250
1250
1250
IORDY Setup time
IORDY Pulse Width
(max)
IORDY assertion to release
(max)
tC
5
5
5
5
5
(max)
tDDV
10
10
10
10
10
DIOWn assert to data valid
Note:
1. t0 is the minimum total cycle time, t2 is the minimum DIORn / DIOWn assertion time, and t2i is the minimum DIORn / DIOWn
negation time. A host implementation shall lengthen t2 and/or t2i to ensure that t0 is equal to or greater than the value
reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.
2. This parameter specifies the time from the negation edge of DIORn to the time that the data bus is released by the device.
3. The delay from the activation of DIORn or DIOWn until the state of IORDY is first sampled. If IORDY is inactive then the host
shall wait until IORDY is active before the register transfer cycle is completed. If the device is not driving IORDY negated at
the tA after the activation of DIORn or DIOWn, then t5 shall be met and tRD is not applicable. If the device is driving IORDY
negated at the time tA after the activation of DIORn or DIOWn, then tRD shall be met and t5 is not applicable.
4. Timings based upon software control. See User’s Guide.
5. ATA / ATAPI standards prior to ATA / ATAPI-5 inadvertently specified an incorrect value for mode 2 time t0 by utilizing the
16-bit PIO value.
6. All IDE timing is based upon HCLK = 100 MHz.
32
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
ADDR valid
(Note 1)
t9
t1
t2
t2i
DIORn/
DIOWn
t0
tDDV
WRITE
DD (7:0)
(Note 2)
t3
t4
READ
DD (7:0)
(Note 2)
t5
t6
t6z
IORDY
(Note 3,3-1)
tA
IORDY
(Note 3,3-2)
tC
tRD
IORDY
(Note 3,3-3)
tB
Note:
tC
1. Device address consists of signals IDECS0n, IDECS1n and IDEDA (2:0)
2. Data consists of DD (7:0)
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is
to be extended is made by the host after tA from the assertion of DIORn or DIOWn. The assertion and negation or IORDY
are described in the following three cases:
3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation
and may be asserted for no more than tC before release: no wait generated.
3-3 Device negates IORDY before tA. IORDY is released prior to negation and may be asserted for no more than tC
before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated
and DIORn is asserted, the device shall place read data on DD (7:0) for tRD before asserting IORDY.
Figure 19. Register Transfer to/from Device
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
33
EP9315
Enhanced Universal Platform SOC Processor
PIO Data Transfers
Parameter
Symbol
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
(in ns)
(in ns)
(in ns)
(in ns)
(in ns)
Cycle time
(min)
(Note 1, 4)
t0
600
383
240
180
120
Address valid to DIORn / DIOWn setup
(min)
(Note 4)
t1
70
50
30
30
25
DIORn / DIOWn 16-bit
(min)
(Note 1, 4)
t2
165
125
100
80
70
DIORn / DIOWn recovery time
(min)
(Note 1, 4)
t2i
-
-
-
70
25
DIOWn data setup
(min)
(Note 4)
t3
60
45
30
30
20
DIOWn data hold
(min)
t4
0
0
0
0
0
DIORn data setup
(min)
t5
20
20
20
20
20
DIORn data hold
(min)
t6
0
0
0
0
0
DIORn data high impedance state
(max)
(Note 2, 4)
t6z
30
30
30
30
30
DIORn / DIOWn to address valid hold
(min)
(Note 4)
t9
20
15
10
10
10
Read Data Valid to IORDY
active (if IORDY initially low after tA)
(min)
(Note 4)
tRD
0
0
0
0
0
(Note 3, 4)
tA
35
35
35
35
35
(Note 4)
tB
1250
1250
1250
1250
1250
IORDY Setup time
IORDY Pulse Width
(max)
IORDY assertion to release
(max)
tC
5
5
5
5
5
(max)
tDDV
10
10
10
10
10
DIOWn assert to data valid
Note:
34
1. t0 is the minimum total cycle time, t2 is the minimum DIORn / DIOWn assertion time, and t2i is the minimum DIORn / DIOWn
negation time. A host implementation shall lengthen t2 and/or t2i to ensure that t0 is equal to or greater than the value
reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.
2. This parameter specifies the time from the negation edge of DIORn to the time that the data bus is released by the device.
3. The delay from the activation of DIORn or DIOWn until the state of IORDY is first sampled. If IORDY is inactive then the host
shall wait until IORDY is active before the register transfer cycle is completed. If the device is not driving IORDY negated at
the tA after the activation of DIORn or DIOWn, then t5 shall be met and tRD is not applicable. If the device is driving IORDY
negated at the time tA after the activation of DIORn or DIOWn, then tRD shall be met and t5 is not applicable.
4. Timings based upon software control. See User’s Guide.
5. All IDE timing is based upon HCLK = 100 MHz.
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
ADDR valid
(Note 1)
t9
t1
t2
t2i
DIORn/
DIOWn
t0
tDDV
WRITE
DD(15:0)
(Note 2)
t3
t4
READ
DD(15:0)
(Note 2)
t5
t6
t6z
IORDY
(Note 3,3-1)
tA
IORDY
(Note 3,3-2)
tC
tRD
IORDY
(Note 3,3-3)
tB
Note:
tC
1. Device address consists of signals IDECS0n, IDECS1n and IDEDA (2:0)
2. Data consists of DD (15:0)
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is
to be extended is made by the host after tA from the assertion of DIORn or DIOWn. The assertion and negation or IORDY
are described in the following three cases:
3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation
and may be asserted for no more than tC before release: no wait generated.
3-3 Device negates IORDY before tA. IORDY is released prior to negation and may be asserted for no more than tC
before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated
and DIORn is asserted, the device shall place read data on DD (15:0) for tRD before asserting IORDY.
Figure 20. PIO Data Transfer to/from Device
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
35
EP9315
Enhanced Universal Platform SOC Processor
Ultra DMA Data Transfer
Figure 21 through Figure 30 define the timings associated with all phases of Ultra DMA bursts. The following table
contains the values for the timings for each of the Ultra DMA modes.
Timing reference levels = 1.5 V
Parameter
Symbol
Mode 0
(in ns)
Mode 1
(in ns)
Mode 2
(in ns)
Mode 3
(in ns)
min
max
min
max
min
max
min
max
tCYCRD
112
-
73
-
54
-
39
-
Two-cycle time allowing for clock variations (from rising edge to next
rising edge or from falling edge to next falling edge of DSTROBE)
t2CYCRD
230
-
154
-
115
-
86
-
Cycle time allowing for asymmetry and clock variations
(from HSTROBE edge to HSTROBE edge)
tCYCWR
230
-
170
-
130
-
100
-
Two-cycle time allowing for clock variations (from rising edge to next
rising edge or from falling edge to next falling edge of HSTROBE)
t2CYCWR
460
-
340
-
260
-
200
-
tDS
15
-
10
-
7
-
7
-
tDH
8
-
8
-
8
-
8
-
tDVS
70
-
48
-
30
-
20
-
tDVH
6
-
6
-
6
-
6
-
tFS
0
230
0
200
0
170
0
130
Cycle time allowing for asymmetry and clock variations
(from DSTROBE edge to DSTROBE edge)
Data setup time at recipient (Read)
Data hold time at recipient (Read)
Data valid setup time at sender (Write)
(from data valid until STROBE edge)
(Note 2)
Data valid hold time at sender (Write)
(from STROBE edge until data may become invalid)
(Note 2)
First STROBE time (for device to first negate DSTROBE from STOP
during a data in burst)
Limited interlock time
(Note 3)
tLI
0
150
0
150
0
150
0
100
Interlock time with minimum
(Note 3)
tMLI
20
-
20
-
20
-
20
-
Unlimited interlock time
(Note 3)
tUI
0
-
0
-
0
-
0
-
tAZ
-
10
-
10
-
10
-
10
Minimum delay time required for output
tZAH
20
-
20
-
20
-
20
-
Drivers to assert or negate (from released)
tZAD
0
-
0
-
0
-
0
-
Envelope time (from DMACKn to STOP and HDMARDYn during data in
burst initiation and from DMACKn to STOP during data out burst initiation)
tENV
20
70
20
70
20
70
20
55
Ready-to-final-STROBE time (no STROBE edges shall be sent this long
after negation of DMARDYn)
tRFS
-
75
-
70
-
60
-
60
Ready-to-pause time
(that recipient shall wait to pause after negating DMARDYn)
tRP
160
-
125
-
100
-
100
-
tIORDYZ
-
20
-
20
-
20
-
20
tZIORDY
0
-
0
-
0
-
0
-
Setup and hold times for DMACKn (before assertion or negation)
tACK
20
-
20
-
20
-
20
-
Time from STROBE edge to negation of DMARQ or assertion of STOP
(when sender terminates a burst)
tSS
50
-
50
-
50
-
50
-
Maximum time allowed for output drivers to release
(from asserted or negated)
Maximum time before releasing IORDY
Minimum time before driving STROBE
Note:
36
(Note 4)
1. Timing parameters shall be measured at the connector of the sender or receiver to which the parameter applies.
2. The test load for tDVS and tDVH shall be a lumped capacitor load with no cable or receivers. Timing for tDVS and tDVH shall be
met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value.
3. tUI, tMLI and tLI indicate sender-to-recipient or recipient-to-sender interlocks, i.e., either sender or recipient is waiting for the
other to respond with a signal before proceeding. tUI is an unlimited interlock that has no maximum time value. tMLI is a limited
time-out that has a defined minimum. tLI is a limited time-out that has a defined maximum.
4. tZIORDY may be greater than tENV since the device has a pull up on IORDYn giving it a known state when released.
5. All IDE timing is based upon HCLK = 100 MHz.
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
DMARQ
(device)
tUI
DMACKn
(host)
tFS
tACK
tENV
tZAD
tACK
tENV
tZAD
STOP
(host)
HDMARDYn
(host)
tZIORDY
DSTROBE
(device)
tAZ
tDVS
tDVH
DD (15:0)
tACK
IDEDA[2:0]
IDECS0n,
IDECS1n
Note:
The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are not
in effect until DMARQ and DMACKn are asserted.
Figure 21. Initiating an Ultra DMA data-in Burst
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
37
EP9315
Enhanced Universal Platform SOC Processor
t2CYCRD
tCYCRD
tCYCRD
t2CYCRD
DSTROBE
(device)
tDVH
tDVS
tDVH
tDVS
tDVH
DD (15:0)
(device)
DSTROBE
(host)
tDH
tDS
tDH
tDS
tDH
DD (15:0)
(host)
Note:
DD (15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as
cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven
by the device.
Figure 22. Sustained Ultra DMA data-in Burst
DMARQ
(device)
DMACKn
(host)
tRP
STOP
(host)
HDMARDYn
(host)
tSR
tRFS
DSTROBE
(device)
DD(15:0)
(device)
Figure 23. Host Pausing an Ultra DMA data-in Burst
38
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
DMARQ
(device)
tMLI
DMACKn
(host)
tLI
tLI
tACK
STOP
(host)
tLI
tACK
HDMARDYn
(host)
tSS
tIORDYZ
DSTROBE
(device)
tZAH
tAZ
tDVS
tDVH
CRC
DD (15:0)
IDEDA[2:0]
tACK
IDECS0n,
IDECS1n
Note:
The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are no
longer in effect after DMARQ and DMACKn are negated.
Figure 24. Device Terminating an Ultra DMA data-in Burst
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
39
EP9315
Enhanced Universal Platform SOC Processor
DMARQ
(device)
tLI
tMLI
DMACKn
(host)
tZAH
tRP
tAZ
tACK
STOP
(host)
tACK
HDMARDYn
(host)
tRFS
tLI
tMLI
tIORDYZ
DSTROBE
(device)
tDVS
tDVH
CRC
DD (15:0)
IDEDA[2:0]
tACK
IDECS0n,
IDECS1n
Note:
The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are no
longer in effect after DMARQ and DMACKn are negated.
Figure 25. Host Terminating an Ultra DMA data-in Burst
40
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
DMARQ
(device)
tUI
DMACKn
(host)
tACK
tENV
STOP
(host)
tZIORDY
tLI
tUI
DDMARDYn
(device)
HSTROBE
(host)
tACK
DD (15:0)
tDVS
tDVH
IDEDA[2:0]
tACK
IDECS0n,
IDECS1n
Note:
The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are not
in effect until DMARQ and DMACKn are asserted.
Figure 26. Initiating an Ultra DMA data-out Burst
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
41
EP9315
Enhanced Universal Platform SOC Processor
t2CYCWR
tCYCWR
tCYCWR
t2CYCWR
HSTROBE
(host)
tDVH
tDVS
tDVH
tDVS
tDVH
DD (15:0)
(host)
HSTROBE
(device)
tDH
tDS
tDH
tDS
tDH
DD (15:0)
(device)
Note:
DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as
cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are
driven by the host.
Figure 27. Sustained Ultra DMA data-out Burst
DMARQ
(device)
tRP
DMACKn
(host)
STOP
(host)
DDMARDYn
(device)
tSR
tRFS
HSTROBE
(host)
DD (15:0)
(host)
Note:
1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDYn is
negated.
2. If the tSR timing is not satisfied, the device may receive zero, one, or two more data words from the host.
Figure 28. Device Pausing an Ultra DMA data-out Burst
42
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
DMARQ
(device)
tLI
tMLI
DMACKn
(host)
tLI
tSS
tACK
STOP
(host)
tLI
tIORDYZ
DDMARDYn
(device)
tACK
HSTROBE
(host)
tDVS
DD (15:0)
(host)
tDVH
CRC
IDEDA[2:0]
tACK
IDECS0n,
IDECS1n
Note:
The definitions for the DIOWn:STOP, IORDY:DDMARDYn:DSTROBE and DIORn:HDMARDYn:HSTROBE signal lines are no
longer in effect after DMARQ and DMACKn are negated.
Figure 29. Host Terminating an Ultra DMA data-out Burst
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
43
EP9315
Enhanced Universal Platform SOC Processor
DMARQ
(device)
tLI
DMACKn
(host)
tRP
tMLI
tACK
STOP
(host)
tIORDYZ
DDMARDYn
(device)
tRFS
tLI
tMLI
tACK
HSTROBE
(host)
tDVS
DD (15:0)
(host)
tDVH
CRC
IDEDA[2:0]
tACK
IDECS0n,
IDECS1n
Note:
The definitions for the DIOWn:STOP, IORDY:DDMARDYn:DSTROBE and DIORn:HDMARDYn:HSTROBE signal lines are no
longer in effect after DMARQ and DMACKn are negated.
Figure 30. Device Terminating an Ultra DMA data-out Burst
44
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Ethernet MAC Interface
Min
Parameter
Typ
Max
Symbol
10 Mbit
mode
100 Mbit
mode
10 Mbit
mode
100 Mbit
mode
10 Mbit
mode
100 Mbit
mode
Unit
TXCLK cycle time
tTX_per
-
-
400
40
-
-
ns
TXCLK high time
tTX_high
140
14
200
20
260
26
ns
TXCLK low time
tTX_low
140
14
200
20
260
26
ns
TXCLK to signal transition delay time
tTXd
0
0
10
10
25
25
ns
TXCLK rise/fall time
tTXrf
-
-
-
-
5
5
ns
RXCLK cycle time
tRX_per
-
-
400
40
-
-
ns
RXCLK high time
tRX_high
140
14
200
20
260
26
ns
RXCLK low time
tRX_low
140
14
200
20
260
26
ns
tRXs
10
10
-
-
-
-
ns
RXDVAL / RXERR hold time
tRXh
10
10
-
-
-
-
ns
RXCLK rise/fall time
tRXrf
-
-
-
-
5
5
ns
RXDVAL / RXERR setup time
MDC cycle time
tMDC_per
-
-
400
400
-
-
ns
MDC high time
tMDC_high
160
160
-
-
-
-
ns
MDC low time
tMDC_low
160
160
-
-
-
-
ns
MDC rise/fall time
tMDCrf
-
-
-
-
5
5
ns
MDIO setup time (STA sourced)
tMDIOs
10
10
-
-
-
-
ns
MDIO hold time (STA sourced)
tMDIOh
10
10
-
-
-
-
ns
MDC to MDIO signal transition delay time
(PHY sourced)
tMDIOd
-
-
-
-
300
300
ns
STA - Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer
(PHY) interface to the wireless medium.
PHY - Ethernet physical layer interface.
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
45
EP9315
Enhanced Universal Platform SOC Processor
tTX_high
tTX_low
TXCLK
TXD[3:0]/
TXEN/
TXERR
tTXd
tTX_per
tRX_low
tRX_high
RXCLK
tRXh
RXD[3:0]/
RXDVAL/
RXERR
tRX_per
tRXs
MDC
MDIO
(Sourced
by STA)
tMDC_high
tMDC_low
tMDIOs
tMDIOh
tMDC_per
MDC
MDIO
(Sourced
by PHY)
tMDIOd
Figure 31. Ethernet MAC Timing Measurement
46
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Audio Interface
The following table contains the values for the timings of each of the SPI modes.
Parameter
Symbol
Min
Typ
Max
Unit
SCLK cycle time
tclk_per
-
tspix_clk
-
ns
SCLK high time
tclk_high
-
(tspix_clk) / 2
-
ns
SCLK low time
tclk_low
-
(tspix_clk) / 2
-
ns
SCLK rise/fall time
tclkrf
1
-
8
ns
Data from master valid delay time
tDMd
-
-
3
ns
Data from master setup time
tDMs
20
-
-
ns
Data from master hold time
tDMh
40
-
-
ns
Data from slave setup time
tDSs
20
-
-
ns
Data from slave hold time
tDSh
40
-
-
ns
Note:
DS638F2
The tspix_clk is programmable by the user.
Copyright 2010 Cirrus Logic (All Rights Reserved)
47
EP9315
Enhanced Universal Platform SOC Processor
Texas Instruments’ Synchronous Serial Format
tclk_per
tclk_high
tclkrf
SCLK
tclk_low
SFRM
SSPTXD/
SSPRXD
MSB
LSB
4 to 16 bits
Figure 32. TI Single Transfer Timing Measurement
Microwire
tclk_high
tclk_per
tclkrf
SCLK
tclk_low
SFRM
SSPTXD
LSB
MSB
8-bit control
SSPRXD
0
MSB
LSB
4 to 16 bits output data
Figure 33. Microwire Frame Format, Single Transfer
48
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Motorola SPI
tclk_per
tclk_high
tclkrf
SCLK
(SPO=0)
tclk_low
SCLK
(SPO=1)
tDMs
SSPTXD
(master)
tDMh
MSB
LSB
tDMd
tDSs
SSPRXD
(slave)
tDSh
MSB
LSB
SFRM
Figure 34. SPI Format with SPH=1 Timing Measurement
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
49
EP9315
Enhanced Universal Platform SOC Processor
Inter-IC Sound - I2S
Parameter
Symbol
Min
Typ
Max
Unit
SCLK cycle time
tclk_per
-
ti2s_clk
-
ns
SCLK high time
tclk_high
-
(ti2s_clk) / 2
-
ns
SCLK low time
tclk_low
-
(ti2s_clk) / 2
-
ns
SCLK rise/fall time
tclkrf
1
4
8
ns
SCLK to LRCLK assert delay time
tLRd
-
-
3
ns
Hold between SCLK assert then LRCLK deassert
or
Hold between LRCLK deassert then SCLK assert
tLRh
0
-
-
ns
SDI to SCLK deassert setup time
tSDIs
12
-
-
ns
SDI from SCLK deassert hold time
tSDIh
0
-
-
ns
SCLK assert to SDO delay time
tSDOd
-
-
9
ns
SDO from SCLK assert hold time
tSDOh
1
-
-
ns
Note:
ti2s_clk is programmable by the user.
tclk_per
tclk_low
tclk_high
tclkrf
SCLK
tLRd
tLRh
LRCLK
tSDIs
tSDIh
SDI
tSDOd
tSDOh
SDO
Figure 35. Inter-IC Sound (I2S) Timing Measurement
50
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
AC’97
Parameter
Symbol
Min
Typ
Max
Unit
ABITCLK input cycle time
tclk_per
-
81.4
-
ns
ABITCLK input high time
tclk_high
36
-
45
ns
ABITCLK input low time
tclk_low
ns
36
-
45
tclkrf
2
-
6
ns
ASDI setup to ABITCLK falling
ts
10
-
-
ns
ASDI hold after ABITCLK falling
th
10
-
-
ns
ASDI input rise/fall time
trfin
2
-
6
ns
ABITCLK rising to ASDO / ASYNC valid, CL = 55 pF
tco
2
-
15
ns
trfout
2
-
6
ns
ABITCLK input rise/fall time
ASYNC / ASDO rise/fall time, CL = 55 pF
tclk_high
tclk_low
tclk_per
ABITCLK
tclkrf
tclkrf
th
ts
trfin
ASDI
ASDO
trfout
tco
tco
tco
ASYNC
trfout
trfout
Figure 36. AC ‘97 Configuration Timing Measurement
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
51
EP9315
Enhanced Universal Platform SOC Processor
LCD Interface
Parameter
Symbol
Min
Typ
Max
Unit
SPCLK rise/fall time
tclkr
2
-
8
ns
SPCLK rising edge to control signal transition time
tCD
-
-
3
ns
SPCLK rising edge to data transition time
tDD
-
-
10
ns
Data valid time
tDv
tSPCLK
-
-
ns
tclkrf
tclkrf
SPCLK
HSYNC/
V_CSYNC/
BLANK/
BRIGHT
tCD
tDD
P [17:0]
tDv
Figure 37. LCD Timing Measurement
52
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
ADC
Parameter
Resolution
Comment
Value
No missing codes
Range of 0 to 3.3 V
50K counts (approximate)
Integral non-linearity
Units
0.01%
Offset error
±15
Full scale error
mV
0.2%
Maximum sample rate
ADIV = 0
ADIV = 1
3750
925
Samples per second
Samples per second
Channel switch settling time
ADIV = 0
ADIV = 1
500
2
μs
ms
120
μV
Noise (RMS) - typical
Note:
ADIV refers to bit 16 in the KeyTchClkDiv register.
ADIV = 0 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 4.
ADIV = 1 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 16.
61A8
0000
FFFF
9E58
0
Vref/2
Vref
A/D Converter Transfer Function
(approximately ±25,000 counts)
Figure 38. ADC Transfer Function
Using the ADC:
This ADC has a state-machine based conversion engine that automates the conversion process. The initiator for a
conversion is the read access of the TSXYResult register by the CPU. The data returned from reading this register
contains the result as well as the status bit indicating the state of the ADC. However, this peripheral requires a delay
between each successful conversion and the issue of the next conversion command, or else the returned value of
successive samples may not reflect the analog input. Since the state of the ADC state machine is returned through the
same channel used to initiate the conversion process, there must be a delay inserted after every complete conversion.
Note that reading TSXYResult during a conversion will not affect the result of the ongoing process.
The following is a recommended procedure for safely polling the ADC from software:
1. Read the TSXYResult register into a local variable to initiate a conversion.
2. If the value of bit 31 of the local variable is '0' then repeat step 1.
3. Delay long enough to meet the maximum sample rate as shown above.
4. Mask the local variable with 0xFFFF to remove extraneous data.
5. If signed mode is used, do a sign extend of the lower halfword.
6. Return the sampled value.
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
53
EP9315
Enhanced Universal Platform SOC Processor
JTAG
Parameter
Symbol
Min
Max
Units
TCK clock period
tclk_per
100
-
ns
TCK clock high time
tclk_high
50
-
ns
TCK clock low time
tclk_low
50
-
ns
TMS / TDI to clock rising setup time
tJPs
20
-
ns
Clock rising to TMS / TDI hold time
tJPh
45
-
ns
JTAG port clock to output
tJPco
-
30
ns
JTAG port high impedance to valid output
tJPzx
-
30
ns
JTAG port valid output to high impedance
tJPxz
-
30
ns
TMS
TDI
tclk_per
tclk_high
tJPs
tJPh
tclk_low
TCK
tJPzx
tJPco
tJPxz
TDO
Figure 39. JTAG Timing Measurement
54
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
352 Pin BGA Package Outline
352-Ball PBGA Diagram
Ø0.30 S C A B
Ø0.10 S C
Øb
E3 E2
3
E
DETAIL B
D3
D2
D
(Top View)
B
2
-A-
A
-CA1
e
ddd C
c
E1
-B-
A'
B
D1
DETAIL A'
A2
(Bottom View)
Figure 40. 352 Pin PBGA Pin Diagram
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
55
EP9315
Enhanced Universal Platform SOC Processor
Table R. 352 Pin Diagram Dimensions
dimension in mm
dimension in inches
Symbol
MIN
MAX
MIN
NOM
MAX
A
2.20
2.30
2.50
0.087
0.092
0.098
A1
-
0.60
-
-
0.024
-
A2
1.12
1.17
1.22
0.044
0.046
0.048
b
-
0.75
-
-
0.030
-
c
0.51
0.56
0.61
0.020
0.022
0.024
D
26.80
27.00
27.20
1.055
1.063
1.071
D1
-
24.13
-
-
0.950
-
D2
23.80
24.00
24.20
0.937
0.945
0.953
D3
17.95
18.00
18.05
0.707
0.709
0.711
E
26.80
27.00
27.20
1.055
1.063
1.071
E1
-
24.13
-
-
0.950
-
E2
23.80
24.00
24.20
0.937
0.945
0.953
E3
17.95
18.00
18.05
0.707
0.709
0.711
e
-
1.27
-
-
0.050
-
ddd
-
-
0.15
-
-
0.006
q
Note:
NOM
30° TYP
30° TYP
1. Controlling Dimension: Millimeter.
2. Primary Datum C and seating plane are defined by the spherical crowns of the solder balls.
3. Dimension b is measured at the maximum solder ball diameter, parallel to Primary Datum C.
4. There shall be a minimum clearance of 0.25 mm between the edge of the solder ball and the body edge.
5. Reference Document: JEDEC MO-151, BAL-2
352 Pin BGA Pinout (Bottom View)
The following table shows the 352 pin BGA pinout. (For better understanding, compare the coordinates on the x and y
axis on Figure 40, "352 PIN BGA PINOUT", on page 57 with Figure 40, "352 Pin PBGA Pin Diagram", on page 55.
• VDD_core is CVDD.
• VDD_ring is RVDD.
• All core and ring grounds are connected together and are labelled GND.
• Other special power requirements are clearly labelled (i.e. H18=ADC_VDD and H19=ADC_GND).
• NC means that the pin is not connected.
56
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
1
Y HSYNC
2
3
4
DD[1]
DD[12]
P[2]
5
6
7
AD[15] DA[6] DA[4]
Copyright 2010 Cirrus Logic (All Rights Reserved)
W
P[12]
P[9]
DD[0]
P[5]
P[3]
V
P[16]
P[11]
P[8]
DD[15]
DD[13]
U
AD[0]
P[15]
P[10]
P[7]
P[6]
T
DA[8]
BLANK
P[13]
SPCLK
R
AD[2]
AD[1]
P[17]
P[14]
P
AD[4]
DA[10]
DA[9] BRIGHT RVDD
8
AD[10
DA[1]
]
10
11
12
13
AD[8]
IDEDA[
0]
DTRN
TDO
14
15
BOOT[0] EEDAT
16
17
ASDO
SFRM1
AD[11
AD[9]
]
IDECS1 IDEDA[
N
1]
TCK
TMS
EECLK
P[1]
AD[1 AD[12
DA[2]
4]
]
IDECS0 IDEDA[
N
2]
TDI
GND
ASYNC SSPTX1 INT[2]
P[4]
P[0]
DA[7] DA[5]
AD[13
DA[3]
]
CVD
V_CSY DD[1
GND
D
NC
4]
RVDD
9
RVDD
DA[0]
GND
DSRN BOOT[1]
GND
RVDD
CVD
RVD
GND
D
D
19
20
RDLED USBP[1] ABITCLK Y
INT[3]
SLA[1]
SLA[0]
RXD[2] W
RTSN
USBP[0]
CTSN
TXD[0]
TXD[1]
ROW[1] U
TXD[2] ROW[2]
ROW[4] T
V
NC
SSPRX1
INT[1]
PWMO
USBM[0] RXD[1]
UT
CVDD
GND
INT[0]
USBM[1
RXD[0]
]
CVDD
GND
RVDD
RVDD
RVDD
RVDD
XTALI
PLL_VD
ROW[6]
D
ROW[7] P
GND
GND
XTALO
COL[0]
COL[1]
COL[2]
N
RVD
D
CVD
D
SCLK1 GRLED
18
ROW[0] ROW[3]
PLL_GN
ROW[5] R
D
GND
GND
GND
GND
GND
GND
CVDD
GND
GND
GND
GND
GND
GND
GND
COL[4]
COL[3]
COL[6]
CSN[0]
M
DA[17] DA[16] DA[15]
GND
GND
GND
GND
GND
GND
GND
CVDD
COL[5]
COL[7] RSTON
PRSTN
L
K AD[22]
DA[20] AD[21] DA[19]
RVDD
GND
GND
GND
GND
GND
GND
CVDD
SYM
SYP
SXM
SXP
K
J DA[21]
DQMN[ DQMN[ DQMN[2
0]
1]
]
GND
GND
GND
GND
GND
GND
GND
CVDD
RTCXTA
LI
XM
YP
YM
J
GND
GND
GND
GND
GND
GND
RVDD
RTCXTA ADC_V ADC_G
LO
DD
ND
XP
H
N DA[13]
DA[12] DA[11]
AD[3]
CVDD
M AD[7]
DA[14]
AD[5]
L DA[18]
AD[6]
SDCSN[
CVDD
2]
H
DQMN[
3]
G
SDCSN[ SDCSN[ SDWE
SDCLK
0]
1]
N
RVDD
RVD
D
F
SDCSN[
DA[22] DA[24] AD[25]
3]
RVDD
GND
CVD
D
GND
GND
CVD CVD
D
D
CASN
RASN
E AD[23]
DA[23] DA[26] CSN[6]
D AD[24]
DA[25] DD[11]
SDCLK
EN
AD[19] DD[9] DD[5]
RVDD
GND
GND
AD[16 MIIRXD[ MIITXD[
TXEN
]
2]
3]
RVDD
DD[10] DD[6] DD[2] MDC
MIITXD[
MIIRXD[
READY
TXCLK
0]
3]
B CSN[2] DA[31] DA[30] DA[27]
DD[7] DD[3] WRN MDIO
MIIRXD[
MIITXD[
RXERR
1]
1]
A CSN[7] DA[28] AD[18]
DD[8]
DD[4]
4
5
2
3
CRS
RXCL MIIRXD[ RXDVA MIITXD[
AD[1
TXERR
RDN
K
0]
L
2]
7]
6
7
8
9
10
11
RVDD EGPIO[7]
EGPIO[ EGPIO[1 EGPIO[11
G
9]
0]
]
CVDD
GND
GND
EGPIO[2]
EGPIO[ EGPIO[6
EGPIO[8] F
4]
]
CVDD
GND
ASDI
DIOWN
EGPIO[ EGPIO[3
EGPIO[5] E
0]
]
MCWAI MCDAE MCADE EGPIO[
TN
NN
NN
14]
C CSN[1] CSN[3] AD[20] DA[29]
1
CVDD
RVDD
12
MCD2
WP
USBM[2] ARSTN DIORN EGPIO[1] D
MCDIR MCELN IORDN MCWRN USBP[2] IORDY DMACKN C
VS1
MCD1
CLD
VS2
13
14
EGPIO[1
MCBVD
MCRDN WAITN
MCEHN
3]
2
TRSTN
B
MCRESE
MCBVD MCREG EGPIO[1 EGPIO[
A
IOWRN
TN
1
N
2]
15]
15
16
17
18
19
20
EP9315
Enhanced Universal Platform SOC Processor
57
Figure 40. 352 PIN BGA PINOUT
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Pin List
The following Plastic Ball Grid Array (PBGA) ball assignment table is sorted in order of ball.
58
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
A1
A2
CSN[7]
E9
RVDD
L3
DA[16]
T13
CVDD
DA[28]
E10
GND
L4
DA[15]
T14
GND
A3
AD[18]
A4
DD[8]
E11
GND
L5
GND
T15
INT[0]
E12
RVDD
L8
GND
T16
USBM[1]
A5
DD[4]
E13
A6
AD[17]
E14
CVDD
L9
GND
T17
RXD[0]
CVDD
L10
GND
T18
TXD[2]
A7
RDN
E15
A8
RXCLK
E16
GND
L11
GND
T19
ROW[2]
ASDI
L12
GND
T20
ROW[4]
A9
MIIRXD[0]
E17
DIOWN
L13
GND
U1
AD[0]
A10
RXDVAL
E18
EGPIO[0]
L16
CVDD
U2
P[15]
A11
MIITXD[2]
E19
EGPIO[3]
L17
COL[5]
U3
P[10]
A12
TXERR
E20
EGPIO[5]
L18
COL[7]
U4
P[7]
A13
CLD
F1
SDCSN[3]
L19
RSTON
U5
P[6]
A14
VS2
F2
DA[22]
L20
PRSTN
U6
P[4]
A15
MCBVD1
F3
DA[24]
M1
AD[7]
U7
P[0]
A16
MCREGN
F4
AD[25]
M2
DA[14]
U8
AD[13]
A17
EGPIO[12]
F5
RVDD
M3
AD[6]
U9
DA[3]
A18
EGPIO[15]
F6
GND
M4
AD[5]
U10
DA[0]
A19
IOWRN
F7
CVDD
M5
CVDD
U11
DSRN
A20
MCRESETN
F14
CVDD
M8
GND
U12
BOOT[1]
B1
CSN[2]
F15
GND
M9
GND
U13
NC
B2
DA[31]
F16
GND
M10
GND
U14
SSPRX1
B3
DA[30]
F17
EGPIO[2]
M11
GND
U15
INT[1]
B4
DA[27]
F18
EGPIO[4]
M12
GND
U16
PWMOUT
B5
DD[7]
F19
EGPIO[6]
M13
GND
U17
USBM[0]
B6
DD[3]
F20
EGPIO[8]
M16
GND
U18
RXD[1]
B7
WRN
G1
SDCSN[0]
M17
COL[4]
U19
TXD[1]
B8
MDIO
G2
SDCSN[1]
M18
COL[3]
U20
ROW[1]
B9
MIIRXD[1]
G3
SDWEN
M19
COL[6]
V1
P[16]
B10
RXERR
G4
SDCLK
M20
CSN[0]
V2
P[11]
B11
MIITXD[1]
G5
RVDD
N1
DA[13]
V3
P[8]
B12
CRS
G6
RVDD
N2
DA[12]
V4
DD[15]
B13
VS1
G15
RVDD
N3
DA[11]
V5
DD[13]
B14
MCD1
G16
RVDD
N4
AD[3]
V6
P[1]
B15
MCBVD2
G17
EGPIO[7]
N5
CVDD
V7
AD[14]
B16
MCEHN
G18
EGPIO[9]
N6
CVDD
V8
AD[12]
B17
EGPIO[13]
G19
EGPIO[10]
N8
GND
V9
DA[2]
B18
MCRDN
G20
EGPIO[11]
N9
GND
V10
IDECS0N
B19
WAITN
H1
DQMN[3]
N10
GND
V11
IDEDA[2]
B20
TRSTN
H2
CASN
N11
GND
V12
TDI
C1
CSN[1]
H3
RASN
N12
GND
V13
GND
C2
CSN[3]
H4
SDCSN[2]
N13
GND
V14
ASYNC
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
C3
AD[20]
H5
CVDD
N15
GND
V15
SSPTX1
C4
DA[29]
H8
GND
N16
GND
V16
INT[2]
C5
DD[10]
H9
GND
N17
XTALO
V17
RTSN
C6
DD[6]
H10
GND
N18
COL[0]
V18
USBP[0]
C7
DD[2]
H11
GND
N19
COL[1]
V19
CTSN
C8
MDC
H12
GND
N20
COL[2]
V20
TXD[0]
C9
MIIRXD[3]
H13
GND
P1
AD[4]
W1
P[12]
C10
TXCLK
H16
RVDD
P2
DA[10]
W2
P[9]
C11
MIITXD[0]
H17
RTCXTALO
P3
DA[9]
W3
DD[0]
C12
READY
H18
ADC_VDD
P4
BRIGHT
W4
P[5]
C13
MCD2
H19
ADC_GND
P5
RVDD
W5
P[3]
C14
MCDIR
H20
XP
P6
RVDD
W6
DA[7]
C15
MCELN
J1
DA[21]
P15
RVDD
W7
DA[5]
C16
IORDN
J2
DQMN[0]
P16
RVDD
W8
AD[11]
C17
MCWRN
J3
DQMN[1]
P17
XTALI
W9
AD[9]
C18
USBP[2]
J4
DQMN[2]
P18
PLL_VDD
W10
IDECS1N
C19
IORDY
J5
GND
P19
ROW[6]
W11
IDEDA[1]
C20
DMACKN
J8
GND
P20
ROW[7]
W12
TCK
D1
AD[24]
J9
GND
R1
AD[2]
W13
TMS
D2
DA[25]
J10
GND
R2
AD[1]
W14
EECLK
D3
DD[11]
J11
GND
R3
P[17]
W15
SCLK1
D4
SDCLKEN
J12
GND
R4
P[14]
W16
GRLED
D5
AD[19]
J13
GND
R5
RVDD
W17
INT[3]
D6
DD[9]
J16
CVDD
R6
RVDD
W18
SLA[1]
D7
DD[5]
J17
RTCXTALI
R7
GND
W19
SLA[0]
D8
AD[16]
J18
XM
R8
CVDD
W20
RXD[2]
D9
MIIRXD[2]
J19
YP
R13
CVDD
Y1
HSYNC
D10
MIITXD[3]
J20
YM
R14
GND
Y2
DD[1]
D11
TXEN
K1
AD[22]
R15
RVDD
Y3
DD[12]
D12
MCWAITN
K2
DA[20]
R16
RVDD
Y4
P[2]
D13
MCDAENN
K3
AD[21]
R17
ROW[0]
Y5
AD[15]
D14
MCADENN
K4
DA[19]
R18
ROW[3]
Y6
DA[6]
D15
EGPIO[14]
K5
RVDD
R19
PLL_GND
Y7
DA[4]
D16
WP
K8
GND
R20
ROW[5]
Y8
AD[10]
D17
USBM[2]
K9
GND
T1
DA[8]
Y9
DA[1]
D18
ARSTN
K10
GND
T2
BLANK
Y10
AD[8]
D19
DIORN
K11
GND
T3
P[13]
Y11
IDEDA[0]
D20
EGPIO[1]
K12
GND
T4
SPCLK
Y12
DTRN
E1
AD[23]
K13
GND
T5
V_CSYNC
Y13
TDO
E2
DA[23]
K16
CVDD
T6
DD[14]
Y14
BOOT[0]
E3
DA[26]
K17
SYM
T7
GND
Y15
EEDAT
E4
CSN[6]
K18
SYP
T8
CVDD
Y16
ASDO
E5
GND
K19
SXM
T9
RVDD
Y17
SFRM1
E6
GND
K20
SXP
T10
GND
Y18
RDLED
E7
CVDD
L1
DA[18]
T11
GND
Y19
USBP[1]
E8
CVDD
L2
DA[17]
T12
RVDD
Y20
ABITCLK
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
59
EP9315
Enhanced Universal Platform SOC Processor
The following section focuses on the EP9315 pin signals
from two viewpoints - the pin usage and pad
characteristics, and the pin multiplexing usage. The first
table (Table S) is a summary of all the EP9315 pin
signals. The second table (Table T) illustrates the pin
signal multiplexing and configuration options.
Table S is a summary of the EP9315 pin signals, which
illustrates the pad type and pad pull type (if any). The
symbols used in the table are defined as follows. (Note: A
blank box means Not Applicable (NA) or, for Pull Type,
No Pull (NP).)
Under the Pad Type column:
• A - Analog pad
• P - Power pad
• G - Ground pad
• I - Pin is an input only
• I/O - Pin is input/output
• 4mA - Pin is a 4 mA output driver
• 8mA - Pin is an 8 mA output driver
• 12mA - Pin is an 12 mA output driver
See the text description for additional information about
bi-directional pins.
Under the Pull Type Column:
•
•
PU - Resistor is a pull up to the RVDD supply
PD - Resistor is a pull down to the RGND supply
Table S. Pin Descriptions (Continued)
.
Table S. Pin Descriptions
Pin Name
TCK
Block
Pad
Type
Pull
Type
JTAG
I
PD
TDI
JTAG
I
TDO
JTAG
4ma
TMS
JTAG
I
TRSTn
BOOT[1:0]
PD
Block
Pad
Type
Pull
Type
SPCLK
Raster
12ma
PU
Pixel clock in/out
HSYNC
Raster
8ma
PU
Horizontal synchronization / line pulse out
V_CSYNC
Raster
8ma
PU
Vertical or composite synchronization / frame
pulse out
JTAG test mode select
BLANK
Raster
8ma
PU
Composite blanking signal out
Pin Name
Description
JTAG clock in
JTAG data in
JTAG data out
PD
Description
JTAG
I
PD
JTAG reset
BRIGHT
Raster
4ma
PWM brightness control out
System
I
PD
Boot mode select in
PWMOUT
PWM
8ma
Pulse width modulator output
XTALI
PLL
A
Main oscillator input
Xp, Xm
ADC
A
Touchscreen ADC X axis
XTALO
PLL
A
Main oscillator output
Yp, Ym
ADC
A
Touchscreen ADC Y axis
Touchscreen ADC X axis feedback
VDD_PLL
PLL
P
Main oscillator power, 1.8V
sXp, sXm
ADC
A
GND_PLL
PLL
G
Main oscillator ground
sYp, sYm
ADC
A
Touchscreen ADC Y axis feedback
RTCXTALI
RTC
A
RTC oscillator input
VDD_ADC
ADC
P
Touchscreen ADC power, 3.3V
RTCXTALO
RTC
A
RTC oscillator output
GND_ADC
ADC
G
Touchscreen ADC ground
WRn
EBUS
4ma
SRAM Write strobe out
COL[7:0]
Key
8ma
PU
RDn
EBUS
4ma
SRAM Read / OE strobe out
ROW[7:0]
Key
8ma
PU
WAITn
EBUS
I
SRAM Wait in
USBp[2:0]
USB
A
USB positive signals
AD[25:0]
EBUS
8ma
Shared Address bus out
USBm[2:0]
USB
A
USB negative signals
PU
Key matrix column inputs
Key matrix row outputs
DA[31:0]
EBUS
8ma
PU
Shared Data bus in/out
TXD0
UART1
4ma
CSn[3:0]
EBUS
4ma
PU
Chip select out
RXD0
UART1
I
PU
CSn[7:6]
EBUS
4ma
PU
Chip select out
CTSn
UART1
I
PU
Clear to send / transmit enable
DQMn[3:0]
EBUS
8ma
Shared data mask out
DSRn
UART1
I
PU
Data set ready / Data Carrier Detect
SDCLK
SDRAM
8ma
SDRAM clock out
DTRn
UART1
4ma
SDCLKEN
SDRAM
8ma
SDRAM clock enable out
RTSn
UART1
4ma
Ready to send
SDCSn[3:0]
SDRAM
4ma
SDRAM chip selects out
TXD1
UART2
4ma
Transmit / IrDA output
RASn
SDRAM
8ma
SDRAM RAS out
RXD1
UART2
I
CASn
SDRAM
8ma
SDRAM CAS out
TXD2
UART3
4ma
SDWEn
SDRAM
8ma
SDRAM write enable out
RXD2
UART3
I
P[17:0]
Raster
4ma
Pixel data bus out
MDC
EMAC
4ma
60
PU
Copyright 2010 Cirrus Logic (All Rights Reserved)
Transmit out
Receive in
Data Terminal Ready output
PU
Receive / IrDA input
Transmit
PU
Receive
Management data clock
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Table S. Pin Descriptions (Continued)
Block
Pad
Type
Pull
Type
MDIO
EMAC
4ma
RXCLK
EMAC
I
MIIRXD[3:0]
EMAC
RXDVAL
EMAC
RXERR
TXCLK
Pin Name
Table S. Pin Descriptions (Continued)
Description
Pin Name
Block
Pad
Type
Pull
Type
PU
Management data input/output
EGPIO[15:0]
GPIO
I/O, 4 ma
PU
Enhanced GPIO
PD
Receive clock in
DD[15:8]
IDE
8ma
PU
IDE data bus
I
PD
Receive data in
DD7
IDE
8ma
PD
IDE data bus
I
PD
Receive data valid
DD[6:0]
IDE
8ma
PU
IDE data bus
EMAC
I
PD
Receive data error
IDEDA[2:0]
IDE
8ma
IDE Device address output
EMAC
I
PU
Transmit clock in
IDECS0n
IDE
8ma
IDE Chip Select 0 output
IDE Chip Select 1 output
Description
MIITXD[3:0]
EMAC
I
PD
Transmit data out
IDECS1n
IDE
8ma
TXEN
EMAC
4ma
PD
Transmit enable
DIORn
IDE
8ma
IDE Read strobe output
TXERR
EMAC
4ma
PD
Transmit error
DIOWn
IDE
8ma
IDE Write strobe output
CRS
EMAC
I
PD
Carrier sense
DMACKn
IDE
8ma
IDE DMA acknowledge output
CLD
PU
EMAC
I
Collision detect
IORDY
IDE
I
GRLED
LED
12ma
Green LED
CVDD
Power
P
RDLED
LED
12ma
Red LED
RVDD
Power
P
Digital power, 3.3V
EECLK
EEPROM
4ma
PU
EEPROM / Two-wire Interface clock
CGND
Ground
G
Digital ground
EEDAT
EEPROM
4ma
PU
EEPROM / Two-wire Interface data
RGND
Ground
G
Digital ground
AC97
8ma
PD
AC97 bit clock
ASYNC
AC97
8ma
PD
AC97 frame sync
ASDI
AC97
I
PD
AC97 Primary input
ASDO
AC97
8ma
PU
AC97 output
ARSTn
AC97
8ma
SCLK1
SPI1
8ma
PD
SPI bit clock
SFRM1
SPI1
8ma
PD
SPI Frame Clock
SSPRX1
SPI1
I
PD
SPI input
SSPTX1
SPI1
8ma
INT[3:0]
INT
I
PD
External interrupts
PRSTn
Syscon
I
PU
Power on reset
ABITCLK
IDE ready input
Digital power, 1.8V
AC97 reset
SPI output
RSTOn
Syscon
4ma
User Reset in out - open drain
SLA[1:0]
EEPROM
4ma
Flash programming voltage control
VS1
PCMCIA
I
PU
Voltage sense
VS2
PCMCIA
I
PU
Voltage sense
MCD1
PCMCIA
I
PU
Card detect
MCD2
PCMCIA
I
PU
Card detect
MCBVD1
PCMCIA
I
PU
Voltage detection / status change
MCBVD2
PCMCIA
I
PU
Voltage detection
MCDIR
PCMCIA
4ma
Data transceiver direction control
MCDAENn
PCMCIA
4ma
Data bus transceiver enable
MCADENn
PCMCIA
4ma
MCREGn
PCMCIA
4ma
PU
Memory card register
MCEHn
PCMCIA
4ma
PU
Memory card high byte select
MCELn
PCMCIA
4ma
PU
Memory card low byte select
IORDn
PCMCIA
4ma
PU
I/O card read
IOWRn
PCMCIA
4ma
PU
I/O card write
MCRDn
PCMCIA
4ma
PU
Memory card read
MCWRn
PCMCIA
4ma
PU
Memory card write
READY
PCMCIA
I
PU
Ready / interrupt
WP
PCMCIA
I
PU
Write protect
MCWAITn
PCMCIA
I
PU
Wait Input
MCRESETn
PCMCIA
4ma
DS638F2
PU
Address bus transceiver enable
Card reset
Copyright 2010 Cirrus Logic (All Rights Reserved)
61
EP9315
Enhanced Universal Platform SOC Processor
Table T illustrates the pin signal multiplexing and configuration options.
Table T. Pin Multiplex Usage Information
62
Physical
Pin Name
Description
Multiplex signal name
COL[7:0]
GPIO
GPIO Port D[7:0]
ROW[7:0]
GPIO
GPIO Port C[7:0]
EGPIO[0]
Ring Indicator Input
RI
EGPIO[1]
1Hz clock monitor
CLK1HZ
EGPIO[2]
IDE DMA request
DMARQ
EGPIO[3]
Transmit Enable output / HDLC clocks
TENn / HDLCCLK1 / HDLCCLK3
EGPIO[4]
I2S Transmit Data 1
SDO1
EGPIO[5]
I2S Receive Data 1
SDI1
EGPIO[6]
I2S Transmit Data 2
SDO2
EGPIO[7]
DMA Request 0
DREQ0
EGPIO[8]
DMA Acknowledge 0
DACK0
EGPIO[9]
DMA EOT 0
DEOT0
EGPIO[10]
DMA Request 1
DREQ1
EGPIO[11]
DMA Acknowledge 1
DACK1
EGPIO[12]
DMA EOT 1
DEOT1
EGPIO[13]
I2S Receive Data 2
SDI2
EGPIO[14]
PWM 1 output
PWMOUT1
EGPIO[15]
IDE Device active / present
DASP
ABITCLK
I2S Serial clock
SCLK
ASYNC
I2S Frame Clock
LRCK
ASDO
I2S Transmit Data 0
SDO0
ASDI
I2S Receive Data 0
SDI0
ARSTn
I2S Master clock
MCLK
SCLK1
I2S Serial clock
SCLK
SFRM1
I2S Frame Clock
LRCK
SSPTX1
I2S Transmit Data 0
SDO0
SSPRX1
I2S Receive Data 0
SDI0
IDEDA[2:0]
GPIO
GPIO Port E[7:5]
IDECS0n
GPIO
GPIO Port E[4]
IDECS1n
GPIO
GPIO Port E[3]
DIORn
GPIO
GPIO Port E[2]
GRLED
LED
GPIO Port E[1]
RDLED
LED
GPIO Port E[0]
DD[7:0]
GPIO
GPIO Port H[7:0]
DD[15:12]
GPIO
GPIO Port G[7:4]
SLA[1:0]
GPIO
GPIO Port G[3:2]
EEDAT
GPIO
GPIO Port G[1]
EECLK
GPIO
GPIO Port G[0]
FGPIO[7]
GPIO
VS2
FGPIO[6]
GPIO
READY
FGPIO[5]
GPIO
VS1
FGPIO[4]
GPIO
MCBVD2
FGPIO[3]
GPIO
MCBVD1
FGPIO[2]
GPIO
MCD2
FGPIO[1]
GPIO
MCD1
FGPIO[0]
GPIO
WP
Copyright 2010 Cirrus Logic (All Rights Reserved)
DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Acronyms and Abbreviations
The following tables list abbreviations and acronyms
used in this data sheet.
Term
Term
Definition
OHCI
Open Host Controller Interface
PHY
Ethernet PHYsical layer interface
PIO
Programmed I/O
RISC
Reduced Instruction Set Computer
SDMI
Secure Digital Music Initiative
SDRAM
Synchronous Dynamic RAM
SPI
Serial Peripheral Interface
SRAM
Static Random Access Memory
STA
Station - Any device that contains an IEEE 802.11
conforming Medium Access Control (MAC) and physical
layer (PHY) interface to the wireless medium
TFT
Thin Film Transistor
TLB
Translation Lookaside Buffer
USB
Universal Serial Bus
Definition
ADC
Analog-to-Digital Converter
ALT
Alternative
AMBA
Advanced Micro-controller Bus Architecture
ATAPI
ATA Packet Interface
CODEC
COder / DECoder
CRC
Cyclic Redundancy Check
DAC
Digital-to-Analog Converter
DMA
Direct-Memory Access
EBUS
External Memory Bus
EEPROM Electronically Erasable Programmable Read Only Memory
EMAC
Ethernet Media Access Controller
FIFO
First In / First Out
FIQ
Fast Interrupt Request
FLASH
Flash memory
GPIO
General Purpose I/O
HDLC
High-level Data Link Control
I/F
Units of Measurement
Symbol
Unit of Measure
°C
degree Celsius
Hz
Hertz = cycle per second
Kbps
Kilobits per second
Interface
kbyte
Kilobyte
I2S
Inter-IC Sound
kHz
KiloHertz = 1000 Hz
IC
Integrated Circuit
Mbps
Megabits per second
ICE
In-Circuit Emulator
MHz
MegaHertz = 1,000 kHz
IDE
Integrated Drive Electronics
μA
microAmpere = 10-6 Ampere
IEEE
Institute of Electronics and Electrical Engineers
μs
microsecond = 1,000 nanoseconds = 10-6 seconds
IrDA
Infrared Data Association
mA
milliAmpere = 10-3 Ampere
IRQ
Standard Interrupt Request
ms
millisecond = 1,000 microseconds = 10-3 seconds
ISO
International Standards Organization
mW
milliWatt = 10-3 Watts
JTAG
Joint Test Action Group
ns
nanosecond = 10-9 seconds
LFSR
Linear Feedback Shift Register
pF
picoFarad = 10-12 Farads
MII
Media Independent Interface
V
Volt
W
Watt
MMU
Memory Management Unit
DS638F2
Copyright 2010 Cirrus Logic (All Rights Reserved)
63
EP9315
Enhanced Universal Platform SOC Processor
Ordering Information
The order numbers for the device are:
EP9315-CBZ
EP9315-IBZ
0 °C to +70 °C
-40 °C to +85 °C
352-pin PBGA
352-pin PBGA
Lead Free
Lead Free
EP9315 — CBZ
Lead Material:
Z = Lead Free
Part Number
Product Line:
Embedded Processor
Note:
Package Type:
B = 352-Ball, Plastic Ball Grid Array (27 mm x 27 mm)
Temperature Range:
C = Commercial Version
E = Extended Operating Version
I = Industrial Operating Version
Go to the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to
change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the
time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this
information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document
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