VRE302JD

VRE302 Product Innovation From P r o d u c t I n n o v a t i o nF r o m VRE302 Precision Voltage Reference FEaTuRES ♦ ♦ ♦ ♦ +2.5 V Output, ± 0.250 mV (.01%) Temperature Drift: 0.6 ppm/ºC Low Noise: 1.5 μVP-P (0.1-10Hz) Industry Standard Pinout: 8-pin DIP or Surface Mount Package ♦ Excellent Line Regulation: 6 ppm/V Typical ♦ Output Trim Capability DESCRIPTION The VRE302 is a low cost, high precision +2.5 V reference. Packaged in the industry standard 8-pin DIP, the device is ideal for upgrading systems that use lower performance references. The device provides ultrastable +2.5 V output with ±0.25 mV (.01%) initial accuracy and a temperature coefficient of 0.6 ppm/ºC. This improvement in accuracy is made possible by a unique, patented multipoint laser compensation technique. Significant improvements have been made in other performance parameters as well, including initial accuracy, warm-up drift, line regulation, and long-term stability, making the VRE302 series the most accurate reference available in the standard 8-pin DIP package. For enhanced performance, the VRE302 has an external trim option for users who want less than 0.01% initial error. A reference ground pin is provided to eliminate socket contact resistance errors. aPPlICaTIONS The VRE302 is recommended for use as a reference for 14, 16, or 18 bit D/A converters which require an external precision reference. The device is also ideal for calibrating scale factor on high resolution A/D converters. The VRE302 offers superior performance over monolithic references. Figure 1. BlOCK DIaGRaM SElECTION GuIDE Model VRE302CS VRE302CD VRE302JS VRE302JD VRE302KS VRE302LS VRE302LD Initial Error Temp. Coeff. (mV) (ppm/ºC) 0.50 0.50 0.25 0.25 0.40 0.50 0.50 2.0 2.0 0.6 0.6 1.0 2.0 2.0 Temp. Range (ºC) 0ºC to +70ºC 0ºC to +70ºC -40ºC to +85ºC -40ºC to +85ºC -40ºC to +85ºC -40ºC to +85ºC -40ºC to +85ºC Package Options SMT8 (GD) DIP8 (KD) SMT8 (GD) DIP8 (KD) SMT8 (GD) SMT8 (GD) DIP8 (KD) 8-pin Surface Mount 8-pin DIP Package Style GD Package Style KD 64 http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2009 (All Rights Reserved) Jul 2009 VRE302DS APEX − VRE302DSREVH P r o d u c t I n n o v a t i o nF r o m VRE302 1. CHARACtERiStiCS AnD SPECifiCAtionS ElECTRICal SPECIFICaTIONS VPS =±15V, T = +25ºC, RL = 10KΩ Unless Otherwise Noted. Model Parameter Power Supply Operating Temperature (A,B) Operating Temperature (K) Storage Temperature Short Circuit Protection OuTPuT VOlTaGE VRE302 Temp. Sensor Voltage (Note 1) OuTPuT VOlTaGE ERRORS Initial Error Warmup Drift TMIN - TMAX Long-Term Stability Noise (0.1 - 10Hz) OuTPuT CuRRENT Range REGulaTION Line Load OuTPuT aDJuSTMENT Range POWER SuPPlY CuRRENT (Note 5) VRE302 +PS 5 7 * * * * mA 10 * * mV 6 3 10 * * * * * * ppm/V ppm/mA ±10 * mA (Note 4) (Note3) 6 1.5 (Note 2) 1 0.6 * * 0.25 2 1.0 * * 0.40 3 2.0 0.50 mV ppm ppm/ºC ppm/1000hrs. µVpp +2.5 630 * * * * V mV Min ±13.5 0 -40 -65 Continuous aBSOluTE MaXIMuM RaTINGS ±15 ±22 +70 +85 +150 * * * * * * * * * * * * * * * * * * * * V ºC ºC ºC a/J Typ Max Min K Typ Max Min C/l Typ Max units NOTES: * 1. 2. 3. Same as A Models. The temp. reference TC is 2.1mV/ ºC The specified values are without external trim. The temperature coefficient is determined by the box method using the following formula: VMAX – VMIN T.C. = x 106 VNOMINAL x (TMAX – TMIN) 4. The specified values are without the external noise reduction capacitor. 5. The specified values are unloaded. VRE302DS 65 VRE302 2. TYPICal PERFORMaNCE CuRVES VOUT vs. TEMPERATURE P r o d u c t I n n o v a t i o nF r o m VOUT vs. TEMPERATURE Temperature oC VRE302A VOUT vs. TEMPERATURE Temperature oC VRE302C VOUT vs. TEMPERATURE VOUT vs. TEMPERATURE Temperature oC VRE302J Temperature oC VRE302K POSITIVE OUTPUT (TYP) Temperature oC VRE302L QUIESCENT CURRENT VS. TEMP JUNCTION TEMP. RISE VS. OUTPUT CURRENT PSRR VS. FREQUENCY Temperature oC Output Current (mA) Frequency (Hz) 66 VRE302DS P r o d u c t I n n o v a t i o nF r o m VRE302 3. tHEoRY of oPERAtion The following discussion refers to the schematic in Figure 1. A FET current source is used to bias a 6.3 V zener diode. The zener voltage is divided by the resistor network R1 and R2. This voltage is then applied to the noninverting input of the operational amplifier which amplifies the voltage to produce a 2.5 V output. The gain is determined by the resistor networks R3 and R4: G=1 + R4/R3. The 6.3 V zener diode is used because it is the most stable diode over time and temperature. The current source provides a closely regulated zener current, which determines the slope of the references’ voltage vs. temperature function. By trimming the zener current a lower drift over temperature can be achieved. But since the voltage vs. temperature function is nonlinear this compensation technique is not well suited for wide temperature ranges. A nonlinear compensation network of thermistors and resistors is used in the VRE series voltage references. This proprietary network eliminates most of the nonlinearity in the voltage vs. temperature function. By adjusting the slope, a very stable voltage is produced over wide temperature ranges. This network is less than 2% of the overall network resistance so it has a negligible effect on long term stability. The proper connection of the VRE302 series voltage references with the optional trim resistor for initial error is shown below. The VRE302 reference has the ground terminal brought out on two pins (pin 4 and pin 7) which are connected together internally. This allows the user to achieve greater accuracy when using a socket. Voltage references have a voltage drop across their power supply ground pin due to quiescent current flowing through the contact resistance. If the contact resistance was constant with time and temperature, this voltage drop could be trimmed out. When the reference is plugged into a socket, this source of error can be as high as 20 ppm. By connecting pin 4 to the power supply ground and pin 7 to a high impedance ground point in the measurement circuit, the error due to the contact resistance can be eliminated. If the unit is soldered into place, the contact resistance is sufficiently small that it does not effect performance. Pay careful attention to the circuit layout to avoid noise pickup and voltage drops in the lines. EXTERNal CONNECTIONS + VIN 2 V TEMP OUT 3 6 OPTIONAL NOISE REDUCTION CAPACITOR CN 1µF 8 + VOUT 10kΩ OPTIONAL FINE TRIM ADJUSTMENT VRE302 5 7 4 REF. GND PIN CONFIGuRaTION N.C. +VIN TEMP GND 1 2 3 4 VRE302 8 7 6 5 NOISE REF. GND VOUT TRIM TOP VIEW VRE302DS 67