VRE4141K

P r o d u c t I n n o v a t i o nF r o m Product Innovation From VRE4112 VRE4100 VRE4125 VRE4141 ApplicAtionS This series is recommended for use as a reference for 14, 16, or 18-bit data converters which require a precision reference. The series offers superior performance over standard on-chip references commonly found with data converters. Precision Voltage Reference FEAtuRES ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ +1.250, +2.500, +4.096 V Output Initial Error: ± 0.05% Max. Temperature Drift: 1.0 ppm/ºC Max. Low Noise: 2.2 μVP-P (0.1 Hz-10 Hz, 1.024 V) Low Thermal Hysteresis: 20 ppm ±8 mA Output Source Power Down Mode Industry Standard SOIC 8-pin Package Commercial and Industrial Temp Ranges Second source for ADR29X, REF19X ,LT1460, LT1461, LT1798, MAX616X, REF102 DEScRiption The VRE4112/VRE4125/VRE4141 are low cost, high precision bandgap references that operate from +5 V. These devices feature low noise, digital error correction, and an SOIC-8 package. The ultra stable output is 0.05% accurate with a temperature coefficient as low as 1.0 ppm/ºC. The improvement in overall accuracy is made possible by using EEPROM registers and CMOS DAC’s for temperature and initial error correction. The DAC trimming is done after assembly which eliminates assembly related shifts. SElEction GuiDE Model VRE4112C VRE4112K VRE4125B VRE4125K VRE4141B VRE4141K output (V) +1.250 +1.250 +2.500 +2.500 +4.096 +4.096 temp. coeff. (ppm/ºc) 2.0 3.0 1.0 3.0 1.0 3.0 temp. Range (ºc) 0ºC to +70ºC -40ºC to +85ºC 0ºC to +70ºC -40ºC to +85ºC 0ºC to +70ºC -40ºC to +85ºC 8-pin Soic package Style FX VRE4100DS http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2009 (All Rights Reserved) ApR 2009 1 APEX − VRE4100DSREVA VRE4100 P r o d u c t I n n o v a t i o nF r o m 1. chARActERiSticS AnD SpEciFicAtionS ABSolutE MAXiMuM RAtinGS Power Supply to any input pin ...... -0.3V to +5.6V Operating Temp. (B,C)...................... 0ºC to 70ºC Operating Temp. (K) .................... -40ºC to +85ºC Storage Temperature Range ..... -65ºC to +150ºC Output Short Circuit Duration .............................. Indefinite ESD Susceptibility Human Body Model....................... 2kV ESD Susceptibility Machine Model ............................ 200V Lead Temperature (soldering, 10 sec) .................... +260ºC ElEctRicAl SpEciFicAtionS VPS = +3 V for VRE4112, VPS = +5 V for VRE4125 and VRE4141. T = +25ºC, ILOAD = 1mA, COUT = 1µF Unless Otherwise Noted. parameter Input Voltage Output Voltage Error (Note 1) Output Voltage Temperature Coefficient (Note 2) Dropout Voltage (Note 3) Turn-On Settling Time Output Noise Voltage (Note 4) Temperature Hysteresis Long Term Stability Supply Current Line Regulation (Note 6) ∆VOUT/T IIN ∆VOUT/ ∆VIN VH IH VL IL 1 Symbol VIN VOUT B Grade C/K Grade B Grade TCVOUT VIN - VOUT TON En C Grade K Grade IL = 8mA To 0.01% of final value 0.1Hz < f < 10Hz Note 5 1000 Hours VLOAD = 0mA 1mA ≤ ILOAD ≤ 8mA VREF + 200mV ≤ VIN ≤ 5.5V 0.8 2 0.4 conditions Min +1.8 ±0.025 ±0.040 +0.5 +1.0 +1.5 160 2 2.2 20 50 230 1 20 320 20 200 typ Max +5.5 ±0.050 ±0.080 +1.0 +2.0 +3.0 235 mV µs µVp-p ppm ppm µA ppm/mA ppm/V V nA V nA ppm/ºC units V % Load Regulation (Note 6) ∆VOUT/ ∆IOUT Logic High Input Voltage Logic High Input Current Logic Low Input Voltage Logic Low Input Current NOTES: 1. High temperature and mechanical stress can effect the initial accuracy of this reference series.See discussion on output accuracy. 2. The temperature coefficient is determined by the box method. See discussion on temperature performance. All units are 100% tested over temperature. 3. The minimum input to output differential voltage at which the output voltage drops by 0.5% from nominal. 4. Based on 1.024 V output. Noise is linearly proportional to VREF. 5. Defined as change in 25ºC output voltage after cycling device over operating temperature range. 6. Line and load regulation are measured with pulses and do not include output voltage changes due to self heating. 2 VRE4100DS P r o d u c t I n n o v a t i o nF r o m VRE4100 2. tYpicAl pERFoRMAncE cuRVES Load Regulation vs Temperature Output Voltage vs Load Current Load Transient Response Line Regulation vs Temperature Power Up/Down Ground Current Line Transient Response Enable Response Output Impedance Power Supply Rejection Ratio VRE4100DS  VRE4100 Total Current (Is(ON)) vs Supply Voltage P r o d u c t I n n o v a t i o nF r o m Total Current (Is(OFF)) vs Supply Voltage Ground Current vs Load Current Output Voltage Change vs Sink Current I(SINK) Dropout Voltage vs Load Current IQ v s T em p e r a t u r e Dropout Voltage vs Load Current (VOUT) = 2.0V Spectral Noise Density (0.1Hz to 10Hz) Spectral Noise Density (10Hz to 100kHz) 4 VRE4100DS P r o d u c t I n n o v a t i o nF r o m VRE4100 . tEMpERAtuRE pERFoRMAncE This series is designed for applications where the initial error at room temperature and drift over temperature are important to the user. For many instrument manufacturers, a voltage reference with a temperature coefficient of 1ppm/ºC makes it possible to eliminate a system temperature calibration, a slow and costly process. Of the three TC specification methods (slope, butterfly, and box), the box method is most commonly used. A box is formed by the min/max limits for the nominal output voltage over the operating temperature range. The equation follows: VMAX – VMIN TC = x 106 VNOMINAL x (TMAX – TMIN) This method corresponds more accurately to the method of test and provides a closer estimate of actual error than the other methods. The box method guarantees limits for the temperature error but does not specify the exact shape or slope of the device under test. 4. BASic ciRcuit connEction The proper connection for the VRE4112/VRE4125/VRE4141 series voltage references is shown below. To achieve the specified performance, pay careful attention to the layout. Commons should be connected to a single point to minimize interconnect resistances. This will reduce voltage errors, noise pickup, and noise coupled from the power supply. pin DEScRiption 4 2 3 1,5,7,8 6 GND VIN Enable NC VOUT These must be connected to ground Positive power supply input Pulled to VIN for nominal operation This pin must be left open Reference output EXtERnAl connEctionS + VIN Enable 2 3 VRE4112 6 VRE4125 VRE4141 1,5,7,8 4 + VOUT COUT 1µF NC VRE4100DS  VRE4100 P r o d u c t I n n o v a t i o nF r o m For example a designer who needs a 14-bit accurate data acquisition system over the industrial temperature range (-40ºC to +85ºC), will need a voltage reference with a temperature coefficient (TC) of 1.0ppm/ºC if the reference is allowed to contribute an error equivalent to 1LSB. The required reference TC vs. ∆T change from 25ºC for resolution ranging from 8 bits to 20 bits is shown below. 10000 1000 Reference TC (ppm/ºC) 100 8 BIT 10 10 BIT 12 BIT 1 14 BIT 16 BIT 18 BIT 0.01 1 10 20 BIT 100 0.1 Reference TC vs. ∆T change from 25°C for 1 LSB change 4. opERAtionAl notES input cApAcitoR An input capacitor is recommended for the VRE4112/VRE4125/VRE4141. A supply bypass capacitor on the input will assure that the reference is working from a low impedance source which will improve stability. It can improve the transient response when the load current is suddenly increased. output cApAcitoR This series requires a 1 μF output capacitor for loop stabilization (compensation) as well as transient response. When the load current changes, the output capacitor must source or sink current during the time it takes the control loop of the device to respond. The output capacitor must meet the requirements of minimum capacitance and equivalent series resistance (ESR) range. See Capacitor Selection below. cApAcitoR SElEction A minimum value of 0.2 μF over the operating temperature range is recommended. For a 0.22 μF capacitor the ESR range for 0°C to +70°C is 0.9 to 6.0; 1.0 μF is 0.8 to 6.0; and 10 μF is 0.4 to 7.0. Surface mount tantalum capacitors offer small size for the value and ESR in the range required for this series. The optimum performance for the output capacitor is achieved with a 1.0 μF value. Aluminum electrolytic capacitors have a relatively large size for the value. They meet the ESR requirements at 1.0 μF as long as the temperature is above 0°C. Below 0°C, the ESR increases and it may exceed the limits indicated in the figures. Multilayer ceramic capacitors have a small size for the value, are available in surface mount, and have excellent RF characteristics. They may not meet the minimum ESR requirements and have a large change in value with temperature.  VRE4100DS P r o d u c t I n n o v a t i o nF r o m VRE4100 REVERSE cuRREnt pAth The P-channel pass transistor used in this series has an inherent diode connected between the Vin and VOUT pins. Forcing the output to voltages higher than the input or pulling Vin below the voltage stored in the output capacitor by more than the Vbe will forward bias this diode and current will flow from the Vout pin to Vin. This will not damage the device as long as the current does not exceed 50 mA. on/oFF opERAtion This series features a sleep mode that is activated by pulling the enable pin low. To turn the reference on, the enable pin is pulled high. If this feature is not used, the enable pin should be tied to Vin to keep the reference on at all times. The enable pin must not be left unconnected (floating). When powered off, these devices will quickly reduce both Vout and IQ to zero. During power down, the charge across the output capacitor is discharged to ground through the internal circuitry. On power up, the Vout is restored in less than 200 μs. The signal source used to drive the enable pin can come from either a totem-pole output or an open collector output with a pull-up resistor to the input voltage. The signal source must be able to swing above and below the voltage thresholds to guarantee an ON or OFF state. It must not exceed the absolute maximum rating for the enable pin. output AccuRAcY The output accuracy after assembly at room temperature is made up of three components: initial accuracy of the device, thermal hysteresis, and mechanical stress. The initial accuracy is measured at the factory and may not reflect the actual output voltage when the devices are mounted to a PCB. The effects of mechanical stress and thermal hysteresis can shift the output voltage. thERMAl hYStERESiS Thermal hysteresis is a change in output voltage as a result of a temperature change. When references experience a temperature change and return to the initial temperature, they do not always have the same initial voltage. Thermal hysteresis is difficult to correct and is a major error source in systems that experience temperature changes greater than 25°C. Reference vendors are starting to include this important specification in their datasheets MEchAnicAl hYStERESiS Recommendations to minimize mechanical stress: 1) Mount the VRE4112/VRE4125/VRE4141 near the edges or corners of the PCB. The center of the board generally has the highest mechanical and thermal stress. 2) Mechanically isolate the device by cutting a U shaped slot around the package. This provides some mechanical and thermal isolation from the rest of the circuit. pin conFiGuRAtion NC +VIN Enable GND 1 2 3 4 8 NC NC VREF NC VRE4100 TOP VIEW 7 6 5 VRE4100DS  VRE4100 P r o d u c t I n n o v a t i o nF r o m contActinG ciRRuS loGic SuppoRt For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America. For inquiries via email, please contact tucson.support@cirrus.com. International customers can also request support by contacting their local Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). 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