WM8213
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24MSPS 16-bit CCD Digitiser
DESCRIPTION
FEATURES
The WM8213 is a 16-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 24MSPS.
•
•
16-bit ADC
24MSPS conversion rate
•
•
•
Low power – 350mW typical
3.3V single supply operation
Single, 2 or 3 channel operation
•
•
•
Correlated double sampling
Programmable gain (9-bit resolution)
Programmable offset adjust (8-bit resolution)
•
•
•
Flexible clamp control with programmable clamp voltage
Flexible timing, can be made compatible with WM819X
and WM815X parts.
8-bit wide multiplexed data output format
•
•
•
8-bit only output mode
4-bit LEGACY multiplexed nibble mode
Internally generated voltage references
•
•
28-lead SSOP package, pin compatible with WM8199
Serial control interface
The device includes three analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset adjust functions. Three multiplexers allow single
channel processing. The output from each of these
channels is time multiplexed into a single high-speed 16-bit
Analogue to Digital Converter. The digital output data is
available in 8-bit wide multiplexed format and there is also
an optional single byte output mode, or 4-bit multiplexed
LEGACY mode.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
signals. An external reference level may also be supplied.
ADC references are generated internally, ensuring optimum
performance from the device.
Using an analogue supply voltage of 3.3V and a digital
interface supply of 3.3V, the WM8213 typically only
consumes 350mW.
APPLICATIONS
•
High speed USB2.0 compatible scanners
•
•
•
Multi-function peripherals
High-performance CCD sensor interface
Digital Copiers
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
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Production Data, July 2008, Rev 4.1
Copyright ©2008 Wolfson Microelectronics plc.
WM8213
Production Data
TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
BLOCK DIAGRAM .................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION...........................................................................................3
ORDERING INFORMATION ..................................................................................3
PIN DESCRIPTION ................................................................................................4
ABSOLUTE MAXIMUM RATINGS.........................................................................5
RECOMMENDED OPERATING CONDITIONS .....................................................5
THERMAL PERFORMANCE .................................................................................5
ELECTRICAL CHARACTERISTICS ......................................................................6
INPUT VIDEO SAMPLING ............................................................................................ 9
SERIAL INTERFACE................................................................................................... 11
INTERNAL POWER ON RESET CIRCUIT ..........................................................12
DEVICE DESCRIPTION.......................................................................................14
INTRODUCTION ......................................................................................................... 14
INPUT SAMPLING ...................................................................................................... 14
RESET LEVEL CLAMPING (RLC)............................................................................... 15
CDS/NON-CDS PROCESSING................................................................................... 17
OFFSET ADJUST AND PROGRAMMABLE GAIN ...................................................... 18
ADC INPUT BLACK LEVEL ADJUST.......................................................................... 19
OVERALL SIGNAL FLOW SUMMARY........................................................................ 20
CALCULATING THE OUTPUT CODE FOR A GIVEN INPUT ..................................... 21
OUTPUT FORMATS ................................................................................................... 22
REFERENCES ............................................................................................................ 22
POWER MANAGEMENT ............................................................................................ 22
LINE-BY-LINE OPERATION ....................................................................................... 23
CONTROL INTERFACE.............................................................................................. 23
NORMAL OPERATING MODES ................................................................................. 25
LEGACY MODE INFORMATION................................................................................. 26
LEGACY OPERATING MODES .................................................................................. 27
LEGACY MODE TIMING DIAGRAMS ......................................................................... 28
DEVICE CONFIGURATION .................................................................................30
REGISTER MAP ......................................................................................................... 30
REGISTER MAP DESCRIPTION ................................................................................ 31
APPLICATIONS INFORMATION .........................................................................36
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 36
RECOMMENDED EXTERNAL COMPONENT VALUES ............................................. 36
PACKAGE DIMENSIONS ....................................................................................37
IMPORTANT NOTICE ..........................................................................................38
ADDRESS: .................................................................................................................. 38
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WM8213
Production Data
PIN CONFIGURATION
RINP
1
28
GINP
AGND2
2
27
BINP
DVDD1
3
26
VRLC/VBIAS
OEB
4
25
VRX
VSMP
5
24
VRT
RSMP
6
23
VRB
MCLK
7
22
AGND1
DGND
8
21
AVDD
SEN
9
20
OP[7]/SDO
DVDD2
10
19
OP[6]
SDI
11
18
OP[5]
SCK
12
17
OP[4]
OP[0]
13
16
OP[3]
OP[1]
14
15
OP[2]
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
MOISTURE
SENSITIVITY LEVEL
PEAK SOLDERING
TEMPERATURE
WM8213SCDS/V
0 to 70oC
28-lead SSOP
(Pb-free)
MSL3
260oC
WM8213SCDS/RV
0 to 70oC
28-lead SSOP
(Pb-free, tape and reel)
MSL3
260oC
Note:
Reel quantity = 2,000
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WM8213
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PIN DESCRIPTION
PIN
NAME
TYPE
1
RINP
Analogue input
DESCRIPTION
2
AGND2
Supply
Analogue ground reference.
3
DVDD1
Supply
Digital supply for logic and clock generator. This must be operated at the same
potential as AVDD.
4
OEB
Digital input
Output Hi-Z control, all digital outputs disabled when register bit OEB = 1 or register
bit OPD = 1.
Red channel input video.
5
VSMP
Digital input
Video sample timing pulse.
6
RSMP
Digital input
Reset sample timing pulse (also used for RLC control).
7
MCLK
Digital input
Master (ADC) clock. This determines the ADC conversion rate.
8
DGND
Supply
9
SEN
Digital input
10
DVDD2
Supply
11
SDI
Digital input
Serial data input.
12
SCK
Digital input
Serial clock.
Digital ground reference.
Enables the serial interface when high.
Digital supply, all digital I/O pins.
Digital multiplexed output data bus.
ADC output data (d15:d0) is available in multiplexed format as shown. See ‘Output
Formats’ description in Device Description section for details of other output modes.
A
B
d8
d0
13
OP[0]
Digital output
14
OP[1]
Digital output
d9
d1
15
OP[2]
Digital output
d10
d2
16
OP[3]
Digital output
d11
d3
17
OP[4]
Digital output
d12
d4
18
OP[5]
Digital output
d13
d5
19
OP[6]
Digital output
d14
d6
20
OP[7]/SDO
Digital output
d15
d7
Alternatively, pin OP[7]/SDO may be used to output register read-back data when
register bit OEB = 0, OPD = 0 and SEN has been pulsed high. See Serial Interface
description in Device Description section for further details.
21
AVDD
Supply
Analogue supply. This must be operated at the same potential as DVDD1.
22
AGND1
Supply
Analogue ground reference.
23
VRB
Analogue output
Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
24
VRT
Analogue output
Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
25
VRX
Analogue output
Input return bias voltage.
This pin must be connected to AGND via a decoupling capacitor.
26
VRLC/VBIAS
Analogue I/O
27
BINP
Analogue input
Blue channel input video.
28
GINP
Analogue input
Green channel input video.
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Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at Red… offset and gain registers applied to
the red input channel.
When auto-cycling is enabled, the RSMP pin cannot be used to
control reset level clamping. The CLMPCTRL bit may be used
instead (enabled when high, disabled when low).
NB, when auto-cycling is enabled, the RSMP pin cannot be used
for reset sampling (i.e. CDS must be set to 0).
3:2
INTM[1:0]
00
When LINEBYLINE=0 or ACYC=1 this bit has no effect.
When LINEBYLINE=1 and ACYC=0:
Controls the PGA/offset mux selector:
00 = Red PGA/Offset registers applied to input channel
01 = Green PGA/Offset registers applied to input channel
10 = Blue PGA/Offset registers applied to input channel
11 = Reserved.
7:4
Reserved
0000
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Must be set to 0
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WM8213
ADDRESS
REGISTER
000111
(07h)
Setup
Register 5
Production Data
BIT
NO
BIT
DEFAULT
DESCRIPTION
NAME(S)
0
REDPD
0
When set powers down red S/H, PGA
1
GRNPD
0
When set powers down green S/H, PGA
2
BLUPD
0
When set powers down blue S/H, PGA
3
ADCPD
0
When set powers down ADC. Allows reduced power
consumption without powering down the references which have a
long time constant when switching on/off due to the external
4
VRLCDACPD
0
When set powers down 4-bit RLCDAC, setting the output to a
high impedance state and allowing an external reference to be
5
ADCREFPD
0
When set disables VRT, VRB buffers to allow external references
to be used.
6
VRXPD
0
When set disables VRX buffer to allow an external reference to
7
0
Reserved
VSMPDET
0
0
Must be set to 0
When LEGACY=0 this register bit has no effect.
When LEGACY=1:
0 = Normal operation, signal on VSMP input pin is applied directly
to Timing Control block.
1 = Programmable VSMP detect circuit is enabled. An internal
synchronisation pulse is generated from signal applied to VSMP
input pin and is applied to Timing Control block in place of VSMP.
3:1
VDEL[2:0]
000
When LEGACY=0 or VSMPDET=0 these bits have no effect.
The VDEL bits set a programmable delay from the detected edge
of the signal applied to the VSMP pin. The internally generated
pulse is delayed by VDEL MCLK periods from the detected edge.
See Figure 20, Internal VSMP Pulses Generated for details.
4
POSNNEG
0
When LEGACY=0 or VSMPDET=0 this bit has no effect.
When LEGACY=1 and VSMPDET=1 this bit controls whether
positive or negative edges on the VSMP input pin are detected:
0 = Negative edge on VSMP pin is detected and used to generate
internal timing pulse.
1 = Positive edge on VSMP pin is detected and used to generate
internal timing pulse.
See Figure 20 for further details.
5
RLCEN
1
Reset Level Clamp Enable. When set Reset Level Clamping is
decoupling capacitors.
driven in on the VRLC/VBIAS pin.
be used.
001000
(08h)
Setup
Register 6
enabled. The method of clamping is determined by CLAMPCTRL
and LEGACY.
In LEGACY mode clamping will still occur on every pixel at a time
defined by the CDSREF[1:0] bits.
6
CLAMPCTRL
0
This bit has no effect if LEGACY=1. See Table 2 for more
information.
0 = RLC switch is controlled directly from RSMP input pin:
RSMP = 0: switch is open
RMSP = 1: switch is closed
1 = RLC switch is controlled by logical combination of RSMP and
VSMP.
RSMP && VSMP = 0: switch is open
RSMP && VSMP = 1: switch is closed
7
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Reserved
0
Must be set to 0
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Production Data
ADDRESS
REGISTER
BIT
NO
BIT
NAME(S)
DEFAULT
100000
(20h)
Offset DAC
(Red)
7:0
DACR[7:0]
10000000
Red channel 8-bit offset DAC value (mV) = 260*(DACR[7:0]127.5)/127.5
100001
(21h)
Offset DAC
(Green)
7:0
DACG[7:0]
10000000
Green channel 8-bit offset DAC value (mV) = 260*(DACG[7:0]127.5)/127.5
100010
(22h)
Offset DAC
(Blue)
7:0
DACB[7:0]
10000000
Blue channel 8-bit offset DAC value (mV) = 260*(DACB[7:0]127.5)/127.5
100011
(23h)
Offset DAC
(RGB)
7:0
DACRGB[7:0]
-
A write to this register location causes the red, green and blue
offset DAC registers to be overwritten by the new value
100100
(24h)
PGA Gain
LSB
(Red)
0
PGAR[0]
0
This register bit forms the LSB of the red channel PGA gain code.
PGA gain is determined by combining this register bit and the 8
MSBs contained in register address 28 hex.
7:1
Reserved
0000000
100101
(25h)
PGA Gain
LSB
0
PGAG[0]
0
7:1
Reserved
0000000
0
PGAB[0]
0
7:1
Reserved
0000000
0
PGARGB[0]
-
(Green)
100110
(26h)
PGA Gain
LSB
(Blue)
100111
(27h)
PGA Gain
LSB
101000
(28h)
(RGB)
PGA gain
MSBs
(Red)
DESCRIPTION
Must be set to 0
This register bit forms the LSB of the green channel PGA gain
code. PGA gain is determined by combining this register bit and
the 8 MSBs contained in register address 29 hex.
Must be set to 0
This register bit forms the LSB of the blue channel PGA gain
code. PGA gain is determined by combining this register bit and
the 8 MSBs contained in register address 2A hex.
7:1
Reserved
0000000
7:0
PGAR[8:1]
00001100
Must be set to 0
Writing a value to this location causes red, green and blue PGA
LSB gain values to be overwritten by the new value.
Must be set to 0
Bits 8 to 1 of red PGA gain. Combined with red LSB register bit to
form complete PGA gain code. This determines the gain of the
red channel PGA according to the equation:
Red channel PGA gain (V/V) = 0.66 + PGAR[8:0]x7.34/511
101001
(29h)
PGA gain
MSBs
(Green)
7:0
PGAG[8:1]
00001100
Bits 8 to 1 of green PGA gain. Combined with green LSB register
bit to form complete PGA gain code. This determines the gain of
the green channel PGA according to the equation:
Green channel PGA gain (V/V) = 0.66 + PGAG[8:0]x7.34/511
101010
(2Ah)
PGA gain
MSBs
(Blue)
7:0
PGAB[8:1]
00001100
Bits 8 to 1 of blue PGA gain. Combined with blue LSB register bit
to form complete PGA gain code. This determines the gain of the
blue channel PGA according to the equation:
Blue channel PGA gain (V/V) = 0.66 + PGAB[8:0]x7.34/511
101011
(2Bh)
PGA gain
MSBs(RGB)
7:0
PGARGB[8:1]
-
A write to this register location causes the red, green and blue
PGA MSB gain registers to be overwritten by the new value.
Table 8 Register Control Bits
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WM8213
Production Data
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 25 External Components Diagram
RECOMMENDED EXTERNAL COMPONENT VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1
100nF
De-coupling for DVDD1.
C2
100nF
De-coupling for DVDD2.
C3
100nF
De-coupling for AVDD.
C4
10nF
High frequency de-coupling between VRT and VRB.
C5
1µF
Low frequency de-coupling between VRT and VRB (non-polarised).
C6
100nF
De-coupling for VRB.
C7
100nF
De-coupling for VRX.
C8
100nF
De-coupling for VRT.
C9
100nF
De-coupling for VRLC.
C10
10µF
Reservoir capacitor for DVDD1.
C11
10µF
Reservoir capacitor for DVDD2.
C12
10µF
Reservoir capacitor for AVDD.
Table 9 External Components Descriptions
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WM8213
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PACKAGE DIMENSIONS
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)
b
DM007.E
e
28
15
E1
1
D
E
GAUGE
PLANE
14
c
A A2
A1
Θ
L
0.25
L1
-C0.10 C
Symbols
A
A1
A2
b
c
D
e
E
E1
L
L1
θ
MIN
----0.05
1.65
0.22
0.09
9.90
7.40
5.00
0.55
o
0
REF:
Dimensions
(mm)
NOM
--------1.75
0.30
----10.20
0.65 BSC
7.80
5.30
0.75
1.25 REF
o
4
SEATING PLANE
MAX
2.0
0.25
1.85
0.38
0.25
10.50
8.20
5.60
0.95
o
8
JEDEC.95, MO-150
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8213
Production Data
IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer
product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for
such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.
Any use of products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other
intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or
services might be or are used. Any provision or publication of any third party’s products or services does not constitute
Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document
belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is
not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or
accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any
reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
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