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WM8255
Single Channel 16-bit CIS/CCD AFE with RGB LED Current Drive
DESCRIPTION
FEATURES
The WM8255 is a 16-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 12 MSPS.
16-bit ADC
12 MSPS conversion rate
Low power – 250 mW typical
5.75V and 3.3V supply operation
The device includes a complete signal processing channel
containing Reset Level Clamping, Correlated Double
Sampling, Programmable Gain and Offset adjust functions.
Internal multiplexers allow fast switching of offset and gain
for line-by-line colour processing. The output from this
channel is time multiplexed into a high-speed 16-bit
Analogue to Digital Converter. The digital output data is
available in a 2 bit or 4-bit wide multiplexed format.
Single channel operation
Correlated double sampling
Programmable gain (8-bit resolution)
Programmable offset adjust (8-bit resolution)
Programmable clamp voltage
RGB LED current drive using current and PWM
2-bit or 4-bit wide multiplexed data output format
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
signals. An external reference level may also be supplied.
ADC references are generated internally, ensuring optimum
performance from the device.
Internally generated voltage references
28-lead QFN package
3 wire serial control interface
The device includes an RGB LED current drive using current
and PWM functionality to control the operation of sensor
LEDs.
APPLICATIONS
Flatbed and sheetfeed scanners
USB compatible scanners
Multi-function peripherals
The device typically uses an analogue supply voltage of
5.75V and a digital interface supply of 3.3V.
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
Production Data, August 2013, Rev 4.7
Copyright 2013 Wolfson Microelectronics plc
WM8255
Production Data
TABLE OF CONTENTS
DESCRIPTION ....................................................................................................... 1
FEATURES ............................................................................................................ 1
APPLICATIONS..................................................................................................... 1
BLOCK DIAGRAM ................................................................................................ 1
TABLE OF CONTENTS ......................................................................................... 2
PIN CONFIGURATION .......................................................................................... 4
ORDERING INFORMATION .................................................................................. 4
PIN DESCRIPTION ................................................................................................ 5
ABSOLUTE MAXIMUM RATINGS ........................................................................ 6
RECOMMENDED OPERATING CONDITIONS ..................................................... 6
THERMAL PERFORMANCE ................................................................................. 6
ELECTRICAL CHARACTERISTICS ..................................................................... 7
INPUT VIDEO SAMPLING ............................................................................................. 10
OUTPUT DATA TIMING................................................................................................. 10
SERIAL INTERFACE ..................................................................................................... 11
PWM TIMING ................................................................................................................. 12
DEVICE DESCRIPTION ...................................................................................... 13
INTRODUCTION ............................................................................................................ 13
INPUT SAMPLING ......................................................................................................... 13
RESET LEVEL CLAMPING (RLC) ................................................................................. 13
CDS/NON-CDS PROCESSING ..................................................................................... 14
OFFSET ADJUST AND PROGRAMMABLE GAIN ........................................................ 15
ADC INPUT BLACK LEVEL ADJUST ............................................................................ 16
OVERALL SIGNAL FLOW SUMMARY .......................................................................... 16
CALCULATING OUTPUT FOR ANY GIVEN INPUT ...................................................... 16
OUTPUT FORMATS ...................................................................................................... 18
LED CURRENT DRIVE CONTROL ............................................................................... 19
LED CURRENT DRIVE SEQUENCE SYNCHRONISATION AND PROGRESSION ..... 20
LED CURRENT DRIVE INTENSITY CONTROL ............................................................ 21
LED CURRENT DRIVE CURRENT PWM CONTROL .................................................. 25
LED CURRENT DRIVE CURRENT BLANKING PERIOD ............................................. 26
CURRENT ACCURACY AND ABSOLUTE MAXIMUM CURRENT LIMIT ..................... 30
LED CONTROL WORKED EXAMPLE ........................................................................... 32
CONTROL INTERFACE................................................................................................. 34
TIMING REQUIREMENTS ............................................................................................. 34
PROGRAMMABLE VSMP DETECT CIRCUIT ............................................................... 35
REFERENCES ............................................................................................................... 36
POWER SUPPLY ........................................................................................................... 36
POWER MANAGEMENT ............................................................................................... 36
POWER ON SEQUENCE .............................................................................................. 37
OPERATING MODES .................................................................................................... 37
OPERATING MODE TIMING DIAGRAMS ..................................................................... 38
DEVICE REVISION CODES .......................................................................................... 39
DEVICE CONFIGURATION ................................................................................. 40
REGISTER MAP .................................................................................................. 40
EXTENDED PAGE REGISTERS ................................................................................... 41
REGISTER MAP DESCRIPTION ................................................................................... 41
EXTENDED PAGE REGISTER MAP DESCRIPTION ................................................... 45
RECOMMENDED EXTERNAL COMPONENTS.................................................. 46
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PACKAGE DIMENSIONS .................................................................................... 47
QFN 5 X 5 X 0.85MM ..................................................................................................... 47
QFN 4 X 4 X 0.85MM ..................................................................................................... 47
IMPORTANT NOTICE ......................................................................................... 48
ADDRESS: ..................................................................................................................... 48
REVISION HISTORY ........................................................................................... 49
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LEDSTART
TG
AVDD2
NC
SDI
VRX
AGND2
SCK
VRT
NC
SEN
VRB
EXTRES
VSMP
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE
TEMPERATURE
RANGE
WM8255BGEFL/V
0 to 85 C
PACKAGE
MOISTURE
SENSITIVITY LEVEL
PEAK SOLDERING
TEMPERATURE
MSL3
260 C
MSL3
260 C
4x4x0.85mm
o
28-lead QFN
o
(Pb-free)
4x4x0.85mm
WM8255BGEFL/RV
o
0 to 85 C
28-lead QFN
o
(Pb-free, tape and reel)
Note:
Reel quantity = 3,500
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PIN DESCRIPTION
PIN NO
NAME
TYPE
1
MCLK
Digital input
DESCRIPTION
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 4, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
Digital multiplexed output data bus.
ADC output data (d15:d0) is available in a 4-bit multiplexed format as shown below.
A 2-bit multiplexed output is also available as described in the OUTPUT FORMATS
section of this datasheet on page 18.
A
B
C
D
2
OP[3]/SDO
Digital output
d15
d11
d7
d3
3
OP[2]
Digital output
d14
d10
d6
d2
4
OP[1]
Digital output
d13
d9
d5
d1
5
OP[0]
Digital output
d12
d8
d4
d0
Alternatively, pin OP[3]/SDO may be used to output register read-back data when
address bit 4=1 and SEN has been pulsed high. See Serial Interface description in
Device Description section for further details.
6
DVDD
Supply
Digital supply (3.3V)
7
DGND
Supply
Digital ground (0V).
8
EXTRES
Analogue input
9
VRB
Analogue output
Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
10
VRT
Analogue output
Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
11
VRX
Analogue output
Input return bias voltage
External resistor connection for LED absolute current control. Must be connected to
ground via a suitable resistor.
This pin must be connected to AGND via a decoupling capacitor.
Not Connected.
12
NC
No Connect
13
AGND2
Supply
Analogue ground pin (0V)
14
AVDD2
Supply
Analogue supply (3.3V) Not required to be driven if AVDD1 is being used. A
decoupling capacitor must be connected to AGND.
15
VINP
Analogue input
16
VRLC/VBIAS
Analogue I/O
17
ILEDB
Analogue input
Blue LED pin
18
ILEDG
Analogue input
Green LED pin
19
ILEDR
Analogue input
Red LED pin
20
AVDD1
Supply
Analogue Supply (5.75V)
21
AGND1
Supply
Analogue ground (0V).
22
TG
Digital input
Line synchronisation pulse
23
LEDSTART
Digital input
LED start pulse
24
NC
No Connect
Not Connected.
25
SDI
Digital input
Serial data input.
26
SCK
Digital input
Serial clock
27
SEN
Digital input
Enables the serial interface when high.
28
VSMP
Digital input
Video sample synchronisation pulse.
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Video input.
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
o
The WM8255 has been classified as MSL1, which has an unlimited floor life at 65535 D1[15:0] = 65535
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP.
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D2[15:0] = D1[15:0] (INVOP = 0)
Eqn. 9
D2[15:0] = 65535 – D1[15:0]
Eqn. 10
(INVOP = 1)
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OUTPUT FORMATS
The digital data output from the ADC is available in a 4-bit wide multiplexed. Latency of valid output
data with respect to VSMP is programmable by writing to control bits DEL[1:0]. The latency is shown
in the Operating Mode Timing Diagrams section.
Figure 11 shows the output data formats for all modes. Table 2 summarises the output data obtained
for each format.
Figure 11 Output Data Formats (4 bit - Modes 1 & 3, 2 bit – Mode 1 )
OUTPUT
OUTPUT FORMAT
OUTPUT
PINS
4+4+4+4-bit
OP[3:0]
A = d15, d14, d13, d12
B = d11, d10, d9, d8
C = d7, d6, d5, d4
D = d3, d2, d1, d0
OP[1:0]
A = d15, d14
(nibble)
2+2+2+2+2+2+2+2-bit
B = d13, d12
C = d11, d10
D = d9 , d8
E = d7 , d6
F = d5 , d4
G = d3 , d2
H = d1, d0
Table 2 Details of Output Data Shown in Figure 11
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LED CURRENT DRIVE CONTROL
The WM8255 allows the user to control:
the sequence of illumination
the period of illumination
the intensity of illumination
of the red, blue and green LEDs used to illuminate the image during a scan.
A sequence state machine is used to progress the sequence and control the duration of the LED
selection. The progression of the sequence state machine is dependent on whether the WM8255 is in
colour mode or monochromatic mode. The intensity of illumination is controlled on either control of the
LED drive current or pulsing of the LED driving current.
LED CURRENT DRIVE SEQUENCE CONTROL
With reference to Figure 12, the WM8255 uses a LED sequence state machine to control the
sequence and duration of the illumination of the red, green and blue LEDs.
The LED sequence state machine can progress through up to 4 states each sequence. Each of the
sequence states (STATE_0 to STATE_3) may be set to one of four values to determine on whether a
red, green or blue LED is illuminated or all LEDs are off. The register STATERST will determine the
number of states the sequence state machine can progress through. Once the sequence state
machine has reached the reset state, the LED state machine will remain in this state until again
initiated.
LED CURRENT DRIVE SEQUENCE DEFINITION
Figure 13 illustrates the functionality of the sequence state mapping. The current state of the
sequence machine (SEQ_STATE) is an internal register used to select one of the four register state
mappings.
This register increments until the value specified by STATERST at which point the
sequence will hold. Figure 14 shows two examples when STATERST is set to “11bin” for a 4 state
sequence, and to “01bin” for a 2 state sequence.
State0
State1
State2
State3
StateRst
3
LEDEnRBG
Mono_ColourMode
LEDEnStart
LEDEn
LEDEnable
Fine Counter
(7-bit)
LEDOn
AVDD1
ILEDG
3
LEDEnStop
ILEDR
LED Control Register Map
LEDENSTART
LEDENSTOPRed
LEDENSTOPGrn
LEDENSTOPBlue
LEDTarget
ILEDB
LEDIDACRed
LEDIDACGrn
LEDIDACBlue
3
PWMEn
LEDOff
LEDPWMDCRed
LEDPWMDCGrn
LEDPWMDCBlue
INITBLANK
8
PWMCtr
l
LEDPWMDutyCyc
Blanking
Counter
LED Target
Current
Register
LEDPWMPer
LEDPWMPER
Ena
CLKDIV
En
MCLK
Divider
PWM Counter
(12-bit)
0->LEDPWMPER
PWMMaxCount
Figure 12 Block Diagram of PWM LED Control
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Figure 13 State Mapping Functionality
STATE_0
SEQ_STATE = 00
STATE_1
SEQ_STATE = 01
STATE_0
SEQ_STATE = 00
STATE_1
SEQ_STATE = 01
STATE_2
SEQ_STATE = 10
STATE_3
SEQ_STATE = 11
STATERST = 11
STATERST = 01
Figure 14 Setting the Sequence Length with STATERST
LED CURRENT DRIVE SEQUENCE SYNCHRONISATION AND PROGRESSION
The trigger to progress the state machine through the sequence states is dependent on whether the
LED driver is operating in colour mode or monochrome mode.
COLOUR MODE
In Colour Mode operation, LEDSTART and TG are used to synchronise and progress the sequence
state machine. This allows a single LED change for each line scan.
With both LEDSTART and TG high, the sequence state machine is synchronously set to STATE_0 by
MCLK. With LEDSTART low and at the next high pulse of TG, the sequence state machine is
progressed to the next state, STATE_1, by MCLK. This is repeated until the maximum number of
states determined by STATERST has been reached. At this point the LED drive current will be
switched away from the selected LED. The sequence state machine will be held in this state until
restarted by LEDSTART and TG.
If at any time both TG and LEDSTART are high, the sequence is synchronously set back to STATE_0
by MCLK.
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MONOCHROME (COMPOSITE) MODE
In Monochrome Mode, the progression between sequence states is triggered by the completion of the
previous sequence state. This allows a complete LED sequence change for each line scan.
With both TG and LEDSTART high, the sequence state machine is synchronously set to the
STATE_0 by MCLK. When the STATE_0 has reached the end of its enable period, the sequence
state machine is progressed to the next state by MCLK. This is repeated until the maximum number
of states determined by STATERST has been reached. At this point the LED drive current will be
switched away from the selected LEDs. The sequence state machine will be held in this state until
restarted by LEDSTART and TG.
If at any time both TG and LEDSTART are high, the sequence is synchronously set back to
STATE_0 by MCLK.
LED CURRENT DRIVE INTENSITY CONTROL
The LED current driver is programmable to allow the LED light intensity to be adjusted independent of
the LED light wavelength. Two methods are available for this:
The absolute LED current drive may be set using a programmable 8-bit current DAC.
The current DAC range for each of the LEDs may be adjusted to one of four ranges
using the register LEDIRNG.
The LED current drive may be pulsed using a pulse width modulated. The pulse width
modulated period is set using the register LEDPWMPER and on time using the
registers LEDPWMDCR, LEDPWMDCB and LEDPWMDCG.
Control of the absolute LED current drive and PWM modulation are independently programmable for
each of the red, green and blue LEDs using the register map. The signals LEDSTART, TG and MCLK
determine timing.
LED CURRENT DRIVE STATE TRANSITION AND PWM SWITCHING
The WM8255 is the combination of a LED current switching matrix and an AFE. With reference to
Figure 15, during a typical line scan the video signal of the previous line scan is digitised by the AFE
while the image of the current line scan is illuminated. To suppress any switching noise of the LED
switching matrix coupling into the AFE, care is taken while switching the current.
Two types of current switching are available in the WM8255, state transition switching and PWM
switching. State transition switching occurs when either a new LED is to be selected or the LED
current DAC has to be updated. PWM transition switching occurs when the illumination intensity is
controlled by pulsing the LED drive current. In colour mode, state transition switching should occur at
the start of a line scan. In mono mode, state transition switching can occur during the line scan. In
either colour mode or mono mode, PWM transition switching can occur during the line scan.
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Figure 15 Relationship between Line Scan Illumination and Video Signal Readout
Two current switching techniques are used for state and PWM transition switching, slew rate
controlled current switching and current steering switching.
With reference to Figure 16, the LED drive current has three blocks, the LED current DAC, the LED
RGB matrix switch and a shunt current path switch.
With reference to Figure 16, for current slew rate controlled switching, the LED current DAC value is
reset from the current value to zero then set to an updated value. Slew rate limited current switch
may be partitioned into four operations:
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Figure 16 Current Slew Rate Controlled Switching
1.
The red RGB switch is initially closed and the LED drive current will flow in the red diode
2.
The Red RGB switch will open and the shunt current path switch is closed. The LED drive
current will flow in the shunt current path. During this period the LED current DAC is reset
to zero then updated to the next value. No current will flow in any LEDs.
3.
The green RGB switch will be closed.
4.
The auxiliary current path switch will be opened and LED drive current will flow in the green
LED.
The finite time taken for a slew rate controlled current switch is the period necessary to change the
value of the LED current DAC. The slew rate of the current change is limited by the dynamic
performance of the LED current DAC. During this time the LED IDAC current will flow through the
shunt current path switch and no illumination will occur. This period of time is defined by blanking
period
MONO MODE REQUIREMENTS
During a slew rate limited current switch of the LED IDAC, the change of current flowing in the IDAC
will couple a minor disturbance into the AFE. In colour mode this disturbance is not an issue since the
state change switching will occur at the beginning of a line scan when no imaging is occurring. In
mono mode a red, blue and green state switching may occur during a line scan and couple correlated
switching noise into the signal path.
In mono mode to minimise switching noise into the signal path::
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The blanking period must be disabled. In this mode during a state change, no slew rate limiting
switching will occur, Only the RGB switches will be switched. Table 3 defines the method to
disable blanking during a state transition.
-
In this mode of operation, between states the absolute value of the LED IDAC current must not
change.
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-
In this mode of operation, setting the duty cycle to zero is an invalid state. The RGB switches
should be used to switch off the LED current.
This method will have no effect on colour mode performance.
BLANKING DISABLE CODE SET
Address
Data
0x01
0xA3
Comment
This will put the part into test configuration mode. Any address will now point to
the extended page reconfiguration register
0x24
0x1C
This will:
-- force the LED IDAC control state machine to stay on at all time
- force the value to be held in LEDIDACR to be loaded into the LED current DAC
0x01
0x23
This will take the part back into normal operating mode.
Notes:
1. If this COMPLETE SEQUENCE of operation is not carried out TOGETHER the part may go into an unsupported mode
To finish a mono mode scan with blanking period disabled and perform another operation, the part needs to get into a know state. Two
options are available for a complete reset of the device or a reset of the LED sequence controller:
Option 1: WM8255 global reset from blanking period disable
Address
Data
Comment
0x04
0x00
This will reset the WM8255 into its default condition. The part should now be fully
reconfigured into the user configuration.
Option 2: WM8255 LED sequence controller reset from blanking period disable
Address
Data
Comment
0x2F
0x00
This will reset LED sequence controller WM8255. All configuration data will be held.
Table 3 Blanking Period Disable
With reference to Figure 17 for current steering,
1.
The appropriate RGB matrix switch is closed allowing the LED current DAC current to flow in the
LED
2.
The first step to switch off the LED current is to close the shunt current path switch
3.
The LED is switched off by opening the RGB switch matrix.
4.
To switch on the LED, first the shunt current path switch is closed and the cycle repeats.
A make before break switch sequence is used when the LED is switched on or off. As a result the
LED current DAC always has a path to flow and never changes value.
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1
2
3
4
Figure 17 Current Steering Switching
LED CURRENT DRIVE CURRENT PWM CONTROL
During each sequence state, the LED control module can be pulsed by Pulse Width Modulating
(PWM) the LED current drive. For each sequence state, the PWM frequency, duty cycle, and number
of PWM cycles can be configured.
The PWM controller consists of two blocks; the MCLK divider and the PWM counter. The MCLK
divider divides the MCLK by an amount set by the register CLKDIV.
The divided MCLK is then used to clock the PWM counter. The PWM counter will increment until it
reaches its maximum count set by the register LEDPWMPER. At this point, the PWM counter will
reset to zero, then continue to increment. This will set the period of the PWM control.
As the PWM counter is incremented, its state is compared with the duty cycle setting, which is set by
the value in register LEDPWMDC. PWMCtrl is set while the counter value is smaller than the duty
cycle setting. When the counter is larger than or equal to the duty cycle, PWMCTRL is reset for the
rest of the PWM period. This will set the duty cycle of the PWM control.
The reset of the PWM counter will increment the LEDEnable counter. When the LEDEnable counter
has reached LEDENSTART, PWMEn is set high, which allows PWMCtrl to control the LED current
drive. The LEDEnable counter will continue to increment until it has reached LEDENSTOP. At this
point PWMEn is set low, which stops PWMCtrl from controlling the LED current drive. This will set the
number of cycles of the PWM control.
The PWM frequency is defined by LEDPWMPER and the divider CLKDIV. LEDPWMPER and
CLKDIV may be calculated as the nearest integral of the MCLK frequency divided by the PWM
frequency. If the maximum value of LEDPWMPER would reach its maximum before the desired
PWM period is achieved, CLKDIV should be incremented to scale LEDPWMPER correctly.
The PWM duty cycle is defined by LEDPWMDC and CLKDIV. For a chosen PWM frequency, an
integral number of PWM cycles for the period of TG may be calculated. The range of the PWM period
and the duty cycle can be up to (2^4 X 2^12) MCLK cycles.
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There is an operational difference in monochrome mode in that LEDENSTART is only used in the first
state. In subsequent states the LED enable is always activated after the appropriate number of
blanking periods (LEDENSTOP is used in the same method as colour mode operation).
NON PWM MODE
The PWM functionality can be disabled and just the current DAC can be used. The duty cycle
LEDPWMDC register for each colour should be set to equal the duty cycle period register,
LEDPWMPER. The value of both these registers should be set to an appropriate value.
LED CURRENT DRIVE CURRENT BLANKING PERIOD
At the start of a LED sequence state transition the LED controller performs a blanking period. The
blanking period is a period of time reserved to switch to the next LED drive current state in the
sequence. In addition, during the blanking period the absolute LED drive current will be updated, a
Safe Operating Area (SOA) test may be performed and finally the next LED in the sequence will be
selected then driven. At completion of the blanking period, the PWM controller is enabled.
Figure 18 shows a basic blanking period during a state transition of switching the Red LED off, then
Green LED on.
The blanking period may be split into a sequence of five operations:
1.
The Red RGB switch will be switched off and any current forced to flow in the shunt current
path.
2.
The LED current DAC will be disabled. During this period, the current flow in the auxiliary
current path will tend to zero.
3.
The LED current DAC value will be updated to the value necessary to drive the Green LED.
During this time, the current flow in the auxiliary current path will tend to the updated LED
current DAC current.
4.
A SOA test will be performed on the updated LED current DAC current.
5.
The Green RGB switch will be switched on.
The transition from one state to the next takes the finite time defined by the period tblank.
With reference to Table 4, the basic blanking period may be optimised dependant on the mode of
operation.
Figure 18 LED Current DAC Current during a Blanking Period
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ILIMITEN [1:0]
00
DESCRIPTION
At a state transition, one blanking period will be used before the LED can be
enabled.
LED DAC current will be changed and next LED in sequence shall be selected.
No Safe Operating Area test will be performed.
01
At a state transition, two blanking periods will be used before the LED can be
enabled.
During the first blanking period, should the LED DAC current exceed
LEDIMAX, ILIMITFLAG is set and the LED DAC current is reduced by the
percentage set by ILIMITDEC.
During the second blanking period, should the LED current exceed LEDIMAX,
ILIMITFLAG is set and the LED DAC current will be shutdown.
10
At a state transition, one blanking period will be used before the LED can be
enabled.
Should the LED current exceed LEDIMAX, ILIMITFLAG is set. The LED
current will not be reduced automatically. In this situation, the user should take
measures to protect the LED by reducing the LED current.
11
Not a valid setting
Table 4 Modes of Operation of ILIMITEN Register
SETTING THE INITBLANK REGISTER
With reference to Figure 19, the period tBLANK is the initial blank period with no illumination. The initial
blank period time must be controlled by setting a value for a 9-bit register INITBLANK. Setting this
register will enable a counter that is clocked by MCLK to allow for the necessary minimum 25
microseconds. The last three LSBs are fixed to zero and only the 6 MSBs are adjustable.
The value needed for the register INITBLANK is calculated by :(tBLANK *0.8)/ MCLK period = INITBLANKdec.
decimal number.
This number should be rounded up to an integral
The binary equivalent of INITBLANKdec should be calculated and, making sure the last 3 LSBs are
zero, should be set in the register.
For example:MCLK = 24 Mhz
=> 41.6ns (tPER)
(tBLANK * 0.8) / tPER = (25s * 0.8) / 41.6ns = 480.77
The nearest integral number where the binary equivalent has zero values in the last 3 LSBs is 480.
480 = 111100000 bin. Therefore the 6 MSBs to be set to the register INITBLANK are:- 111100
By default INITBLANK is set to zero which sets the initial blank period to equal the PWM period/0.8
set by LEDPWMPER.
If ILIMITEN is set to ‘01’ then this blanking period will be doubled. Note that the INITBLANK register
value does not require a new value in this situation.
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Figure 19 PWMLED Current Control Timing, CLKDIV = 0 – RGB Colour Scan
Blank 1
Blank 2
(optional)
tblank
Figure 20 PWMLED Current Control Timing, CLKDIV = 1 – RGB Colour Scan
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Figure 21 PWMLED Current Control Timing – Monochrome Scan with PWM Duty Cycle
Blank 1
Blank 2
(optional)
Blank 1
Blank 2
(optional)
tBLANK
Figure 22 PWMLED Current Control Timing – Monochrome Scan with 100% PWM Duty Cycle (PWM functionality
disabled)
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0
1
2
3
0
1
Figure 23 PWM LED Current Control Timing - Monochromatic Scan with PWM Duty Cycle and Blanking Period
Disabled
CURRENT ACCURACY AND ABSOLUTE MAXIMUM CURRENT LIMIT
To protect the LED when operated near its maximum operating current range, an accurate absolute
maximum current limit can be set.
An external resistor connected to the EXTRES pin must be provided to generate an accurate
reference current for the LED circuit. As the current DAC is designed for low compliance voltage, a
separate higher accuracy current detection circuit is provided.
At the start of every state change the Current DAC setting for that LED is measured (Red, Green or
Blue). If the state machine is at RED and the current, LEDIDACR, exceeds the absolute maximum
current limit, a register, LEDRFLAG will be set. If ILIMITEN is set to the appropriate mode, the current
will be automatically reduced and the current retested. Should this new current be within the safe
operating area the Red LED will be enabled. The LEDRFLAG register will remain set to indicate that
the reduction has been implemented.
The next time the state machine enters the RED state, the current value is measured again. If the
current, LEDIDACR is now an acceptable value (without a reduction) the LEDRFLAG will reset. This
is the same when in the GREEN and BLUE states, where LEDIDACG and LEDIDACB are measured
respectively. Note that for the initial current test of a new state, the machine always loads the Current
DAC register setting, not a reduced value previously used.
Throughout the DAC loading and current limit testing, the LED is disabled and the current is steered
through the power supply AVDD1. This prevents stress in the LED, by ensuring that it is not enabled
until the current is within the safe operating area.
A register bit ILIMITFLAG will get set when any of the LED Flags are set. All of the Flags will be reset
when applying a LED Software Reset.
For example:
The Red LED maximum current is 53mA in this example.
LEDIRNGR = 11 which gives an absolute maximum current of 68 mA.
LEDIMAX = 1 which gives a maximum limit of up to 53 mA.
ILIMITDEC = 1 which sets reduction to 25%
ILIMITEN = 01 which enables current reduction
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LEDRFLAG and subsequently ILIMITFLAG will be set and LED current will be reduced to: 68 mA * (10.25) = 51 mA
This is within the safe operating area of the LED to be driven.
In the case of a safe operating area test fail, the LED current will be reduced by 25% to give a
maximum limit of up to 39.75 mA
Should this LED current drive be insufficient during operation it may be calibrated until a target is met.
The algorithm used to control the calibration of the LED DAC current is user specific but it has access
to the LED Flags, ILIMITFLAG and the LED current DAC register values.
A binary incremental or binary weighted search may be used to increase the LED DAC current to the
absolute current maximum limit. An indication of how to perform a binary incremental search is
mentioned below.
A SUGGESTED BINARY INCREMENTAL SEARCH IMPLEMENTED BY THE
USER
When the LED maximum current is detected, the LED current can be trimmed back by either 12.5%
or 25%, depending on ILIMITDEC. At 25% this will guarantee the LED current is below the LED DAC
absolute maximum current limit. The LED current can then be incremented by an LSB of the LED
current register. The LED current will continue to be incremented until ILIMITFLAG is again set.
Figure 24 shows this process graphically.
The LSB of the current is 0.4% of the full LED current DAC full scale range. As a result the LED
current DAC may trim the LED current drive to within +/-0.2% of target.
If the coarse LED current limit is 35mA to 53mA when LEDIMAX=1, this means the trip point accuracy
will be:Min. Limit – ((Min. Full Scale Range/255)/2) >> Max. Limit + ((Max. Full Scale Range/255)/2)
In this case LEDRNG = 11 so Min. FSR is 50 and Max FSR is 68.
LEDIMAX=1 so Min. Limit is 35 and Max. Limit is 53.
Therefore:35 - ((50/255) /2) >> 53 + ((68/255) /2)
= 34.9 >> 53.13
gives
35 - (0.196/2) >> 53 + (0.266/2)
or 44 +/-20.75%.
During the binary incremental search, the LED current will continue to be incremented until
ILIMITFLAG is again set. At this point it is desirable to disable the reduction of the LED current.
Different options to disable the reduction of current can be achieved through the register bit ILIMITEN.
Refer to Table 4 in the Blank Period Section.
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Figure 24 An Example of How LED Current Limiting Can Be Operated
LED CONTROL WORKED EXAMPLE
As an example of configuring the LED current drive control, consider the scan of a US Letter page
size with the AFE configured to sample at 12 MHz MCLK and 3:1 MCLK:VSMP ratio.
The aim is to calculate LEDPWMPER for the given MCLK frequency to give a PWM frequency of
typically 2.5kHz. Then the number of PWM cycles per line scan is calculated to check that there is
sufficient imaging time and coarse trim range.
Assumptions
MCLK:VSMP ratio
= 3:1
MCLK frequency
= 12MHz
VSMP frequency
= 4MHz
LED Enable counter range
= 2^7 (maximum) PWM clock periods
LED PWM counter range
= 2^12 (maximum) PWM clock periods
Colour Scan Mode
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Target blanking period
= 25uSec
Desired PWM frequency
= 2.5kHz
Colour sequence
= red, green, blue
Sensor scan width
= 9 inches
Scan resolution
= 2400 dpi
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1.
The number of MCLK cycles per PWM period is given by:
LEDPWMPER = 12 MHz / 2.5kHz = 4800.
This exceeds the maximum 4095 so CLKDIV must be set to ‘0001’.
Therefore 12Mhz / 2 = 6MHz
Therefore LEDPWMPER = 6MHz / 2.5kHz = 2400
2.
The number of MCLK cycles necessary for blanking period is given by:
(tBLANK *0.8)*MCLK = INITBLANKdec.
(25uSec * 0.8)*12MHz = 240
The binary equivalent of INITBLANKdec should be calculated and, making sure the last 3 LSBs are
zero, should be set in the register.
240 = 0 1111 0000bin. Therefore the 6 MSBs to be set to the register INITBLANK are :- 011110bin
By default INITBLANK is set to zero which sets the initial blank period to equal the PWM period/0.8
3.
The number of MCLK cycles per line scan is given by:
MCLK cycles per line scan = 9inch * 2400dpi * 3 = 64800
4.
The number of MCLK cycles available for imaging is given by:
MCLK cycles per line scan - MCLK cycles per line scan = 64800 – 240 = 64560
5.
The Number of PWM cycles per line scan is given by:
MCLK cycles per PWM period LEDPWMPER = 2400
Number of PWM cycles per line scan = 64560 / 2400 = 26.9
The nearest integral number of PWM cycles per line scan then 26.
The illumination period should be checked. Assuming 26 PWM cycles per line, with the first
cycle reserved for the current DAC setup and transition, and an 80% duty cycle
Period of illumination
= 26 * 0.8 / 2.5kHz = 8.32 msec
Period of illumination coarse trim LSB
= 1 / 2.5kHz
= 400 usec
Period of illumination fine trim LSB
= 1 / 6MHz
= 166.66 nsec
PWM
If the period of illumination per line scan is too short, the imaging period is limiting the scan period.
The period between TG pulses should be increased and step 2 should be repeated to calculate the
number of MCLK cycles per line scan.
Set values for LEDPWMDCR / G / B as appropriate.
Using the number of PWM cycles per line scan for reference, set values for LEDENSTART and
LEDENSTOPR / G / B as appropriate.
Set values for LEDIDACR / G / B as appropriate.
A red, green, blue, red, green, blue colour transition is required, so set STATE0 = 00 for red,
STATE1 = 01 for green and STATE2 = 10 for blue. Set STATERST = 10
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CONTROL INTERFACE
The internal control registers are programmable via the serial digital control interface. The register
contents can be read back via the serial interface on pin OP[3]/SDO.
It is recommended that a software reset is carried out after the power-up sequence, before writing to
any other register. This ensures that all registers are set to their default values (as shown in Table 8).
SERIAL INTERFACE: REGISTER WRITE
Figure 25 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit
address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data word
(b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK. When
the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the
appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode.
SCK
SDI
a5
0
a3
a2
a1
a0
b7
b6
b5
Address
b4
b3
b2
b1
b0
Data Word
SEN
Figure 25 Serial Interface Register Write
A software reset is carried out by writing to Address “000100” with any value of data, (i.e. Data Word
= XXXXXXXX.
SERIAL INTERFACE: REGISTER READ-BACK
Figure 26 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus
as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing
address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of
corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge of
SCK). Note that pin SDO is shared with an output pin, OP[3], so no data can be read when reading
from a register. The next word may be read in to SDI while the previous word is still being output on
SDO.
SCK
SDI
a5
1 a3 a2 a1 a0
Address
x
x
x
x
x
x
x
x
Data Word
SEN
SDO
d7 d6 d5 d4 d3 d2 d1 d0
Output Data Word
Figure 26 Serial Interface Register Read-back
TIMING REQUIREMENTS
To use this device a master clock (MCLK) of up to 24MHz and a per-pixel synchronisation clock
(VSMP) of up to 12MHz is required. These clocks drive a timing control block, which produces
internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum
sample rates for the various modes are shown in Table 6.
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PROGRAMMABLE VSMP DETECT CIRCUIT
The VSMP input is used to determine the sampling point and frequency of the WM8255. Under
normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling
frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on
the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal
may not be readily available. The programmable VSMP detect circuit in the WM8255 allows the
sampling point to be derived from any signal of the correct frequency, such as a CCD shift register
clock, when applied to the VSMP pin.
When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge
(determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse.
This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits.
Figure 27 shows the internal VSMP pulses that can be generated by this circuit for a typical clock
input signal. The internal VSMP pulse is then applied to the timing control block in place of the normal
VSMP pulse provided from the input pin. The sampling point then occurs on the first rising MCLK
edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams.
MCLK
INPUT
PINS
VSMP
POSNNEG = 1
(VDEL = 000) INTVSMP
VS
(VDEL = 001) INTVSMP
VS
VS
(VDEL = 010) INTVSMP
VS
VS
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
VS
VS
VS
VS
VS
(VDEL = 101) INTVSMP
VS
VS
VS
VS
(VDEL = 110) INTVSMP
VS
VS
VS
VS
(VDEL = 111) INTVSMP
VS
VS
VS
VS
VS
VS
POSNNEG = 0
(VDEL = 000) INTVSMP
VS
(VDEL = 001) INTVSMP
VS
(VDEL = 010) INTVSMP
VS
VS
VS
(VDEL = 101) INTVSMP
VS
VS
VS
(VDEL = 100) INTVSMP
VS
VS
VS
(VDEL = 011) INTVSMP
VS
VS
VS
(VDEL = 110) INTVSMP
(VDEL = 111) INTVSMP
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
Figure 27 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit
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REFERENCES
The ADC reference voltages are derived from an internal band-gap reference, and buffered to pins
VRT and VRB, where they must be decoupled to ground. The output buffer from the RLCDAC also
requires decoupling at pin VRLC/VBIAS when this is configured as an output.
POWER SUPPLY
The WM8255 operates from either a 5.75V (AVDD1) supply or a 3.3V (AVDD2).
POWER MANAGEMENT
The WM8255 has a power management system to detect the presence and correct level of the power
supplies AVDD1, AVDD2 and DVDD.
With reference to Figure 28, the WM8255 is partitioned into three power domains, a digital domain
powered by DVDD, LED current drive domain powered by AVDD1 and AFE domain powered by
AVDD2. In the digital domain, until DVDD has reached the correct level, a Power On Reset (POR)
shall disable the WM8255. The LDO voltage regulator and AFE voltage references shall be enabled
and allowed to power up as AVDD1 is applied when the POR released. With AVDD1, AVDD2 and
AFE voltage references at the correct level a system enable is set and WM8255 shall power up in a
controlled manner.
Figure 28 Power Management System
Power management for the device is performed via the Control Interface. The device can be powered
on or off completely by setting the EN bit low.
All the internal registers maintain their previously programmed value in power down mode and the
Control Interface inputs remain active.
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POWER ON SEQUENCE
In order to guarantee correct operation, the digital supply (DVDD) and analogue supply (AVDD1)
should be applied as specified in Figure 29 and Table 5.
If it is not possible to apply the recommended power up sequence, the user must wait until both
DVDD and AVDD1 have risen fully, then disable and enable the WM8255 by software write to EN
(R0, b0). It is then possible to apply further register writes and operate the WM8255 correctly.
When powering down the WM8255, no specific power down sequence is required.
REDUCED POWER
With DVDD applied, AVDD1 may be powered down with no loss to digital configuration data. This will
reduce the power consumption of the device whilst still keeping register settings and configurations.
Figure 29 Power On Sequence
Test Conditions
AVDD1 = 5.75V, DVDD = 3.3V, AGND = DGND = AVDD2 = 0V, TA = 25C, MCLK = 24MHz unless otherwise stated.
PARAMETER
SYMBOL
DVDD set up time to AVDD1 rising
edge
TEST CONDITIONS
tPSU
MIN
TYP
MAX
UNITS
100
μs
Table 5 Power On Timing
OPERATING MODES
Table 6 summarises the most commonly used modes, the clock waveforms required and the register
contents required for CDS and non-CDS operation.
MODE
DESCRIPTION
CDS
AVAILABLE
MAX
SAMPLE
RATE
TIMING
REQUIREMENTS
REGISTER
CONTENTS WITH
CDS
REGISTER
CONTENTS
WITHOUT CDS
1
Monochrome/
Colour Line-by-Line
Yes
6 MSPS
MCLK max = 24MHz
SetReg1: 0F(hex)
SetReg1: 0D(hex)
Fast Monochrome/
Colour Line-by-Line
Yes
MCLK:VSMP ratio is
3:1
Identical to Mode
1 plus SetReg3:
bits 5:4 must be
set to 0(hex)
Identical to
Mode 1
Maximum speed
Monochrome/
Colour Line-by-Line
No
MCLK max = 24MHz
CDS not possible
SetReg1: 4D(hex)
2
3
MCLK:VSMP ratio is
2n:1 n 2
8 MSPS
12 MSPS
MCLK max = 24MHz
MCLK:VSMP ratio is
2:1
Table 6 WM8255 Operating Modes
*Note: Maximum sample rate depends on the MCLK to VSMP ratio. A higher ratio will mean a lower
maximum sample rate for a specified MCLK speed.
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OPERATING MODE TIMING DIAGRAMS
The following diagrams show 4-bit multiplexed output data and MCLK, VSMP and input video
requirements for operation of the most commonly used modes as shown in Table 6. The diagrams are
identical for both CDS and non-CDS operation.
16.5 MCLK PERIODS
MCLK
VSMP
VINP
OP[3:0]
(DEL = 00)
OP[3:0]
(DEL = 01)
A B C
A B C
A B C
D
OP[3:0]
(DEL = 10)
OP[3:0]
(DEL = 11)
D
D
D
D
D
D
D
D
A B C
A B C
D
A B C D
A B C
A B C
D
A B C
D
A B C
A B C
A B C
D
A B C
D
A B C
A B C
A B C
D
A B C
D
D
A B C D
D
Figure 30 Mode 1 Operation
24.5 MCLK PERIODS
MCLK
VSMP
VINP
SAMPLE
RESET
RS
SAMPLE
VIDEO
RS
VS
RS
VS
RS
VS
RS
VS
RS
VS
VS
OP[3:0]
(DEL = 00)
C
D
A B C
D
A B C
D
A B C
D
AB C
D
A B C
D
A B CD
OP[3:0]
(DEL = 01)
C
D
A B C
D
A B C
D
A B CDD
AB C
D
A B C
D
A B CD
OP[3:0]
(DEL = 10)
C
D
A B C
D
A B C
D
A B C
D
AB C
D
A B C
D
A B CD
OP[3:0]
(DEL = 11)
C
D
A B C
D
A B C
D
A B C
D
AB C
D
A B C
D
A B CD
Figure 31 Mode 2 Operation
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16.5 MCLK PERIODS
MCLK
VSMP
VINP
OP[3:0]
(DEL = 00)
A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D
OP[3:0]
(DEL = 01)
A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D
OP[3:0]
(DEL = 10)
A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D
OP[3:0]
(DEL = 11)
A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D
Figure 32 Mode 3 Operation
DEVICE REVISION CODES
To read the device revision code the test registers must be accessed. Table 7 defines the method:
DEVICE REVISION CODE
Address
Data
Comment
0x01
0xA3
This will put the part into test configuration mode. Any address will
now point to
0x27
Read
0x01
0x23
the extended page reconfiguration register
Read all eight bits of this register. Bit[7:1] contain the revision code
information, Bit[0]
should be ignored
This will take the part back into normal operating mode.
Table 7 Revision Code
Note: For Rev C devices it will read ‘01’
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DEVICE CONFIGURATION
REGISTER MAP
The following table describes the location of each control bit used to determine the operation of the
WM8255. The register map is programmed by writing the required codes to the appropriate
addresses via the serial interface.
Address Description
Def
RW
(hex)
BIT
b7
b6
b5
b4
b3
b2
b1
b0
TREG_OPEN
MODE3
PGAFS[1]
PGAFS[0]
VSMPDET
0
CDS
EN
000001
Setup Reg 1
03
RW
000010
Setup Reg 2
00
RW
DEL[1]
DEL[0]
0
RLCINT
VRLCEXT
INVOP
2BITOP
POSNEG
000011
Setup Reg 3
13
RW
INTM[1]
INTM[0]
CDSREF [1]
CDSREF [0]
RLCV[3]
RLCV[2]
RLCV[1]
RLCV[0]
000100
Software
Reset
00
W
000101
Setup Reg 4
00
RW
0
LEDIMAX
0
0
0
VDEL[2]
VDEL[1]
VDEL[0]
000110
Setup Reg 5
20
RW
LEDIDACR
[7]
LEDIDACR
[6]
LEDIDACR
[5]
LEDIDACR
[4]
LEDIDACR
[3]
LEDIDACR
[2]
LEDIDACR
[1]
LEDIDACR
[0]
000111
Setup Reg 6
20
RW
LEDIDACG LEDIDACG
[7]
[6]
LEDIDACG
[5]
LEDIDACG LEDIDACG
[4]
[3]
LEDIDAC
[2]
LEDIDACG
[1]
LEDIDACG
[0]
001000
Setup Reg 7
20
RW
LEDIDACB
[7]
LEDIDACB
[6]
LEDIDACB
[5]
LEDIDACB
[4]
LEDIDACB
[2]
LEDIDACB
[1]
LEDIDACB
[0]
001001
Setup Reg 8
C0
RW
STATE_
RST[1]
STATE_
RST[0]
0
0
LEDIRNGR
[1]
LEDIRNGR
[0]
001010
Setup Reg 9
00
RW ILIMITEN [1] ILIMITEN[0] MONOMODE
0
LEDIRNGB
[1]
LEDIRNGB
[0]
001011
Setup Reg 10
E4
RW
STATE2 [0] STATE1 [1] STATE1 [0] STATE0 [1]
STATE0 [0]
001100
Setup Reg 11
00
RW
LEDPWM
PER[7]
LEDPWM
PER[6]
LEDPWM
PER[5]
LEDPWM
PER[4]
LEDPWM
PER[3]
LEDPWM
PER[2]
LEDPWM
PER[1]
LEDPWM
PER[0]
001101
Setup Reg 12
00
RW
CLKDIV[3]
CLKDIV[2]
CLKDIV[1]
CLKDIV[0]
LEDPWM
PER[11]
LEDPWM
PER[10]
LEDPWM
PER[9]
LEDPWM
PER[8]
001110
Setup Reg 13
00
RW
LEDPWM
DCR[7]
LEDPWM
DCR[6]
LEDPWM
DCR[5]
LEDPWM
DCR[4]
LEDPWM
DCR[3]
LEDPWM
DCR[2]
LEDPWM
DCR[1]
LEDPWM
DCR[0]
001111
Setup Reg 14
00
RW
LEDPWM
DCG[7]
LEDPWM
DCG[6]
LEDPWM
DCG[5]
LEDPWM
DCG[4]
LEDPWM
DCG[3]
LEDPWM
DCG[2]
LEDPWM
DCG[1]
LEDPWM
DCG[0]
100000
DAC Value
(Red)
80
RW
DACR[7]
DACR[6]
DACR[5]
DACR[4]
DACR[3]
DACR[2]
DACR[1]
DACR[0]
100001
DAC Value
(Green)
80
RW
DACG[7]
DACG[6]
DACG[5]
DACG[4]
DACG[3]
DACG[2]
DACG[1]
DACG[0]
100010
DAC Value
(Blue)
80
RW
DACB[7]
DACB[6]
DACB[5]
DACB[4]
DACB[3]
DACB[2]
DACB[1]
DACB[0]
100011
DAC Value
(RGB)
80
W
DAC[7]
DAC[6]
DAC[5]
DAC[4]
DAC[3]
DAC[2]
DAC[1]
DAC[0]
100100
Setup Reg 15
00
RW
LEDPWM
DCB[7]
LEDPWM
DCB[6]
LEDPWM
DCB[5]
LEDPWM
DCB[4]
LEDPWM
DCB[3]
LEDPWM
DCB[2]
LEDPWM
DCB[1]
LEDPWM
DCB[0]
100101
Setup Reg 16
11
RW
LEDPWM
DCG[11]
LEDPWM
DCG[10]
LEDPWM
DCG[9]
LEDPWM
DCG[8]
LEDPWM
DCR[11]
LEDPWM
DCR[10]
LEDPWM
DCR[9]
LEDPWM
DCR[8]
100110
Setup Reg 17
01
RW
LEDSTART LEDSTART
[3]
[2]
LEDSTART
[1]
LEDSTART
[0]
LEDPWM
DCB[11]
LEDPWM
DCB[10]
LEDPWM
DCB[9]
LEDPWM
DCB[8]
100111
Setup Reg 18
10
RW
LEDSTART LEDSTOPR
[6]
[4]
LEDSTOPR
[5]
LEDSTOPR LEDSTOPR LEDSTOPR LEDSTOPR LEDSTOPR
[4]
[3]
[2]
[1]
[0]
101000
PGA Gain
(Red)
00
RW
PGAR[7]
PGAR[6]
PGAR[5]
PGAR[4]
PGAR[3]
PGAR[2]
PGAR[1]
PGAR[0]
101001
PGA Gain
(Green)
00
RW
PGAG[7]
PGAG[6]
PGAG[5]
PGAG[4]
PGAG[3]
PGAG[2]
PGAG[1]
PGAG[0]
101010
PGA Gain
(Blue)
00
RW
PGAB[7]
PGAB[6]
PGAB[5]
PGAB[4]
PGAB[3]
PGAB[2]
PGAB[1]
PGAB[0]
w
STATE3 [1] STATE3 [0]
STATE2 [1]
LEDIDACB
[3]
LEDIRNGG LEDIRNGG
[1]
[0]
MONOTG
REQLEDST
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WM8255
Production Data
Address Description
Def
RW
BIT
(hex)
b7
b6
b5
b4
b3
b2
b1
b0
PGA[7]
PGA[6]
PGA[5]
PGA[4]
PGA[3]
PGA[2]
PGA[1]
PGA[0]
101011
PGA Gain
(RGB)
00
W
101100
Setup Reg 19
10
RW
LEDSTART LEDSTOPG
[6]
[5]
LEDSTOPG
[5]
LEDSTOPG LEDSTOPG LEDSTOPG LEDSTOPG LEDSTOPG
[4]
[3]
[2]
[1]
[0]
101101
Setup Reg 20
10
RW
LEDSTART LEDSTOPB
[6]
[6]
LEDSTOPB
[5]
LEDSTOPB LEDSTOPB LEDSTOPB LEDSTOPB LEDSTOPB
[4]
[3]
[2]
[1]
[0]
101110
Setup Reg 21
00
RW ILIMITFLAG ILIMITDEC
INITBLANK
[8]
INITBLANK INITBLANK INITBLANK INITBLANK
[7]
[6]
[5]
[4]
101111
LED Software
Reset
00
W
LED RGB
Flags
00
R
INITBLANK
[3]
LEDRFLAG LEDGFLAG LEDBFLAG
Table 8 Register Map
EXTENDED PAGE REGISTERS
Address Description
Def
RW
BIT
(hex)
100100
LED Control
100111
Revision
Number
b7
b6
b5
b4
b3
b2
b1
b0
0
0
LED_TEST
CTRL[3]
LED_TEST
CTRL[2]
LED_TEST
CTRL[1]
LED_TEST
CTRL[0]
0
0
REV_NUM
[6]
REV_NUM
[5]
REV_NUM
[4]
REV_NUM
[3]
REV_NUM
[2]
REV_NUM
[1]
REV_NUM
[0]
X
Table 9 Extended Page Registers
Note: To access the Extended Page Registers the TREG_OPEN bit must be set to ‘1’ in Setup Reg 1. This bit must then be
set to ‘0’ once access is complete. Please refer to Pages 23 and 38 for details on when to access these registers.
REGISTER MAP DESCRIPTION
The following table describes the function of each of the control bits shown in Table 8.
REGISTER
Setup
Register 1
BIT
NO
BIT NAME(S)
DEFAULT
DESCRIPTION
0
EN
1
0 = complete power down, 1 = fully active.
1
CDS
1
Select correlated double sampling mode: 0 = single ended mode,
1 = CDS mode.
2
Reserved
0
Must be set to zero
3
VSMPDET
0
0 = Normal operation, signal on VSMP input pin is applied directly to
Timing Control block.
1 = Programmable VSMP detect circuit is enabled. An internal
synchronization pulse is generated from signal applied to VSMP input
pin and is applied to Timing Control block.
5:4
PGAFS[1:0]
00
Offsets PGA output to optimize the ADC range for different polarity
sensor output signals. Zero differential PGA input signal gives:
00 = Zero output
(use for bipolar video)
01 = Zero output
10 = Full-scale positive output
(use for negative going video)
11 = Full-scale negative output
(use for positive going video)
6
MODE3
0
Required when operating in MODE3: 0 = other modes, 1 = MODE3.
7
TREG_OPEN
0
Enables the extended page register access
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41
WM8255
Production Data
REGISTER
Setup
Register 2
BIT
NO
BIT NAME(S)
DEFAULT
DESCRIPTION
0
POSNEG
0
When VSMPDET = 0 this bit has no effect.
When VSMPDET = 1 this bit controls whether positive or negative edges
are detected:
0 = Negative edge on VSMP pin is detected and used to generate
internal timing pulse.
1 = Positive edge on VSMP pin is detected and used to generate
internal timing pulse.
See Figure 27 for further details.
1
2BITOP
0
Changes the digital output from 4 bit muxed to 2 bit muxed output.
2
INVOP
0
Digitally inverts the polarity of output data.
0 = negative going video gives negative going output,
1 = negative-going video gives positive going output data.
3
VRLCEXT
0
When set powers down the RLCDAC, changing its output to Hi-Z,
allowing VRLC/VBIAS to be externally driven.
4
RLCINT
0
This bit is used to determine whether Reset Level Clamping is enabled.
5
Reserved
0
Must be set to zero.
7:6
DEL[1:0]
00
Sets the output latency in ADC clock periods.
0 = RLC disabled, 1 = RLC enabled.
1 ADC clock period = 2 MCLK periods except in Mode 2 where 1 ADC
clock period = 3 MCLK periods.
00 = Minimum latency
01 = Delay by one ADC clock
period
Setup
Register 3
3:0
RLCV[3:0]
0011
5:4
CDSREF[1:0]
01
Controls RLCDAC driving VRLC pin to define single ended signal
reference voltage or Reset Level Clamp voltage. See Electrical
Characteristics section for ranges.
CDS mode reset timing adjust.
00 = Advance 1 MCLK period
01 = Normal
7:6
INTM[1:0]
00
10 = Delay by two ADC clock periods
11 = Delay by three ADC clock periods
10 = Retard 1 MCLK period
11 = Retard 2 MCLK periods
Colour selection bits used in internal modes.
00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.
See Table 1 for details.
Any write to Software Reset causes all cells (including LED) to be reset.
Software
Reset
Setup
Register 4
It is recommended that a software reset be performed after a power-up
before any other register writes.
2:0
VDEL[2:0]
000
When VSMPDET = 0 these bits have no effect.
When VSMPDET = 1 these bits set a programmable delay from the
detected edge of the signal applied to the VSMP pin. The internally
generated pulse is delayed by VDEL MCLK periods from the detected
edge.
5:3
Reserved
000
Must be set to zero
6
LEDIMAX
0
Sets the maximum current limit to one of two ranges (see electrical
characteristics section).
Must be set to zero
See Figure 27, Internal VSMP Pulses Generated for details.
7
Reserved
0
Setup
Register 5
7:0
LEDIDACR [7:0]
00100000
Fine LED current during imaging for Red LED
Setup
Register 6
7:0
LEDIDACG [7:0]
00100000
Fine LED current during imaging for Green LED
Setup
Register 7
7:0
LEDIDACB [7:0]
00100000
Fine LED current during imaging for Blue LED
Setup
Register 8
1:0
LEDIRNGR [1:0]
00
Coarse LED current range during imaging for Red LED
2
Reserved
0
Must be set to zero
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42
WM8255
REGISTER
Setup
Register 9
Production Data
BIT
NO
BIT NAME(S)
DEFAULT
DESCRIPTION
4:3
LEDIRNGG [1:0]
00
Coarse LED current range during imaging for Green LED
5
Reserved
0
Must be set to zero
7:6
STATERST [1:0]
11
State reset. Sets the number of states to be used.
00 = State_0 only
01 = State_0 to State_1
10 = State_0 to State_2
11 = State_0 to State_3
LEDIRNGB [1:0]
00
Coarse LED current range during imaging for Blue LED
2
Reserved
0
Must be set to zero
3
REQLEDST
0
If LEDSTART is to be used this register must be set high
4
MONOTG
0
When MONOMODE=0 this register has no effect.
1:0
When set high allows the TG pin to restart the colour sequence when in
mono mode.
Setup
Register 10
5
MONOMODE
0
When set, puts the LED control in to monochrome (composite mode)
7:6
ILIMITEN[1:0]
00
Specifies the mode of operation of current limiting of the LED DAC. See
Table 4 for details.
1:0
STATE0[1:0]
00
Sets the State 0 colour setting.
3:2
5:4
7:6
STATE1[1:0]
STATE2[1:0]
STATE3[1:0]
01
10
11
Red = 00
Green = 01
Blue = 10
Off = 11
Sets the State 1 colour setting.
Red = 00
Green = 01
Blue = 10
Off = 11
Sets the State 2 colour setting.
Red = 00
Green = 01
Blue = 10
Off = 11
Sets the State 3 colour setting.
Red = 00
Green = 01
Blue = 10
Off = 11
Sets the LSBs of the maximum value for the LED PWM period. [7:0]
Setup
Register 11
7:0
LEDPWMPER
[7:0] (LSBs)
00000000
Setup
Register 12
3:0
LEDPWMPER
[11:8] (MSBs)
0000
Sets the MSBs of the maximum value for the LED PWM period. [11:8]
7:4
CLKDIV [3:0]
0000
Sets the division of MCLK applied to the PWM counter.
Setup
Register 13
7:0
LEDPWMDCR
[7:0] (LSBs)
00000000
Sets the LSBs of the LED PWM Duty Cycle for the RED LED. [7:0]
Setup
Register 14
7:0
LEDPWMDCG
[7:0] (LSBs)
00000000
Sets the LSBs of the LED PWM Duty Cycle for the GREEN LED. [7:0]
Offset DAC
(Red)
7:0
DACR[7:0]
10000000
Red channel offset DAC value. Used under control of the INTM[1:0]
control bits.
Offset DAC
(Green)
7:0
DACG[7:0]
10000000
Green channel offset DAC value. Used under control of the INTM[1:0]
control bits.
Offset DAC
(Blue)
7:0
DACB[7:0]
10000000
Blue channel offset DAC value. Used under control of the INTM[1:0]
control bits.
Offset DAC
7:0
DAC[7:0]
Setup
Register 15
7:0
LEDPWMDCB
[7:0] (LSBs)
00000000
Sets the LSBs of the LED PWM Duty Cycle for the BLUE LED. [7:0]
Setup
Register 16
3:0
LEDPWMDCR
[11:8] (MSBs)
0001
Sets the MSBs of the LED PWM Duty Cycle for the RED LED. [11:8]
7:4
LEDPWMDCG
[11:8] (MSBs)
0001
Sets the MSBs of the LED PWM Duty Cycle for the GREEN LED. [11:8]
The LEDPWMDCG must not be set to zero (MSB and LSB both zero)
3:0
LEDPWMDCB
[11:8] (MSBs)
0001
Sets the MSBs of the LED PWM Duty Cycle for the BLUE LED. [11:8]
7:4
LEDSTART [3:0]
0000
Sets the LSBs of the 7 bit LEDSTART time. [3:0]
A write to this register location causes the red, green and blue offset
DAC registers to be overwritten by the new value.
(RGB)
Set up
Register 17
w
The LEDPWMDCR must not be set to zero (MSB and LSB both zero)
The LEDPWMDCB must not be set to zero (MSB and LSB both zero)
PD, Rev 4.7, August 2013
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WM8255
Production Data
REGISTER
BIT
NO
BIT NAME(S)
DEFAULT
Setup
Register 18
6:0
LEDSTOPR [6:0]
0010000
7
LEDSTART [4]
0
PGA gain
(Red)
7:0
PGAR[7:0]
0
PGA gain
(Green)
7:0
DESCRIPTION
Sets the LED stop time for the RED LED.
Sets the next significant bit of the 7 bit LEDSTART time. [4]
Determines the gain of the red channel PGA according to the equation:
Red channel PGA gain = [0.78+(PGAR[7:0]*7.57)/255]. Used under
control of the INTM[1:0] control bits.
PGAG[7:0]
0
Determines the gain of the green channel PGA according to the
equation:
Green channel PGA gain = [0.78+(PGAG[7:0]*7.57)/255]. Used under
control of the INTM[1:0] control bits.
PGA gain
(Blue)
7:0
PGA gain
7:0
PGA[7:0]
Setup
Register 19
6:0
LEDSTOPG [6:0]
0010000
7
LEDSTART [5]
0
Setup
Register 20
6:0
LEDSTOPB [6:0]
0010000
7
LEDSTART [6]
0
Setup
Register 21
5:0
INITBLANK [8:3]
000000
6
ILIMITDEC
0
PGAB[7:0]
0
Determines the gain of the blue channel PGA according to the equation:
Blue channel PGA gain = [0.78+(PGAB[7:0]*7.57)/255]. Used under
control of the INTM[1:0] control bits.
A write to this register location causes the red, green and blue PGA gain
registers to be overwritten by the new value
(RGB)
Sets the LED stop time for the GREEN LED.
Sets the next significant bit of the 7 bit LEDSTART time. [5]
Sets the LED stop time for the BLUE LED.
Sets the MSB of the 7 bit LEDSTART time. [6]
Sets the 6 MSBs of the 9 bit register to adjust the initial blank period
following a sequence transition. The 3 LSBs are fixed to zero. Must be
set so the initial blank period is 25s. See Initial Blank Period on page
25 for details.
When ILIMITEN = 0 this register has no effect.
When the maximum LED current limit is exceeded and the ILIMITFLAG
is set, the current is reduced to a safe level to protect the LED.
0 = 12.5% reduction in current
1 = 25% reduction in current
7
ILIMITFLAG
0
When ILIMITEN=00 this read register will not be active.
Read only register. Set high by the device when the current limit has
been exceeded.
LED
Resets all LED timing control to its reset state at register write
Reset
LED RGB
FLAGS
0
LEDBFLAG
0
Set high by the device when the current limit has been exceeded for the
Blue LED. May be read.
1
LEDGFLAG
0
Set high by the device when the current limit has been exceeded for the
Green LED. May be read.
2
LEDRFLAG
0
Set high by the device when the current limit has been exceeded for the
Red LED. May be read.
Table 10 Register Control Bits
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WM8255
Production Data
EXTENDED PAGE REGISTER MAP DESCRIPTION
REGISTER
BIT
NO
BIT NAME(S)
DEFAULT
LED Control
1:0
Reserved
0
5:2
LED_TESTCTRL
[3:0]
0000
DESCRIPTION
Must be set to zero
General LED test modes:
LED_TESTCTRL[1:0] = Mode override. The IDAC can be forced into
one of three modes:
01 = IDAC_LOAD: IDAC is loaded with new current value (based on
the current state), and CHANGE_SETUP & IDAC_DISABLE are high.
10 = IDAC_CHECK: RGB switch is enabled (based on current state)
and IDAC_CALIBRATE is set high. Current setting will not change
unless test load is enabled.
11 = IDAC_ON: IDAC is fully out of reset. PWM_LEDON will still be
driven by the counters unless the test override is used. Current setting
will not change unless test load is enabled.
LED_TESTCTRL[2] = Test update. The current setting is continuously
reloaded (from Red register when machine in reset).
LED_TESTCTRL[3] = PWM test enable. PWM_LEDON is now driven
using the LEDSTART pin.
7:6
Reserved
00
Must be set to zero
Revision
0
Reserved
X
This bit should be ignored
Number
7:1
REV_NUM
[6:0]
Revision Number of device
Table 11 Extended Page Register Bits
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WM8255
Production Data
RECOMMENDED EXTERNAL COMPONENTS
Figure 33 External Components Diagram
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
R1
13k7ohm
C1
100nF
De-coupling for AVDD1
C2
100nF
De-coupling for AVDD2
C3
100nF
De-coupling for DVDD
C4
10nF
High frequency de-coupling between VRT and VRB
C5
1uF
Low frequency de-coupling between VRT and VRB
C6
100nF
De-coupling for VRB
C7
100nF
De-coupling for VRX
C8
100nF
De-coupling for VRT
C9
100nF
De-coupling for VRLC
C10
10uF
Reservoir capacitor for DVDD
C11
10uF
Reservoir capacitor for AVDD1
C12
10uF
Reservoir capacitor for AVDD2
Resistor used for LED current maximum limit accuracy
Table 12 External Components Descriptions
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WM8255
Production Data
PACKAGE DIMENSIONS
DM090.A
FL: 28 PIN QFN PLASTIC PACKAGE 4 X 4 X 0.85 mm BODY, 0.40 mm LEAD PITCH
PIN 1
D2
eee C A B
28
22
A
D
B
INDEX AREA
(D/2 X E/2)
L
21
1
E2
eee C A B
E
7
15
2X
14
8
e
2X
b
ddd
M
aaa C
aaa C
CAB
TOP VIEW
BOTTOM VIEW
ccc C
A2
(A3)
A
bbb C
A1
C
SEATING PLANE
M
M
VIEW M - M
Symbols
A
A1
A2
A3
b
D
D2
E
E2
e
L
aaa
bbb
ccc
ddd
eee
REF
MIN
0.8
0
0.15
2.60
2.60
0.30
Dimensions (mm)
NOM
MAX
0.85
0.9
0.05
0.035
0.65
0.67
0.203 REF
0.20
0.25
4.00 BSC
2.70
2.80
4.00 BSC
2.70
2.80
0.4 BSC
0.40
0.35
NOTE
1
Tolerances of Form and Position
0.10
0.08
0.10
0.10
0.10
JEDEC, MO-220 VGGE
NOTES:
1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP.
2. ALL DIMENSIONS ARE IN MILLIMETRES
3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-002.
4. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
5. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION.
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47
Production Data
WM8255
IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer
product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for
such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.
Any use of products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other
intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or
services might be or are used. Any provision or publication of any third party’s products or services does not constitute
Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document
belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is
not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or
accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any
reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
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WM8255
Production Data
REVISION HISTORY
DATE
REV
ORIGINATOR
CHANGES
04/04/12
4.6
JMacD
Order codes changed from WM8255SEFL and WM8255SEFL/R to
WM8255CSEFL/R and WM8255CSEFL/R to reflect change to copper wire
bonding.
04/04/12
4.6
JMacD
Package diagram changed to DM109.A. A1 changed from 0.9mm to 0.85mm
19/08/13
4.7
JMacD
Order codes WM8255CSEFL and WM8255CSEFL/R removed.
19/08/13
4.7
JMacD
Package diagram DM109A removed.
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49
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