WM8716
High Performance 24-bit, 192 kHz Stereo DAC
DESCRIPTION
FEATURES
The WM8716 is a high performance stereo DAC designed
for audio applications such as CD, DVD, home theatre
systems, set top boxes and digital TV. The WM8716
supports data input word lengths from 16 to 24-bits and
sampling rates up to 192kHz. The WM8716 consists of a
serial interface port, digital interpolation filter, multi-bit sigma
delta modulator and stereo DAC in a small 28-lead SSOP
package. The WM8716 also includes a digitally controllable
mute and attenuator function on each channel.
112dB SNR (‘A’ weighted @ 48kHz), THD: -97dB @
-1dB FS
The internal digital filter has two selectable roll-off
characteristics. A sharp or slow roll-off can be selected
dependent on application requirements. Additionally, the
internal digital filter can be by-passed and the WM8716
used with an external digital filter.
Sampling frequency: 8kHz to 192kHz
Selectable digital filter roll-off
Optional interface to industry standard external filters
Differential mono mode
Input data word: 16 to 24-bit
Hardware or SPI compatible serial port control modes:
The WM8716 supports two connection schemes for audio
DAC control. The SPI-compatible serial control port provides
access to a wide range of features including on-chip mute,
attenuation and phase reversal. A hardware controllable
interface is also available.
Hardware mode: mute, de-emphasis, audio format
control
Serial mode: mute, de-emphasis, attenuation (256
steps), phase reversal
Compatible upgrade to PCM1716
APPLICATIONS
CD, DVD audio
Home theatre systems
Set top boxes
Digital TV
BLOCK DIAGRAM
MODE ML/I2S MC/DM1 MD/DM0 DIFFHW MUTEB CSBIWO RSTB ZERO MODE8X AGNDR AVDDR
(24)
(28)
(27)
(26)
(17)
(25)
(23)
(22) (21)
(12)
(10) (9)
W
WM8716
(11) VMIDR
CONTROL INTERFACE
MUTE/
ATTEN
BCKIN (3)
LRCIN (1)
SERIAL
INTERFACE
DIN (2)
MUX
SIGMA
DELTA
MODULATOR
RIGHT
DAC
LOW
PASS
FILTER
(13) VOUTR
MUX
SIGMA
DELTA
MODULATOR
LEFT
DAC
LOW
PASS
FILTER
(16) VOUTL
DIGITAL
FILTERS
MUTE/
ATTEN
(18) VMIDL
CRYSTAL/OSC
(4)
(5)
CLKO XTI
http://www.cirrus.com
(6)
XTO
(15)
(8)
AVDD DVDD
(20) (19)
(14)
AVDDL. AGNDL AGND
Copyright Cirrus Logic, Inc., 2004–2020
(All Rights Reserved)
(7)
DGND
Rev 4.3
JAN 2020
WM8716
TABLE OF CONTENTS
DESCRIPTION ................................................................................................................ 1
FEATURES ..................................................................................................................... 1
APPLICATIONS.............................................................................................................. 1
BLOCK DIAGRAM ......................................................................................................... 1
TABLE OF CONTENTS .................................................................................................. 2
PIN CONFIGURATION ................................................................................................... 3
ORDERING INFORMATION ........................................................................................... 3
ABSOLUTE MAXIMUM RATINGS ................................................................................. 3
RECOMMENDED OPERATING CONDITIONS .............................................................. 3
ELECTRICAL CHARACTERISTICS .............................................................................. 4
TERMINOLOGY ......................................................................................................................... 5
SIGNAL TIMING REQUIREMENTS ............................................................................... 6
AUDIO INTERFACE TIMING ..................................................................................................... 6
SYSTEM CLOCK TIMING .......................................................................................................... 6
PROGRAM REGISTER TIMING ................................................................................................ 7
PIN DESCRIPTION ......................................................................................................... 8
DEVICE DESCRIPTION ................................................................................................. 9
SYSTEM CLOCK ....................................................................................................................... 9
AUDIO DATA INTERFACE .......................................................................................... 10
NORMAL SAMPLE RATE ........................................................................................................ 10
8 X FS INPUT SAMPLE RATE................................................................................................. 11
MODES OF OPERATION ........................................................................................................ 12
HARDWARE CONTROL MODES ............................................................................................ 12
SOFTWARE CONTROL INTERFACE ..................................................................................... 13
REGISTER MAP ...................................................................................................................... 13
MUTE MODES ......................................................................................................................... 18
FILTER RESPONSES .............................................................................................................. 19
APPLICATIONS INFORMATION ................................................................................. 22
RECOMMENDED EXTERNAL COMPONENTS ...................................................................... 22
RECOMMENDED EXTERNAL COMPONENTS VALUES ....................................................... 22
PACKAGE DIMENSIONS ............................................................................................. 25
IMPORTANT NOTICE .................................................................................................. 26
REVISION HISTORY .................................................................................................... 27
2
Rev 4.3
WM8716
PIN CONFIGURATION
LRCIN
1
28
M L/I2S
DIN
2
27
M C/DM 1
BCKIN
3
26
M D/DM 0
CLKO
4
25
M UTEB
XTI
5
24
M ODE
XTO
6
23
CSBIWO
DGND
7
22
RSTB
DVDD
8
21
ZERO
AVDDR
9
20
AVDDL
AGNDR
10
19
AGNDL
VM IDR
11
18
VM IDL
M ODE8X
12
17
DIFFHW
VOUTR
13
16
VOUTL
AGND
14
15
AVDD
ORDERING INFORMATION
DEVICE
TEMPERATURE
RANGE
WM8716SEDS/V
-25 to +85C
WM8716SEDS/RV
-25 to +85C
PEAK SOLDERING
TEMPERATURE
PACKAGE
28-lead SSOP
(Pb- free)
28-lead SSOP
(Pb- free, tape and reel)
260C
260C
Note:
Reel quantity = 2,000
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
CONDITION
MIN
MAX
Supply voltage
-0.3V
+7.0V
Reference input
VDD + 0.3V
Operating temperature range, TA
-25C
+85C
Storage temperature
-65C
+150C
DGND -0.3V
DVDD +0.3V
Voltage range digital inputs
Master clock frequency
37MHz
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Digital supply range
Rev 4.3
SYMBOL
DVDD
TEST CONDITIONS
MIN
TYP
MAX
UNIT
-10%
3.3 to 5
+10%
V
3
WM8716
Analogue supply range
Ground
AVDD
-10%
AGND, DGND
Digital supply current
+10%
0
Difference DGND to AGND
Analogue supply current
3.3 to 5
-0.3
V
V
0
+0.3
V
AVDD = 5V
26
40
mA
35
mA
DVDD = 5V
22
Analogue supply current
AVDD = 3.3V
25
mA
Digital supply current
DVDD = 3.3V
13
mA
ELECTRICAL CHARACTERISTICS
TEST CONDITIONS
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
105
MAX
UNIT
DAC Circuit Specifications
SNR (See Notes 1 and 2)
112
dB
THD (full-scale)
0dB FS
-92
dB
(See Note 2)
-1dB FS
-97
dB
112
dB
Dynamic range
(See Note 2)
THD @ -60dB FS
105
Passband
0.0012 dB
0.4535fs
Stopband
-3dB
Filter Characteristics (Sharp Roll-off)
dB
0.491fs
0.0012
Passband ripple
Stopband Attenuation
f > 0.5465fs
-82
Delay time
dB
dB
30/fs
s
Filter Characteristics (Slow Roll-off)
Passband
0.001dB
0.274fs
Stopband
-3dB
0.459fs
f > 0.732fs
-82
0.001
Passband ripple
Stopband Attenuation
Delay time
dB
dB
9/fs
s
-3dB
195
kHz
20kHz
-0.043
dB
Internal Analogue Filter
Bandwidth
Passband edge response
Digital Logic Levels
Input LOW level
VIL
Input HIGH level
VIH
0.8
2.0
V
(See Note 3)
4
Output LOW level
VOL
IOL = 2mA
Output HIGH level
VOH
IOH = 2mA
DGND + 0.3V
V
DVDD - 0.3V
Rev 4.3
WM8716
TEST CONDITIONS
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Output Levels
Output level
Minimum resistance load
Maximum capacitance load
Into 10kΩ, full scale 0dB,
(5V supply)
Into 10kΩ, full scale 0dB,
(3.3V supply)
To midrail or AC coupled
(5V supply)
To midrail or AC coupled
(3.3V supply)
5V or 3.3V
Output DC level
VRMS
1.1
0.72
VRMS
1
kΩ
600
Ω
100
pF
AVDD/2
Gain mismatch channel to
channel
0.5
V
2
%FSR
Reference Levels
Potential divider resistance
AVDD to VMIDL/VMIDR and
10
kΩ
VMIDL/VMIDR to AGND
Voltage at VMIDL/VMIDR
AVSS/2
POR
POR threshold
2.5V
V
Notes:
1.
Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’
weighted over a 20Hz to 20kHz bandwidth.
2.
All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher THD+N and
lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of
band noise; although it is not audible it may affect dynamic specification values.
3.
Except for Pin 12 (MODE8X) and Pin 17 (DIFFHW), where VIH = 2.6V min.
TERMINOLOGY
1.
Signal-to-noise ratio (dB) (SNR) is a measure of the difference in level between the full-scale output and the output with no
signal applied.
2.
Dynamic range (dB) (DNR) is a measure of the difference between the highest and lowest portions of a signal. Normally a
THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (eg THD+N @
-60dB= -32dB, DR= 92dB).
3.
THD+N (dB) is a ratio of the r.m.s. values, of (Noise + Distortion)/Signal.
4.
Stop band attenuation (dB) is the degree to which the frequency spectrum is attenuated (outside audio band).
5.
Channel Separation (dB) (also known as Cross-Talk) is a measure of the amount one channel is isolated from the other.
Normally measured by sending a full-scale signal down one channel and measuring the other.
6.
Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
Rev 4.3
5
WM8716
SIGNAL TIMING REQUIREMENTS
AUDIO INTERFACE TIMING
LRCIN
tBCH
tBCL
tLB
BCKIN
tBCY
tBL
DIN
tDS
tDH
Figure 1 Audio Data Input Timing
TEST CONDITIONS
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN pulse cycle time
tBCY
100
ns
BCKIN pulse width high
tBCH
50
ns
BCKIN pulse width low
tBCL
50
ns
BCKIN rising edge
to LRCIN edge
tBL
30
ns
LRCIN rising edge
to BCKIN rising edge
tLB
30
ns
DIN setup time
tDS
30
ns
DIN hold time
tDH
30
ns
SYSTEM CLOCK TIMING
tSCKIL
SCKI
tSCKIH
Figure 2 System Clock Timing Requirements
TEST CONDITIONS
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
6
SCKI System clock pulse width high
tSCKIH
13
ns
SCKI System clock pulse width low
tSCKIL
13
ns
Rev 4.3
WM8716
PROGRAM REGISTER TIMING
tMLL
M L/I2S (PIN 28)
tMHH
tMCY
tMCH
tMCL
tMLH
tMLS
M C/DM 1 (PIN 27)
tMDS
tMDH
M D/DM 0 (PIN 26)
LSB
tCSML
tMLCS
CSBIWO (PIN 23)
Figure 3 Program Register Input Timing
TEST CONDITIONS
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
MC/DM1 Pulse cycle time
tMCY
100
ns
MC/DM1 Pulse width LOW
tMCL
40
ns
MC/DM1 Pulse width HIGH
tMCH
40
ns
MD/DM0 Hold time
tMDH
40
ns
MD/DM0 Set-up time
tMDS
40
ns
ML/I2S Low level time
(See Note 3)
tMLL
40 +
1SYSCLK
ns
ML/I2S High level time
(See Note 3)
tMHH
40 +
1SYSCLK
ns
ML/I2S Hold time
tMLH
40
ns
ML/I2S Set-up time
tMLS
40
ns
CSBIWO Low to ML/I2S low time
tCSML
10
ns
ML/I2S High to CSBIWO high time
tMLCS
10
ns
Note:
3.
System clock cycle.
Rev 4.3
7
WM8716
PIN DESCRIPTION
PIN
NAME
TYPE
DESCRIPTION
Hardware Mode
Normal Mode
Differential Mode
1
LRCIN
Digital input
Sample rate clock input.
2
DIN
Digital input
Audio data serial input
3
BCKIN
Digital input
Audio data bit clock input.
4
CLKO
Digital output
5
XTI
Analogue input
6
XTO
Analogue output
7
DGND
Supply
Digital ground supply.
8
DVDD
Supply
Digital positive supply.
9
AVDDR
Supply
Analogue positive supply.
10
AGNDR
Supply
Analogue ground supply.
11
VMIDR
Analogue output
12
MODE8X
Digital input
13
VOUTR
Analogue output
14
AGND
Supply
Analogue ground supply.
15
AVDD
Supply
Analogue positive supply.
16
VOUTL
Analogue output
Left channel DAC output.
17
DIFFHW
Digital input
18
VMIDL
Analogue output
19
AGNDL
Supply
Analogue ground supply.
20
AVDDL
Supply
Analogue positive supply.
21
ZERO
Digital output
22
RSTB
Digital input
23
CSBIWO
Digital input
Internal pull-down
8X Mode
DINL
Software
Mode
Audio data
serial input
Oscillator buffered output (system clock).
Oscillator input.
Oscillator output.
Mid rail right channel.
Internal pull-down, active high, 8 x fs mode.
Right channel DAC output.
Internal pull-down, active high, differential mono mode
Mid rail left channel.
Infinite zero detect – active low. Open drain type output with active pull-down.
Reset input – active low. Internal pull-up.
Wordlength:
Wordlength:
Wordlength:
Low for 16-bit data.
Low for 16-bit data.
Low for 20-bit data.
High for 20-bit
(normal) or 24-bit
I2S data.
High for 20-bit
(normal) or 24-bit
I2S data.
High for 24-bit data.
Low for
serial
interface
operation.
24
MODE
Digital input
Internal pull-up
Low for hardware
mode.
Low for left
mono mode. High for
right mono mode
DINR
High for
software
mode.
25
MUTEB
Digital input
Internal pull-up
Low to soft mute.
Low to soft mute.
Low to soft mute.
High for normal
operation.
High for normal
operation.
High for normal
operation.
Low to soft
mute.
Z for automute.
Z for automute.
Z for automute.
High for
normal
operation.
Z for
automute.
26
MD/DM0
Digital input
Internal pull-up
De-emphasis mode
select bit 0.
Low for no
de-emphasis.
LRP – LRCLK
polarity select.
Control serial
interface
data signal.
Unused.
Control serial
interface
clock signal.
High for 44.1kHz
de-emphasis.
27
MC/DM1
Digital input
Internal pull-up
De-emphasis mode
select bit 1.
Low for normal filter
operation.
Leave unconnected.
High for filter slow rolloff.
28
Note:
8
ML/I2S
Digital input
Internal pull-up
Audio serial format:
Audio serial format:
Input data format:
Low – right justified.
Low – right justified.
Low – right justified.
High – I2S.
High – I2S.
High – left justified.
Control serial
interface
load signal.
Digital input pins have Schmitt trigger input buffers except Pin 12 and Pin 17.
Rev 4.3
WM8716
DEVICE DESCRIPTION
The WM8716 is a high performance 128fs oversampling rate stereo DAC employing a novel 64 level
sigma delta DAC design which provides optimised signal-to-noise performance and clock jitter
tolerance. It is ideally suited to high quality audio applications such as CD, DVD-audio, home theatre
receivers and professional mixing consoles. The WM8716 supports sample rates from 8ks/s to
192ks/s.
The control functions of the WM8716 are either pin selected (hardware mode) or programmed via the
serial interface (software mode). Control functions that are available include: data input word length
and format selection (16-24 bits: I2S, left justified or right justified): de-emphasis sample rate selection
(48kHz, 44.1kHz and 32kHz); differential output modes; a software or hardware mute and
independently digitally controllable attenuation on both channels.
The digital filtering may be bypassed entirely by selecting MODE8X. Data is then input directly to the
DAC, bypassing the digital filters. Left and right channels are input separately, using the MODE pin as
the right channel input. This mode allows the use of alternative digital filters, such as the Pacific
Microsonics PMD100 HDCD filter.
In addition to the normal stereo operating mode the WM8716 may also be used in dual differential
mode with either the left or right channel (selectable) being output differentially. Two WM8716s can
then be used in parallel to implement a stereo channel, each supporting a single channel differentially.
This mode is available in both software and hardware modes and may also be used in conjunction
with MODE8X.
SYSTEM CLOCK
Sample rates from 8ks/s up to 96ks/s are available, and automatically selected, with a system clock of
256fs, 384fs, 512fs or 768fs. In addition a system clock of 128fs or 192fs may be used, with sample
rates up to 192ks/s. With a 128fs or 192fs system clock 64x oversampling mode operation is
automatically selected and the first stage of the digital filter is bypassed.
WM8716 has an asynchronous monitor circuit, which in the event of removal of the master system
clock, resets the digital filters and analogue circuits, muting the output. Re-application of the system
clock re-starts the filters from an intitialised state. Control registers are not reset under this condition.
The WM8716 is tolerant of asynchronous bit clock jitter. The internal signal processing resynchronises
to the external LRCIN once the phase difference between bit clock and the system clock exceeds half
an LRCIN period. During this re-synch period the interpolating filters will either miss or repeat an audio
sample, minimising the audible effects of the operation. Table 1 shows the typical system clock
frequency inputs for the WM8716.
SAMPLING
RATE
(LRCIN)
32kHz
44.1kHz
48kHz
96kHz
192kHz
SYSTEM CLOCK FREQUENCY (MHZ)
128fs
192fs
256fs
384fs
512fs
768fs
4.096
5.6448
6.114
12.288
24.576
6.144
8.467
9.216
18.432
36.864
8.192
11.2896
12.288
24.576
Unavailable
12.288
16.9340
18.432
36.864
Unavailable
16.384
22.5792
24.576
Unavailable
Unavailable
24.576
33.8688
36.864
Unavailable
Unavailable
Table 1 System Clock Frequencies Versus Sampling Rate
Rev 4.3
9
WM8716
AUDIO DATA INTERFACE
Data may be input at a rate corresponding to the system clock having a rate of 256fs or 384fs or 512fs
or 768fs, in which case an oversampling ratio of 128x is selected. Alternatively a rate of 128fs or 192fs
may be used, in which case the first filter stage is bypassed and an oversampling ratio of 64x results.
Finally, in MODE8X, data may be input at 8x the normal rate, in which case separate input pins are
used to input the two stereo channels of data (unless DIFFHW mode and MODE8X are both selected,
in which case only a mono channel is converted differentially). In MODE8X all filter stages are bypassed, prior to the sigma delta modulator. Data is input MSB first in all modes.
NORMAL SAMPLE RATE
In normal mode, the data is input serially on one pin for both left and right channels.
Data can be “right justified” meaning that the last 16, 20 or 24 bits (depending on chosen PCM word
length) that were clocked in prior to the transition on LRCIN are valid.
Alternatively data can be “left justified” (20 and 24-bit PCM data only), where the bits are clocked in as
the first 20 or 24 bits after a transition on LRCIN.
For the three I2S modes supported (16-bit, 20-bit and 24-bit PCM data), data is clocked “left justified”
except with one additional preceding clock cycle.
1/f s
LEFT
RIGHT
LRCIN (PIN 1)
BCKIN (PIN 3)
16-BIT RIGHT
JUSTIFIED
DIN (PIN 2)
B2
B1 B0
20-BIT RIGHT
JUSTIFIED
DIN (PIN 2)
B2
B1
24-BIT RIGHT
JUSTIFIED
DIN (PIN 2)
B2 B1
B15
B2
B1
B0
B15
B2
B1
B0
B0
B19 B18 B17
B2
B1
B0
B19 B18 B17
B2
B1
B0
B0
B23 B22 B21 B20 B19
B2
B1
B0
B23 B22 B21 B20 B19
B2
B1
B0
24-BIT LEFT
JUSTIFIED
DIN (PIN 2)
B0
B23 B22 B21
B4
20-BIT LEFT
JUSTIFIED
DIN (PIN 2)
B0
B19 B18 B17
B0
B3
B2
B1
B0
B23 B22 B21
B4
B19 B18 B17
B0
LEFT
B3
B2
B1
B0
RIGHT
LRCIN (PIN 1)
BCKIN (PIN 3)
16-BIT I2S
DIN (PIN 2)
B15
B2
B1 B0
24-BIT I2S
DIN (PIN 2)
B23
B6
B5 B4 B3
20-BIT I2S
DIN (PIN 2)
B19
B2
B1 B0
B2
B1
B0
B15
B2
B1
B0
B23
B6
B5
B4
B19
B2
B1
B0
B15
B3
B2
B1
B0
B23
B19
Figure 4 Audio Data Input Format
10
Rev 4.3
WM8716
8 X FS INPUT SAMPLE RATE
Due to the higher speed of the interface in 8 x fs mode, audio data is input on two pins. The MODE
pin (pin 24) is used as the second input for the right channel data and left data is input on DIN (pin 2).
In this mode, software control of the device is not available. The data can be input in two formats, left
or right justified, selectable by ML/I2S and two word lengths (20 or 24 bit), selectable by CSBIWO. In
both modes the data is always clocked in MSB first.
For left justified data the word start is marked by the falling edge of LRCIN. The data is clocked in on
the next 20/24 BCKIN rising edges. This format is compatible with devices such as the PMD100.
For right justified the data is justified to the rising edge of LRCIN and the data is clocked in on the
preceding 20/24 BCKIN rising edges before the LRCIN rising edge. This format is compatible with
devices such as the DF1704 or SM5842.
In both modes the polarity of LRCIN can be switched using MD/DM0.
Differential hardware mode can be used in conjunction with 8fs mode by setting the DIFFHW pin high.
In differential 8fs mode the data is input on DIN and output differentially. MODE is unused and must
be tied low.
1/8fs
LRCIN (PIN 1)
BCKIN (PIN 3)
LEFT AUDIO
DATA DIN
(PIN 2)
B23
B22
B21
B20
B19
B2
B1
B0
B23
B22
B21
B20
RIGHT AUDIO
DATA M ODE
(PIN 24)
B23
B22
B21
B20
B19
B2
B1
B0
B23
B22
B21
B20
1/8fs
LRCIN (PIN 1)
BCKIN (PIN 3)
LEFT AUDIO
DATA DIN
(PIN 2)
B23
B22
B21
B20
B19
B2
B1
B0
RIGHT AUDIO
DATA M ODE
(PIN 24)
B23
B22
B21
B20
B19
B2
B1
B0
Figure 5 Audio Data Input Format (8 x fs Operation)
Rev 4.3
11
WM8716
MODES OF OPERATION
Control of the various modes of operation is either by software control over the serial interface, or
by hard-wired pin control. Selection of software or hardware mode is via MODE pin. The following
functions may be controlled either via the serial control interface or by hard wiring of the
appropriate pins.
HARDWARE CONTROL MODES
When the MODE pin is held ‘low’ the following hardware modes of operation are available. In
Hardware differential mode or 8X mode some of these modes/control words are altered or
unavailable.
DE-EMPHASIS CONTROL
MDDM1
MCDMO
PIN 27
PIN 26
DE-EMPHASIS
L
L
H
H
L
H
L
H
Off
48kHz
44.1kHz
32kHz
CSBIIS
CSBIWO
DATA FORMAT
PIN 28
PIN 23
L
L
H
H
L
H
L
H
Table 2 De-Emphasis Control
AUDIO INPUT FORMAT
16 bit normal right justified
20 bit normal right justified
16 bit I2S
24 bit I2S
Table 3 Audio Input Format
SOFT MUTE
MUTEB
FUNCTION
PIN 25
L
Z
H
Mute On (no output)
Automute
Mute Off (normal operation)
Table 4 Soft Mute
A logic low on the MUTEB pin will cause the attenuation to ramp to infinite attenuation at a rate of
128/fs seconds per 0.5dB step. Setting MUTEB high will cause the attenuation to ramp back to its
previous value.
Leaving MUTEB undriven allows operation of the automute circuit in both hardware and software
modes. On receiving 1024 consecutive zero value audio samples, the analogue stage output mute is
asserted. This may be overdriven from the MUTEB pin to disable the automute function, or output as
a weak (10kohm) output signal.
12
Rev 4.3
WM8716
SOFTWARE CONTROL INTERFACE
The WM8716 can be controlled using a 3-wire serial interface. MD/DM0 (pin 26) is used for the
program data, MC/DM1 (pin 22) is used to clock in the program data and ML/I2S (pin 28) is use to
latch in the program data. The 3-wire interface protocol is shown in Figure 6. CSB/IWO (pin 23) must
be low when writing.
M L/I2S (PIN 28)
M C/DM 1 (PIN 27)
M D/DM 0 (PIN 26)
B15
B14
B13
B2
B1
B0
Figure 6 Three-Wire Serial Interface
REGISTER MAP
WM8716 controls the special functions using 4 program registers, which are 16-bits long. These
registers are all loaded through input pin MD/DM0. After the 16 data bits are clocked in, ML/I2S is
used to latch in the data to the appropriate register. Table 5 shows the complete mapping of the
4 registers. Note that in hardware differential mode and 8X modes, software control is not available.
The hardware differential mode (Diff[1:0]) clock loss detector disable (CDD) can only be accessed by
writing to M2[8:5] with the pattern 1111. Register M4 is then accessible by setting A[2:0] to 110.
B15
B14
B13
B12
M0
-
-
-
-
M1
-
-
-
M2
-
-
M3
-
M4
-
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
A2 (0) A1(0)
A0(0)
LDL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
-
A2(0)
A1(0)
A0(1)
LDR
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
-
-
A2(0)
A1(1)
A0(0)
-
-
-
-
IW1
IW0
OPE
DEM
MUT
-
-
-
A2(0)
A1(1)
A0(1)
IZD
SF1
SF0
CK0
REV
SR0
ATC
LRP
I2S
-
-
-
A2(1)
A1(1)
A0(0)
-
-
CDD
-
-
-
-
DIFF1 DIFF0
Table 5 Mapping of Program Registers
Rev 4.3
13
WM8716
REGISTER
BITS
NAME
DEFAULT
0
[7:0]
AL[7:0]
FF
8
LDL
0
1
[7:0]
AR[7:0]
FF
8
LDR
0
Attenuation data load control for right channel.
0
MUT
0
Left and right DACs soft mute control.
1
DEM
0
De-emphasis control.
2
OPE
0
Left and right DACs operation control.
[4:3]
IW[1:0]
0
Input audio data bit select.
0
I2S
0
Audio data format select.
1
LRP
0
Polarity of LRCIN select.
2
ATC
0
Attenuator control.
3
SR0
0
Digital filter slow roll-off select.
4
REV
0
Output phase reverse.
5
CKO
0
CLKO frequency select.
[7:6]
SF[1:0]
0
Sampling rate select.
2
3
4
DESCRIPTION
Attenuation data for left channel.
Attenuation data load control for left channel.
Attenuation data for right channel.
8
IZD
0
Infinite zero detection circuit control.
[5:4]
DIFF
0
Differential output mode.
6
CDD
0
Clock loss detector disable.
Table 6 Register Bit Descriptions
DAC OUTPUT ATTENUATION
The level of attenuation for eight bit code X, is given by:
0.5 (X - 255) dB,
1 X 255
- dB (mute),
X=0
Bit 8 in register 0 (LDL) is used to control the loading of attenuation data in B[7:0]. When LDL is set to
0, attenuation data will be loaded into AL[7:0], but it will not affect the filter attenuation. LDR in register
1 has the same function for right channel attenuation. Only when LDL or LDR is set to '1' will the filter
attenuation be updated. This permits left and right channel attenuation to be updated simultaneously.
Attenuation level is controlled by AL[7:0] (left channel) or AR[7:0] (right channel). Attenuation levels
are given in Table 4.
X[7:0]
ATTENUATION LEVEL
00(hex)
01(hex)
:
:
FD(hex)
FE(hex)
FF(hex)
- dB (mute)
-127.0dB
:
:
-1.0dB
-0.5dB
0.0dB
Table 7 Attenuation Control Level
Bit 2 in Reg3 is used to control the attenuator (ATC). When ATC is “high”, the attenuation data loaded
in program register 0 is used for both the left and the right channels. When ATC is low, the attenuation
data for each register is applied separately to left and right channels.
14
Rev 4.3
WM8716
SOFT MUTE
MUT
(REG2, B0)
L
Soft Mute off (normal operation)
H
Soft Mute on (no output)
Table 8 Soft Mute
Setting MUT causes the attenuation to ramp from the current value down to 00. The values held in the
attenuation registers are unchanged. When MUT is reset the attenuation will ramp back up to the
previous value. The ramp rate is 128/fs s/0.5dB step.
DIGITAL DE-EMPHASIS
DEM
(REG2, B1)
L
De-emphasis off
H
De-emphasis on
Table 9 Digital De-Emphasis
DAC OPERATION ENABLE
OPE
(REG2,B2)
L
Normal operation
H
DAC output forced to bipolar zero,
irrespective of input data.
Table 10 DAC Operation Enable
AUDIO DATA INPUT FORMAT
I2S
IW1
IW0
(REG3, B0)
(REG2, B4)
(REG2, B3)
AUDIO INTERFACE
0
0
0
16-bit standard right justified
0
0
1
20-bit standard right justified
0
1
0
24-bit standard right justified
0
1
1
24-bit left justified (MSB first)
1
0
0
16-bit I2S
1
0
1
24-bit I2S
1
1
0
20-bit I2S
1
1
1
20-bit left justified (MSB first)
Table 11 Audio Data Input Format
POLARITY OF LR INPUT CLOCK
The left channel data for a particular sample instant is always input first, then the right channel data.
LRP
(REG3, B1)
L
LR High – left channel
LR Low – right channel
H
LR Low – left channel
LR High – right channel
Table 12 Polarity of LR Input Clock
Rev 4.3
15
WM8716
INDIVIDUAL OR COMMON ATTENUTATION CONTROL
ATC
(REG3, B2)
L
Individual control
H
Common control from Reg0
Table 13 Individual or Common Attenuation Control
DIGITAL FILTER ROLL-OFF SELECTION
SRO
(REG3, B3)
L
Sharp
H
Slow
Table 14 Digital Filter Roll-Off Selection
ANALOGUE OUTPUT POLARITY REVERSAL
REV
(REG3, B4)
L
Normal
H
Inverted
Table 15 Analogue Output Polarity Reversal
CLKO OUTPUT FREQUENCY
CKO
(REG3, B5)
L
XTI
H
XTI/2
Table 16 CLKO Output Frequency
DE-EMPHASIS SAMPLE RATE
SF1
SF0
(REG3, B7)
(REG3, B6)
0
0
1
1
0
1
0
1
SAMPLE RATE
No de-emphasis
48kHz
44.1kHz
32kHz
Table 17 De-Emphasis Sample Rate
INFINITE ZERO DETECT
IZD
(REG3, B8)
L
Zero detect mute off
H
Zero detect mute on
Table 18 Infinite Zero Detect
16
Rev 4.3
WM8716
DIFFERENTIAL MONO MODE
Using bits 4 and 5, the differential output mode may be selected to be one of normal stereo, reversed
stereo, mono left or mono right, as shown in Table 19.
DIFF[1:0]
DIFFERENTIAL OUTPUT MODE
B[4:5])
00
Stereo
01
Stereo reverse.
10
Mono left – differential outputs.
VOUTL is left channel.
VOUTR is the negative of left channel.
Mono right – differential outputs.
11
VOUTL is the negative right channel.
VOUTR is right channel.
Table 19 Differential Output Modes
Using these controls a pair of WM8716 devices may be used to build a ‘dual differential’ stereo
implementation with higher performance and differential output.
CLOCK LOSS DETECTOR DISABLE
CDD (REG4, B6)
L
Clock loss detector on
R
Clock loss detector off
Table 20 Clock Loss Detector Disable
When the system clock is inactive for approximately 100s, the clock loss detector circuit detects the
loss of clock and the analogue circuitry is forced into a mute condition and the digital filters reset.
Setting the CDD bit disables this behaviour.
Rev 4.3
17
WM8716
MUTE MODES
The device has various mute modes.
DIGITAL FILTER
ANALOGUE
ANRES
ANMUTE
Reg bit OPE = ‘1’
Unaffected
Asserted
MUTEB pin
Gain ramped to zero
Asserted when
gain = 0
On release volume ramps
to previous value
AUTOMUTE
Automute has no effect on digital filters
Asserted after
1024 zero input
samples if IZD = 1
Reg bit MUT
As MUTEB pin
As MUTEB pin
Gain = 00
(left & right)
Gain = -dB
Asserted
RAM initialise
Gain initialised to 0dB
Loss of system clock
Not running (no clock). On clock
restart, filters initialised, RAM
initialised. Registers unchanged
Asserted
Asserted
No LRCLK or invalid
SCLK/LRCLK ratio
Filters initialised, RAM initialised.
Registers unchanged
Asserted
Asserted
RB
Reset – gain initialised to 0dB
Asserted
Asserted
Power-on reset
Reset
Asserted
Asserted
(detect 1024 zero
input samples)
Asserted
Table 21 Mute Modes
ANRES is the reset to the switched capacitor filter.
ANMUTE is an analogue muting signal gating the analogue signal at the output (after the
SC filter)
AUTOMUTE is asserted when both the IZD register bit is asserted and the input audio data has been zero
on both left and right channels for 1024 input samples. The first non-zero sample de-asserts.
Applying a logic low to MUTEB or setting MUT in Reg2 causes the gain registers to ramp to zero. When a
logic high is applied, the gain ramps slowly back up to the value held in the appropriate attenuation
register (AL or AR). The ramp rate = 128/fs s/0.5dB step.
If SOFT MUT E is set or
MUT EB=0 then GAINL and
GAINR are overridden to 00
GAINL[0: 7]
SOFT MUT E
Signal
Proc es sing
GAINR[0: 7]
MUT EB
gain ramps between
previous and new gain
setting
Automute:
Detect 1024
zero input
samples
IZD
OPE
FREQ_INVALID
INIT
ANMUT E
ZERO
Figure 7 Mute Modes
18
Rev 4.3
WM8716
FILTER RESPONSES
Figure 8 Digital Filter Response (Sharp Roll-off Mode)
Figure 9 Digital Filter Response (Sharp Roll-off Mode)
Figure 10 Digital Filter Response (Slow Roll-off Mode)
Figure 11 Digital Filter Response (Slow Roll-off Mode)
Figure 12 Digital Filter Response 128fs Mode (192kHz
Sample Rate) Normal Mode – Solid, Slow Mode – Dashed
Rev 4.3
19
WM8716
Figure 14 Impulse Response (Slow Roll-off,
no De-emphasis)
0.0
0.0
-1.0
-1.0
-2.0
-2.0
-3.0
-3.0
Response (dB)
Response (dB)
Figure 13 Impulse Response (Normal Roll-off,
no De-emphasis)
-4.0
-5.0
-6.0
-4.0
-5.0
-6.0
-7.0
-7.0
-8.0
-8.0
-9.0
-9.0
-10.0
-10.0
0
2000
4000
6000
8000
10000
12000
14000
16000
0
5000
10000
Frequency (Fs)
15000
20000
Frequency (Fs)
Figure 15 De-emphasis frequency response (fs=32kHz)
Figure 15 De-emphasis frequency response (fs=44.1kHz)
0.0
0.4
-1.0
0.3
-2.0
0.2
Response (dB)
Response (dB)
-3.0
-4.0
-5.0
-6.0
0.1
0.0
-0.1
-7.0
-0.2
-8.0
-0.3
-9.0
-10.0
-0.4
0
2000
4000
6000
8000
10000
12000
14000
16000
18000
20000
Frequency (Fs)
Figure 16 De-emphasis frequency response (fs=48kHz)
20
0
2000
4000
6000
8000
10000
12000
14000
16000
Frequency (Fs)
Figure 17 De-emphasis frequency response error
(fs=32kHz)
Rev 4.3
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
Response (dB)
Response (dB)
WM8716
0.0
-0.1
0.0
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
0
2000
4000
6000
8000
10000
12000
14000
16000
18000
Frequency (Fs)
Figure 18 De-emphasis frequency response error
(fs=44.1kHz)
Rev 4.3
20000
0
2000
4000
6000
8000
10000
12000
14000
16000
18000
20000
Frequency (Fs)
Figure 19 De-emphasis frequency response error
(fs=48kHz)
21
WM8716
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
DVDD
AVDD
8
DVDD
+
C1
AVDD
C2
AVDDR
7
DGND
AVDDL
9
20
+
C3
DGND
AGND
AGNDR
AGNDL
28
27
Software I/F or
Hardware Control
15
26
23
22
C5
C6
14
10
AGND
19
ML/I2S
MC/DM1
MD/DM0
CSB/IWO
RSTB
VOUTR
VOUTL
AC-Coupled Output
to External LPF
C8
16
+
MODE8X
C7
13
+
12
C4
WM8716
17
AVDD
DIFFHW
R1
24
25
MODE
ZERO
MUTEB
VMIDR
VMIDL
1
2
Audio Serial Data I/F
3
5
System Clock Input or
Oscillator Input/Output
NOTES:
6
21
11
18
+
+ C11
C9
LRCIN
C12
C10
DIN
BCKIN
AGND
CLKO
4
XTI
XTI Buffered Output
XTO
1. AGND and DGND should be connected as close to the WM8716 as possible.
2. C2 to C5, C9 and C11 should be positioned as close to the WM8716 as possible.
3. Capacitor type used can have a big effect on device performance. It is
recommended that capacitors with very low ESR are used and that ceramics
are either NPO or COG type material to achieve best performance from the
WM8716.
Figure 20 External Components Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1 and C6
10F
De-coupling for DVDD and AVDD.
C2 to C5
0.1F
De-coupling for DVDD and AVDD.
C7 and C8
10F
Output AC coupling caps to remove VMID DC level from outputs.
C9 and C11
C10 and C12
R1
0.1F
10F
10k
Reference de-coupling capacitors for VMIDR and VMIDL.
Resistor to AVDD for open drain output operation.
Table 22 External Components Description
22
Rev 4.3
WM8716
RIGHT DAC
DVDD
AVDD
8
+
DVDD
AVDD
AVDDR
7
1
LRCIN
2
DIN
AUDIO
SERIAL
DATA
3
BCKIN
5
SCKI
6
4
DGND
LRCIN
25
22
AGND
DIN
AGNDR
BCKIN
AGNDL
XTI
VOUTR
27
Hardw are
Control
26
23
+
14
10
19
13
+
CLKO
LPF
VOUTL
WM8716
MODE
ZERO
16
-
RIGHT
OUTPUT
DATA
21
MUTEB
RSTB
VMIDR
VMIDL
28
9
20
XTO
DVDD
24
AVDDL
15
11
18
+
+
ML/I2S
MC/DM1
MD/DM0
CSB/IWO
MODE8X
12
AVDD
DIFFHW
17
LEFT DAC
DVDD
AVDD
8
+
DVDD
AVDD
AVDDR
7
1
2
3
5
6
4
DGND
LRCIN
25
22
AGND
DIN
AGNDR
BCKIN
AGNDL
XTI
VOUTR
27
26
23
+
14
10
19
13
+
CLKO
LPF
WM8716
MODE
VOUTL
ZERO
16
-
LEFT
OUTPUT
DATA
21
MUTEB
RSTB
VMIDR
VMIDL
28
9
20
XTO
DVDD
24
AVDDL
15
11
+
18
+
ML/I2S
MC/DM1
MD/DM0
CSB/IWO
MODE8X
12
AVDD
DIFFHW
NOTE:
17
1. MODE selects left/right data. High for right, Low for left.
Figure 21 Example of 2 WM8716 Stereo DACs Configured in Hardware Differential Mode to Provide an Optimum
Performance Stereo Output
Rev 4.3
23
WM8716
+VDD
MODE8X
SCKI
XTI
PMD-100
XTI
Serial Interf ace Data
LRCIN
WCKO
LRCIN
BCKO
BCKIN
LRCI
BCKIN
BCKI
DIN
DOL
DIN
DOR
MODE
VOUTL
DIN
PROG
WM8716
VOUTR
(STAND ALONE
MODE)
+VDD
ML/I2S
NOTES:
1. ML/I2S selects left or right justified inputs.
CSB/IWO
MD/DM0
2. MD/DM0 selects LRCLK polarity.
MUTEB
3. CSBIWO selects 20 or 24-bit data.
Figure 22 Example of WM8716 in MODE8X Operation
24
Rev 4.3
WM8716
PACKAGE DIMENSIONS
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)
b
DM007.E
e
28
15
E1
1
D
E
GAUGE
PLANE
14
c
A A2
A1
L
0.25
L1
-C0.10 C
Symbols
A
A1
A2
b
c
D
e
E
E1
L
L1
REF:
MIN
----0.05
1.65
0.22
0.09
9.90
7.40
5.00
0.55
o
0
Dimensions
(mm)
NOM
--------1.75
0.30
----10.20
0.65 BSC
7.80
5.30
0.75
1.25 REF
o
4
SEATING PLANE
MAX
2.0
0.25
1.85
0.38
0.25
10.50
8.20
5.60
0.95
o
8
JEDEC.95, MO-150
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
Rev 4.3
25
WM8716
IMPORTANT NOTICE
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com.
For the purposes of our terms and conditions of sale, "Preliminary" or "Advanced" datasheets are non-final datasheets that include
but are not limited to datasheets marked as “Target”, “Advance”, “Product Preview”, “Preliminary Technical Data” and/or “Preproduction.” Products provided with any such datasheet are therefore subject to relevant terms and conditions associated with
"Preliminary" or "Advanced" designations. The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.;
and other companies in the Cirrus Logic group (collectively either “Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms
and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and
limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right to make changes to its
products and specifications or to discontinue any product or service. Customers should therefore obtain the latest version of relevant
information from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are
utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In
order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to
minimize inherent or procedural hazards. Cirrus Logic is not liable for applications assistance or customer product design. The
customer is solely responsible for its product design, including the specific manner in which it uses Cirrus Logic components, and
certain uses or product designs may require an intellectual property license from a third party. Features and operations described
herein are for illustrative purposes only and do not constitute a suggestion or instruction to adopt a particular product design or a
particular mode of operation for a Cirrus Logic component.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL
INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS LOGIC PRODUCTS
ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY,
AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL
APPLICATIONS. INCLUSION OF CIRRUS LOGIC PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT
THE CUSTOMER’S RISK AND CIRRUS LOGIC DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR
IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE,
WITH REGARD TO ANY CIRRUS LOGIC PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR
CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS LOGIC PRODUCTS IN CRITICAL APPLICATIONS,
CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS LOGIC, ITS OFFICERS, DIRECTORS, EMPLOYEES,
DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT
MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
This document is the property of Cirrus Logic, and you may not use this document in connection with any legal analysis concerning
Cirrus Logic products described herein. No license to any technology or intellectual property right of Cirrus Logic or any third party is
granted herein, including but not limited to any patent right, copyright, mask work right, or other intellectual property rights. Any
provision or publication of any third party’s products or services does not constitute Cirrus Logic’s approval, license, warranty or
endorsement thereof. Cirrus Logic gives consent for copies to be made of the information contained herein only for use within your
organization with respect to Cirrus Logic integrated circuits or other products of Cirrus Logic, and only if the reproduction is without
alteration and is accompanied by all associated copyright, proprietary and other notices and conditions (including this notice). This
consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for
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All statutory warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus Logic for
the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement
of patents or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design, and SoundClear are among the
trademarks of Cirrus Logic. Other brand and product names may be trademarks or service marks of their respective owners.
Copyright © 2004–2020 Cirrus Logic, Inc. All rights reserved.
26
Rev 4.3
WM8716
REVISION HISTORY
DATE
REV
ORIGINATOR
13/05/04
4.0
MT
CHANGES
PAGE
TOC added
2
Peak Soldering Temperature added
3
Order Codes:
27/07/06
4.1
LucyE
X added to WM8716EDS/WM8716EDS/R
3
Lead free product codes added
3
MSL nfo added
3
De-emphasis Filter response diagrams added
20
Package diagram updated to DM007.D
25
Updated Front page
1
Updated footers
13/09/06
21/07/08
CM
4.2
JMacD
Updated ordering information- removed 2 devices and changed 28pin to 28-lead
3
Updated package dimensions diagram to DM007.E
25
Updated Important Notice
26
Voltage range digital inputs and Master clock frequency added to
conditions table
4
Changed AVDD/AVSS to DVDD/DGND in Electrical Characteristics
5
Order Info: /V and /RV added to part number.
3
MSL updated from MSL1 to MSL2
20/01/20
Rev 4.3
4.3
PH
Ordering Information and Absolute Maximum Ratings updated – MSL
information removed
3
27
