WM8753CLGEFL/V

w WM8753L Hi-Fi and Telephony Dual CODEC DESCRIPTION FEATURES The WM8753L is a low power, high quality stereo CODEC with integrated Voice CODEC designed for portable digital telephony applications such as mobile phone, or headset with hi-fi playback capability.   The device integrates dual interfaces to two differentially connected microphones, and includes drivers for speakers, headphone and earpiece. External component requirements are reduced as no separate microphone or headphone amplifiers are required, and Cap-less connections can be made to all loads. Advanced on-chip digital signal processing performs tone control, Bass Boost and automatic level control for the microphone or line input through the ADC. The two ADCs may be used to support Voice noise cancellation in a partnering DSP, or for stereo recording. The WM8753L hi-fi DAC can operate as a master or a slave, with various master clock frequencies including 12 or 24MHz for USB devices, 13MHz or 19.2MHz for cellular systems, or standard 256fs rates like 12.288MHz and 24.576MHz. Internal PLLs generate all required clocks for both Voice and hi-fi converters. If audio system clocks already exist, the PLLs may be committed to alternative uses. The WM8753L operates at a nominal supply voltage of 2V, although the digital core can operate at voltages down to 1.42V to save power, and the maximum for all supplies is 3.6 Volts. Different sections of the chip can also be powered down under software control. 2 Hi-fi DAC: interfaced over I S type link Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96  DAC SNR 98dB, THD -84dB (‘A’ weighted @ 48kHz)  ADC SNR 95dB, THD -82dB (‘A’ weighted @ 48kHz)  On-chip Headphone Driver with cap-less output option - 40mW output power on 16 / 3.3V - with 16 load: SNR 90dB, THD –75dB - with 10k load: SNR 94dB, THD –90dB  On-chip speaker driver with 0.5W into 8R  Voice CODEC: interfaced over Voice interface  supports sample rates from 8ks/s to 48ks/s  ADC and DAC SNR 82dB, THD -74dB  Two Differential Microphone Interfaces - Dual ADCs support noise cancellation in external DSP - Programmable ALC / Noise Gate  Low-noise bias supplied for electret microphones Other Features  On-chip PLLs supporting 12, 13, 19.2MHz and other clocks  Cap-less connection options to headphones, earpiece, spkr.  Low power, low voltage - 1.8V to 3.6V (digital core: 1.42V to 3.6V) - power consumption 0.53fs -30 Group Delay dB 7/fs Voice DAC Filter Passband +/- 0.3dB 0 -14dB 0.414fs 0.5fs Passband Ripple +/-0.3 Stopband Stopband Attenuation dB 0.53fs f > 0.53fs -30 Group Delay dB 7/fs Table 75 Voice CODEC Digital Filter Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC High Pass Filter (HPMODE[1:0] = 00) (256fs, fs=48kHz) High Pass Filter Corner Frequency -3dB 3.7 -0.5dB 10.4 -0.1dB 21.6 Hz ADC High Pass Filter (HPMODE[1:0] = 01) (256fs, fs=16kHz) High Pass Filter Corner Frequency -3dB 82 -0.5dB 203 -0.1dB 341 Hz ADC High Pass Filter (HPMODE[1:0] = 10) (256fs, fs=8kHz) High Pass Filter Corner Frequency -3dB 82 -0.5dB 185 -0.1dB 272 Hz ADC High Pass Filter (HPMODE[1:0] = 11) (256fs, fs=8kHz) High Pass Filter Corner Frequency -3dB 170 -0.5dB 321 -0.1dB 415 Hz Table 76 ADC Highpass Filter Characteristics TERMINOLOGY 1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple – any variation of the frequency response in the pass-band region w PD, Rev 4.2, November 2011 80 WM8753L Production Data DAC FILTER RESPONSES 0.02 0 0.01 0 Response (dB) Response (dB) -20 -40 -60 -0.01 -0.02 -0.03 -0.04 -80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 Figure 32 DAC Digital Filter Frequency Response – Type 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 0.45 0.5 Figure 33 DAC Digital Filter Ripple – Type 0 0.02 0 0.01 0 Response (dB) Response (dB) -20 -40 -60 -0.01 -0.02 -0.03 -0.04 -80 -0.05 -0.06 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 0 3 Figure 34 DAC Digital Filter Frequency Response – Type 1 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 Figure 35 DAC Digital Filter Ripple – Type 1 0.02 0 0.01 0 Response (dB) Response (dB) -20 -40 -60 -0.01 -0.02 -0.03 -0.04 -80 -0.05 -0.06 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 Figure 36 DAC Digital Filter Frequency Response – Type 2 w 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 37 DAC Digital Filter Ripple – Type 2 PD, Rev 4.2, November 2011 81 WM8753L Production Data 0.25 0 0.2 0.15 -20 Response (dB) Response (dB) 0.1 -40 -60 0.05 0 -0.05 -0.1 -80 -0.15 -100 -0.25 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 38 DAC Digital Filter Frequency Response – Type 3 Figure 39 DAC Digital Filter Ripple – Type 3 ADC FILTER RESPONSES 0.04 0 0.03 0.02 Response (dB) Response (dB) -20 -40 -60 0.01 0 -0.01 -0.02 -80 -0.03 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 -0.04 3 0 Figure 40 ADC Digital Filter Frequency Response – Type 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 41 ADC Digital Filter Ripple – Type 0 0.02 0 0.01 0 Response (dB) Response (dB) -20 -40 -60 -0.01 -0.02 -0.03 -0.04 -80 -0.05 -0.06 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 Figure 42 ADC Digital Filter Frequency Response – Type 1 w 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 43 ADC Digital Filter Ripple – Type 1 PD, Rev 4.2, November 2011 82 WM8753L Production Data 0.25 0 0.2 0.15 -20 Response (dB) Response (dB) 0.1 -40 -60 0.05 0 -0.05 -0.1 -80 -0.15 -100 -0.25 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 Figure 44 ADC Digital Filter Frequency Response – Type 2 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 45 ADC Digital Filter Ripple – Type 2 0.25 0 0.2 0.15 -20 Response (dB) Response (dB) 0.1 -40 -60 0.05 0 -0.05 -0.1 -80 -0.15 -100 -0.25 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 46 ADC Digital Filter Frequency Response – Type 3 Figure 47 ADC Digital Filter Ripple – Type 3 w PD, Rev 4.2, November 2011 83 WM8753L Production Data VOICE FILTER RESPONSES VOICE DAC FILTER RESPONSES 2 0 0 -10 -2 -20 -4 Response (dB) Response (dB) 10 -30 -40 -50 -6 -8 -10 -60 -12 -70 -14 -16 -80 0 0.5 1 1.5 2 2.5 3 3.5 0 4 0.1 0.2 0.3 0.4 0.5 Frequency (Fs) Frequency (Fs) Figure 48 Voice DAC Digital Filter Frequency Response Figure 49 Voice DAC Digital Filter Frequency Response 0.4 0.3 Response (dB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 0.1 0.2 0.3 0.4 0.5 Frequency (Fs) Figure 50 Voice DAC Digital Filter Ripple VOICE ADC FILTER RESPONSES 2 0 0 -10 -2 -20 -4 Response (dB) Response (dB) 10 -30 -40 -50 -6 -8 -10 -12 -60 -14 -70 -16 -80 0 0.5 1 1.5 2 2.5 3 3.5 4 Frequency (Fs) Figure 51 Voice ADC Digital Filter Frequency Response 0 0.1 0.2 0.3 0.4 0.5 Frequency (Fs) Figure 52 Voice ADC Digital Filter Frequency Response 0.4 0.3 Response (dB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 0 0.1 0.2 0.3 0.4 0.5 Frequency (Fs) Figure 53 Voice ADC Digital Filter Ripple w PD, Rev 4.2, November 2011 84 WM8753L Production Data DE-EMPHASIS FILTER RESPONSES 0.4 0 0.3 -2 Response (dB) Response (dB) 0.2 -4 -6 0.1 0 -0.1 -0.2 -8 -0.3 -0.4 -10 0 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 0 16000 Figure 54 De-emphasis Frequency Response (32kHz) 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 16000 Figure 55 De-emphasis Error (32kHz) 0.4 0 0.3 -2 Response (dB) Response (dB) 0.2 -4 -6 0.1 0 -0.1 -0.2 -8 -0.3 -0.4 -10 0 5000 10000 Frequency (Fs) 15000 0 20000 Figure 56 De-emphasis Frequency Response (44.1kHz) 5000 10000 Frequency (Fs) 15000 20000 15000 20000 Figure 57 De-emphasis Error (44.1kHz) 0.4 0 0.3 -2 Response (dB) Response (dB) 0.2 -4 -6 0.1 0 -0.1 -0.2 -8 -0.3 -0.4 -10 0 5000 10000 Frequency (Fs) 15000 Figure 58 De-emphasis Frequency Response (48kHz) w 20000 0 5000 10000 Frequency (Fs) Figure 59 De-emphasis Error (48kHz) PD, Rev 4.2, November 2011 85 WM8753L Production Data HIGHPASS FILTER The WM8753 has a selectable digital highpass filter in the ADC filter path to remove DC offsets. HPMODE[1:0] = 00 The filter response is characterised by the following polynomial: -1 H(z) = 1–z 1 – 0.9995z -1 5 Response (dB) 0 -5 -10 -15 0.0000 0.0005 0.0010 0.0015 0.0020 Frequency (Fs) Figure 60 ADC Highpass Filter Response, HPMODE[1:0] = 00 HPMODE[1:0] = 01 The filter response is characterised by the following polynomial: H(z) = -1 1–z 1 – 0.96875z -1 5 0 Response (dB) -5 -10 -15 -20 -25 0.00 0.01 0.02 0.03 0.04 0.05 Freque ncy (Fs) Figure 61 ADC Highpass Filter Response, HPMODE[1:0] = 01 w PD, Rev 4.2, November 2011 86 WM8753L Production Data HPMODE[1:0] = 10 The filter response is characterised by the following polynomial: H(z) = -1 1–z -1 1 – 0.9375z 5 0 Response (dB) -5 -10 -15 -20 -25 -30 0.00 0.01 0.02 0.03 0.04 0.05 Frequency (Fs) Figure 62 ADC Highpass Filter Response, HPMODE[1:0] = 10 HPMODE[1:0] = 11 The filter response is characterised by the following polynomial: H(z) = -1 1–z 1 – 0.875z -1 5 0 Response (dB) -5 -10 -15 -20 -25 -30 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 Freque ncy (Fs) Figure 63 ADC Highpass Filter Response, HPMODE[1:0] = 11 w PD, Rev 4.2, November 2011 87 Production Data WM8753L APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 64 Recommended External Components Diagram w PD, Rev 4.2, November 2011 88 WM8753L Production Data MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS To minimise any pop or click noise when the system is powered up or down, the following procedures are recommended. POWER SUPPLIES The ideal way to apply power to the WM8753 is to all supplies at the same time. This is not always possible in many designs due to supplies being sourced from different voltage regulators or direct from batteries. In these situations, it is recommended that supplies are applied in the following order. 1. DCVDD, DBVDD and PVDD (if not at the same time, any order may be used) 2. AVDD 3. HPVDD and SPKRVDD (if not at the same time, any order may be used) Supplies may be removed in any order. However, it is recommended that HPVDD and SPKRVDD supplies be removed last. POWER UP  Switch on power supplies. By default the WM8753L is in Standby Mode, the DAC is digitally muted and the Audio Interface and Outputs are all OFF  Enable Vmid and VREF. Allow VREF to settle. The settling time depends on the value of the capacitor connected at VMID, and the size of the resistors selected using VMIDSEL ( = RC).  Enable DACs, etc. as required.  Enable outputs as required.  Set DACMU = 0 to un-mute the audio DACs. POWER DOWN (MINIMUM NOISE)  Set DACMU = 1 to mute the audio DACs.  Disable all Outputs.  Disable VREF and VMIDSEL.  Switch off the power supplies POWER DOWN (QUICKEST MIDRAIL DISCHARGE)  Set DACMU = 1 to mute the audio DACs.  Disable VREF and VMIDSEL.  Switch off the power supplies. A choice of two power down sequences have been recommended. The first is completely noise free with the disadvantage that the mid-rail voltage can take some time to discharge due to the large amount of capacitance attached to the outputs. The second offers a quick discharge of the output capacitors but as the outputs have not been powered down it does allow for the small possibility that noise may be heard during power down. w PD, Rev 4.2, November 2011 89 WM8753L Production Data PACKAGE DIAGRAM DM103.A FL: 48 PIN QFN PLASTIC PACKAGE 7 X 7 X 0.9 mm BODY, 0.50 mm LEAD PITCH D2 SEE DETAIL 1 D D2/2 48 37 L 36 INDEX AREA (D/2 X E/2) 1 EXPOSED GROUND 6 PADDLE E2/2 E2 E SEE DETAIL 2 12 25 24 13 e aaa C 2X b 2X BOTTOM VIEW aaa C TOP VIEW ccc C (A3) A 0.08 C SEATING PLANE SIDE VIEW A1 DETAIL 1 DETAIL 2 DETAIL 3 Datum W 45° T (A3) b Exposed lead EXPOSED GROUND PADDLE Terminal Tip e/2 0.30mm G H 1 C e Half etch tie bar DETAIL 3 Symbols A A1 A3 b D D2 E E2 e G H L T W aaa bbb ccc REF Dimensions (mm) NOM MAX 0.90 1.00 0.05 0.02 0.20 REF 0.18 0.25 0.30 7.00 BSC 5.55 5.65 5.75 7.00 BSC 5.55 5.65 5.75 0.5 BSC 0.20 0.10 0.50 0.30 0.4 0.103 0.15 Tolerances of Form and Position 0.15 0.10 0.10 MIN 0.80 0 NOTE 1 JEDEC, MO-220, VARIATION VKKD-4 NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. ALL DIMENSIONS ARE IN MILLIMETRES 3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-002. 4. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 5. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. w PD, Rev 4.2, November 2011 90 WM8753L Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. 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ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w PD, Rev 4.2, November 2011 91 WM8753L Production Data REVISION HISTORY DATE REV ORIGINATOR CHANGES 07/10/11 4.1 JMacD Order codes updated from WM8753LGEFL/V and WM8753LGEFL/RV to WM8753CLGEFL/V, WM8753CLGEFL/RV, to reflect change to copper wire bonding. WM8753LGEB/V and WM8753LGEB/RV removed. 07/10/11 4.1 JMacD WM8753LGEB and BGA reference removed from datasheet. 07/10/11 4.1 JMacD BGA Package Diagram removed from datasheet. 07/10/11 4.1 JMacD QFN Package Diagram changed to DM103.A 07/11/11 4.2 JMacD Corrected reference to WM8753CLGEFL/V and WM8753CLGEFL/RV which was shown incorrectly in Revision History, Rev 4.1. w PD, Rev 4.2, November 2011 92