WM8962ECSN/R

WM8962 Ultra-Low Power Stereo CODEC with Audio Enhancement DSP, 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers DESCRIPTION FEATURES The WM8962 is a low power, high performance stereo CODEC designed for portable digital audio applications.  DAC SNR 98dB (‘A’ weighted), THD -84dB at 48kHz, 1.8V  ADC SNR 94dB (‘A’ weighted), THD -85dB at 48kHz, 1.8V An integrated charge pump provides a ground referenced output which removes the need for DC-blocking capacitors on the headphone outputs, and uses the Wolfson ‘Class-W’ amplifier techniques - incorporating an innovative dual-mode charge pump architecture - to optimise efficiency and power consumption during playback. A DC Servo is used to reduce DC ground offsets. This improves power consumption and minimises pops and clicks.  Stereo Class D Speaker Driver Stereo class D speaker drivers provide 1W per channel into 8 loads, or 2W mono into a 4 load, with a 5V supply. Low leakage, excellent PSRR and pop/click suppression mechanisms also allow direct battery connection to the speaker supply. Flexible speaker boost settings allow speaker output power to be maximised while minimising other analogue supply currents. Control sequences for audio path setup can be pre-loaded and executed by an integrated sequencer to reduce software driver development and eliminate pops and clicks via SilentSwitch™ technology. Flexible input configuration: four stereo inputs or eight mono inputs on Left or Right ADC, with a complete analogue (four single-ended stereo inputs) and digital microphone interface. External component requirements are drastically reduced as no separate microphone, speaker or headphone amplifiers are required. Advanced on-chip digital signal processing performs automatic level control for the microphone or line input. Stereo 24-bit sigma-delta ADCs and DACs are used with low power over-sampling digital interpolation and decimation filters and a flexible digital audio interface. A programmable audio enhancement DSP is included with multiple preset algorithms. Virtual Surround Sound widens the stereo speaker audio image, HD Bass enhances low frequencies, and ReTuneTM flattens the frequency response of the speaker or microphone path. A configurable DSP includes additional functions such as 3D widening for recording, a 5-band parametric EQ and Dynamic Range Controller. Two high performance PLLs and one Frequency Locked Loop (FLL) are integrated to enable the user to clock a full audio system. The WM8962 operates at analogue supply voltages down to 1.7V, although the digital supplies can operate at voltages down to 1.62V to save power. The speaker supply can operate at up to 5.5V. Unused functions can be disabled using software control to save power. The WM8962 is supplied in a very small W-CSP package, ideal for use in hand-held and portable systems. http://www.cirrus.com - 1W per channel into 8 BTL speakers - 2W mono into 4 BTL speakers - Flexible internal switching clock  Wolfson ‘Class-W’ ultra-low power headphone driver - Up to 31mW per channel output power at 1% THD+N - Ground Referenced - Low offset (+/- 1.2mV) - Pop and click suppression - Control sequencer for pop-minimised power-up/down - Single register write for default start-up sequence  Microphone Interface - Single ended four stereo analogue input - Integrated low noise MICBIAS - Digital microphone interface - Programmable ALC / Limiter and Noise Gate  Programmable Audio Enhancement DSP with Presets - Virtual Surround Sound - HD Bass - ReTuneTM  Fixed Audio Processing DSP - 3D stereo widening - 5-band Parametric EQ - Dynamic range controller - Beep generator   Two integrated PLLs enable clocking of full audio system Low Power Consumption - 7.7mW headphone playback - 8.3mW analogue record mode  Low Supply Voltages - Analogue 1.7V to 2.0V (Speaker supply up to 5.5V) - Charge pump 1.7V to 2.0V - MIC bias amp supply 1.7V to 3.6V - Digital 1.62V to 2.0V  2-wire I2C and 3- or 4-wire SPI serial control interface  Standard sample rates from 8kHz to 96kHz  W-CSP, 3.6x3.9mm 49-pin APPLICATIONS    Portable gaming, Voice recorders Mobile multimedia Stereo DSC-Camcorder Copyright  Cirrus Logic, Inc., 2009–2016 (All Rights Reserved) Rev 4.4 SEP ‘16 2 MICBIAS IN2R IN3R IN1R IN4R IN2L IN3L IN1L IN4L VMID VMID 50k -23.25 to +24dB, 0.75dB steps + + -23.25 to +24dB, 0.75dB steps WM8962 50k ADCREF, DACREF EFS FLL ADC + GPIOs ADC + DCVDD CONTROL INTERFACE Digital Mic Interface Digital Volume Mono Mix ALC ADC Digital Filters DGND T-Loopback mixer 5-Band EQ DRC 2nd order HPF VSS HD Bass ReTuneTM DAC Signal Enhancement A-law and u-law support DIGITAL AUDIO INTERFACE 2nd order HPF 1st order LPF/HPF 3D Surround DF1 Filter ReTuneTM DRC ADC Signal Enhancement DBVDD DAC Digital Filters Digital Volume Oscillator, FLL, 2 x PLL DAC DAC SPKVDD1 SPKGND1 AVDD supply to FLL + + + + SPKVDD2 CHARGE PUMP -68dB to 6dB 1dB steps, mute -68dB to 6dB 1dB steps, mute -68dB to 6dB 1dB steps, mute -68dB to 6dB 1dB steps, mute SPKGND2 0dB to 9dB 1.5dB steps, plus 12dB CLASS D -7 to 0dB 1dB steps -7 to 0dB 1dB steps CLASS D 0dB to 9dB 1.5dB steps, plus 12dB CPVOUTN CPVOUTP SPKOUTRP SPKOUTRN HPOUTR HPOUTFB HPOUTL SPKOUTLN SPKOUTLP Capless HP WM8962 BLOCK DIAGRAM CPVDD CPCB CPCA CPGND PLLGND PLLVDD CLKOUT3/GPIO3 CLKOUT2/GPIO2 XTO MCLK/XTI CLKOUT5 BCLK DACDAT LRCLK ADCDAT CS/GPIO6 SDA SCLK CIFMODE GPIO5 AVDD VMIDC AGND MICVDD Rev 4.4 WM8962 TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS .................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 2 TABLE OF CONTENTS......................................................................................... 3 PIN CONFIGURATION .......................................................................................... 7 ORDERING INFORMATION .................................................................................. 7 PIN DESCRIPTION ................................................................................................ 8 ABSOLUTE MAXIMUM RATINGS ........................................................................ 9 RECOMMENDED OPERATING CONDITIONS ..................................................... 9 ELECTRICAL CHARACTERISTICS ................................................................... 10 TERMINOLOGY ............................................................................................................. 20 TYPICAL PERFORMANCE ................................................................................. 21 TYPICAL POWER CONSUMPTION .............................................................................. 21 SIGNAL TIMING REQUIREMENTS .................................................................... 25 MASTER CLOCK ........................................................................................................... 25 AUDIO INTERFACE TIMING ......................................................................................... 26 DIGITAL MICROPHONE (DMIC) INTERFACE TIMING ............................................................................ 26 DIGITAL AUDIO INTERFACE - MASTER MODE ..................................................................................... 27 DIGITAL AUDIO INTERFACE - SLAVE MODE ......................................................................................... 28 DIGITAL AUDIO INTERFACE - TDM MODE ............................................................................................. 29 CONTROL INTERFACE TIMING ................................................................................... 30 2-WIRE (I2C) CONTROL MODE ............................................................................................................... 30 3-WIRE (SPI) CONTROL MODE ............................................................................................................... 31 4-WIRE (SPI) CONTROL MODE ............................................................................................................... 32 POWER ON RESET TIMING ......................................................................................... 33 DEVICE DESCRIPTION ...................................................................................... 36 INTRODUCTION ............................................................................................................ 36 INPUT SIGNAL PATH .................................................................................................... 37 MICROPHONE INPUT CONNECTION ..................................................................................................... 38 LINE INPUT CONNECTION ...................................................................................................................... 38 MICROPHONE BIAS CONTROL .............................................................................................................. 39 MICBIAS CURRENT DETECT .................................................................................................................. 39 MICBIAS CURRENT DETECT FILTERING............................................................................................... 40 MICROPHONE HOOK SWITCH DETECTION .......................................................................................... 42 INPUT PGA ENABLE ................................................................................................................................ 43 INPUT PGA CONFIGURATION ................................................................................................................ 44 INPUT PGA VOLUME CONTROL ............................................................................................................. 45 INPUT MIXER ENABLE............................................................................................................................. 46 INPUT MIXER CONFIGURATION AND VOLUME CONTROL .................................................................. 47 AUTOMATIC LEVEL CONTROL (ALC) ......................................................................... 49 LIMITER MODE ......................................................................................................................................... 51 ALC GAIN CONTROL................................................................................................................................ 53 ALC DYNAMIC CHARACTERISTICS........................................................................................................ 54 PEAK LIMITER .......................................................................................................................................... 56 ALC NOISE GATE ..................................................................................................................................... 57 ALC STATUS READBACK ........................................................................................................................ 61 DIGITAL MICROPHONE INTERFACE .......................................................................... 62 ANALOGUE TO DIGITAL CONVERTER (ADC) ............................................................ 65 ADC CLOCKING CONTROL ..................................................................................................................... 65 ADC DIGITAL VOLUME CONTROL .......................................................................................................... 66 Rev 4.4 3 WM8962 ADC OVERSAMPLING RATIO (OSR)....................................................................................................... 68 ADC MONOMIX ......................................................................................................................................... 68 DSP SIGNAL ENHANCEMENTS ................................................................................... 69 ENABLE SEQUENCE - ENHANCEMENTS INITIALLY DISABLED .......................................................... 69 ENABLE / DISABLE SEQUENCE - ENHANCEMENTS INITIALLY ENABLED ......................................... 70 DISABLE ALL SOUND ENHANCEMENTS SEQUENCE .......................................................................... 71 UPDATE / READBACK SEQUENCE - ENHANCEMENTS INITIALLY ENABLED .................................... 72 UPDATE / READBACK SEQUENCE - ENHANCEMENTS INITIALLY DISABLED ................................... 73 ADC SIGNAL PATH ENHANCEMENTS ........................................................................ 74 ADC SECOND ORDER HIGH-PASS FILTER ........................................................................................... 74 LOW-PASS / HIGH-PASS FILTER (LPF/HPF) .......................................................................................... 76 3D SURROUND ........................................................................................................................................ 77 DF1 FILTER............................................................................................................................................... 80 ADC RETUNE ........................................................................................................................................... 82 DYNAMIC RANGE CONTROL (DRC) ....................................................................................................... 83 DIGITAL MIXING ............................................................................................................ 91 DIGITAL MIXING PATHS .......................................................................................................................... 91 DIGITAL SIDETONE.................................................................................................................................. 92 T-LOOPBACK ............................................................................................................................................ 94 DAC SIGNAL PATH ENHANCEMENTS ........................................................................ 96 5-BAND EQ ............................................................................................................................................... 96 DYNAMIC RANGE CONTROL (DRC) ..................................................................................................... 100 DAC SECOND ORDER HIGH-PASS FILTER ......................................................................................... 101 VIRTUAL SURROUND SOUND (VSS).................................................................................................... 102 HD BASS ................................................................................................................................................. 103 DAC RETUNE ......................................................................................................................................... 104 DIGITAL-TO-ANALOGUE CONVERTER (DAC) ......................................................... 105 DAC CLOCKING CONTROL ................................................................................................................... 106 DAC DIGITAL VOLUME CONTROL ........................................................................................................ 106 DAC SOFT MUTE AND UN-MUTE ......................................................................................................... 108 DAC AUTO-MUTE ................................................................................................................................... 110 DAC MONO MIX ...................................................................................................................................... 110 DAC DE-EMPHASIS................................................................................................................................ 111 DAC OVERSAMPLING RATIO (OSR)..................................................................................................... 111 DIGITAL BEEP GENERATOR ..................................................................................... 112 OUTPUT SIGNAL PATH .............................................................................................. 113 OUTPUT SIGNAL PATHS ENABLE ........................................................................................................ 114 SPEAKER OUTPUT PATHS ........................................................................................ 115 SPEAKER MIXER CONTROL ................................................................................................................. 115 SPEAKER OUTPUT PGA CONTROL ..................................................................................................... 118 SPEAKER OUTPUT CONFIGURATIONS ............................................................................................... 120 HEADPHONE OUTPUT PATHS .................................................................................. 123 HEADPHONE SIGNAL PATHS ENABLE ................................................................................................ 123 HEADPHONE MIXER CONTROL ........................................................................................................... 125 HEADPHONE OUTPUT PGA CONTROL ............................................................................................... 128 HEADPHONE OUTPUT CONFIGURATIONS ......................................................................................... 129 CHARGE PUMP ........................................................................................................... 130 DC SERVO ................................................................................................................... 132 DC SERVO ENABLE AND START-UP.................................................................................................... 132 DC SERVO ACTIVE MODES .................................................................................................................. 134 REFERENCE VOLTAGES AND BIAS CONTROL ...................................................... 135 ANALOGUE REFERENCE AND MASTER BIAS .................................................................................... 135 INPUT SIGNAL PATH BIAS CONTROL SETTINGS ............................................................................... 135 OUTPUT SIGNAL PATH BIAS CONTROL SETTINGS ........................................................................... 136 4 Rev 4.4 WM8962 DIGITAL AUDIO INTERFACE ...................................................................................... 137 MASTER AND SLAVE MODE OPERATION ........................................................................................... 138 OPERATION WITH TDM ......................................................................................................................... 138 BCLK FREQUENCY ................................................................................................................................ 139 AUDIO DATA FORMATS (NORMAL MODE) .......................................................................................... 139 AUDIO DATA FORMATS (TDM MODE).................................................................................................. 141 DIGITAL AUDIO INTERFACE CONTROL ................................................................... 143 AUDIO INTERFACE TRI-STATE ............................................................................................................. 144 BCLK AND LRCLK CONTROL ................................................................................................................ 144 COMPANDING ........................................................................................................................................ 145 LOOPBACK ............................................................................................................................................. 147 CLOCKING AND SAMPLE RATES ............................................................................. 148 SYSCLK CONTROL ................................................................................................................................ 149 AUTOMATIC CLOCKING CONFIGURATION ......................................................................................... 151 DSP, ADC, DAC CLOCK CONTROL....................................................................................................... 153 CLASS D, 256K, DC SERVO CLOCK CONTROL ................................................................................... 154 OPCLK CONTROL .................................................................................................................................. 155 TOCLK, DBCLK CONTROL .................................................................................................................... 155 BCLK AND LRCLK CONTROL ................................................................................................................ 156 CONTROL INTERFACE CLOCKING ...................................................................................................... 156 INTERNAL / EXTERNAL CLOCK GENERATION........................................................ 157 START-UP OPTIONS FOR INTERNAL / EXTERNAL CLOCK GENERATION ....................................... 158 INTERNAL OSCILLATOR CONTROL ..................................................................................................... 159 CLKOUT CONTROL ................................................................................................................................ 161 FREQUENCY LOCKED LOOP (FLL) ...................................................................................................... 163 FREE-RUNNING FLL CLOCK ................................................................................................................. 167 EXAMPLE FLL CALCULATION............................................................................................................... 168 PHASE LOCKED LOOP (PLL) ................................................................................................................ 169 EXAMPLE PLL CALCULATION .............................................................................................................. 173 GENERAL PURPOSE INPUT/OUTPUT (GPIO) .......................................................... 174 INTERRUPTS .............................................................................................................. 178 CONTROL INTERFACE .............................................................................................. 183 SELECTION OF CONTROL INTERFACE MODE ................................................................................... 183 2-WIRE (I2C) CONTROL MODE ............................................................................................................. 184 3-WIRE (SPI) CONTROL MODE ............................................................................................................. 187 4-WIRE (SPI) CONTROL MODE ............................................................................................................. 188 CONTROL WRITE SEQUENCER ............................................................................... 189 INITIATING A SEQUENCE...................................................................................................................... 189 PROGRAMMING A SEQUENCE ............................................................................................................ 190 DEFAULT SEQUENCES ......................................................................................................................... 193 THERMAL SHUTDOWN .............................................................................................. 197 SOFTWARE RESET AND CHIP ID ............................................................................. 198 REGISTER MAP ................................................................................................ 199 REGISTER BITS BY ADDRESS .................................................................................. 208 DIGITAL FILTER CHARACTERISTICS ............................................................ 273 DAC FILTER RESPONSES ......................................................................................... 274 ADC FILTER RESPONSES ......................................................................................... 276 ADC HIGH PASS FILTER RESPONSES ................................................................................................ 277 DE-EMPHASIS FILTER RESPONSES ........................................................................ 278 APPLICATIONS INFORMATION ...................................................................... 279 ANALOGUE INPUT PATHS .................................................................................................................... 279 MICROPHONE BIAS CIRCUIT ............................................................................................................... 279 CHARGE PUMP COMPONENTS ........................................................................................................... 281 RECOMMENDED EXTERNAL COMPONENTS DIAGRAM .................................................................... 282 Rev 4.4 5 WM8962 PCB LAYOUT CONSIDERATIONS ............................................................................. 284 MIC DETECTION SEQUENCE USING MICBIAS CURRENT ..................................... 285 PACKAGE DIMENSIONS .................................................................................. 287 PACKAGE DIAGRAM FOR DEVICES MARKED KBC ................................................ 287 PACKAGE DIAGRAM FOR DEVICES MARKED BCA HN8 ........................................ 288 IMPORTANT NOTICE ....................................................................................... 289 REVISION HISTORY ......................................................................................... 290 6 Rev 4.4 WM8962 PIN CONFIGURATION 1 2 3 4 5 6 7 A SPKOUTLP SPKVDD1 MICVDD MICBIAS HPOUTR CPVOUTP CPVOUTN B SPKGND1 SPKOUTRP SPKOUTLN HPOUTFB HPOUTL CPCA CPCB C SPKGND2 SPKVDD2 SPKOUTRN IN1L VMIDC CPVDD CPGND D DACDAT ADCDAT LRCLK IN1R IN2L AVDD AGND TOP VIEW – WM8962 E BCLK SDA CS/GPIO6 CLKOUT2/ GPIO2 IN2R IN4L IN4R F SCLK CIFMODE DGND CLKOUT3/ GPIO3 IN3L IN3R XTO G GPIO5 DCVDD DBVDD PLLVDD PLLGND CLKOUT5 MCLK/XTI ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8962ECS/R -40C to +85C 49-ball CSP, 3.6 x 3.9 mm, Pb-free, tape and reel, Backside-coated. MSL1 260°C WM8962ECSN/R -40C to +85C 49-ball CSP, 3.6 x 3.9 mm, Pb-free, tape and reel. MSL1 260°C Note: Reel quantity = 5,000 Rev 4.4 7 WM8962 PIN DESCRIPTION 8 PIN NO NAME TYPE A1 SPKOUTLP Analogue Output DESCRIPTION A2 SPKVDD1 Supply Supply for left speaker drivers A3 MICVDD Supply Microphone bias amp supply A4 MICBIAS Reference A5 HPOUTR Analogue Output A6 CPVOUTP Supply Charge pump positive supply (powers HPOUTL, HPOUTR) A7 CPVOUTN Supply Charge pump negative supply (powers HPOUTL, HPOUTR) B1 SPKGND1 Supply Ground for left speaker drivers B2 SPKOUTRP Analogue Output Right speaker positive output B3 SPKOUTLN Analogue Output Left speaker negative output B4 HPOUTFB Analogue Input B5 HPOUTL Analogue Output B6 CPCA Analogue Input Charge pump fly-back capacitor pin B7 CPCB Analogue Input Charge pump fly-back capacitor pin C1 SPKGND2 Supply Ground for right speaker drivers C2 SPKVDD2 Supply Supply for right speaker drivers C3 SPKOUTRN Analogue Output Right speaker negative output C4 IN1L Analogue Input C5 VMIDC Reference C6 CPVDD Supply Charge pump power supply Charge pump ground (return path for CPVDD) Left speaker positive output Microphone bias Right output (Line or headphone) HPOUTL/R ground loop noise rejection feedback Left output (Line or headphone) Left channel single-ended input 1 Mid-rail voltage (AVDD/2) - (requires decoupling capacitor) C7 CPGND Supply D1 DACDAT Digital Input DAC digital audio data D2 ADCDAT Digital Output ADC digital audio data D3 LRCLK Digital Input / Output D4 IN1R Analogue Input Right channel single-ended input 1 D5 IN2L Analogue Input Left channel single-ended input 2 D6 AVDD Supply Analogue supply D7 AGND Supply Analogue ground (return path for AVDD and MICVDD) E1 BCLK Digital Input / Output Audio interface bit clock E2 SDA Digital Input / Output Control interface data input / 2-wire acknowledge output E3 CS ¯¯ /GPIO6 Digital Input / Output CS ¯¯ input / Digital Microphone input / General purpose input / output E4 CLKOUT2/GPIO2 Digital Output E5 IN2R Analogue Input Right channel single-ended input 2 E6 IN4L Analogue Input Left channel single-ended input 4 E7 IN4R Analogue Input Right channel single-ended input 4 F1 SCLK Digital Input Control interface clock input F2 CIFMODE Digital Input Selects 2-wire or 3 / 4-wire control wire interface F3 DGND Supply F4 CLKOUT3/GPIO3 Digital Output F5 IN3L Analogue Input Left channel single-ended input 3 F6 IN3R Analogue Input Right channel single-ended input 3 F7 XTO Analogue Output G1 GPIO5 Digital Input / Output G2 DCVDD Supply Digital Core Supply G3 DBVDD Supply Digital Buffer Supply G4 PLLVDD Supply PLL Supply PLL Ground Audio interface left / right clock PLL2 Clock output / General purpose input / output Digital ground PLL3 / FLL Clock output / GPIO xtal output Digital Microphone Input / General purpose input / output Important: See page 174 for start-up requirements. G5 PLLGND Supply G6 CLKOUT5 Analogue Output FLL / Oscillator Clock output G7 MCLK / XTI Digital Input Master clock input / xtal input Rev 4.4 WM8962 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Cirrus tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at 48kHz 0000 0.104ms 0.020ms 0.104ms 0001 0.208ms 0.041ms 0.208ms 0010 0.416ms 0.082ms 0.416ms 0011 0.832ms 0.164ms 0.832ms 0100 1.66ms 0.328ms 1.66ms 0101 3.33ms 0.655ms 3.33ms 0110 6.66ms 1.31ms 6.66ms 0111 13.3ms 2.62ms 13.3ms 1000 26.6ms 5.24ms 26.6ms 1001 53.2ms 10.5ms 53.2ms 1010 106ms 21.0ms 106ms Table 17 ALC Attack Rate (Time per 1.5dB Gain Step) PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dBFS), the PGA gain is ramped down at the maximum attack rate (as when ALC_ATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is in Active Mode, but has no effect when ALC is in Monitor Mode. Note that if ALC_ATK = 0000, then the peak limiter makes no difference to the operation of the ALC; ALC_ATK is already at 0000 and the ALC is therefore already ramping down at its maximum rate. The Peak Limiter is designed to prevent clipping when long attack times are used. 56 Rev 4.4 WM8962 ALC NOISE GATE To avoid ‘noise pumping’ when the signal is very quiet and consists mainly of noise, the ALC function has a noise gate function. This prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, ALC_NGATE_THR. The noise gate cuts in when: Signal level at ADC [dB] < ALC_NGATE_THR [dB] + PGA gain [dB] + Input Mixer gain [dB] This is equivalent to: Signal level at input pin [dB] < ALC_NGATE_THR [dB] Whenever the signal level at the input pins drops below the Noise Gate Threshold (ALC_NGATE_THR), the ALC Noise Gate is activated in one of three modes. The Noise Gate Mode is selected by ALC_NGATE_MODE. As soon as the peak input signal level drops below the Noise Gate Threshold, control of the PGA gain is passed from the ALC to the Noise Gate system. The Noise Gate modes are:  Mode 00: The PGA Gain remains static while the input signal is below the ALC Noise Gate Threshold (ALC_NGATE_THR) level. As soon as the input signal rises back above the ALC Noise Gate Threshold, PGA gain is once again controlled by the ALC.  Mode 01: The PGA Gain is muted while the input signal is below the ALC Noise Gate Threshold (ALC_NGATE_THR) level. The muting of the PGA Gain is immediate (a hard mute), and is performed by setting ADCL_VOL or ADCR_VOL or both to zero. Note that with Mode 01, it is the ADCL_VOL and ADCR_VOL registers that are muted, and not the INL_VOL and INR_VOL registers that are changed in the other modes. As soon as the input signal rises back above the ALC Noise Gate Threshold, ADCL_VOL and ADCR_VOL are restored to their previous values. Again this is immediate (a hard unmute).  Mode 10: The PGA Gain is either ramped down to the ALC_NGATE_GAIN at a rate determined by ALC_NGATE_ATK, or ramped up to the ALC_NGATE_GAIN level at a rate determined by ALC_NGATE_DCY. As soon as the input signal rises back above the ALC Noise Gate Threshold, PGA gain is once again controlled by the ALC. The PGA gain is ramped up (or down) at a rate determined by ALC_DCY (or ALC_ATK). The noise gate control register is described in Table 18. The ALC_NGATE_THR variable sets the Noise Gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 1.5dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set–up of the function. Note that the Noise Gate only works in conjunction with the ALC function, and always operates on the same channel(s) as the ALC (left, right, both, or none). Rev 4.4 57 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R19 (13h) ALC3 12:10 ALC_NGATE_GAIN [2:0] 111 Noise Gate Gain level. This is the PGA gain level used within the ALC Noise Gate function. 000 = -23.25dB 001 = -18dB 010 = -12dB 011 = -6dB 100 = 0dB 101 = +6dB 110 = +12dB 111 = +18dB R20 (14h) Noise Gate 15:12 ALC_NGATE_DCY [3:0] 0011 Sets the Noise Gate Gain Decay Rate (time taken to ramp up to the ALC_NGATE_GAIN level), measured in time per 1.5dB step. If ALC_MODE = 0 0000 = 0.41ms / step 0001 = 0.82ms / step …doubling with each step to… 1010 = 420ms / step 1011 = 840ms / step 1100 to 1111 = Reserved If ALC_MODE = 1 0000 = 0.082ms / step 0001 = 0.164ms / step …doubling with each step to… 1010 = 83.9ms / step 1011 = 168ms / step 1100 to 1111 = Reserved Note that when 88.2kHz or 96kHz sample rate is selected, the Noise Gate Gain Decay time is defined as for the ALC_MODE=0 case above. See Table 16 for further details. 58 Rev 4.4 WM8962 REGISTER ADDRESS BIT 11:8 LABEL DEFAULT DESCRIPTION 0010 Sets the Gain Attack Rate (time taken to ramp down to the ALC_NGATE_GAIN level), measured in time per 1.5dB step. ALC_NGATE_ATK [3:0] If ALC_MODE = 0 0000 = 0.10ms / step 0001 = 0.21ms / step …doubling with each step to… 1010 = 106ms / step 1011 to 1111 = Reserved If ALC_MODE = 1 0000 = 0.020ms / step 0001 = 0.041ms / step …doubling with each step to… 1010 = 21.0ms / step 1011 to 1111 = Reserved Note that when 88.2kHz or 96kHz sample rate is selected, the Noise Gain Attack time is defined as for the ALC_MODE=0 case above. See Table 17 for further details. 7:3 ALC_NGATE_THR [4:0] 2:1 ALC_NGATE_MODE [1:0] 0 ALC_NGATE_ENA 0_0000 (-76.5dBFS) 00 0 Noise Gate Threshold. If the input signal falls below this level, the Noise Gate function is triggered. -76.5dB to -30dB in 1.5dB steps. See Table 19 for further details. Noise gate mode 00 = Hold PGA gain static when noise gate triggers 01 = Mute ADC output immediately when noise gate triggers. 10 = Ramp PGA Gain to ADC_NGATE_GAIN level when Noise Gate triggers. 11 = Reserved Noise Gate function enable 0 = Disable 1 = Enable Table 18 ALC Noise Gate Control Rev 4.4 59 WM8962 ALC_NGATE_THR [4:0] THRESHOLD (dBFS) 0_0000 -76.5 0_0001 -75.0 0_0010 -73.5 0_0011 -72.0 0_0100 -70.5 0_0101 -69.0 0_0110 -67.5 0_0111 -66.0 0_1000 -64.5 0_1001 -63.0 0_1010 -61.5 0_1011 -60.0 0_1100 -58.5 0_1101 -57.0 0_1110 -55.5 0_1111 -54.0 1_0000 -52.5 1_0001 -51.0 1_0010 -49.5 1_0011 -48.0 1_0100 -46.5 1_0101 -45.0 1_0110 -43.5 1_0111 -42.0 1_1000 -40.5 1_1001 -39.0 1_1010 -37.5 1_1011 -36.0 1_1100 -34.5 1_1101 -33.0 1_1110 -31.5 1_1111 -30.0 Table 19 ALC Noise Gate Threshold (ALC_NGATE_THR) Settings 60 Rev 4.4 WM8962 ALC STATUS READBACK There are five ALC status registers that provide monitoring of the Automatic Level Control (ALC). These are particularly useful when ALC is in Monitor Mode (ALC_INACTIVE_ENA = 1), and the PGA Gains are not being changed by the ALC. These five Register bits and their settings are summarised in Table 20. REGISTER ADDRESS R18 (12h) ALC2 BIT LABEL DEFAULT DESCRIPTION 15 ALC_LOCK_ST S 0 Readback of the ALC Lock Status. Set when ADC signal = ALC_LVL 14 ALC_THRESH_ STS 0 Readback of the ALC Threshold Level status (when ALC_LOCK_STS = 0) 0 = ADC signal < ALC_LVL 1 = ADC signal > ALC_LVL 13 ALC_SAT_STS 0 Readback of the ALC saturation status. 0 = ADC signal = ALC_LVL 1 = ADC signal < ALC_LVL but maximum ALC Gain has been reached 12 ALC_PKOVR_S TS 0 Readback of the ALC Peak Limiter Overload status. Set when ADC input signal exceeds -1.16dBFS 11 ALC_NGATE_S TS 0 Readback of the ALC Noise Gate status. 0 = ADC input signal level > ALC_NGATE_THR 1 = ADC input signal level < ALC_NGATE_THR Table 20 ALC Status Readback Rev 4.4 61 WM8962 DIGITAL MICROPHONE INTERFACE The WM8962 supports a stereo digital microphone interface. Two channels of audio data are multiplexed on a GPIO pin configured for digital microphone input. The digital microphone data input (DMICDAT) is provided on GPIO5 or GPIO6 by setting the respective GPn_FN register to 1_0100. The associated clock (DMICCLK) is provided on a separate GPIO pin by setting the respective GPn_FN register to 1_0011. See “General Purpose Input/Output (GPIO)” section for details on these registers. Note that care must be taken to ensure that the respective digital logic levels of the microphone are compatible with the digital input thresholds of the WM8962. The digital input thresholds are referenced to DBVDD, as defined in “Electrical Characteristics”. It is recommended to power the digital microphones from DBVDD. When digital microphone input is enabled, the WM8962 outputs a clock signal (DMICCLK) on the Digital Microphone Clock Output pin (this must be configured on one of the GPIO pins). The clock frequency for all supported digital microphone clocking modes is described later in this section. A pair of digital microphones is connected as illustrated in Figure 20. The microphones must be configured to ensure that the Left mic transmits a data bit when DMICCLK is high, and the Right mic transmits a data bit when DMICCLK is low. The WM8962 samples the digital microphone data at the end of each DMICCLK phase. Each microphone must tri-state its data output when the other microphone is transmitting. DBVDD 0.1uF DMICCLK DMICDAT VDD VDD CLK DATA VDD Digital Mic CHAN Digital Microphone Interface CLK DATA Digital Mic CHAN DGND DMICCLK is available on GPIO2, GPIO3, GPIO5 and GPIO6 DMICDAT is supported on GPIO5 and GPIO6 Figure 20 Digital Microphone Input The digital microphone signal paths are enabled using the DMIC_ENA register. When DMIC_ENA is set, the ADC path is disconnected and the digital microphone data is routed to the digital core, as illustrated in “Digital Mixing”. Two microphone channels are interleaved on DMICDAT; the timing is illustrated in Figure 21. Each microphone must tri-state its data output when the other microphone is transmitting. 62 Rev 4.4 WM8962 DMICCLK pin hi-Z MIC1 output (Left Channel) 1 MIC2 output (Right Channel) DMICDAT (Left/Right channels interleaved) 1 1 2 1 2 2 1 2 2 1 2 Figure 21 Digital Microphone Interface Timing The digital microphone interface control fields are described in Table 21. Note that the ADC and Record Path filters must be enabled and the sample rate must be set in order to ensure correct operation of all DSP functions associated with the digital microphone. Volume control for the Digital Microphone Interface signals is provided using the ADC Volume Control. See “Analogue To Digital Converter (ADC)” for details of the ADC Enable and ADC digital volume control functions. See “General Purpose Input/Output (GPIO)” for details of configuring the DMICCLK and DMICDAT functions. See “Clocking and Sample Rates” for details of the sample rate control. REGISTER ADDRESS BIT R25 (19h) Pwr Mgmt (1) 10 LABEL DEFAULT DESCRIPTION DMIC_ENA 0 Enables Digital Microphone mode. 0 = Audio DSP input is from ADC 1 = Audio DSP input is from digital microphone interface Note that, when the digital microphone interface is selected, the ADCL_ENA and ADCR_ENA registers must also be set to enable the left and right digital microphone channels respectively. 3 ADCL_ENA 0 Left ADC Enable 0 = Disabled 1 = Enabled 2 ADCR_ENA 0 Right ADC Enable 0 = Disabled 1 = Enabled Table 21 Digital Microphone Interface Control Note that, in addition to setting the DMIC_ENA bit as described in Table 21, the pins GPIO2, GPIO3, GPIO5 or GPIO6 must also be configured to provide the digital microphone interface function. See “General Purpose Input/Output (GPIO)” for details. Rev 4.4 63 WM8962 Clocking for the digital microphone interface is derived from SYSCLK. The DMICCLK frequency is configured automatically, according to the SAMPLE_RATE, MCLK_RATE, and ADC_HP registers. (See “Clocking and Sample Rates” for further details of the system clocks and control registers.) The DMICCLK is enabled whenever a digital microphone input path is enabled on the GPIO2 or GPIO3 pins. Note that the SYSCLK_ENA register must also be set. The DMICCLK frequency is as described in Table 22 (for ADC_HP=0) and Table 23 (for ADC_HP=1). The ADC_HP bit is set to 0 by default, giving reduced power consumption. Note that the only valid DMICCLK configurations are the ones listed in Table 22 and Table 23. Note that the system clock, SYSCLK, must be present and enabled when using the digital microphone interface. SAMPLE RATE (kHz) MCLK RATE (MCLK / fs ratio) 512 768 1024 1536 3072 6144 8 1.024 256 384 1.024 1.024 1.024 1.024 1.024 1.024 11.025 1.4112 1.4112 1.4112 1.4112 1.4112 1.4112 12 1.536 1.536 1.536 1.536 1.536 1.536 16 1.024 1.024 1.024 1.024 1.024 1.024 1.024 22.05 1.4112 1.4112 1.4112 1.4112 1.4112 1.4112 24 1.536 1.536 1.536 1.536 1.536 1.536 32 2.048 2.048 2.048 2.048 2.048 2.048 44.1 2.8224 1.4112 2.8224 1.4112 2.8224 48 3.072 1.536 3.072 1.536 3.072 88.2 2.8224 2.8224 96 3.072 3.072 When ADC_HP=0, digital microphone operation is only supported for the above configurations. Digital microphone operation is not supported for 64fs, 128fs or 192fs MCLK ratios. Table 22 DMICCLK Frequency (MHz) - ADC_HP = 0 (Default) SAMPLE RATE (kHz) MCLK RATE (MCLK / fs ratio) 256 384 512 1024 1536 3072 6144 8 1.024 2.048 768 2.048 2.048 2.048 2.048 11.025 1.4112 2.8224 2.8224 12 1.536 3.072 16 2.048 2.048 2.048 22.05 2.8224 2.8224 2.8224 24 3.072 3.072 3.072 32 2.048 2.048 2.048 44.1 2.8224 2.8224 2.8224 48 3.072 3.072 3.072 88.2 2.8224 2.8224 96 3.072 3.072 3.072 2.048 2.048 When ADC_HP=1, digital microphone operation is only supported for the above configurations. Digital microphone operation is not supported for 64fs, 128fs or 192fs MCLK ratios. Table 23 DMICCLK Frequency (MHz) - ADC_HP = 1 64 Rev 4.4 WM8962 ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8962 uses stereo 24-bit, 128x oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC full scale input level is proportional to AVDD - see “Electrical Characteristics”. Any input signal greater than full scale may overload the ADC and cause distortion. The ADCs are enabled by the ADCL_ENA and ADCR_ENA register bits. Note that when disabling the ADC, the digital volume controls ADCL_VOL and ADCR_VOL should be muted before clearing ADCL_ENA or ADCR_ENA to 0. This ensures that the last ADC code does not appear at the Audio Interface (ADCDAT) pin when ADCL_ENA or ADCR_ENA are cleared. REGISTER ADDRESS R25 (19h) Pwr Mgmt (1) BIT LABEL DEFAULT DESCRIPTION 3 ADCL_ENA 0 Left ADC Enable 0 = Disabled 1 = Enabled 2 ADCR_ENA 0 Right ADC Enable 0 = Disabled 1 = Enabled Table 24 ADC Enable Control ADC CLOCKING CONTROL Clocking for the ADCs is derived from SYSCLK. The required clock is enabled when the SYSCLK_ENA register is set. The ADC clock rate is configured automatically, according to the SAMPLE_RATE and MCLK_RATE registers. See “Clocking and Sample Rates” for further details of the system clocks and associated control registers. Note that the ADC and the ADC signal path enhancements functions are only supported under specific clocking configurations. The valid clocking ratios for ADC operation are identified in Table 95. See also Table 96 for details of the supported functions for different MCLK / fs ratios. Rev 4.4 65 WM8962 ADC DIGITAL VOLUME CONTROL The output of the ADCs can be digitally amplified or attenuated over a range from -71.625dB to +23.625dB in 0.375dB steps. The volume of each channel can be controlled separately. The gain for a given eight-bit code X is given by: 0.375  (X-192) dB for 1  X  255; MUTE for X = 0 The ADC_VU bit controls the loading of digital volume control data. When ADC_VU is set to 0, the ADCL_VOL or ADCR_VOL control data will be loaded into the respective control register, but will not actually change the digital gain setting. Both left and right gain settings are updated when a 1 is written to ADC_VU. This makes it possible to update the gain of both channels simultaneously. REGISTER ADDRESS R21 (15h) Left ADC Volume BIT 8 7:0 R22 (16h) Right ADC Volume 8 7:0 LABEL ADC_VU ADCL_VOL [7:0] ADC_VU ADCR_VOL [7:0] DEFAULT DESCRIPTION N/A ADC Volume Update Writing a 1 to this bit will cause left and right ADC volume to be updated simultaneously C0h (0dB) N/A C0h (0dB) Left ADC Digital Volume 00h = mute 01h = -71.625dB 02h = -71.250dB …0.375dB steps C0h = 0dB (default) … FFh = 23.625dB (See Table 26 for volume range) ADC Volume Update Writing a 1 to this bit will cause left and right ADC volume to be updated simultaneously Right ADC Digital Volume 00h = mute 01h = -71.625dB 02h = -71.250dB …0.375dB steps C0h = 0dB (default) … FFh = 23.625dB (See Table 26 for volume range) Table 25 ADC Digital Volume Control 66 Rev 4.4 WM8962 ADCL_VOL or ADCL_VOL or ADCL_VOL or ADCL_VOL or ADCR_VOL Volume (dB) ADCR_VOL Volume (dB) ADCR_VOL Volume (dB) ADCR_VOL Volume (dB) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F MUTE -71.625 -71.250 -70.875 -70.500 -70.125 -69.750 -69.375 -69.000 -68.625 -68.250 -67.875 -67.500 -67.125 -66.750 -66.375 -66.000 -65.625 -65.250 -64.875 -64.500 -64.125 -63.750 -63.375 -63.000 -62.625 -62.250 -61.875 -61.500 -61.125 -60.750 -60.375 -60.000 -59.625 -59.250 -58.875 -58.500 -58.125 -57.750 -57.375 -57.000 -56.625 -56.250 -55.875 -55.500 -55.125 -54.750 -54.375 -54.000 -53.625 -53.250 -52.875 -52.500 -52.125 -51.750 -51.375 -51.000 -50.625 -50.250 -49.875 -49.500 -49.125 -48.750 -48.375 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F -48.000 -47.625 -47.250 -46.875 -46.500 -46.125 -45.750 -45.375 -45.000 -44.625 -44.250 -43.875 -43.500 -43.125 -42.750 -42.375 -42.000 -41.625 -41.250 -40.875 -40.500 -40.125 -39.750 -39.375 -39.000 -38.625 -38.250 -37.875 -37.500 -37.125 -36.750 -36.375 -36.000 -35.625 -35.250 -34.875 -34.500 -34.125 -33.750 -33.375 -33.000 -32.625 -32.250 -31.875 -31.500 -31.125 -30.750 -30.375 -30.000 -29.625 -29.250 -28.875 -28.500 -28.125 -27.750 -27.375 -27.000 -26.625 -26.250 -25.875 -25.500 -25.125 -24.750 -24.375 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF -24.000 -23.625 -23.250 -22.875 -22.500 -22.125 -21.750 -21.375 -21.000 -20.625 -20.250 -19.875 -19.500 -19.125 -18.750 -18.375 -18.000 -17.625 -17.250 -16.875 -16.500 -16.125 -15.750 -15.375 -15.000 -14.625 -14.250 -13.875 -13.500 -13.125 -12.750 -12.375 -12.000 -11.625 -11.250 -10.875 -10.500 -10.125 -9.750 -9.375 -9.000 -8.625 -8.250 -7.875 -7.500 -7.125 -6.750 -6.375 -6.000 -5.625 -5.250 -4.875 -4.500 -4.125 -3.750 -3.375 -3.000 -2.625 -2.250 -1.875 -1.500 -1.125 -0.750 -0.375 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF 0.000 0.375 0.750 1.125 1.500 1.875 2.250 2.625 3.000 3.375 3.750 4.125 4.500 4.875 5.250 5.625 6.000 6.375 6.750 7.125 7.500 7.875 8.250 8.625 9.000 9.375 9.750 10.125 10.500 10.875 11.250 11.625 12.000 12.375 12.750 13.125 13.500 13.875 14.250 14.625 15.000 15.375 15.750 16.125 16.500 16.875 17.250 17.625 18.000 18.375 18.750 19.125 19.500 19.875 20.250 20.625 21.000 21.375 21.750 22.125 22.500 22.875 23.250 23.625 Table 26 ADC Digital Volume Range Rev 4.4 67 WM8962 ADC OVERSAMPLING RATIO (OSR) The ADC oversampling rate is programmable to allow power consumption versus audio performance trade-offs. The default oversampling rate is low for reduced power consumption; using the higher OSR setting improves the ADC signal-to-noise performance. See the “Reference Voltages and Bias Control” section for details of the supported bias control settings for the input signal paths. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 5 ADC_HP 0 ADC Oversampling Ratio 0 = Low Power (typically 64 x fs) 1 = High Performance (typically 128 x fs) R23 (17h) Additional control (1) Table 27 ADC Oversampling Ratio ADC MONOMIX A mono mix of the Left and Right channels can be created by setting the ADC_MONOMIX register bit, as described in Table 28. When ADC_MONOMIX is set, 3D Surround must be disabled (THREED_ENA = 0, as described Table 33) for the ADC_MONOMIX setting to be effective. An attenuation of -6dB is applied to the sum of the Left and Right channels in order to avoid clipping. REGISTER ADDRESS BIT R268 (010Ch) THREED1 6 LABEL ADC_MONOMIX DEFAULT DESCRIPTION 0 ADC Monomix enable 0 = Disabled 1 = Enabled Note that THREED_ENA (see Table 33) must be disabled for ADC_MONOMIX to be effective. Table 28 ADC Monomix 68 Rev 4.4 WM8962 DSP SIGNAL ENHANCEMENTS The WM8962 incorporates several advanced signal enhancement features within the digital audio signal paths, as illustrated in Figure 22. The ADC signal path incorporates a 2nd order High-Pass Filter (HPF), 1st order Low/High-Pass Filter (LPF/HPF), 3D surround, DF1 Filter, ReTuneTM and Dynamic Range Control (DRC). The DAC signal path incorporates a 5-Band EQ, Dynamic Range Control (DRC), 2nd order High-Pass Filter (HPF), Virtual Surround Sound (VSS), HD Bass and ReTuneTM. Note that ReTuneTM can be enabled on the ADC or DAC signal paths; it can also be enabled on both paths at the same time, with unique coefficient sets on each path. Dynamic Range Control (DRC) can be enabled on either the ADC path or on the DAC path, but not on both at the same time. Note that specific sequences must be followed when enabling or configuring ADC ReTune, DAC ReTune, DAC 2nd order HPF, VSS, and HD Bass sound enhancement functions. Different control sequences are applicable, depending on whether any of the advanced signal enhancements is initially enabled or not. The configuration parameters in registers R16896 (4200h) to R21139 (5293h) are 24-bit words, arranged within the 16-bit register address space. Each 24-bit word must be written to the register map in full, MSBs first, before attempting to read back the value. Failure to do this may give incorrect read/write behaviour. When updating the configuration parameters for any DSP feature(s), it is recommended to write all of the associated registers, in incremental address order, before reading back any values. ENABLE SEQUENCE - ENHANCEMENTS INITIALLY DISABLED When enabling any of ADC ReTune, DAC ReTune, DAC 2nd order HPF, VSS, or HD Bass, the following sequence is required. Note that this sequence assumes that, under initial conditions, all of these enhancement functions are disabled. A separate sequence is described for use when sound enhancement is initially enabled. 1. MCLK must be present and configured at >= 512 fs (see Table 98) 2. Set ADCL_VOL = 00h in Register R21 (15h), and ADCR_VOL = 00h in Register R22 (16h) (see Table 25) 3. Set ADCL_ENA = 0 and ADCR_ENA = 0 in Register R25 (19h) (see Table 24) 4. Set DAC_MUTE = 1 in Register R5 (5h) (see Table 62) 5. Set DACL_ENA = 0 and DACR_ENA = 0 in Register R26 (1Ah) (see Table 59) 6. Set DSP2_ENA = 1 in Register R768 (300h) (see Table 29) 7. Set the configuration parameters in registers R16896 (4200h) to R21139 (5293h) 8. Readback the configuration parameters in registers R16896 (4200h) to R21139 (5293h) 9. Set DSP2_RUNR = 1 in Register R1037 (40Dh) (see Table 29) 10. Set the enable bits in Register R16389 (4005h) for any required sound enhancement RTN_ADC_ENA RTN_DAC_ENA HDBASS_ENA HPF1_ENA (see note below) HPF2_ENA (see note below) VSS_ENA 11. Set ADCL_ENA = 1 and ADCR_ENA = 1 in Register R25 (19h), if required (see Table 24) 12. Set ADCL_VOL in Register R21 (15h), and ADCR_VOL in Register R22 (16h), to their previous values 13. Set DACL_ENA = 1 and DACR_ENA = 1 in Register R26 (1Ah), if required (see Table 59) Rev 4.4 69 WM8962 14. Set DAC_MUTE = 0 in Register R5 (5h) (see Table 62) Note that the DAC high pass filters cannot be enabled unless one or more other sound enhancement functions is enabled. If HPF1_ENA = 1 or HPF2_ENA = 1, then at least one other of the enable bits in Register R16389 must also be set (ie. RTN_ADC_ENA, RTN_DAC_ENA, HDBASS_ENA or VSS_ENA). Note that DSP2_ENA in Register R768 (300h) must remain asserted whenever any of the sound enhancement functions listed above is being used. ENABLE / DISABLE SEQUENCE - ENHANCEMENTS INITIALLY ENABLED When enabling or disabling any of ADC ReTune, DAC ReTune, DAC 2nd order HPF, VSS, or HD Bass, the following sequence is required. Note that this sequence assumes that, under initial conditions, one or more of these enhancement functions is enabled. A separate sequence is described for use when the sound enhancements are initially disabled. Note that this sequence assumes that the applicable enhancement functions have already been configured (using default settings or otherwise). This sequence is only for enabling/disabling the selected functions. Separate sequences are described for configuring any of the sound enhancement functions. 1. Set ADCL_VOL = 00h in Register R21 (15h), and ADCR_VOL = 00h in Register R22 (16h) (see Table 25) 2. Set DAC_MUTE = 1 in Register R5 (5h) (see Table 62) 3. Set the enable bits in Register R16389 (4005h) for any required sound enhancement RTN_ADC_ENA RTN_DAC_ENA HDBASS_ENA HPF1_ENA (see note below) HPF2_ENA (see note below) VSS_ENA 4. Set ADCL_VOL in Register R21 (15h), and ADCR_VOL in Register R22 (16h), to their previous values 5. Set DAC_MUTE = 0 in Register R5 (5h) (see Table 62) Note that the DAC high pass filters cannot be enabled unless one or more other sound enhancement functions is enabled. If HPF1_ENA = 1 or HPF2_ENA = 1, then at least one other of the enable bits in Register R16389 must also be set (ie. RTN_ADC_ENA, RTN_DAC_ENA, HDBASS_ENA or VSS_ENA). Note that DSP2_ENA in Register R768 (300h) must remain asserted whenever any of the sound enhancement functions listed above is being used. To disable all sound enhancement functions, refer to the control sequence described in the next section (“Disable All Sound Enhancements”). 70 Rev 4.4 WM8962 DISABLE ALL SOUND ENHANCEMENTS SEQUENCE When disabling all of the sound enhancement functions (ADC ReTune, DAC ReTune, DAC 2nd order HPF, VSS, and HD Bass), the following sequence is required: 1. Set ADCL_VOL = 00h in Register R21 (15h), and ADCR_VOL = 00h in Register R22 (16h) (see Table 25) 2. Set DAC_MUTE = 1 in Register R5 (5h) (see Table 62) 3. Set the enable bits in Register R16389 (4005h) to 0 for all sound enhancements RTN_ADC_ENA = 0 RTN_DAC_ENA = 0 HDBASS_ENA = 0 HPF1_ENA = 0 HPF2_ENA = 0 VSS_ENA = 0 Rev 4.4 4. Set ADCL_VOL in Register R21 (15h), and ADCR_VOL in Register R22 (16h), to their previous values 5. Set DAC_MUTE = 0 in Register R5 (5h) (see Table 62) 6. Set DSP2_STOP = 1 in Register R1037 (40Dh) (see Table 29) 7. Set DSP2_ENA = 0 in Register R768 (300h) (see Table 29). 71 WM8962 UPDATE / READBACK SEQUENCE - ENHANCEMENTS INITIALLY ENABLED The required control sequence to update or read back the configuration parameters differs according to whether one or more of the sound enhancements is enabled under the initial conditions. If ADC ReTune, DAC ReTune, DAC 2nd order HPF, VSS, or HD Bass is already enabled, then the following sequence is required when updating or reading back the configuration parameters: 1. Set ADCL_VOL = 00h in Register R21 (15h), and ADCR_VOL = 00h in Register R22 (16h) (see Table 25) 2. Set ADCL_ENA = 0 and ADCR_ENA = 0 in Register R25 (19h) (see Table 24) 3. Set DAC_MUTE = 1 in Register R5 (5h) (see Table 62) 4. Set DACL_ENA = 0 and DACR_ENA = 0 in Register R26 (1Ah) (see Table 59) 5. Disable all sound enhancement registers in Register R16389 (4005h) RTN_ADC_ENA = 0 RTN_DAC_ENA = 0 HDBASS_ENA = 0 HPF2_ENA = 0 HPF1_ENA = 0 VSS_ENA = 0 6. Set DSP2_STOP = 1 in Register R1037 (40Dh) (see Table 29) 7. Set the configuration parameters in registers R16896 (4200h) to R21139 (5293h) 8. Readback the configuration parameters in registers R16896 (4200h) to R21139 (5293h) 9. Set DSP2_RUNR = 1 in Register R1037 (40Dh) (see Table 29) 10. Set the enable bits in Register R16389 (4005h) for any required sound enhancement RTN_ADC_ENA RTN_DAC_ENA HDBASS_ENA HPF1_ENA HPF2_ENA VSS_ENA 11. Set ADCL_ENA = 1 and ADCR_ENA = 1 in Register R25 (19h), if required (see Table 24) 12. Set ADCL_VOL in Register R21 (15h), and ADCR_VOL in Register R22 (16h), to their previous values 13. Set DACL_ENA = 1 and DACR_ENA = 1 in Register R26 (1Ah), if required (see Table 59) 14. Set DAC_MUTE = 0 in Register R5 (5h) (see Table 62) 72 Rev 4.4 WM8962 UPDATE / READBACK SEQUENCE - ENHANCEMENTS INITIALLY DISABLED The required control sequence to update or read back the configuration parameters differs according to whether one or more of the sound enhancements is enabled under the initial conditions. If ADC ReTune, DAC ReTune, DAC 2nd order HPF, VSS, or HD Bass are all disabled, then the following sequence is required when updating or reading back the configuration parameters: 1. MCLK must be present and configured at >= 512 fs (see Table 98) 2. Set ADCL_VOL = 00h in Register R21 (15h), and ADCR_VOL = 00h in Register R22 (16h) (see Table 25) 3. Set ADCL_ENA = 0 and ADCR_ENA = 0 in Register R25 (19h) (see Table 24) 4. Set DAC_MUTE = 1 in Register R5 (5h) (see Table 62) 5. Set DACL_ENA = 0 and DACR_ENA = 0 in Register R26 (1Ah) (see Table 59) 6. Set DSP2_ENA = 1 in Register R768 (300h) (see Table 29) 7. Set the configuration parameters in registers R16896 (4200h) to R21139 (5293h) 8. Readback the configuration parameters in registers R16896 (4200h) to R21139 (5293h) 9. Set DSP2_ENA = 0 in Register R768 (300h) (see Table 29) 10. Set ADCL_ENA = 1 and ADCR_ENA = 1 in Register R25 (19h), if required (see Table 24) 11. Set ADCL_VOL in Register R21 (15h), and ADCR_VOL in Register R22 (16h), to their previous values 12. Set DACL_ENA = 1 and DACR_ENA = 1 in Register R26 (1Ah), if required (see Table 59) 13. Set DAC_MUTE = 0 in Register R5 (5h) (see Table 62) The DSP2 audio processor control registers are described in Table 29. Other registers associated with ADC ReTune, DAC ReTune, DAC 2nd order HPF, VSS, or HD Bass are described in the respective sections in the following pages. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R768 (R300h) DSP2 Power Management 0 DSP2_ENA 0 DSP2 Audio Processor Enable. 0 = Disabled 1 = Enabled This bit must be set before any of ADC ReTune, DAC ReTune, DAC HPF, VSS or HD Bass is enabled. It must remain set whenever any of these functions is enabled. R1037 (40Dh) DSP2_ExecC ontrol 2 DSP2_STOP N/A Stop the DSP2 audio processor Writing a 1 to this bit will cause the DSP2 processor to stop processing audio data 1 DSP2_RUNR N/A Start the DSP2 audio processor Writing a 1 to this bit will cause the DSP2 processor to start processing audio data Table 29 DSP Signal Enhancement Control Rev 4.4 73 WM8962 ADC SIGNAL PATH ENHANCEMENTS The ADC signal path incorporates a number of sound enhancement features, as illustrated in Figure 22. These features are described more fully in the following sections. 2nd order HPF 5-Band EQ Dynamic Range Control* 2nd order HPF Virtual Surround Sound HD Bass ReTuneTM 1st order LPF/HPF 3D Surround ADC DF1 Filter ReTuneTM Dynamic Range Control* DAC * Dynamic Range Control (DRC) can be enabled on either the ADC path or the DAC path, but not on both at the same time DIGITAL AUDIO INTERFACE Signal Enhancement Blocks Figure 22 ADC Signal Path Enhancements ADC SECOND ORDER HIGH-PASS FILTER Second Order HPF First Order LPF/HPF 3D Surround DF1 Filter ADC ReTuneTM DRC ADC Signal Enhancement path A digital high-pass filter is enabled by default in the ADC path to remove DC offsets. This filter can also be used to remove low frequency noise in voice applications (e.g. wind noise or mechanical vibration). The filter can be disabled by setting the ADC_HPF_DIS register bit. The filter operates in one of two modes, selected by ADC_HPF_MODE. The ADC_HPF_SR register should be set according to the selected ADC sample rate. See “Clocking and Sample Rates” for details of the ADC sample rate. In Hi-Fi mode, the high-pass filter is optimised for removing DC offsets without degrading the bass response and has a cut-off frequency of 3.5Hz when the sample rate (fs) = 44.1kHz. In Application mode, the HPF cut-off frequency is set using ADC_HPF_CUT. This mode is intended for voice communication; it is recommended to set the cut-off frequency below 300Hz (e.g. ADC_HPF_CUT = 101 when fs = 8kHz or ADC_HPF_CUT = 101 when fs = 16kHz). 74 Rev 4.4 WM8962 REGISTER ADDRESS BIT R5 (05h) ADC & DAC Control 1 0 R6 (06h) ADC & DAC Control 2 13:12 LABEL DEFAULT DESCRIPTION ADC_HPF_DIS 0 ADC High-Pass Filter Disable 0 = Enable 1 = Disable ADC_HPF_SR [1:0] 10 ADC High-Pass Filter Sample rate 00 = 8k, 11.025k, 12k 01 = 16k, 22.025k, 24k 10 = 32k, 44.1, 48k 11 = 88.2k, 96k This field is for read-back only; it is set automatically and cannot be adjusted 10 ADC_HPF_MODE 0 ADC High-Pass Filter Mode select 0 = Hi-Fi mode (1st order) 1 = Application mode (2nd order) 9:7 ADC_HPF_CUT[2:0] 000 ADC High-Pass Filter Cutoff Note that the cut-off frequency scales with sample rate. See Table 31 for cut-off frequencies at all supported sample rates Table 30 ADC High-Pass Filter CUT-OFF FREQUENCY (Hz) APPLICATION MODE / ADC_HPF_CUT[2:0] SAMPLE HI-FI FREQUENCY MODE (kHz) 000 001 010 011 100 101 110 111 8.000 3.0 80.5 100.5 129.0 160.5 200.5 256.5 320.5 400.5 11.025 4.5 111.0 138.5 177.5 221.0 276.5 353.0 442.0 551.5 12.000 4.5 120.5 151.0 193.0 240.5 300.5 384.5 481.0 600.5 16.000 3.0 80.0 101.0 129.0 161.0 200.5 256.5 321.0 401.0 22.050 4.5 110.5 139.0 177.5 221.5 276.0 353.5 442.0 552.5 24.000 4.5 120.5 151.5 193.5 241.5 300.5 385.0 481.5 601.0 32.000 2.5 80.0 101.5 129.0 160.5 200.0 257.5 320.0 401.0 44.100 3.5 110.0 139.5 177.5 221.0 275.5 355.0 441.0 552.5 48.000 4.0 119.5 152.0 193.0 240.5 300.0 386.5 480.0 601.0 88.200 3.5 112.5 139.0 177.0 220.0 274.0 355.0 442.0 551.0 96.000 4.0 122.5 151.5 192.5 239.5 298.0 386.5 481.0 600.0 Note: ‘Hi-Fi Mode’ refers to the mode when ADC_HPF_MODE = 0 (first order filtering and a cutoff frequency of 3.5Hz at a sample rate of 44.1kHz); ‘Application Mode’ refers to the mode when ADC_HPF_MODE = 1 (second order filtering and the cut-off frequency set by ADC_HPF_CUT) Table 31 ADC High-Pass Filter Cut-Off Frequencies The high-pass filter characteristics are shown in the “Digital Filter Characteristics” section. Rev 4.4 75 WM8962 LOW-PASS / HIGH-PASS FILTER (LPF/HPF) First Order LPF/HPF Second Order HPF 3D Surround ADC ReTuneTM DF1 Filter DRC ADC Signal Enhancement path The Low-Pass / High-Pass filter is part of the ADC Signal Enhancement path. This first-order filter can be configured to be high-pass or low-pass. It can be used to removed unwanted ‘out of band’ noise from the ADC signal path. The filter is enabled using the LHPF_ENA register bit defined in Table 32. The default setting is bypass (OFF). The High-Pass or Low-Pass configuration is selected using the LHPF_MODE register bit. The filter can be programmed using the LHPF_COEFF register field (R265). For the derivation of this parameter, refer to the WISCETM configuration tool supplied with the WM8962 Evaluation Kit. REGISTER ADDRESS BIT R264 (0108h) LHPF1 LABEL DEFAULT DESCRIPTION 1 LHPF_MODE 0 Low/High-Pass Filter mode select 0 = Low-Pass 1 = High-Pass 0 LHPF_ENA 0 Low/High-Pass Filter 0 = Disable 1 = Enable Table 32 Low-Pass / High-Pass Filter Control Example plots of the Low-pass / High-pass filter response are shown in Figure 23. 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 20 39.91 79.62 158.9 317 632.5 1.262k 2.518k 5.024k 10.02k 1kLPF.res Magnitude(dB) 1kHPF.res Magnitude(dB) 5kLPF.res Magnitude(dB) 5kHPF.res Magnitude(dB) 200LPF.res Magnitude(dB) 200HPF.res Magnitude(dB) 20k Figure 23 Low-pass / High-pass Filter Responses 76 Rev 4.4 WM8962 3D SURROUND Second Order HPF First Order LPF/HPF 3D Surround DF1 Filter ADC ReTuneTM DRC ADC Signal Enhancement path The 3D Surround function is part of the ADC Signal Enhancement path. The 3D Surround processing can be used in ADC record applications to select between a directional or wide-angle microphone response. Depending on the target application, the stereo widening capability could be selected manually, or else could be configured automatically for different operational modes, for example. Note that the stereo widening is most effective at frequencies above 2kHz; lower frequencies may be attenuated by the phase cancellation process employed by the 3D Surround function. The DF1 filter (also part of the the ADC Signal Enhancement path) can be used to compensate for the attenuation of low frequencies; a low-shelf filter can be implemented in the DF1, as described later. The 3D Surround effect is programmable; it uses time delays and controlled cross-talk mechanisms to adjust the depth or width of the stereo audio. The 3D Surround effect includes programmable highpass or low-pass filtering to limit the effect to specific frequency bands if required. The structure of the 3D Surround processing is illustrated in Figure 24. THREED_FGAINL + L THREED_SIGN_L HPF LPF bypass z-n THREED_DELAYL THREED_CGAINR THREED_LHPF_ENA THREED_LHPF_MODE THREED_DELAYR R z-n THREED_CGAINL HPF LPF bypass THREED_SIGN_R + THREED_FGAINR Figure 24 3D Surround Processing The 3D Surround effect is enabled using the THREED_ENA register. Note that enabling 3D Surround will cause any ADC_MONOMIX settings to be ignored. When 3D Surround is enabled, the left and right audio channels connect to the outputs using forward (same channel) paths and cross-feed (opposite channel) paths. The forward gain levels are determined by the THREED_FGAINL and THREED_FGAINR registers; the cross-feed gain levels are set by THREED_CGAINL (for right-to-left cross-feed) and THREED_CGAINR (for left-to-right crossfeed). The polarity of the cross-feed mixing is controlled by the THREED_SIGN_L and THREED_SIGN_R register bits. If THREED_SIGN_L = 1 or THREED_SIGN_R = 1, then the respective cross-feed signal is subtracted from the main signal. If THREED_SIGN_L = 0 or THREED_SIGN_R = 0, then the respective cross-feed signal is added to the forward path signal. A time delay can be applied to the cross-feed signals; this is selected using the THREED_DELAYL and THREED_DELAYR registers for the left and right channels respectively. The signals can be delayed up to a maximum of 8 samples. High-Pass or Low-Pass filtering can be applied to the cross-feed signals. This is enabled by the THREED_LHPF_ENA register. The High-Pass or Low-Pass configuration is selected using the Rev 4.4 77 WM8962 THREED_LHPF_MODE register bit. This is typically used to filter out fixed-frequency noise or resonances. The 3D Surround High-Pass / Low-Pass filter can be programmed using the THREED_LHPF_COEFF register field (R270). For the derivation of this parameter, refer to the WISCE TM configuration tool supplied with the WM8962 Evaluation Kit. REGISTER ADDRESS BIT LABEL DEFAULT R268 (010Ch) THREED1 5 THREED_SIGNL 0 3D Left Cross mixing polarity (from the right channel to the left) 0 = Positive 1 = Negative 4 THREED_SIGNR 0 3D Right Cross mixing polarity (from the left channel to the right) 0 = Positive 1 = Negative 2 THREED_LHPF_ MODE 0 3D Low/High-Pass filter mode 0 = Low-Pass 1 = High-Pass 1 THREED_LHPF_ ENA 0 3D Low/High-Pass filter enable 0 = Disabled 1 = Enabled 0 THREED_ENA 0 3D Surround Sound enable 0 = Disabled 1 = Enabled Note that setting THREED_ENA will cause any ADC_MONOMIX setting to be ignored R269 (010Dh) THREED2 78 DESCRIPTION 15:11 THREED_FGAIN L [4:0] 00000 3D Left Forward Gain 00000 = Mute 00001 = -11.25dB 00010 = -10.875dB (…in steps of -0.375dB) 11110 = -0.375dB 11111 = 0.0dB See Table 34 for a full list of gain settings 10:6 THREED_CGAIN L [4:0] 00000 3D Left Cross Gain (from the right channel to the left) 00000 = Mute 00001 = -11.25dB 00010 = -10.875dB (…in steps of -0.375dB) 11110 = -0.375dB 11111 = 0.0dB See Table 34 for a full list of gain settings 5:2 THREED_DELAY L [3:0] 0000 3D Left Filter Delay (measured from the sample rate) 0000 = 0 samples 0001 = 1 samples 0010 = 2 samples 0011 = 3 samples 0100 = 4 samples 0101 = 5 samples 0110 = 6 samples 0111 = 7 samples 1000 = 8 samples 1001 to 1111 = Reserved Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R271 (010Fh) THREED4 15:11 THREED_FGAIN R [4:0] 00000 3D Right Forward Gain 00000 = Mute 00001 = -11.25dB 00010 = -10.875dB (…in steps of -0.375dB) 11110 = -0.375dB 11111 = 0.0dB See Table 34 for a full list of gain settings 10:6 THREED_CGAIN R [4:0] 00000 3D Right Cross Gain (from the left channel to the right) 00000 = Mute 00001 = -11.25dB 00010 = -10.875dB (…in steps of -0.375dB) 11110 = -0.375dB 11111 = 0.0dB See Table 34 for a full list of gain settings 5:2 THREED_DELAY R [3:0] 0000 3D Filter Delay (measured from the sample rate) 0000 = 0 samples 0001 = 1 samples 0010 = 2 samples 0011 = 3 samples 0100 = 4 samples 0101 = 5 samples 0110 = 6 samples 0111 = 7 samples 1000 = 8 samples 1001 to 1111 = Reserved Table 33 3D Surround Processing Rev 4.4 79 WM8962 THREED_FGAINL [4:0], THREED_CGAINL [4:0], THREED_FGAINR [4:0] OR THREED_CGAINR [4:0] GAIN (dB) THREED_FGAINL [4:0], THREED_CGAINL [4:0], THREED_FGAINR [4:0] OR THREED_CGAINR [4:0] GAIN (dB) 0_0000 Mute 1_0000 -5.625 0_0001 -11.250 1_0001 -5.250 0_0010 -10.875 1_0010 -4.875 0_0011 -10.500 1_0011 -4.500 0_0100 -10.125 1_0100 -4.125 0_0101 -9.750 1_0101 -3.750 0_0110 -9.375 1_0110 -3.375 0_0111 -9.000 1_0111 -3.000 0_1000 -8.625 1_1000 -2.625 0_1001 -8.250 1_1001 -2.250 0_1010 -7.875 1_1010 -1.875 0_1011 -7.500 1_1011 -1.500 0_1100 -7.125 1_1100 -1.125 0_1101 -6.750 1_1101 -0.750 0_1110 -6.375 1_1110 -0.375 0_1111 -6.000 1_1111 0.000 Table 34 3D Surround Forward Gain and Cross Gain Range DF1 FILTER First Order LPF/HPF Second Order HPF 3D Surround DF1 Filter ADC ReTuneTM DRC ADC Signal Enhancement path The DF1 Filter function is implemented in the ADC Signal Enhancement path. The Direct-Form 1 (DF1) filter can be used to implement a wide variety of user-defined algorithms. Typical applications of this function include low-shelf, high-shelf or all-pass filters. (A low-shelf filter boosts or attenuates low frequencies; a high-shelf filter boosts or attenuates high frequencies. Allpass filters can be defined which pass all frequencies, but adjust the phase response of the signal.) One of the recommended uses for the DF1 filter is as a low-shelf filter compensating for low frequency effects in the 3D Surround function. In this case, the DF1 filter should provide gain at low frequencies (eg. Below 2kHz). An example low-shelf filter response is illustrated in Figure 25. Gain 6dB 0dB fc1 fc2 Frequency Figure 25 DF1 Low Shelf Filter Response The Direct-Form 1 (DF1) standard filter is illustrated in Figure 26. All of the filter coefficients are programmable for the left and right channels independently, but DF1 can also be configured for both channels to share the filter coefficients from one or other of the channels. The default coefficients give a transparent filter response. 80 Rev 4.4 WM8962 x c1 + + y z-1 z-1 c2 c3 Figure 26 Direct-Form 1 Standard Filter Structure The DF1 response is defined by the following equations: y[n]  c1 x[n]  c2 x[n  1]  c3 y[n  1] H y c1  c2 z 1  x 1  c3 z 1 The DF1 filter is enabled on the ADC signal path using the DF1_ENA register bit defined in Table 35. The DF1 filter can be configured for both channels to use the same filter coefficients; this is selected by setting the DF1_SHARED_COEFF register bit. When this bit is set, then the applicable coefficients are selected using DF1_SHARED_COEFF_SEL; it is possible to select either the left or right channel coefficients. The DF1 filter can be used to implement very complex response patterns, with specific phase and gain responses at different frequencies. Typical applications of this type of filter include refinements or compensations to the 3D Surround, or other user-selected filters. For the derivation of the DF1 Filter coefficients (registers R257 to R259 and for the left channel, R260 to R262 for the right channel), refer to the WISCETM configuration tool supplied with the WM8962 Evaluation Kit. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R256 (0100h) DF1 2 DF1_SHARED_ COEFF 0 DF1 Shared Coefficients Enable 0 = Disabled 1 = Enabled 1 DF1_SHARED_ COEFF_SEL 0 DF1 Shared Coefficients Select 0 = Both channels use left coefficients 1 = Both channels use right coefficients 0 DF1_ENA 0 DF1 Enable in ADC path 0 = Disabled 1 = Enabled Table 35 Direct Form 1 (DF1) Filtering Rev 4.4 81 WM8962 ADC RETUNE Second Order HPF First Order LPF/HPF 3D Surround DF1 Filter ADC ReTuneTM DRC ADC Signal Enhancement path The ReTune function is part of both the ADC and the DAC Signal Enhancement paths. It can be enabled on either path independently. Unique coefficient sets are supported for each path. ReTuneTM is an advanced feature that is intended to perform frequency linearisation according to the particular needs of the application microphone, loudspeaker or housing. The ReTune algorithms can provide acoustic equalisation and selective phase (delay) control of specific frequency bands. In a typical application, ReTune™ is used to flatten the response across the audio frequency band. ReTune™ can also be configured to achieve other response patterns if required. Note that, when using ReTune™ to boost any frequency band, it is recommended to take care not to introduce distortion, taking into account the gain that may be applied by other audio enhancement functions. Before ReTuneTM is enabled, it must be initialised and configured using the DSP2_ENA bit described in Table 36. Note that this bit only needs to be enabled once before using any or all of ADC ReTune, DAC ReTune, DAC HPF, VSS or HD Bass. Note that specific sequences must be followed when enabling or configuring ADC ReTune, DAC ReTune, DAC HPF, VSS, and HD Bass sound enhancement functions (see “Enable Sequence Enhancements Initially Disabled”). The ReTune function is enabled on the ADC path using the RTN_ADC_ENA register bit as described in Table 36. Under default conditions, the Left and Right channels each use unique tuning coefficients. When the ADC_RETUNE_SCV register is set, then both channels are controlled by the Right channel coefficients. For the derivation of ADC ReTune configuration parameters in registers R17920 to R19007, the Cirrus WISCE™ software must be used to analyse the requirements of the application (refer to WISCETM for further information.) If desired, one or more sets of register coefficients might be derived for different operating scenarios, and these may be recalled and written to the CODEC registers as required in the target application. The ADC ReTune configuration procedure involves the generation and analysis of test signals as outlined below. Note that DSP2_ENA must be enabled before there is any type of access of any of the parameters associated with ADC ReTune. To determine the characteristics of the microphone in an application, a test signal is applied to a loudspeaker that is in the acoustic path to the microphone. The received signal through the application microphone is analysed and compared with the received signal from a reference microphone in order to determine the characteristics of the application microphone. Note that the ReTune configuration coefficients are specific to a particular speaker or microphone; it is therefore required that the part-to-part variation in these components is small. 82 Rev 4.4 WM8962 ADC ReTune is controlled using the register bits as described in Table 36. REGISTER ADDRESS BIT R768 (R300h) DSP2 Power Management 0 R16384 (4000h) RETUNEADC _SHARED_C OEFF_1 R16389 (4005h) SOUNDSTAG E_ENABLES_ 0 LABEL DEFAULT DESCRIPTION DSP2_ENA 0 DSP2 Audio Processor Enable. 0 = Disabled 1 = Enabled This bit must be set before any of ADC ReTune, DAC ReTune, DAC HPF, VSS or HD Bass is enabled. It must remain set whenever any of these functions is enabled. 7 ADC_RETUNE_ SCV 0 ADC ReTune Coefficient sharing 0 = Left and Right channels each use unique coefficients 1 = Both channels use the Right Channel coefficients 5 RTN_ADC_ENA 0 ADC ReTune enable 0 = disabled 1 = enabled Table 36 ADC ReTune Enable DYNAMIC RANGE CONTROL (DRC) Second Order HPF First Order LPF/HPF 3D Surround DF1 Filter ADC ReTuneTM DRC ADC Signal Enhancement path The dynamic range controller (DRC) is a circuit that can be enabled in either the digital record (ADC) or the digital playback (DAC) path of the WM8962. Note that the DRC cannot be enabled in both signal paths at the same time. The function of the DRC is to adjust the signal gain in conditions where the input amplitude is unknown or varies over a wide range, e.g. when recording from microphones built into a handheld system. The DRC can apply Compression and Automatic Level Control to the signal path. It incorporates ‘anti-clip’ and ‘quick release’ features for handling transients in order to improve intelligibility in the presence of loud impulsive noises. The DRC also incorporates a Noise Gate function, which provides additional attenuation of very lowlevel input signals. This means that the signal path is quiet when no signal is present, giving an improvement in background noise level under these conditions. The DRC is enabled using DRC_ENA, as described in Table 37. The DRC is selected in the ADC signal path by setting DRC_MODE = 0. REGISTER ADDRESS R276 (0114h) DRC 1 BIT LABEL DEFAULT DESCRIPTION 1 DRC_MODE 0 DRC path select 0 = ADC path 1 = DAC path 0 DRC_ENA 0 DRC Enable 0 = Disabled 1 = Enabled Table 37 DRC Mode and Enable Rev 4.4 83 WM8962 DRC COMPRESSION / EXPANSION / LIMITING The DRC supports two different compression regions, separated by a “Knee” at a specific input amplitude. In the region above the knee, the compression slope DRC_HI_COMP applies; in the region below the knee, the compression slope DRC_LO_COMP applies. The DRC also supports a noise gate region, where low-level input signals are heavily attenuated. This function can be enabled or disabled according to the application requirements. The DRC response in this region is defined by the expansion slope DRC_NG_EXP. For additional attenuation of signals in the noise gate region, an additional “knee” can be defined (shown as “Knee2” in Figure 27). When this knee is enabled, this introduces an infinitely steep dropoff in the DRC response pattern between the DRC_LO_COMP and DRC_NG_EXP regions. The overall DRC compression characteristic in “steady state” (i.e. where the input amplitude is nearconstant) is illustrated in Figure 27. DRC Output Amplitude (dBFS) (Y0) Knee1 DRC_KNEE_OP DRC DR C_ C _HI_ OMP P OM _C O L Knee2 DR C_ NG _E XP DRC_KNEE2_OP DRC_KNEE2_IP DRC_KNEE_IP 0dB DRC Input Amplitude (dBFS) Figure 27 DRC Response Characteristic The slope of the DRC response is determined by register fields DRC_HI_COMP and DRC_LO_COMP. A slope of 1 indicates constant gain in this region. A slope less than 1 represents compression (i.e. a change in input amplitude produces only a smaller change in output amplitude). A slope of 0 indicates that the target output amplitude is the same across a range of input amplitudes; this is infinite compression. When the noise gate is enabled, the DRC response in this region is determined by the DRC_NG_EXP register. A slope of 1 indicates constant gain in this region. A slope greater than 1 represents expansion (i.e. a change in input amplitude produces a larger change in output amplitude). When the DRC_KNEE2_OP knee is enabled (“Knee2” in Figure 27), this introduces the vertical line in the response pattern illustrated, resulting in infinitely steep attenuation at this point in the response. The DRC parameters are listed in Table 38. 84 Rev 4.4 WM8962 REF PARAMETER DESCRIPTION 1 DRC_KNEE_IP Input level at Knee1 (dB) 2 DRC_KNEE_OP Output level at Knee2 (dB) 3 DRC_HI_COMP Compression ratio above Knee1 4 DRC_LO_COMP Compression ratio below Knee1 5 DRC_KNEE2_IP Input level at Knee2 (dB) 6 DRC_NG_EXP Expansion ratio below Knee2 7 DRC_KNEE2_OP Output level at Knee2 (dB) Table 38 DRC Response Parameters The noise gate is enabled when the DRC_NG_ENA register is set. When the noise gate is disabled, parameters 5, 6, and 7 above are ignored, and the DRC_LO_COMP slope applies to all input signal levels below Knee1. The DRC_KNEE2_OP knee is enabled when the DRC_KNEE2_OP_ENA register is set. When this bit is not set, then parameter 7 above is ignored, and the Knee2 position always coincides with the low end of the DRC_LO_COMP region. The “Knee1” point in Figure 27 is determined by register fields DRC_KNEE_IP and DRC_KNEE_OP. Parameter Y0, the output level for a 0dB input, is not specified directly, but can be calculated from the other parameters, using the equation: Y0 = DRC_KNEE_OP – (DRC_KNEE_IP x DRC_HI_COMP) The DRC Compression / Expansion / Limiting parameters are defined in Table 39. REGISTER ADDRESS R276 (0114h) DRC1 R278 (0116h) DRC 3 Rev 4.4 BIT LABEL DEFAULT DESCRIPTION 7 DRC_NG_ENA 0 DRC Noise Gate Enable 0 = Disabled 1 = Enabled 4 DRC_KNEE2_OP _ENA 0 DRC_KNEE2_OP Enable 0 = Disabled 1 = Enabled 7:6 DRC_NG_EXP [1:0] 00 Noise Gate slope 00 = 1 (no expansion) 01 = 2 10 = 4 11 = 8 5:3 DRC_HI_COMP [2:0] 011 Compressor slope (upper region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 (default) 100 = 1/16 101 = 0 (ALC Mode) 110 = Reserved 111 = Reserved 2:0 DRC_LO_COMP [2:0] 000 Compressor slope (lower region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 to 111 = Reserved 85 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R279 (0117h) DRC 4 10:5 DRC_KNEE_IP [5:0] 000000 Input signal level at the Compressor ‘Knee’. 000000 = 0dB 000001 = -0.75dB 000010 = -1.5dB … (-0.75dB steps) 111100 = -45dB 111101 to 111111 = Reserved 4:0 DRC_KNEE_OP [4:0] 00000 Output signal at the Compressor ‘Knee’. 00000 = 0dB 00001 = -0.75dB 00010 = -1.5dB … (-0.75dB steps) 11110 = -22.5dB 11111 = Reserved 9:5 DRC_KNEE2_IP [4:0] 00000 Input signal level at the Noise Gate threshold ‘Knee2’. 00000 = -36dB 00001 = -37.5dB 00010 = -39dB … (-1.5dB steps) 11110 = -81dB 11111 = -82.5dB Only applicable when DRC_NG_ENA = 1. 4:0 DRC_KNEE2_OP [4:0] 00000 Output signal at the Noise Gate threshold ‘Knee2’. 00000 = -30dB 00001 = -31.5dB 00010 = -33dB … (-1.5dB steps) 11110 = -75dB 11111 = -76.5dB Only applicable when DRC_KNEE2_OP_ENA = 1. R280 (0117h) DRC 4 Table 39 DRC Control Registers 86 Rev 4.4 WM8962 DRC GAIN LIMITS The minimum and maximum gain applied by the DRC is set by register fields DRC_MINGAIN, DRC_MAXGAIN and DRC_NG_MINGAIN. These limits can be used to alter the DRC response from that illustrated in Figure 27. If the range between maximum and minimum gain is reduced, then the extent of the dynamic range control is reduced. The minimum gain in the Compression regions of the DRC response is set by DRC_MINGAIN. The minimum gain in the Noise Gate region is set by DRC_NG_MINGAIN. The minimum gain limit prevents excessive attenuation of the signal path. The maximum gain limit set by DRC_MAXGAIN prevents quiet signals (or silence) from being excessively amplified. REGISTER ADDRESS BIT R277 (0115h) DRC 2 4:2 DRC_MINGAIN [2:0] 001 Minimum gain the DRC can use to attenuate audio signals 000 = 0dB 001 = -12dB (default) 010 = -18dB 011 = -24dB 100 = -36dB 101to 111 = Reserved 1:0 DRC_MAXGAIN [1:0] 01 Maximum gain the DRC can use to boost audio signals (dB) 00 = 12dB 01 = 18dB (default) 10 = 24dB 11 = 36dB 15:12 DRC_NG_MING AIN [3:0] 0000 Minimum gain the DRC can use to attenuate audio signals when the noise gate is active. 0000 = -36dB 0001 = -30dB 0010 = -24dB 0011 = -18dB 0100 = -12dB 0101 = -6dB 0110 = 0dB 0111 = 6dB 1000 = 12dB 1001 = 18dB 1010 = 24dB 1011 = 30dB 1100 to 1111 = Reserved R278 (0116h) DRC 3 LABEL DEFAULT DESCRIPTION Table 40 DRC Gain Limits Rev 4.4 87 WM8962 DRC DYNAMIC CHARACTERISTICS The dynamic behaviour determines how quickly the DRC responds to changing signal levels. Note that the DRC responds to the average (RMS) signal amplitude over a period of time. The DRC_ATK determines how quickly the DRC gain decreases when the signal amplitude is high. The DRC_DCY determines how quickly the DRC gain increases when the signal amplitude is low. These register fields are described in Table 15. Note that the register defaults are suitable for general purpose microphone use. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R277 (0115h) DRC Control 2 12:9 DRC_ATK [3:0] 0100 Gain attack rate (seconds/6dB) 0000 = Reserved 0001 = 181us 0010 = 363us 0011 = 726us 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011 = 185.6ms 1100-1111 = Reserved 8:5 DRC_DCY [3:0] 1001 Gain decay rate (seconds/6dB) 0000 = 1.45ms 0001 = 2.9ms 0010 = 5.8ms 0011 = 11.6ms 0100 = 23.25ms 0101 = 46.5ms 0110 = 93ms 0111 = 186ms 1000 = 372ms 1001 = 743ms (default) 1010 = 1.49s 1011 = 2.97s 1100 = 5.94s 1101 = 11.89s 1110 = 23.78s 1111 = 47.56s Table 41 DRC Time Constants 88 Rev 4.4 WM8962 DRC ANTI-CLIP CONTROL The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very quickly. This feature uses a feed-forward technique for early detection of a rising signal level. Signal clipping is avoided by dynamically increasing the gain attack rate when required. The Anti-Clip feature is enabled using the DRC_ANTICLIP bit. Note that the feed-forward processing increases the latency in the input signal path. The DRC AntiClip control is described in Table 42. REGISTER ADDRESS BIT LABEL DEFAULT R276 (0114h) DRC Control 1 2 DRC_ANTICLIP 1 DESCRIPTION DRC Anti-clip Enable 0 = Disabled 1 = Enabled Table 42 DRC Anti-Clip Control Note that the Anti-Clip feature operates entirely in the digital domain. It cannot be used to prevent signal clipping in the analogue domain nor in the source signal. Analogue clipping can only be prevented by reducing the analogue signal gain or by adjusting the source signal. DRC QUICK-RELEASE CONTROL The DRC includes a Quick-Release feature to handle short transient peaks that are not related to the intended source signal. For example, in handheld microphone recording, transient signal peaks sometimes occur due to user handling, key presses or accidental tapping against the microphone. The Quick Release feature ensures that these transients do not cause the intended signal to be masked by the longer time constants of DRC_DCY. The Quick-Release feature is enabled by setting the DRC_QR bit. When this bit is enabled, the DRC measures the crest factor (peak to RMS ratio) of the input signal. A high crest factor is indicative of a transient peak that may not be related to the intended source signal. If the crest factor exceeds the level set by DRC_QR_THR, then the normal decay rate (DRC_DCY) is ignored and a faster decay rate (DRC_QR_DCY) is used instead. The DRC Quick-Release control bits are described in Table 43. REGISTER ADDRESS BIT R276 (0114h) DRC 1 3 R278 (0116h) DRC 3 LABEL DEFAULT DESCRIPTION DRC_QR 1 DRC Quick-release Enable 0 = Disabled 1 = Enabled 11:10 DRC_QR_THR [1:0] 00 DRC Quick-release threshold (crest factor in dB) 00 = 12dB 01 = 18dB 10 = 24dB 11 = 30dB 9:8 DRC_QR_DCY [1:0] 00 DRC Quick-release decay rate (seconds/6dB) 00 = 0.725ms 01 = 1.45ms 10 = 5.8ms 11 = reserved Table 43 DRC Quick-Release Control Rev 4.4 89 WM8962 DRC SIGNAL ACTIVITY DETECT The DRC incorporates a configurable signal detect function, allowing the signal level at the DRC input to be monitored and to be used to trigger other events. This can be used to detect the presence of a microphone signal on an ADC channel, or can be used to detect an audio signal received over the digital audio interface. The Peak signal level or the RMS signal level of the DRC input can be selected as the detection threshold. When the threshold condition is exceeded, an interrupt or GPIO output can be generated. See “General Purpose Input/Output (GPIO)” and “Interrupts” for further details. When the DRC is enabled, then signal activity detection can be enabled by setting the DRC_SIG_DET register bit. The applicable threshold can be defined either as a Peak level (Crest Factor) or an RMS level, depending on the DRC_SIG_DET_MODE register bit. When Peak level is selected, the threshold is determined by DRC_SIG_DET_PK, which defines the applicable Crest Factor (Peak to RMS ratio) threshold. If RMS level is selected, then the threshold is set using DRC_SIG_DET_RMS. These register fields are described in Table 44. REGISTER ADDRESS BIT R276 (0114h) DRC1 14:10 LABEL DEFAULT DESCRIPTION DRC_SIG_DET_ RMS [4:0] 00000 DRC Signal Detect RMS Threshold. This is the RMS signal level for signal detect to be indicated when DRC_SIG_DET_MODE=1. 00000 = -27dB 00001 = -28.5dB …. (1.5dB steps) 11110 = -72dB 11111 = -73.5dB 9:8 DRC_SIG_DET_ PK [1:0] 00 DRC Signal Detect Peak Threshold. This is the Peak/RMS ratio, or Crest Factor, level for signal detect to be indicated when DRC_SIG_DET_MODE=0. 00 = 14dB 01 = 20dB 10 = 26dB 11 = 32dB 6 DRC_SIG_DET_ MODE 0 DRC Signal Detect Mode 0 = Peak threshold mode 1 = RMS threshold mode 5 DRC_SIG_DET 0 DRC Signal Detect Enable 0 = Disabled 1 = Enabled Table 44 DRC Signal Activity Detect GPIO/Interrupt Control 90 Rev 4.4 WM8962 DIGITAL MIXING The ADC and DAC data can be combined in various ways to support a range of different usage modes. Under default conditions, data from the Left and Right ADCs is routed to the Left and Right channels respectively of the digital audio interface. The channels can be swapped if required and digital inversion of either signal is also possible. See “Digital Audio Interface” for more information on the audio interface. By default, the Left and Right input channels of the digital audio interface are routed to the Left and Right DACs respectively on the WM8962. The channels can be swapped if required and digital inversion of either signal is also possible. A mono mix of the two audio channels into a single DAC can be selected, as described in the “Digitalto-Analogue Converter (DAC)” section. Digital sidetone from the ADCs can also be selectively mixed into the DAC output path, as described later in this section. DIGITAL MIXING PATHS Figure 28 shows the digital mixing paths available in the WM8962 digital core. DIGITAL CORE ADCL_ENA DAC L ADC L ADC Signal Enhancement DAC Signal Enhancement DACL_ENA DACR_ENA ADC R DAC R ADCR_ENA ADC_VU ADCL_VOL[7:0] ADCR_VOL[7:0] MONO MIX DAC_MONOMIX + ADC_TO_DACR[1:0] ADC_TO_DACL[1:0] + ADCR_DAC_SVOL[3:0] ADCL_DAC_SVOL[3:0] ADC_LRSWAP ADCR_DAT_INV ADCL_DAT_INV LR RL LR RL DIGITAL AUDIO INTERFACE A-law and -law Support TDM Support DAC_LRSWAP DACR_DAT_INV DACL_DAT_INV DAC_DEEMP[1:0] DAC_COMP DAC_COMPMODE ADC_COMP ADC_COMPMODE BCLK LRCLK DACDAT ADCDAT AIFDAC_TDM_MODE AIFDAC_TDM_SLOT AIFADC_TDM_MODE AIFADC_TDM_SLOT WL[1:0] FMT[1:0] LOOPBACK DAC_VU DACL_VOL[7:0] DACR_VOL[7:0] DAC_MUTE DAC_AUTOMUTE DAC_MUTERATE DAC_UNMUTE_RAMP Figure 28 Digital Mixing Paths Rev 4.4 91 WM8962 The polarity of each ADC output signal can be changed under software control using the ADCR_DAT_INV and ADCL_DAT_INV register bits. The ADC_LRSWAP register bit may be used to swap the left and right digital audio interface data. These register bits are described in Table 45. REGISTER ADDRESS R5 (05h) ADC & DAC Control 1 R7 (07h) Audio Interface 0 BIT LABEL DEFAULT DESCRIPTION 6 ADCR_DAT_INV 0 Right ADC Invert 0 = Right ADC output not inverted 1 = Right ADC output inverted 5 ADCL_DAT_INV 0 Left ADC Invert 0 = Left ADC output not inverted 1 = Left ADC output inverted 8 ADC_LRSWAP 0 Swap left/right ADC data on the interface 0 = Normal 1 = ADCDAT channels swapped Table 45 ADC Routing and Control The input data source for each DAC can be controlled using the DAC_LRSWAP register bit; this swaps the left and right channel input data within the digital audio interface. The polarity of each DAC input may also be modified using register bits DACR_DAT_INV and DACL_DAT_INV. These register bits are described in Table 46. REGISTER ADDRESS R6 (06h) ADC & DAC Control 2 R7 (07h) Audio Interface 0 BIT LABEL DEFAULT DESCRIPTION 6 DACR_DAT_INV 0 Right DAC Invert 0 = Right DAC input not inverted 1 = Right DAC input inverted 5 DACL_DAT_INV 0 Left DAC Invert 0 = Left DAC input not inverted 1 = Left DAC input inverted 5 DAC_LRSWAP 0 Swap left/right DAC data on the interface 0 = Normal 1 = DACDAT channels swapped Table 46 DAC Routing and Control DIGITAL SIDETONE Digital sidetone mixing (from ADC output into DAC input) is available. Digital data from either left or right ADC can be mixed with the audio interface data on the left and right DAC channels. Sidetone data is taken from the ADC high-pass filter output, to reduce low frequency noise in the sidetone (e.g. wind noise or mechanical vibration). When using the digital sidetone, it is recommended that the ADCs are enabled before un-muting the DACs to prevent pop noise. The DAC volumes and sidetone volumes should be set to an appropriate level to avoid clipping at the DAC input. When digital sidetone is used, it is recommended that the Charge Pump operates in Register Control mode only (CP_DYN_PWR = 0). If Dynamic Control mode (CP_DYN_PWR = 1) is used, the headphone output may be clipped. See “Charge Pump” for details. The digital sidetone is controlled as shown in Table 47. 92 Rev 4.4 WM8962 REGISTER ADDRESS R57 (39h) DAC DSP Mixing (1) R58 (3Ah) DAC DSP Mixing (2) BIT LABEL DEFAULT DESCRIPTION 7:4 ADCR_DAC_SV OL [3:0] 0000 Right ADC Digital Sidetone Volume 0000 = -36dB 0001 = -33dB (… 3dB steps) 1011 = -3dB 11XX = 0dB (See Table 48 for volume range) 3:2 ADC_TO_DACR [1:0] 00 Right DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = No sidetone 7:4 ADCL_DAC_SV OL [3:0] 0000 Left ADC Digital Sidetone Volume 0000 = -36dB 0001 = -33dB (… 3dB steps) 1011 = -3dB 11XX = 0dB (See Table 48 for volume range) 3:2 ADC_TO_DACL [1:0] 00 Left DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = No sidetone Table 47 Digital Sidetone Control The digital sidetone volume settings are shown in Table 48. ADCR_DAC_SVOL OR ADCL_DAC_SVOL SIDETONE VOLUME 0000 -36 0001 -33 0010 -30 0011 -27 0100 -24 0101 -21 0110 -18 0111 -15 1000 -12 1001 -9 1010 -6 1011 -3 1100 0 1101 0 1110 0 1111 0 Table 48 Digital Sidetone Volume Rev 4.4 93 WM8962 T-LOOPBACK The T-Loopback function provides a specialised mode for use in communications applications such as VOIP handset configurations. The T-Loopback configuration provides a mono ADC and mono DAC signal to be output via the Digital Audio Interface transmit path. This allows Acoustic Echo Cancellation to be performed using difference algorithms implemented on an external processor. T-Loopback is enabled by setting the TLB_ENA register bit, as described in Table 50. When T-Loopback is enabled, the Digital Audio Interface outputs are configured according to the TLB_MODE bit, as described below. DESCRIPTION LEFT AIF OUTPUT RIGHT AIF OUTPUT TLB_MODE = 0 Left ADC (Left DAC + Right DAC)/2 TLB_MODE = 1 (Left DAC + Right DAC)/2 Right ADC Table 49 T-Loopback Mode Select Note that the Left ADC and Right ADC signals can be digitally mixed, if required. This enables the sum of the Left and Right ADC channels to be output in T-Loopback. The ADC Monomix feature is described in the “ADC Monomix” section. Note that the Left DAC and Right DAC signals used in the T-Loopback are also controlled by the DAC Digital Volume controls (see “Digital-to-Analogue Converter (DAC)”). It is possible to output just a single DAC channel in T-Loopback mode by setting the Digital Volume to zero in the unwanted channel. The register bits associated with T-Loopback are described in Table 50. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R285 (011Dh) Tloopback 1 TLB_ENA 0 T-Loopback Enable 0 = Disabled 1 = Enabled 0 TLB_MODE 0 T-Loopback Mode Select 0: Left AIF Output = Left ADC; Right AIF Output = (Left DAC + Right DAC) / 2 1: Left AIF Output = (Left DAC + Right DAC) / 2; Right AIF Output = Right ADC Table 50 T-Loopback Control The signal paths when T-Loopback is enabled (TLB_ENA = 1) are illustrated in Figure 29. 94 Rev 4.4 WM8962 DACL DAC MONOMIX (DACL + DACR) / 2 Digital Sidetone Mixing DACR ADCL ADC DACL DSP DSP ADCR ADC DAC DACL_VOL DACR DAC DACR_VOL ADC_MONOMIX TLB_MODE WM8962 Digital Audio Interface R L L R AEC External DSP Tx Rx VOIP VOIP Figure 29 T-Loopback Signal Paths Rev 4.4 95 WM8962 DAC SIGNAL PATH ENHANCEMENTS The DAC signal path incorporates a number of sound enhancement features, as illustrated in Figure 30. These features are described more fully in the following sections. 2nd order HPF 5-Band EQ Dynamic Range Control* nd 2 order HPF Virtual Surround Sound HD Bass ReTuneTM 1st order LPF/HPF ADC 3D Surround DF1 Filter ReTuneTM Dynamic Range Control* DAC * Dynamic Range Control (DRC) can be enabled on either the ADC path or the DAC path, but not on both at the same time DIGITAL AUDIO INTERFACE Signal Enhancement Blocks Figure 30 DAC Signal Enhancements 5-BAND EQ 5-band EQ DRC Second Order HPF VSS HD Bass DAC ReTune™ DAC Signal Enhancement path The 5-band EQ function is implemented in the DAC Signal Enhancement path. The 5-band EQ can be used to support user preferences for different music types, such as allowing selection of ‘rock’, ‘dance’, ‘classical’ or other user-defined EQ profiles. The 5-band EQ can also be used to provide compensation for imperfect characteristics of other components in the audio chain, such as the loudspeaker in portable applications in particular. Note that the functionality of the 5-band EQ has similarities to some of the other DAC signal enhancements; it is important to select the most appropriate processing block for each requirement. The 5-band EQ provides a basic level of signal control, whilst the other enhancements can provide superior performance in many cases. Frequency compensation of loudspeakers and other components can be implemented using the DAC ReTune function, which provides a more powerful capability to normalise the frequency response; this is achieved through the use of calibrated measurement procedures. The 5-band EQ provides a simpler and coarser type of signal control. Reduction of bass frequencies (removing signal content that the speaker is unable to reproduce) can be implemented using the 2nd order High Pass Filter (DAC HPF); this provides greater attenuation of the bass frequencies, without affecting the desired pass-band. Enhancement of bass frequencies (compensation for poor sensitivity in headphones or loudspeakers at low frequencies) can be implemented using the HD Bass function; this is a more intelligent and adaptive audio enhancement than the 5-band EQ. Note that, when using the 5-band EQ to boost any frequency band, it is recommended to take care not to introduce distortion, taking into account the gain that may be applied by other audio enhancement functions. The 5-band EQ allows the gain within five frequency bands to be controlled. The upper and lower frequency bands are controlled by low-pass and high-pass filters respectively. The middle three frequency bands are notch filters. The 5-band EQ is enabled by setting the EQ_ENA register as described in Table 52. 96 Rev 4.4 WM8962 In default mode, the cut-off / centre frequencies are fixed as described in Table 51. The filter bandwidths are also fixed in this mode. The gain of the individual bands (-12dB to +12dB) can be controlled as described in Table 53. The cut-off / centre frequencies noted in Table 51 are applicable to a sample rate of 48kHz. Note that, when using other sample rates, these frequencies will be scaled in proportion to the selected sample rate (see “Clocking and Sample Rates”). EQ BAND CUT-OFF/CENTRE FREQUENCY 1 100 Hz 2 300 Hz 3 875 Hz 4 2400 Hz 5 6900 Hz Table 51 EQ Band Cut-off / Centre Frequencies The gain for each of the five EQ bands on each of the channels is individually programmable using the register bits described in Table 52. The gain in each band on each channel is controllable in 1dB steps from -12dB to +12dB. The 5-band EQ can be configured for both channels to use the same configuration settings; this is selected by setting the EQ_SHARED_COEFF register bit. When this bit is set, then the applicable coefficients are selected using EQ_SHARED_COEFF_SEL; it is possible to select either the left or right channel coefficients. It is also possible for the user to define the cut-off/centre frequencies and the filter bandwidth for each EQ band, in addition to the gain controls already defined. This enables the EQ to be accurately customised for a specific transducer characteristic or desired sound profile. For the derivation of the 5-Band EQ configuration parameters in registers R338 to R355 (Left channel) and R358 to R375 (Right channel), refer to the WISCETM configuration tool supplied with the WM8962 Evaluation Kit. REGISTER ADDRESS BIT R335 (014Fh) EQ1 2 EQ_SHARED_C OEFF 1 5-Band EQ Shared Coefficient enable 0 = Right and Left channels use unique coefficients 1 = Left and right channels share filter coefficients 1 EQ_SHARED_C OEFF_SEL 0 5-Band EQ Shared Coefficient select 0 = Both channels use the left channel filter coefficients 1 = Both channels use the right channel filter coefficients 0 EQ_ENA 0 5-Band EQ Enable 0 = Disabled 1 = Enabled R336 (0150h) EQ2 Rev 4.4 LABEL DEFAULT DESCRIPTION 15:11 EQL_B1_GAIN[4: 0] 01100 Left Channel Band 1 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved See Table 53 for the full range 10:6 EQL_B2_GAIN[4: 0] 01100 Left Channel Band 2 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved See Table 53 for the full range 97 WM8962 REGISTER ADDRESS R337 (0151h) EQ2 R356 (0164h) EQ2 R357 (0165h) EQ2 BIT LABEL DEFAULT DESCRIPTION 5:1 EQL_B3_GAIN[4: 0] 01100 Left Channel Band 3 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved See Table 53 for the full range 15:11 EQL_B4_GAIN[4: 0] 01100 Left Channel Band 4 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved See Table 53 for the full range 10:6 EQL_B5_GAIN[4: 0] 01100 Left Channel Band 5 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved See Table 53 for the full range 15:11 EQR_B1_GAIN[4: 0] 01100 Right Channel Band 1 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved See Table 53 for the full range 10:6 EQR_B2_GAIN[4: 0] 01100 Right Channel Band 2 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved See Table 53 for the full range 5:1 EQR_B3_GAIN[4: 0] 01100 Right Channel Band 3 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved See Table 53 for the full range 15:11 EQR_B4_GAIN[4: 0] 01100 Right Channel Band 4 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved See Table 53 for the full range 10:6 EQR_B5_GAIN[4: 0] 01100 Right Channel Band 5 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved See Table 53 for the full range Table 52 5-Band EQ Control 98 Rev 4.4 WM8962 5-BAND EQ GAIN GAIN (dB) 5-BAND EQ GAIN GAIN (dB) 0_0000 -12 0_1101 +1 0_0001 -11 0_1110 +2 0_0010 -10 0_1111 +3 0_0011 -9 1_0000 +4 0_0100 -8 1_0001 +5 0_0101 -7 1_0010 +6 0_0110 -6 1_0011 +7 0_0111 -5 1_0100 +8 0_1000 -4 1_0101 +9 0_1001 -3 1_0110 +10 0_1010 -2 1_0111 +11 0_1011 -1 1_1000 +12 0_1100 0 1_1001 to 1_1111 Reserved Table 53 5-Band EQ Gain Range Rev 4.4 99 WM8962 DYNAMIC RANGE CONTROL (DRC) Second Order HPF DRC 5-band EQ VSS HD Bass DAC ReTune™ DAC Signal Enhancement path The dynamic range controller (DRC) is a circuit that can be enabled in either the digital record (ADC) or the digital playback (DAC) path of the WM8962. Note that the DRC cannot be enabled in both signal paths at the same time. The function of the DRC is to adjust the signal gain in conditions where the input amplitude is unknown or varies over a wide range, e.g. when recording from microphones built into a handheld system. The DRC can apply Compression and Automatic Level Control to the signal path. It incorporates ‘anti-clip’ and ‘quick release’ features for handling transients in order to improve intelligibility in the presence of loud impulsive noises. The DRC also incorporates a Noise Gate function, which provides additional attenuation of very lowlevel input signals. This means that the signal path is quiet when no signal is present, giving an improvement in background noise level under these conditions. The DRC is enabled using DRC_ENA, as described in Table 54. The DRC is selected in the DAC signal path by setting DRC_MODE = 1. Additional registers for configuring the DRC are described in the “ADC Signal Path Enhancements” section. REGISTER ADDRESS R276 (0114h) DRC 1 BIT LABEL DEFAULT DESCRIPTION 1 DRC_MODE 0 DRC path select 0 = ADC path 1 = DAC path 0 DRC_ENA 0 DRC Enable 0 = Disabled 1 = Enabled Table 54 DRC Mode and Enable 100 Rev 4.4 WM8962 DAC SECOND ORDER HIGH-PASS FILTER DRC 5-band EQ Second Order HPF VSS HD Bass DAC ReTune™ DAC Signal Enhancement path The 2nd order High-Pass Filter (HPF) is part of the DAC Signal Enhancement path. The DAC High-Pass filter is provided to remove DC offsets and low frequencies from the DAC signal path. This is an important function as DC offsets in the audio signal will reduce the signal headroom and increase power consumption. DC offsets and low frequency signals that are outside the capabilities of the loudspeaker will result in audible distortion and can cause damage to speakers or headphones. The cut-off frequency of the DAC High-Pass filter should be set to attenuate the frequencies that the speaker cannot reproduce, but without unnecessarily removing higher frequencies that can be supported. The 2nd order cut-off slope of 12dB per octave provides good selectivity between the frequencies to be cut and the frequencies to be retained. The DAC High-Pass filter is particularly recommended for use with the VSS, HD Bass and DAC ReTune functions in order to prevent distortion and speaker damage. Before the DAC High-Pass filter is enabled, it must be initialised and configured using the DSP2_ENA bit described in Table 55. Note that this bit only needs to be enabled once before using any or all of ADC ReTune, DAC ReTune, DAC HPF, VSS or HD Bass. Note that specific sequences must be followed when enabling or configuring ADC ReTune, DAC ReTune, DAC HPF, VSS, and HD Bass sound enhancement functions (see “Enable Sequence Enhancements Initially Disabled”). The 2nd order High Pass Filter comprises two 1st order filters, which are enabled using the HPF1_ENA and HPF2_ENA register bits as described in Table 55. Either one of the filters, or both filters, may be enabled. Each filter provides a cut-off slope of 6dB per octave; when both filters are enabled together, the combined effect is a second-order filter, with a cut-off slope of 12dB per octave. Note that the DAC high pass filters cannot be enabled unless one or more other sound enhancement functions is enabled. If HPF1_ENA = 1 or HPF2_ENA = 1, then at least one other of the enable bits in Register R16389 must also be set (ie. RTN_ADC_ENA, RTN_DAC_ENA, HDBASS_ENA or VSS_ENA). For the derivation of the High-Pass Filter configuration parameters in registers R17408 and R17409, refer to the WISCETM configuration tool supplied with the WM8962 Evaluation Kit. Note that both filters (HPF1 and HPF2) use the same configuration parameters. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R768 (R300h) DSP2 Power Management 0 DSP2_ENA 0 DSP2 Audio Processor Enable. 0 = Disabled 1 = Enabled This bit must be set before any of ADC ReTune, DAC ReTune, DAC HPF, VSS or HD Bass is enabled. It must remain set whenever any of these functions is enabled. R16389 (4005h) SOUNDSTAGE _ENABLES_0 2 HPF2_ENA 0 High-Pass Filter (HPF2) enable 0 = Disabled 1 = Enabled 1 HPF1_ENA 0 High Pass Filter (HPF1) enable 0 = Disabled 1 = Enabled Table 55 DAC High Pass Filter Enable Rev 4.4 101 WM8962 VIRTUAL SURROUND SOUND (VSS) DRC 5-band EQ Second Order HPF VSS HD Bass DAC ReTune™ DAC Signal Enhancement path The Virtual Surround Sound (VSS) function is part of the DAC Signal Enhancement path. Virtual Sound Sound (VSS) is a digital processing function that creates a perception of wider speaker separation, generating a rich and immersive listening experience. It is aimed at portable applications, but is effective on larger systems also. Note that VSS is not suited to single-speaker systems, nor to headphone outputs. Portable applications, where the speaker separation is small, suffer from significant acoustic crosstalk, where the Right speaker output is heard strongly in the Left ear, and vice versa. The VSS algorithms are designed to minimise these crosstalk effects, thus increasing the stereo experience. The VSS process is finely tuned to produce a compelling three-dimensional experience, but without the listening fatigue associated with some other stereo enhancement systems. The VSS algorithms (and the user perception) are most effective at high frequencies; low frequency content is therefore configured to bypass the VSS crosstalk processing. The crossover frequency (for the low-frequency bypass) is adjustable, enabling the user to trade-off the stereo widening effect against the required degree of integrity in the original audio. The VSS algorithms are programmable and can be optimised for specific application or user geometries. It is recommended to use the DAC HPF in conjunction with VSS in order to prevent distortion and speaker damage. Before VSS is enabled, it must be initialised and configured using the DSP2_ENA bit described in Table 56. Note that this bit only needs to be enabled once before using any or all of ADC ReTune, DAC ReTune, DAC HPF, VSS or HD Bass. Note that specific sequences must be followed when enabling or configuring ADC ReTune, DAC ReTune, DAC HPF, VSS, and HD Bass sound enhancement functions (see “Enable Sequence Enhancements Initially Disabled”). VSS is enabled using the VSS_ENA register bit as described in Table 56. It is possible to configure the VSS function to create a stereo effect that is optimised and tailored specifically for a particular application. For the derivation of the VSS configuration parameters in registers R20992 to R21139, refer to the WISCE configuration tool supplied with the WM8962 Evaluation Kit. Note that DSP2_ENA must be enabled before there is any type of access of any of the parameters associated with VSS. REGISTER ADDRESS BIT R768 (R300h) DSP2 Power Management 0 R16389 (4005h) SOUNDSTAG E_ENABLES_ 0 0 LABEL DEFAULT DESCRIPTION DSP2_ENA 0 DSP2 Audio Processor Enable. 0 = Disabled 1 = Enabled This bit must be set before any of ADC ReTune, DAC ReTune, DAC HPF, VSS or HD Bass is enabled. It must remain set whenever any of these functions is enabled. VSS_ENA 0 Virtual Surround Sound (VSS) enable 0 = Disabled 1 = Enabled Table 56 Virtual Surround Sound (VSS) Enable 102 Rev 4.4 WM8962 HD BASS DRC 5-band EQ Second Order HPF VSS HD Bass DAC ReTune™ DAC Signal Enhancement path The HD Bass function is part of the DAC Signal Enhancement path. HD Bass is a dynamic bass boost enhancement which is designed to improve the bass response of small speakers for portable applications in particular. It is also effective on larger speaker systems and on headphones if desired. HD Bass provides an adaptive gain control of a narrow frequency band towards the low end of the audio spectrum. At low frequencies, where the loudspeaker response is poor, the HD Bass function applies gain in order to increase the bass content of the loudspeaker output. The amount of gain is controlled adaptively, to ensure that distortion is not introduced. Note that fixed gain can be applied to bass frequencies using the 5-band EQ. The DRC can also apply gain to the DAC signal path. If these enhancements are used in conjunction with HD Bass, then it is important to limit the maximum gain of the 5-band EQ or DRC, to ensure that sufficient headroom is allowed for the HD Bass dynamic boost function. It is recommended to use the DAC HPF in conjunction with HD Bass in order to prevent distortion and speaker damage. Before HD Bass is enabled, it must be initialised and configured using the DSP2_ENA bit described in Table 57. Note that this bit only needs to be enabled once before using any or all of ADC ReTune, DAC ReTune, DAC HPF, VSS or HD Bass. Note that specific sequences must be followed when enabling or configuring ADC ReTune, DAC ReTune, DAC HPF, VSS, and HD Bass sound enhancement functions (see “Enable Sequence Enhancements Initially Disabled”). HD Bass is enabled using the HDBASS_ENA register bit as described in Table 57. HD Bass is preconfigured with a default set of parameters, but it is possible to select alternative settings. For the derivation of the HD Bass configuration parameters in registers R16896 to R16925, refer to the WISCETM configuration tool supplied with the WM8962 Evaluation Kit. Note that DSP2_ENA must be enabled before there is any type of access of any of the parameters associated with HD Bass. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R768 (R300h) DSP2 Power Management 0 DSP2_ENA 0 DSP2 Audio Processor Enable. 0 = Disabled 1 = Enabled This bit must be set before any of ADC ReTune, DAC ReTune, DAC HPF, VSS or HD Bass is enabled. It must remain set whenever any of these functions is enabled. R16389 (4005h) SOUNDSTAGE _ENABLES_0 3 HDBASS_ENA 0 HD Bass enable 0 = HD Bass disabled 1 = HD Bass enabled Table 57 HD Bass Control Rev 4.4 103 WM8962 DAC RETUNE 5-band EQ DRC Second Order HPF VSS HD Bass DAC ReTune™ DAC Signal Enhancement path The ReTune function is part of both the ADC and the DAC Signal Enhancement paths. It can be enabled on either path independently. Unique coefficient sets are supported for each path. ReTuneTM is an advanced feature that is intended to perform frequency linearisation according to the particular needs of the application microphone, loudspeaker or housing. The ReTune algorithms can provide acoustic equalisation and selective phase (delay) control of specific frequency bands. In a typical application, ReTune™ is used to flatten the response across the audio frequency band. ReTune™ can also be configured to achieve other response patterns if required. It is particularly recommended to use ReTune™ to flatten the DAC signal path response when using the VSS or HD Bass functions. The signal processing algorithms of the VSS and HD Bass functions assume a flat system response, and the performance of these enhancements will be compromised if the speaker response is poor or uncalibrated. Note that, when using ReTune™ to boost any frequency band, it is recommended to take care not to introduce distortion, taking into account the gain that may be applied by other audio enhancement functions. It is recommended to use the DAC HPF in conjunction with DAC ReTune in order to prevent distortion and speaker damage. Before ReTuneTM is enabled, it must be initialised and configured using the DSP2_ENA bit described in Table 58. Note that this bit only needs to be enabled once before using any or all of ADC ReTune, DAC ReTune, DAC HPF, VSS or HD Bass. Note that specific sequences must be followed when enabling or configuring ADC ReTune, DAC ReTune, DAC HPF, VSS, and HD Bass sound enhancement functions (see “Enable Sequence Enhancements Initially Disabled”). The ReTune function is enabled on the DAC path using the RTN_DAC_ENA register bit as described in Table 58. Under default conditions, the Left and Right channels each use unique tuning coefficients. When the DAC_RETUNE_SCV register is set, then both channels are controlled by the Right channel coefficients. For the derivation of DAC ReTune configuration parameters in registers R19456 to R20543, the Cirrus WISCE™ software must be used to analyse the requirements of the application (refer to WISCE for further information.) If desired, one or more sets of register coefficients might be derived for different operating scenarios, and these may be recalled and written to the CODEC registers as required in the target application. The DAC ReTune configuration procedure involves the generation and analysis of test signals as outlined below. Note that DSP2_ENA must be enabled before there is any type of access of any of the parameters associated with DAC ReTune. To determine the characteristics of the loudspeaker in an application, a test signal is applied to the target application. A reference microphone is positioned in the normal acoustic path of the loudspeaker, and the received signal is analysed to determine how accurately the loudspeaker has reproduced the test signal. Note that the ReTune configuration coefficients are specific to a particular speaker or microphone; it is therefore required that the part-to-part variation in these components is small. 104 Rev 4.4 WM8962 DAC ReTune is controlled using the register bits as described in Table 58. REGISTER ADDRESS BIT R768 (R300h) DSP2 Power Management 0 R16386 (4002h) RETUNEDAC _SHARED_C OEFF_1 R16389 (4005h) SOUNDSTAG E_ENABLES_ 0 LABEL DEFAULT DESCRIPTION DSP2_ENA 0 DSP2 Audio Processor Enable. 0 = Disabled 1 = Enabled This bit must be set before any of ADC ReTune, DAC ReTune, DAC HPF, VSS or HD Bass is enabled. It must remain set whenever any of these functions is enabled. 7 DAC_RETUNE_ SCV 0 DAC ReTune Coefficient sharing 0 = Left and Right channels each use unique coefficients 1 = Both channels use the Right Channel coefficients 4 RTN_DAC_ENA 0 DAC ReTuneTM enable 0 = disabled 1 = enabled Table 58 DAC ReTune Enable DIGITAL-TO-ANALOGUE CONVERTER (DAC) The WM8962 DACs receive digital input data from the digital audio interface. The digital audio data is converted to oversampled bit-streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to high quality analogue audio signals. The DACs provide digital volume control with soft mute / un-mute. Digital mono mix and de-emphasis filtering is also supported. The DACs are enabled by the DACL_ENA and DACR_ENA register bits. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R26 (1Ah) Pwr Mgmt (2) 8 DACL_ENA 0 Left DAC Enable 0 = Disabled 1 = Enabled Note that DACL_ENA must be set to 1 when processing left channel data from the DAC or Digital Beep Generator. 7 DACR_ENA 0 Right DAC Enable 0 = Disabled 1 = Enabled Note that DACR_ENA must be set to 1 when processing right channel data from the DAC or Digital Beep Generator. Table 59 DAC Enable Control Rev 4.4 105 WM8962 DAC CLOCKING CONTROL Clocking for the DACs is derived from SYSCLK. The required clock is enabled when the SYSCLK_ENA register is set. The DAC clock rate is configured automatically, according to the SAMPLE_RATE and MCLK_RATE registers. See “Clocking and Sample Rates” for further details of the system clocks and associated control registers. Note that the DAC and the DAC signal path enhancements functions are only supported under specific clocking configurations. The valid clocking ratios for DAC operation are identified in Table 95. See also Table 96 for details of the supported functions for different MCLK / fs ratios. DAC DIGITAL VOLUME CONTROL The output level (digital volume) of each DAC can be controlled digitally over a range from -71.625dB to +23.625dB in 0.375dB steps. The level of attenuation for an eight-bit code X is given by: 0.375  (X-192) dB for 1  X  255; MUTE for X = 0 The DAC_VU bit controls the loading of digital volume control data. When DAC_VU is set to 0, the DACL_VOL or DACR_VOL control data will be loaded into the respective control register, but will not actually change the digital gain setting. Both left and right gain settings are updated when a 1 is written to DAC_VU. This makes it possible to update the gain of both channels simultaneously. See "DAC Digital Volume Control" section for a description of the volume update function, the zero cross function and the timeout operation. REGISTER ADDRESS R10 (0Ah) Left DAC volume R11 (0Bh) Right DAC volume BIT LABEL DEFAULT DESCRIPTION 8 DAC_VU N/A DAC Volume Update Writing a 1 to this bit will cause left and right DAC volume to be updated simultaneously 7:0 DACL_VOL [7:0] C0h (0dB) Left DAC Digital Volume Control 00h = Digital Mute 01h = -71.625dB 02h = -71.250dB ... 0.375dB steps up to C0h = 0dB (default) …. FFh = 23.625dB (See Table 61 for volume range) 8 DAC_VU N/A DAC Volume Update Writing a 1 to this bit will cause left and right DAC volume to be updated simultaneously 7:0 DACR_VOL [7:0] C0h (0dB) Right DAC Digital Volume Control 00h = Digital Mute 01h = -71.625dB 02h = -71.250dB ... 0.375dB steps up to C0h = 0dB (default) …. FFh = 23.625dB (See Table 61 for volume range) Table 60 Digital Volume Control 106 Rev 4.4 WM8962 DACL_VOL or DACL_VOL or DACL_VOL or DACL_VOL or DACR_VOL Volume (dB) DACR_VOL Volume (dB) DACR_VOL Volume (dB) DACR_VOL Volume (dB) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F MUTE -71.625 -71.250 -70.875 -70.500 -70.125 -69.750 -69.375 -69.000 -68.625 -68.250 -67.875 -67.500 -67.125 -66.750 -66.375 -66.000 -65.625 -65.250 -64.875 -64.500 -64.125 -63.750 -63.375 -63.000 -62.625 -62.250 -61.875 -61.500 -61.125 -60.750 -60.375 -60.000 -59.625 -59.250 -58.875 -58.500 -58.125 -57.750 -57.375 -57.000 -56.625 -56.250 -55.875 -55.500 -55.125 -54.750 -54.375 -54.000 -53.625 -53.250 -52.875 -52.500 -52.125 -51.750 -51.375 -51.000 -50.625 -50.250 -49.875 -49.500 -49.125 -48.750 -48.375 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F -48.000 -47.625 -47.250 -46.875 -46.500 -46.125 -45.750 -45.375 -45.000 -44.625 -44.250 -43.875 -43.500 -43.125 -42.750 -42.375 -42.000 -41.625 -41.250 -40.875 -40.500 -40.125 -39.750 -39.375 -39.000 -38.625 -38.250 -37.875 -37.500 -37.125 -36.750 -36.375 -36.000 -35.625 -35.250 -34.875 -34.500 -34.125 -33.750 -33.375 -33.000 -32.625 -32.250 -31.875 -31.500 -31.125 -30.750 -30.375 -30.000 -29.625 -29.250 -28.875 -28.500 -28.125 -27.750 -27.375 -27.000 -26.625 -26.250 -25.875 -25.500 -25.125 -24.750 -24.375 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF -24.000 -23.625 -23.250 -22.875 -22.500 -22.125 -21.750 -21.375 -21.000 -20.625 -20.250 -19.875 -19.500 -19.125 -18.750 -18.375 -18.000 -17.625 -17.250 -16.875 -16.500 -16.125 -15.750 -15.375 -15.000 -14.625 -14.250 -13.875 -13.500 -13.125 -12.750 -12.375 -12.000 -11.625 -11.250 -10.875 -10.500 -10.125 -9.750 -9.375 -9.000 -8.625 -8.250 -7.875 -7.500 -7.125 -6.750 -6.375 -6.000 -5.625 -5.250 -4.875 -4.500 -4.125 -3.750 -3.375 -3.000 -2.625 -2.250 -1.875 -1.500 -1.125 -0.750 -0.375 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF 0.000 0.375 0.750 1.125 1.500 1.875 2.250 2.625 3.000 3.375 3.750 4.125 4.500 4.875 5.250 5.625 6.000 6.375 6.750 7.125 7.500 7.875 8.250 8.625 9.000 9.375 9.750 10.125 10.500 10.875 11.250 11.625 12.000 12.375 12.750 13.125 13.500 13.875 14.250 14.625 15.000 15.375 15.750 16.125 16.500 16.875 17.250 17.625 18.000 18.375 18.750 19.125 19.500 19.875 20.250 20.625 21.000 21.375 21.750 22.125 22.500 22.875 23.250 23.625 Table 61 DAC Digital Volume Range Rev 4.4 107 WM8962 DAC SOFT MUTE AND UN-MUTE A signal can be muted and unmuted using the DAC_MUTE register. The type of muting or unmuting performed (hard or soft) is controlled by the DAC_MUTE_RAMP and DAC_UNMUTE_RAMP registers. Note that the DAC is muted by default. To play back an audio signal, this function must first be disabled by setting the DAC_MUTE bit to zero. If DAC_MUTE_RAMP = 0 when a signal is muted, any muting of the output volume is instantaneous (a ‘hard’ mute). If DAC_MUTE_RAMP = 1 (‘soft’ mute), the signal is gradually attenuated until the volume of the digital signal reaches zero, as illustrated in Figure 31. Similarly, the hard and soft unmute functions are controlled by the DAC_UNMUTE_RAMP register. If DAC_UNMUTE_RAMP = 0, the signal gain returns instantaneously to the current PGA gain setting. If DAC_UNMUTE_RAMP = 1, the signal is gradually boosted until the volume of the digital signal reaches the current PGA gain setting. This is illustrated in Figure 31. DAC_UNMUTE_RAMP would typically be enabled when using soft mute during playback of audio data so that when mute is then disabled, the sudden volume increase will not create pop noise by jumping immediately to the previous volume level (e.g. resuming playback after pausing during a track). DAC_UNMUTE_RAMP would typically be disabled when un-muting at the start of a digital music file, so that the first part of the track is not attenuated (e.g. when starting playback of a new track, or resuming playback after pausing between tracks). DAC muting and un-muting with soft mute and soft unmute disabled (DAC_MUTE_RAMP = 0 and DAC_UNMUTE_RAMP = 0) DAC_MUTE = 0 DAC_MUTE = 1 DAC_MUTE = 0 DAC_MUTE_RAMP = 0 and DAC_UNMUTE_RAMP = 0 DAC muting and un-muting with soft mute and soft unmute enabled (DAC_MUTE_RAMP = 1 and DAC_UNMUTE_RAMP = 1) DAC_MUTE = 0 DAC_MUTE = 1 DAC_MUTE = 0 DAC_MUTE_RAMP = 1 and DAC_UNMUTE_RAMP = 1 Figure 31 DAC Mute Control 108 Rev 4.4 WM8962 The volume ramp rate during soft mute and un-mute is controlled by the DAC_MUTERATE bit as shown in Table 62. REGISTER ADDRESS R5 (05h) ADC & DAC Control 1 BIT LABEL DEFAULT DESCRIPTION 4 DAC_MUTE_RAMP 1 DAC Soft Mute Control 0 = Muting the DAC (DAC_MUTE = 1) will cause the volume to change immediately to mute. 1 = Muting the DAC (DAC_MUTE = 1) will cause the volume to ramp down gradually to mute. 3 DAC_MUTE 1 Digital DAC Mute 0 = Un-mute 1 = Mute Note that this bit also exists in R49. Reading or writing to either location has the same effect. R49 (31h) 4 DAC_MUTE 1 Digital DAC Mute 0 = Un-mute 1 = Mute Note that this bit also exists in R5. Reading or writing to either location has the same effect. R6 (06h) ADC & DAC Control 2 3 DAC_UNMUTE_RAMP 1 DAC Soft Unmute Control 0 = Unmuting the DAC (DAC_MUTE = 0) will cause the volume to change immediately to the DACL_VOL/DACR_VOL settings. 1 = Unmuting the DAC (DAC_MUTE = 0) will cause the volume to ramp up gradually to the DACL_VOL/DACR_VOL settings. 2 DAC_MUTERATE 0 DAC Soft Mute Ramp Rate 0 = Fast ramp (maximum ramp time 10.7ms) 1 = Slow ramp (maximum ramp time 171ms). Note that the ramp rate scales with sample rate (fs). Quoted values are correct for fs = 48kHz. Table 62 DAC Soft-Mute Control Rev 4.4 109 WM8962 DAC AUTO-MUTE The DAC digital mute and volume controls are described earlier in Table 60 and Table 62. The DAC also incorporates a digital auto-mute monitor, which is enabled by setting DAC_AUTOMUTE. When the auto-mute is enabled, and a number (DAC_AUTOMUTE_SAMPLES) of consecutive zero-samples is detected, the AUTOMUTE_STS flag is asserted. The WM8962 supports the option to automatically power-down the speaker path when the DAC AutoMute is triggered, and to re-enable the speaker path when audio data is detected. This feature has been designed to work around the Write Sequencer, which mutes and unmutes the speakers in a controlled manner using the Speaker Sleep (see Table 128) and Speaker Wake (see Table 129) write sequences. Auto-mute is enabled by setting the WSEQ_AUTOSEQ_ENA bit in Register R87. See Table 63 for details of this and other Auto-mute register bits. The status of DAC Auto-Mute can be read back from the AUTOMUTE_STS bit. REGISTER ADDRESS R9 (09h) Audio Interface 0 R87 (57h) Write Sequencer Control 1 BIT LABEL DEFAULT DESCRIPTION 11 AUTOMUTE_STS 0 Readback of the DAC Automute status 0 = Automute not detected 1 = Automute detected 9:8 DAC_AUTOMUT E_SAMPLES [1:0] 11 Selects the number of consecutive zero DAC samples that will be interpreted as an Automute. 00 = 128 samples 01 = 256 samples 10 = 512 samples 11 = 1024 samples 7 DAC_AUTOMUT E 0 DAC Auto-Mute Control 0 = Disabled 1 = Enabled 7 WSEQ_AUTOSE Q_ENA 0 Write Sequencer Auto-Sequence Enable (controls the Class D driver via DAC Auto-Mute function) 0 = Disabled 1 = Enabled Table 63 DAC Auto Mute DAC MONO MIX A DAC digital mono-mix mode can be enabled using the DAC_MONOMIX register bit. This mono mix will be output on whichever DAC is enabled. To prevent clipping, a -6dB attenuation is automatically applied to the mono mix. The mono mix is only supported when one or other DAC is disabled. When the mono mix is selected, then the mono mix is output on the enabled DAC only; there is no output from the disabled DAC. If DACL_ENA and DACR_ENA are both set, then stereo operation applies. REGISTER ADDRESS R57(39h) DAC DSP Mixing (1) BIT 9 LABEL DAC_MONOMIX DEFAULT 0 DESCRIPTION DAC Mono Mix 0 = Stereo 1 = Mono (Mono mix output on enabled DAC) Mono Mix is only supported when one or other DAC is disabled. When Mono mix is enabled, 6dB attenuation is applied. Table 64 DAC Mono Mix 110 Rev 4.4 WM8962 DAC DE-EMPHASIS Digital de-emphasis can be applied to the DAC playback data (e.g. when the data comes from a CD with pre-emphasis used in the recording). De-emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz. REGISTER ADDRESS R5 (05h) ADC & DAC Control 1 BIT 2:1 LABEL DAC_DEEMP [1:0] DEFAULT 00 DESCRIPTION De-Emphasis Control 00 = No de-emphasis 01 = De-emphasis for 32kHz sample rate 10 = De-emphasis for 44.1kHz sample rate 11 = De-emphasis for 48kHz sample rate Table 65 DAC De-Emphasis Control DAC OVERSAMPLING RATIO (OSR) The DAC oversampling rate is programmable to allow power consumption versus audio performance trade-offs. The default oversampling rate is low for reduced power consumption; using the higher OSR setting improves the DAC signal-to-noise performance. See the “Reference Voltages and Bias Control” section for details of the supported bias control settings for the output signal paths. REGISTER ADDRESS R6 (06h) ADC & DAC Control 2 BIT LABEL DEFAULT DESCRIPTION 0 DAC_HP 0 DAC Oversampling Ratio 0 = Low Power (typically 64 x fs) 1 = High Performance (typically 128 x fs) Table 66 DAC Oversampling Control Rev 4.4 111 WM8962 DIGITAL BEEP GENERATOR The WM8962 provides a digital signal generator which can be used to inject an audio tone (beep) into the DAC signal path. The output of the beep generator is digitally mixed with the DAC outputs, after the DAC digital volume. The beep is enabled using BEEP_ENA. The beep function creates an approximation of a Sine wave. The audio frequency is set using BEEP_RATE, and is dependent on the SAMPLE_RATE_INT_MODE and the SAMPLE_RATE settings (see “Clocking and Sample Rates” section). The beep volume is set using BEEP_GAIN. Note that the volume of the digital beep generator is not affected by the DAC volume or DAC mute controls. The digital beep generator control fields are described in Table 67. REGISTER ADDRESS BIT LABEL DEFAULT R110 (6Eh) Beep Generator (1) 7:4 BEEP_GAIN [3:0] 0000 2:1 BEEP_RATE [1:0] 01 Digital Beep Waveform Control If SAMPLE_RATE_INT_MODE = 1 00 = 500Hz 01 = 1000Hz 10 = 2000Hz 11 = 4000Hz If SAMPLE_RATE_INT_MODE = 0 00 = 499Hz – 502Hz 01 = 999Hz – 1003Hz 10 = 1998Hz – 2005Hz 11 = 3997Hz – 4009Hz BEEP_ENA 0 Digital Beep Enable 0 = Disabled 1 = Enabled Note that the DAC and associated signal path needs to be enabled when using the digital beep. 0 DESCRIPTION Digital Beep Volume Control 0000 = mute 0001 = -90dB 0010 = -84dB … (6dB steps) 1111 = -6dB Table 67 Digital Beep Generator 112 Rev 4.4 Rev 4.4 DAC IN4R MIXINR DACR_VOL DAC_MUTE DAC_MUTE_RAMP DAC_UNMUTE_RAMP DAC_MUTERATE DACR_ENA IN4L_TO_SPKMIXL / IN4L_SPKMIXL_VOL * * + DACR_TO_HPMIXL * * * MIXINR_TO_HPMIXL / MIXINR_HPMIXL_VOL MIXINR_TO_HPMIXR / MIXINR_HPMIXR_VOL MIXINL_TO_HPMIXR / MIXINL_HPMIXR_VOL + + * * * * + 0 0 1 -73 to 6dB 1dB steps, mute HPOUTL_VOL HPOUTL_ZC HPOUT_VU HPOUTL_PGA_MUTE HPOUTL HPOUTL_PGA_ENA -73 to 6dB 1dB steps, mute SPKOUTL_VOL SPKOUTL_ZC SPKOUT_VU SPKOUTL_PGA_MUTE -73 to 6dB 1dB steps, mute IN4L * = 0dB or -6dB = -15dB to +6dB MIXER PGA KEY 1 -73 to 6dB 1dB steps, mute SPKOUTL_ENA CLASSD_VOL SPKR -7 to 0dB 1dB steps HP1R -7 to 0dB 1dB steps HP1L HP1R_ENA HP1R_VOL HP1L_VOL HP1L_ENA 0dB to 9dB 1.5dB steps, plus 12dB SPKL SPKOUTR_ENA CLASSD_VOL SPKOUTR_VOL 0dB to 9dB SPKOUTR_ZC 1.5dB steps, SPKOUT_VU plus 12dB SPKOUTR_PGA_MUTE HPOUTR_VOL HPOUTR_ZC HPOUT_VU HPOUTR_PGA_MUTE SPKMIXR_TO_SPKOUTR_PGA 0 SPKOUTR SPKOUTR_PGA_ENA 0 1 HPMIXR_TO_HPOUTR_PGA 0 HPOUTR HPOUTR_PGA_ENA 0 SPKMIXR SPKMIXR_ENA / SPKMIXR_MUTE DACL_TO_SPKMIXR / DACL_SPKMIXR_VOL DACR_TO_SPKMIXR / DACR_SPKMIXR_VOL IN4L_TO_SPKMIXR / IN4L_SPKMIXR_VOL MIXINL_TO_SPKMIXR / MIXINL_SPKMIXR_VOL IN4R_TO_SPKMIXR / IN4R_SPKMIXR_VOL 0 SPKOUTL SPKOUTL_PGA_ENA HPMIXL_TO_HPOUTL_PGA HPMIXR HPMIXR_ENA / HPMIXR_MUTE DACL_TO_HPMIXR DACR_TO_HPMIXR IN4L_TO_HPMIXR / IN4L_HPMIXR_VOL IN4R_TO_HPMIXR / IN4R_HPMIXR_VOL IN4R_TO_HPMIXL / IN4R_HPMIXL_VOL * MIXINL_TO_HPMIXL / MIXINL_HPMIXL_VOL IN4L_TO_HPMIXL / IN4L_HPMIXL_VOL 0 1 SPKMIXL_TO_SPKOUTL_PGA HPMIXL HPMIXL_ENA / HPMIXL_MUTE DACL_TO_HPMIXL / MIXINR_TO_SPKMIXL / MIXINR_SPKMIXL_VOL IN4R_TO_SPKMIXL / IN4R_SPKMIXL_VOL MIXINL_TO_SPKMIXL / MIXINL_SPKMIXL_VOL MIXINR_TO_SPKMIXR / MIXINR_SPKMIXR_VOL MIXINL Digital Beep Generator DAC SIGNAL PROCESSING DAC * * SPKMIXL SPKMIXL_ENA / SPKMIXL_MUTE DACL_TO_SPKMIXL / DACL_SPKMIXL_VOL DACR_TO_SPKMIXL / DACR_SPKMIXL_VOL IN4R DACL_VOL DAC_MUTE DAC_MUTE_RAMP DAC_UNMUTE_RAMP DAC_MUTERATE DACL_ENA IN4L MIXINR MIXINL SPKOUTRN SPKOUTRP HPOUTR HPOUTFB HPOUTL SPKOUTLP SPKOUTLN WM8962 OUTPUT SIGNAL PATH The WM8962 input routing and mixers provide a high degree of flexibility, allowing operation of many simultaneous signal paths through the device to the output devices. The analogue output devices are a pair of stereo Headphone Output drivers and a pair of Speaker Output drivers. Support for mono signal output is also provided. The output signal paths and associated control registers are illustrated in Figure 32. MIXINR IN4R MIXINL DACR IN4L DACR DACL DACL Figure 32 Output Signal Paths 113 WM8962 OUTPUT SIGNAL PATHS ENABLE The four output mixers, and each analogue output pin and associated PGA, can be independently enabled or disabled using the register bits described in Table 68. The Class D speaker drivers are controlled using SPKOUTL_ENA and SPKOUTR_ENA. The headphone drivers are controlled by HP1L_ENA and HP1R_ENA. To enable the output PGAs, the reference voltage VMID and the bias current must also be enabled. See “Reference Voltages and Bias Control” for details of the associated controls VMID_SEL and BIAS_ENA. Note that the Speaker and Headphone outputs, the Speaker and Headphone PGAs, and the Speaker and headphone mixers are all disabled by default. The required signal paths must be enabled and unmuted using the control bits described in the respective tables below. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R26 (1Ah) Pwr Mgmt (2) 6 HPOUTL_PGA_E NA 0 5 HPOUTR_PGA_E NA 0 4 SPKOUTL_PGA_ ENA 0 3 SPKOUTR_PGA_ ENA 0 7 SPKOUTR_ENA 0 6 SPKOUTL_ENA 0 4 HP1L_ENA 0 Headphone Left PGA enable 0 = Disabled 1 = Enabled Headphone Right PGA enable 0 = Disabled 1 = Enabled Speaker Left PGA enable 0 = Disabled 1 = Enabled Speaker Right PGA enable 0 = Disabled 1 = Enabled Right channel class D Speaker Enable 0 = Disabled 1 = Enabled Left channel class D Speaker Enable 0 = Disabled 1 = Enabled Enables HP1L input stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set as the final stage of the HP1L Enable sequence. 0 HP1R_ENA 0 Enables HP1R input stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set as the final stage of the HP1R Enable sequence. 3 HPMIXL_ENA 0 Left Headphone Mixer Enable 0 = Disabled 1 = Enabled 2 HPMIXR_ENA 0 Right Headphone Mixer Enable 0 = Disabled 1 = Enabled 1 SPKMIXL_ENA 0 Left Speaker Mixer Enable 0 = Disabled 1 = Enabled 0 SPKMIXR_ENA 0 Right Speaker Mixer Enable 0 = Disabled 1 = Enabled R49 (31h) Class D Control (1) R69 (45h) Analogue HP 0 R99 (63h) Mixer Enables Table 68 Output Signal Paths Enable 114 Rev 4.4 WM8962 SPEAKER OUTPUT PATHS The following sections describe all the speaker output paths and controls. For information on the headphone output paths and controls, refer to the “Headphone Output Paths” section. SPEAKER MIXER CONTROL The two speaker mixers - SPKMIXL and SPKMIXR – can each have any combination of the six available input paths enabled as described in Table 69 (left speaker mixer) and Table 70 (right speaker mixer). The six input signal paths are two from the DACs (DACL and DACR), two from the input mixers (MIXINL and MIXINR) and two bypass paths direct from the IN4 input pins (IN4L and IN4R). The speaker mixers are muted by default. The two signal paths from the left and right DACs to each of the two speaker mixers SPKMIXL and SPKMIXR are enabled using the register bits DACL_TO_SPKMIXL, DACL_TO_SPKMIXR, DACR_TO_SPKMIXL and DACR_TO_SPKMIXR. A selectable -6dB control is available on each of these paths to help avoid signal clipping. The two DAC output signals can also be configured to bypass the speaker mixers using the SPKMIXL_TO_SPKOUTL_PGA and SPKMIXR_TO_SPKOUTR_PGA register bits. Note that the DAC output signals bypass the mixers by default. The direct signal paths from each of the input mixers MIXINL and MIXINR to each of the speaker mixers SPKMIXL and SPKMIXR are enabled using the MIXINL_TO_SPKMIXL, MIXINL_TO_SPKMIXR, MIXINR_TO_SPKMIXL and MIXINR_TO_SPKMIXR register bits. A selectable -6dB control is available on each of these paths to help avoid signal clipping. The direct signal paths from the IN4L and IN4R input pins to the speaker mixers SPKMIXL and SPKMIXR are enabled using the IN4L_TO_SPKMIXL, IN4L_TO_SPKMIXR, IN4R_TO_SPKMIXL, and IN4R_TO_SPKMIXR register bits. Each input signal path from IN4 also has an associated PGA with a gain range from -15dB to +6dB. Rev 4.4 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R105 (69h) Speaker Mixer (1) 7 SPKMIXL_TO_SP KOUTL_PGA 0 Left Speaker PGA Path Select 0 = DACL Output 1 = SPKMIXL Output 5 DACL_TO_SPKM IXL 0 Left DAC to Left Speaker Mixer select 0 = Disabled 1 = Enabled 4 DACR_TO_SPKM IXL 0 Right DAC to Left Speaker Mixer select 0 = Disabled 1 = Enabled 3 MIXINL_TO_SPK MIXL 0 Left Input Mixer to Left Speaker Mixer select 0 = Disabled 1 = Enabled 2 MIXINR_TO_SPK MIXL 0 Right Input Mixer to Left Speaker Mixer select 0 = Disabled 1 = Enabled 1 IN4L_TO_SPKMI XL 0 Input IN4L to Left Speaker Mixer select 0 = Disabled 1 = Enabled 0 IN4R_TO_SPKMI XL 0 Input IN4R to Left Speaker Mixer select 0 = Disabled 1 = Enabled 115 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT R107 (6Bh) Speaker Mixer (3) 8 SPKMIXL_MUTE 1 Left Speaker Mixer Mute 0 = Unmuted 1 = Muted 7 MIXINL_SPKMIX L_VOL 0 Left Input Mixer to Left Speaker Mixer volume 0 = 0dB 1 = -6dB 6 MIXINR_SPKMIX L_VOL 0 Right Input Mixer to Left Speaker Mixer volume 0 = 0dB 1 = -6dB 5:3 IN4L_SPKMIXL_ VOL 111 Input IN4L to Left Speaker Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 2:0 IN4R_SPKMIXL_ VOL 111 Input IN4R to Left Speaker Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 7 DACL_SPKMIXL_ VOL 0 Left DAC to Left Speaker Mixer volume 0 = 0dB 1 = -6dB 6 DACR_SPKMIXL _VOL 0 Right DAC to Left Speaker Mixer volume 0 = 0dB 1 = -6dB R109 (6Dh) Speaker Mixer (5) DESCRIPTION Table 69 Left Speaker Mixer Control 116 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R106 (6Ah) Speaker Mixer (2) 7 SPKMIXR_TO_S PKOUTR_PGA 0 Right Speaker PGA Path Select 0 = DACR Output 1 = SPKMIXR Output 5 DACL_TO_SPKM IXR 0 Left DAC to Right Speaker Mixer select 0 = Disabled 1 = Enabled 4 DACR_TO_SPKM IXR 0 Right DAC to Right Speaker Mixer select 0 = Disabled 1 = Enabled Rev 4.4 WM8962 REGISTER ADDRESS R108 (6Ch) Speaker Mixer (4) R109 (6Dh) Speaker Mixer (5) BIT LABEL DEFAULT DESCRIPTION 3 MIXINL_TO_SPK MIXR 0 Left Input Mixer to Right Speaker Mixer select 0 = Disabled 1 = Enabled 2 MIXINR_TO_SPK MIXR 0 Right Input Mixer to Right Speaker Mixer select 0 = Disabled 1 = Enabled 1 IN4L_TO_SPKMI XR 0 Input IN4L to Right Speaker Mixer select 0 = Disabled 1 = Enabled 0 IN4R_TO_SPKMI XR 0 Input IN4R to Right Speaker Mixer select 0 = Disabled 1 = Enabled 8 SPKMIXR_MUTE 1 Right Speaker Mixer Mute 0 = Unmuted 1 = Muted 7 MIXINL_SPKMIX R_VOL 0 Left Input Mixer to Right Speaker Mixer volume 0 = 0dB 1 = -6dB 6 MIXINR_SPKMIX R_VOL 0 Right Input Mixer to Right Speaker Mixer volume 0 = 0dB 1 = -6dB 5:3 IN4L_SPKMIXR_ VOL 111 Input IN4L to Right Speaker Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 2:0 IN4R_SPKMIXR_ VOL 111 Input IN4R to Right Speaker Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 5 DACL_SPKMIXR _VOL 0 Left DAC to Right Speaker Mixer volume 0 = 0dB 1 = -6dB 4 DACR_SPKMIXR _VOL 0 Right DAC to Right Speaker Mixer volume 0 = 0dB 1 = -6dB Table 70 Right Speaker Mixer Control Rev 4.4 117 WM8962 SPEAKER OUTPUT PGA CONTROL There are four speaker output PGAs – two primary (SPKOUTL and SPKOUTR), and two secondary (SPKL, SPKR). The speaker outputs are each controlled by a primary PGA and a secondary PGA in series. The SPKOUTL and SPKOUTR PGAs give a high degree of control from -68dB to +6dB in 1dB steps. A detailed table of all SPKOUTL and SPKOUTR gain settings is shown in Table 72. Dedicated secondary PGAs are provided for each of the SPKOUT output pins. The secondary PGAs provide control from 0dB to +9dB in 1.5dB steps, and +12dB, on each channel. See Figure 32 for a representation of this layout. The direct signal paths from the IN4L and IN4R input pins to the speaker mixers SPKMIXL and SPKMIXR are enabled using the IN4L_TO_SPKMIXL, IN4L_TO_SPKMIXR, IN4R_TO_SPKMIXL, and IN4R_TO_SPKMIXR register bits. Each input signal path from IN4 also has an associated PGA with a gain range from -15dB to +6dB. To minimise pop and zipper noise, it is recommended that only SPKOUTL PGA and SPKOUTR PGA are modified while the output signal path is active as these are the only Speaker PGAs with Zero Cross. In the case of a long period without zero-crossings, a timeout function is provided. When the zero-cross function is enabled, the volume will update after the timeout period if no earlier zero-cross has occurred. The timeout clock is enabled using TOCLK_ENA; the timeout period is set by TOCLK_DIV. See “Clocking and Sample Rates” for more information on these fields. It is recommended that the other gain controls on the signal paths should not be modified while the signal path is active. The left and right channels on the SPKOUT pins can be boosted using the CLASSD_VOL register. Note that both left and right channels are updated simultaneously with the CLASSD_VOL register. The speaker output signal can be muted using the SPKOUTL_PGA_MUTE SPKOUTR_PGA_MUTE registers. The speaker outputs are un-muted by default. and The SPKOUT_VU bits control the loading of the speaker PGA volume data. When SPKOUT_VU is set to 0, the volume control data will be loaded into the respective control register, but will not actually change the gain setting. The left and right Speaker PGA volume settings are both updated when a 1 is written to any of the SPKOUT_VU bits. This makes it possible to update the gain of the left and right output paths simultaneously. The Speaker PGA volume control register fields are described in Table 71. REGISTER ADDRESS R40 (28h) SPKOUTL volume BIT LABEL DEFAULT DESCRIPTION 8 SPKOUT_VU N/A Speaker Output PGA Volume Update Writing a 1 to this bit will update SPKOUTL_VOL and SPKOUTR_VOL volumes simultaneously. 7 SPKOUTL_ZC 0 SPKOUTL_VOL (Left Speaker Output PGA) Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled 6:0 SPKOUTL_VOL [6:0] 00h (Mute) Left Speaker Output PGA Volume 000_0000 to 010_1111 = Mute 011_0000 to 011_0101 = -68dB 011_0110 = -67dB …in 1dB steps 111_1001 = 0dB … 111_1111 = +6dB (See Table 72 for output PGA volume control range) 118 Rev 4.4 WM8962 REGISTER ADDRESS R41 (29h) SPKOUTR volume BIT LABEL 8 SPKOUT_VU 7 SPKOUTR_ZC 6:0 SPKOUTR_VOL [6:0] DEFAULT DESCRIPTION N/A Speaker Output PGA Volume Update Writing a 1 to this bit will update SPKOUTL_VOL and SPKOUTR_VOL volumes simultaneously. 0 SPKOUTR_VOL (Right Speaker Output PGA) Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled 00h (Mute) Right Speaker Output PGA Volume 000_0000 to 010_1111 = Mute 011_0000 to 011_0101 = -68dB 011_0110 = -67dB …in 1dB steps 111_1001 = 0dB … 111_1111 = +6dB (See Table 72 for output PGA volume control range) R49 (31h) Class D Control 1 2 SPKOUT_VU N/A Speaker Output PGA Volume Update Writing a 1 to this bit will update SPKOUTL_VOL and SPKOUTR_VOL volumes simultaneously. 1 SPKOUTL_PGA_MUTE 0 SPKOUTL_VOL (Left Speaker Output PGA) Mute 0 = Un-mute 1 = Mute 0 SPKOUTR_PGA_MUTE 0 SPKOUTR_VOL (Right Speaker Output PGA) Mute 0 = Un-mute 1 = Mute Table 71 Speaker Output PGA (SPKOUTL_VOL, SPKOUTR_VOL) Control Rev 4.4 119 WM8962 HPOUTL_VOL [6:0], HPOUTR_VOL [6:0], SPKOUTL_VOL [6:0] or SPKOUTR_VOL [6:0] VOLUME (dB) HPOUTL_VOL [6:0], HPOUTR_VOL [6:0], SPKOUTL_VOL [6:0] or SPKOUTR_VOL [6:0] VOLUME (dB) 000_0000 to 010_1111 Mute 101_1010 -31 011_0000 to 011_0101 -68 101_1011 -30 011_0110 -67 101_1100 -29 011_0111 -66 101_1101 -28 011_1000 -65 101_1110 -27 011_1001 -64 101_1111 -26 011_1010 -63 110_0000 -25 011_1011 -62 110_0001 -24 011_1100 -61 110_0010 -23 011_1101 -60 110_0011 -22 011_1110 -59 110_0100 -21 011_1111 -58 110_0101 -20 100_0000 -57 110_0110 -19 100_0001 -56 110_0111 -18 100_0010 -55 110_1000 -17 100_0011 -54 110_1001 -16 100_0100 -53 110_1010 -15 100_0101 -52 110_1011 -14 100_0110 -51 110_1100 -13 100_0111 -50 110_1101 -12 100_1000 -49 110_1110 -11 100_1001 -48 110_1111 -10 100_1010 -47 111_0000 -9 100_1011 -46 111_0001 -8 100_1100 -45 111_0010 -7 100_1101 -44 111_0011 -6 100_1110 -43 111_0100 -5 100_1111 -42 111_0101 -4 101_0000 -41 111_0110 -3 101_0001 -40 111_0111 -2 101_0010 -39 111_1000 -1 101_0011 -38 111_1001 0 101_0100 -37 111_1010 +1 101_0101 -36 111_1011 +2 101_0110 -35 111_1100 +3 101_0111 -34 111_1101 +4 101_1000 -33 111_1110 +5 101_1001 -32 111_1111 +6 Table 72 Headphone PGA and Speaker PGA Volume Range SPEAKER OUTPUT CONFIGURATIONS The speaker outputs SPKOUT are driven by the two speaker PGAs SPKOUTL and SPKOUTR. Fine volume control is available on the speaker paths using the SPKOUTL_VOL and SPKOUTR_VOL PGAs. A volume boost function (CLASSD_VOL) is available on both the speaker paths. The speaker outputs SPKOUTL and SPKOUTR operate in a BTL configuration in Class D amplifier mode. The speaker outputs are capable of supporting up to 1W per channel into stereo 8 BTL loads, or 2W into a mono 4 BTL load. The connections for stereo and mono speaker configurations are shown in Figure 33 120 Rev 4.4 WM8962 SPKOUTLP SPKOUTLN SPKOUTLP SPKOUTLN 8Ω SPKOUTRN SPKOUTRP SPKOUTRN SPKOUTRP 4Ω 8Ω STEREO SPEAKER CONFIGURATION MONO SPEAKER CONFIGURATION SPK_MONO = 0, Class D driving into 8Ω loads SPK_MONO = 1, Class D driving into 4Ω load Figure 33 Mono and Stereo Speaker Output Configuration Eight levels of AC signal boost are provided in order to deliver maximum output power for many commonly-used SPKVDD/AVDD combinations. The AC boost levels from 0dB to +12dB are selected using register bit CLASSD_VOL, which boosts left and right channels equally. To prevent pop noise, CLASSD_VOL should not be modified while the speaker outputs are enabled. Figure 34 illustrates the speaker outputs and gain/boost options available. Ultra-low leakage and high PSRR allow the speaker supply SPKVDD to be directly connected to a lithium battery. Note that an appropriate SPKVDD supply voltage must be provided to prevent waveform clipping when speaker boost is used. DC gain is applied automatically with a shift from VMID to SPKVDD/2. This provides optimum signal swing for maximum output power. AVDD SPKVDD SPKOUTL_VOL[6:0] CLASSD_VOL[2:0] SPKOUTLP SPKOUTLN -73dB to +6dB, 1dB steps SPKGND AGND AVDD SPKOUTR_VOL[6:0] SPKVDD CLASSD_VOL[2:0] SPKOUTRP SPKOUTRN -73dB to +6dB, 1dB steps SPKGND AGND SPKVDD CLASSD_VOL 000 = 1.00x (+0dB) 001 = 1.19x (+1.5dB) 010 = 1.41x (+3.0dB) 011 = 1.68x (+4.5dB) 100 = 2.00x (+6.0dB) 101 = 2.37x (+7.5dB) 110 = 2.81x (+9.0dB) 111 = 3.98x (+12.0dB) AVDD Signal x BOOST SPKVDD/2 VMID AGND Signal x BOOST is automatically centred around SPKVDD/2 Figure 34 Speaker Output Configuration and AC Boost Operation Rev 4.4 121 WM8962 REGISTER ADDRESS R51 (33h) Class D Control 2 BIT LABEL 6 SPK_MONO 2:0 CLASSD_VOL DEFAULT DESCRIPTION 0 Mono Speaker Configuration enable 0 = Class D drives into 8 ohm loads 1 = Class D drives into a mono 4 ohm load When SPK_MONO is enabled, both speakers output the signal from the left channel. Note that the user must tie the outputs together for mono use 011 AC Speaker Gain Boost. Note that both left and right channels are boosted equally 000 = 1.00x boost (+0dB) 001 = 1.19x boost (+1.5dB) 010 = 1.41x boost (+3.0dB) 011 = 1.68x boost (+4.5dB) 100 = 2.00x boost (+6.0dB) 101 = 2.37x boost (+7.5dB) 110 = 2.81x boost (+9.0dB) 111 = 3.98x boost (+12.0dB) Table 73 Class D Speaker Driver Control 122 Rev 4.4 WM8962 HEADPHONE OUTPUT PATHS The following sections describe all the headphone output paths and controls. For information on the speaker output paths and controls, refer to the earlier “Speaker Output Paths” section. HEADPHONE SIGNAL PATHS ENABLE The WM8962 headphone drivers incorporate SilentSwitch technology which enables pops normally associated with Start-Up, Shut-Down or signal path control to be suppressed. To achieve maximum benefit from these features, careful attention is required to the sequence and timing of these controls. Note that, under the recommended usage conditions of the WM8962, these features will be configured by running the default Start-Up and Shut-Down sequences as described in the “Control Write Sequencer” section. In these cases, the user does not need to set these register fields directly. The Headphone output drivers can be actively switched to AGND through internal resistors if desired. This is desirable at start-up in order to achieve a known condition prior to enabling the output. This is also desirable in shutdown to prevent the external connections from being affected by the internal circuits. The HPOUTL and HPOUTR outputs are shorted to AGND by default; the short circuit is removed on each of these paths by setting the applicable fields HP1L_RMV_SHORT and HP1R_RMV_SHORT. The ground-referenced Headphone output drivers are designed to suppress pops and clicks when enabled or disabled. However, it is necessary to control the drivers in accordance with a defined sequence in start-up and shut-down to achieve the pop suppression. It is also necessary to schedule the DC Servo offset correction at the appropriate point in the sequence (see “DC Servo”). Table 74 and Table 75 describe the recommended sequences for enabling and disabling these output drivers. SEQUENCE HPOUT ENABLE Step 1 HP1L_ENA = 1 HP1R_ENA = 1 Step 2 20 μs delay Step 3 HP1L_ENA_DLY = 1 HP1R_ENA_DLY = 1 Step 4 DC offset correction Step 5 HP1L_ENA_OUTP = 1 HP1R_ENA_OUTP = 1 Step 6 20 μs delay Step 7 HP1L_RMV_SHORT = 1 HP1R_RMV_SHORT = 1 Table 74 Headphone Output Enable Sequence SEQUENCE HPOUT DISABLE Step 1 HP1L_RMV_SHORT = 0 HP1R_RMV_SHORT = 0 Step 2 20 μs delay Step 3 HP1L_ENA = 0 HP1L_ENA_DLY = 0 HP1L_ENA_OUTP = 0 HP1R_ENA = 0 HP1R_ENA_DLY = 0 HP1R_ENA_OUTP = 0 Table 75 Headphone Output Disable Sequence The register bits relating to pop suppression control are defined in Table 76. Rev 4.4 123 WM8962 REGISTER ADDRESS R69 (45h) Analogue HP 0 BIT LABEL DEFAULT DESCRIPTION 7 HP1L_RMV_SHO RT 0 Removes HP1L short 0 = HP1L short enabled 1 = HP1L short removed For pop-free operation, this bit should be set to 1 as the final step in the HP1L Enable sequence. 6 HP1L_ENA_OUT P 0 Enables HP1L output stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set to 1 after the DC offset cancellation has been performed. 5 HP1L_ENA_DLY 0 Enables HP1L intermediate stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set to 1 after the output signal path has been configured, and before the DC Offset cancellation is scheduled This bit should be set with at least 20us delay after HP1L_ENA. 4 HP1L_ENA 0 Enables HP1L input stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set as the first stage of the HP1L Enable sequence. 3 HP1R_RMV_SHO RT 0 Removes HP1R short 0 = HP1R short enabled 1 = HP1R short removed For pop-free operation, this bit should be set to 1 as the final step in the HP1R Enable sequence. 2 HP1R_ENA_OUT P 0 Enables HP1R output stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set to 1 after the DC offset cancellation has been performed. 1 HP1R_ENA_DLY 0 Enables HP1R intermediate stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set to 1 after the output signal path has been configured, and before the DC Offset cancellation is scheduled This bit should be set with at least 20us delay after HP1R_ENA. 0 HP1R_ENA 0 Enables HP1R input stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set as the first stage of the HP1R Enable sequence. Table 76 Headphone Output Signal Paths Control 124 Rev 4.4 WM8962 HEADPHONE MIXER CONTROL The two headphone mixers - HPMIXL and HPMIXR – can each have any combination of the six available input paths enabled as described in Table 77 (left headphone mixers) and Table 78 (right headphone mixers). The six input signal paths are two from the DACs (DACL and DACR), two from the input mixers (MIXINL and MIXINR) and two bypass paths direct from the IN4 input pins (IN4L and IN4R). The headphone mixers are muted by default. The two signal paths from the left and right DACs to each of the two headphone mixers HPMIXL and HPMIXR are enabled using the register bits DACL_TO_HPMIXL, DACL_TO_HPMIXR, DACR_TO_HPMIXL and DACR_TO_HPMIXR. There is no selectable gain associated with these mixer paths. The two DAC output signals can also be configured to bypass the headphone mixers using the HPMIXL_TO_HPOUTL_PGA and HPMIXR_TO_HPOUTR_PGA register bits. Note that the DAC output signals bypass the mixers by default. The direct signal paths from each of the input mixers MIXINL and MIXINR to each of the headphone mixers HPMIXL and HPMIXR are enabled using the MIXINL_TO_HPMIXL, MIXINL_TO_HPMIXR, MIXINR_TO_HPMIXL and MIXINR_TO_HPMIXR register bits. A selectable -6dB control is available on each of these paths to help avoid signal clipping. The direct signal paths from the IN4L and IN4R input pins to the headphone mixers HPMIXL and HPMIXR are enabled using the IN4L_TO_HPMIXL, IN4L_TO_HPMIXR, IN4R_TO_HPMIXL, and IN4R_TO_HPMIXR register bits. Each input signal path from IN4 also has an associated PGA with a gain range from -15dB to +6dB. REGISTER ADDRESS R100 (64h) Headphone Mixer (1) R102 (66h) Headphone Mixer (3) Rev 4.4 BIT LABEL DEFAULT DESCRIPTION 7 HPMIXL_TO_HP OUTL_PGA 0 Left Headphone PGA Path Select 0 = DACL Output 1 = HPMIXL Output 5 DACL_TO_HPMI XL 0 Left DAC to Left Headphone Mixer select 0 = Disabled 1 = Enabled 4 DACR_TO_HPMI XL 0 Right DAC to Left Headphone Mixer select 0 = Disabled 1 = Enabled 3 MIXINL_TO_HPM IXL 0 Left Input Mixer to Left Headphone Mixer select 0 = Disabled 1 = Enabled 2 MIXINR_TO_HP MIXL 0 Right Input Mixer to Left Headphone Mixer select 0 = Disabled 1 = Enabled 1 IN4L_TO_HPMIX L 0 Input IN4L to Left Headphone Mixer select 0 = Disabled 1 = Enabled 0 IN4R_TO_HPMIX L 0 Input IN4R to Left Headphone Mixer select 0 = Disabled 1 = Enabled 8 HPMIXL_MUTE 1 Left Headphone Mixer Mute 0 = Unmuted 1 = Muted 7 MIXINL_HPMIXL_ VOL 0 Left Input Mixer to Left Headphone Mixer volume 0 = 0dB 1 = -6dB 125 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 6 MIXINR_HPMIXL _VOL 0 Right Input Mixer to Left Headphone Mixer volume 0 = 0dB 1 = -6dB 5:3 IN4L_HPMIXL_V OL 111 Input IN4L to Left Headphone Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 2:0 IN4R_HPMIXL_V OL 111 Input IN4R to Left Headphone Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Table 77 Left Headphone Mixer Control REGISTER ADDRESS R101 (65h) Headphone Mixer (2) 126 BIT LABEL DEFAULT DESCRIPTION 7 HPMIXR_TO_HP OUTR_PGA 0 Right Headphone PGA Path Select 0 = DACR Output 1 = HPMIXR Output 5 DACL_TO_HPMI XR 0 Left DAC to Right Headphone Mixer select 0 = Disabled 1 = Enabled 4 DACR_TO_HPMI XR 0 Right DAC to Right Headphone Mixer select 0 = Disabled 1 = Enabled 3 MIXINL_TO_HPM IXR 0 Left Input Mixer to Right Headphone Mixer select 0 = Disabled 1 = Enabled 2 MIXINR_TO_HP MIXR 0 Right Input Mixer to Right Headphone Mixer select 0 = Disabled 1 = Enabled 1 IN4L_TO_HPMIX R 0 Input IN4L to Right Headphone Mixer select 0 = Disabled 1 = Enabled 0 IN4R_TO_HPMIX R 0 Input IN4R to Right Headphone Mixer select 0 = Disabled 1 = Enabled Rev 4.4 WM8962 REGISTER ADDRESS R103 (67h) Headphone Mixer (4) BIT LABEL DEFAULT DESCRIPTION 8 HPMIXR_MUTE 1 Right Headphone Mixer Mute 0 = Unmuted 1 = Muted 7 MIXINL_HPMIXR _VOL 0 Left Input Mixer to Right Headphone Mixer volume 0 = 0dB 1 = -6dB 6 MIXINR_HPMIXR _VOL 0 Right Input Mixer to Right Headphone Mixer volume 0 = 0dB 1 = -6dB 5:3 IN4L_HPMIXR_V OL 111 Input IN4L to Right Headphone Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 2:0 IN4R_HPMIXR_V OL 111 Input IN4R to Right Headphone Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Table 78 Right Headphone Mixer Control Rev 4.4 127 WM8962 HEADPHONE OUTPUT PGA CONTROL There are four headphone output PGAs – two primary (HPOUTL and HPOUTR), and two secondary (HP1L, HP1R). The headphone outputs are each controlled by a primary PGA and a secondary PGA in series. The HPOUTL and HPOUTR PGAs give a high degree of control from -68dB to +6dB in 1dB steps. A detailed table of all HPOUTL and HPOUTR gain settings is shown in Table 72. Secondary PGAs for HPOUTL and HPOUTR provide control from -7dB to 0dB in 1dB steps on each channel. See Figure 32 for a representation of this layout. The HPOUT PGAs are controlled using the HPOUTL_VOL and HPOUTR_VOL registers, providing fine volume control to HPOUTL and HPOUTR. To prevent "zipper noise", a zero-cross function is provided on the HPOUTL and HPOUTR output PGAs. When this feature is enabled, volume updates will not take place until a zero-crossing is detected. In the case of a long period without zero-crossings, a timeout function is provided. When the zero-cross function is enabled, the volume will update after the timeout period if no earlier zero-cross has occurred. The timeout clock is enabled using TOCLK_ENA; the timeout period is set by TOCLK_DIV. See “Clocking and Sample Rates” for more information on these fields. It is recommended that only HPOUTL PGA and HPOUTR PGA are modified while the output signal path is active as these are the only Headphone PGAs with the zero-cross function. It is recommended that the other gain controls on the signal paths should not be modified while the signal path is active. The left and right channels can also be attenuated independently using the HP1L_VOL and HP1R_VOL registers. Note that there is no zero-cross function associated with these registers. The headphone output signal can be muted using the HPOUTL_PGA_MUTE HPOUTR_PGA_MUTE registers. The headphone outputs are un-muted by default. and The HPOUT_VU bits control the loading of the Headphone Output PGA volume data and the PGA mute functions. When HPOUT_VU is set to 0, the volume control data will be loaded into the respective control register, but will not actually change the gain setting. The left and right Headphone Output PGA volume settings are both updated when a 1 is written to any of the HPOUT_VU bits. Similarly, the HPOUTL_PGA_MUTE and HPOUTR_PGA_MUTE settings are only effective when a 1 is written to either HPOUT_VU bit. This makes it possible to update the gain of the left and right output paths simultaneously. Note that the HP1L_VOL and HP1R_VOL registers are effective immediately when updated; the HPOUT_VU bits have no control over the Secondary PGA volume registers. For best performance, the Secondary PGA volume registers should be set to 000b (-7dB). See “Reference Voltages and Bias Control” for further details of the High Performance headphone playback configuration. REGISTER ADDRESS R2 (2h) HPOUTL volume BIT LABEL DEFAULT DESCRIPTION Headphone Output PGA Volume and Mute Update. Writing 1 to this bit will cause the HPOUTL and HPOUTR volume and mute settings to be updated simultaneously. 8 HPOUT_VU N/A 7 HPOUTL_ZC 0 6:0 HPOUTL_VOL [6:0] 0 (Mute) Left Headphone Output PGA Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled Left Headphone Output PGA Volume 000_0000 to 010_1111 = Mute 011_0000 to 011_0101 = -68dB 011_0110 = -67dB …in 1dB steps 111_1001 = 0dB … 111_1111 = +6dB (See Table 72 for full volume control range) 128 Rev 4.4 WM8962 REGISTER ADDRESS R3 (2h) HPOUTR volume BIT LABEL 8 HPOUT_VU 7 HPOUTR_ZC 6:0 HPOUTR_VOL [6:0] DEFAULT DESCRIPTION N/A Headphone Output PGA Volume and Mute Update Writing 1 to this bit will cause the HPOUTL and HPOUTR volume and mute settings to be updated simultaneously. 0 0 (Mute) Right Headphone Output PGA Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled Right Headphone Output PGA Volume 000_0000 to 010_1111 = Mute 011_0000 to 011_0101 = -68dB 011_0110 = -67dB …in 1dB steps 111_1001 = 0dB … 111_1111 = +6dB (See Table 72 for full volume control range) R26 (1A) Pwr Mgmt (2) R71 (47h) Analogue HP 2 1 HPOUTL_PGA_MUTE 0 HPOUTL_VOL (Left Headphone Output PGA) Mute 0 = Un-mute 1 = Mute 0 HPOUTR_PGA_MUTE 0 HPOUTR_VOL (Right Headphone Output PGA) Mute 0 = Un-mute 1 = Mute 8:6 HP1L_VOL [2:0] 111 Headphone 1 Left Secondary PGA volume. 000 = -7dB 001 = -6dB 010 = -5dB 011 = -4dB 100 = -3dB 101 = -2dB 110 = -1dB 111 = 0dB (default) 5:3 HP1R_VOL [2:0] 111 Headphone 1 Right Secondary PGA volume. 000 = -7dB 001 = -6dB 010 = -5dB 011 = -4dB 100 = -3dB 101 = -2dB 110 = -1dB 111 = 0dB (default) Table 79 Headphone Output PGA (HPOUTL_VOL, HPOUTR_VOL, HP1L_VOL, HP1R_VOL) Control HEADPHONE OUTPUT CONFIGURATIONS The headphone output driver is capable of driving up to 25mW into a 16Ω or 32Ω load such as a stereo headset or headphones. The outputs are ground-referenced, eliminating any requirement for AC coupling capacitors. This is achieved by having separate positive and negative supply rails Rev 4.4 129 WM8962 powered by an on-chip charge pump. A DC Servo circuit removes any DC offset from the headphone outputs, suppressing ‘pop’ noise and minimising power consumption. The Charge Pump and DC Servo are described separately (see “Charge Pump” and “DC Servo” respectively). It is recommended to connect a zobel network to the headphone output pins HPOUTL and HPOUTR for best audio performance in all applications. The components of the zobel network have the effect of dampening high frequency oscillations or instabilities that can arise outside the audio band under certain conditions. Possible sources of these instabilities include the inductive load of a headphone coil or an active load in the form of an external line amplifier. The capacitance of lengthy cables or PCB tracks can also lead to amplifier instability. The zobel network should comprise of a 20 resistor and 100nF capacitor in series with each other, as illustrated in Figure 35. Note that the zobel network may be unnecessary in some applications; it depends upon the characteristics of the connected load. It is recommended to include these components for best audio quality and amplifier stability in all cases. WM8962 HPOUTL HPOUTR HPOUTFB AGND = 0V 100 nF 100 nF 20Ω 20Ω AGND = 0V Figure 35 Zobel Network Components for HPOUTL and HPOUTR The headphone output incorporates a common mode, or ground loop, feedback path which provides rejection of system-related ground noise. The return path is via HPOUTFB. This pin must be connected to ground for normal operation of the headphone output. No register configuration is required. CHARGE PUMP The WM8962 incorporates a dual-mode Charge Pump which generates the supply rails for the headphone output drivers, HPOUTL and HPOUTR. The Charge Pump has a single supply input, CPVDD, and generates split rails CPVOUTP and CPVOUTN according to the selected mode of operation. The Charge Pump connections are illustrated in Figure 36 (see “Electrical Characteristics” for external component values). An input decoupling capacitor may also be required at CPVDD, depending upon the system configuration. CPCA CPCB CPVOUTP CPVDD Charge Pump CPVOUTN WM8962 CPGND Figure 36 Charge Pump External Connections 130 Rev 4.4 WM8962 The Charge Pump is enabled by setting the CP_ENA bit. When enabled, the charge pump adjusts the output voltages (CPVOUTP and CPVOUTN) as well as the switching frequency in order to optimise the power consumption according to the operating conditions. This can take two forms, which are selected using the CP_DYN_PWR register bit.  Register control (CP_DYN_PWR = 0)  Dynamic control (CP_DYN_PWR = 1) Under Register control, the HPOUTL_VOL and HPOUTR_VOL register settings are used to control the charge pump mode of operation. Under Dynamic control, the audio signal level in the DAC is also used to control the charge pump mode of operation. This is the Wolfson ‘Class W’ mode, which allows the power consumption to be optimised in real time. When selecting Register control (CP_DYN_PWR = 0), a ‘1’ must be written to the HPOUT_VU bit to complete the mode change. HPOUT_VU is defined in the “Headphone Output Paths” section (Table 79). Note that, when selecting Dynamic control (CP_DYN_PWR = 1), the Charge Pump mode change is implemented immediately when CP_DYN_PWR is updated. When digital sidetone is used (see “Digital Mixing”), it is recommended that the Charge Pump operates in Register Control mode only (CP_DYN_PWR = 0). This is because the Dynamic Control mode (Class W) does not measure the sidetone signal level and hence the Charge Pump configuration cannot be optimised for all signal conditions when digital sidetone is enabled; this could lead to signal clipping. When Virtual Surround Sound (VSS), HD Bass or DAC ReTune is used (see “DAC Signal Path Enhancements”), it is recommended that the Charge Pump operates in Register Control mode only (CP_DYN_PWR = 0). This is because the Dynamic Control mode (Class W) does not measure the DSP Signal Enhancements level and hence the Charge Pump cannot be optimised for all signal conditions when VSS, HD Bass or DAC ReTune is enabled; this could lead to signal clipping. Under the recommended usage conditions of the WM8962, the Charge Pump will be enabled by running the default headphone Start-Up sequence as described in the “Control Write Sequencer” section. (Similarly, it will be disabled by running the Shut-Down sequence.) In these cases, the user does not need to write to the CP_ENA bit. The Charge Pump operating mode defaults to Register control; Dynamic control may be selected by setting the CP_DYN_PWR register bit, if appropriate. The SYSCLK signal must be present for the charge pump to function. The clock division from MCLK (or the internal oscillator) is handled transparently by the WM8962 without user intervention, as long as SYSCLK and sample rates are set correctly (see “Clocking and Sample Rates” section). The clock divider ratio depends on the SAMPLE_RATE[2:0] and MCLK_RATE[3:0] register settings. The Charge Pump control fields are described in Table 80. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R72 (48h) Charge Pump 1 0 CP_ENA 0 Enable charge-pump digits 0 = disable 1 = enable R82 (52h) Charge Pump B 0 CP_DYN_PWR 0 Enable dynamic charge pump power control 0 = Charge pump controlled by volume register settings (Class G) 1 = Charge pump controlled by realtime audio level (Class W) Class W is recommended for lowest power consumption When selecting CP_DYN_PWR=0, a ‘1’ must be written to the HPOUT_VU bit (Register R2 or R3) to complete the mode change. Table 80 Charge Pump Control Rev 4.4 131 WM8962 DC SERVO The WM8962 provides four DC servo circuits - two on the headphone outputs HPOUTL and HPOUTR, and two on the analogue input paths INL and INR. The DC servo circuits remove offset from these signal paths. Removal of DC offset on the headphone outputs is important because any deviation from GND at the output pin will cause current to flow through the load under quiescent conditions, resulting in increased power consumption. Additionally, the presence of DC offsets can result in audible pops and clicks at power up and power down. The DC servo ensures that the DC level on the headphone outputs is within 1.2mV of GND. Removal of DC offset on the input paths is important because any deviation from VMID at the ADC input will prevent correct operation of the zero-cross detection and may also restrict the maximum analogue input signal level. (Zero-cross detection is available for PGA volume updates, including when the PGA is controlled by the ALC control.) The recommended usage of the DC Servo is initialised by running the default Start-Up sequence as described in the “Control Write Sequencer” section. The default Start-Up sequence executes a series of DC offset corrections, after which the measured offset correction is maintained on the headphone output channels. Updates to the DC Servo correction can also be scheduled using register writes, including during audio playback. The relevant control fields are described in the following paragraphs and are defined in Table 81. DC SERVO ENABLE AND START-UP The DC Servo circuits are enabled on HPOUTL and HPOUTR by setting HP1L_DCS_ENA and HP1R_DCS_ENA respectively. Equivalent registers are provided for the analogue input paths INL and INR. When the DC Servo is enabled, the DC offset correction can be commanded in different ways, as described below. Writing a logic 1 to HP1L_DCS_STARTUP initiates a series of DC offset measurements and applies the necessary correction to the HPOUTL output. On completion, the output will be within 1.2mV of AGND. This is the DC Servo mode selected by the default Start-Up sequence. Completion of this DC offset correction is indicated by the DCS_STARTUP_DONE_HP1L, as described in Table 81. The DC Servo Start-Up function is supported on all four DC Servo channels; individual register control is provided for each channel. The DC Servo Start-Up can be commanded on multiple channels simultaneously if required. Typically, this operation takes 24ms per channel. The DC Servo control fields associated with start-up operation are described in Table 81. For Headphone output DC offset correction, it is important to note that the DC Servo Start-Up mode should be commanded as part of a control sequence which includes muting and shorting of the headphone outputs; a suitable sequence is defined in the default Start-Up sequence (see “Control Write Sequencer”). See also the “Headphone Output Paths” section for the details of the recommended Headphone Enable/Disable sequence. Note that, once the DC offset correction has been performed, the measured offset will be maintained in memory, even when the associated signal path is disabled. This means that, if required, the DC offset correction can be performed on all channels during start-up, and each channel may then be disabled or enabled when required, without having to re-schedule the DC offset correction. The DC Servo circuit uses the Charge Pump power supply. The Charge Pump must be enabled by setting the CP_ENA register bit and ensuring that a suitable clock (eg. MCLK) is present. If these conditions are not met, then DC offset correction cannot be performed. See “Charge Pump” and “Clocking and Sample Rates” for details of the associated controls. 132 Rev 4.4 WM8962 REGISTER ADDRESS R60 (3Ch) DC Servo 0 R61 (3Dh) DC Servo 1 R66 (42h) DC Servo 6 BIT LABEL DEFAULT DESCRIPTION 7 INL_DCS_ENA 0 DC Servo enable for Left input signal path 0 = Disabled 1 = Enabled 6 INL_DCS_START UP 0 Writing 1 to this bit selects Start-Up DC Servo mode for Left input signal path 3 INR_DCS_ENA 0 DC Servo enable for Right input signal path 0 = Disabled 1 = Enabled 2 INR_DCS_START UP 0 Writing 1 to this bit selects Start-Up DC Servo mode for Right input signal path 7 HP1L_DCS_ENA 0 DC Servo enable for HPOUTL 0 = Disabled 1 = Enabled 6 HP1L_DCS_STA RTUP 0 Writing 1 to this bit selects Start-Up DC Servo mode for HPOUTL 3 HP1R_DCS_ENA 0 DC Servo enable for HPOUTR 0 = Disabled 1 = Enabled 2 HP1R_DCS_STA RTUP 0 Writing 1 to this bit selects Start-Up DC Servo mode for HPOUTR 10 DCS_STARTUP_ DONE_IN1L 0 DC Servo Start-Up Status (Left Input) 0 = Not complete 1 = Complete 9 DCS_STARTUP_ DONE_IN1R 0 DC Servo Start-Up Status (Right Input) 0 = Not complete 1 = Complete 8 DCS_STARTUP_ DONE_HP1L 0 DC Servo Start-Up Status (HPOUTL) 0 = Not complete 1 = Complete 7 DCS_STARTUP_ DONE_HP1R 0 DC Servo Start-Up Status (HPOUTR) 0 = Not complete 1 = Complete Table 81 DC Servo Enable and Start-Up Modes Rev 4.4 133 WM8962 DC SERVO ACTIVE MODES The DC Servo Start-Up mode described above is suitable for initialising the DC offset correction circuit on the input or output signal paths as part of a controlled start-up sequence which is executed before the signal path is fully enabled. The WM8962 also supports DC offset measurement and correction on the HP output paths whilst the signal path is active; this may be of benefit following a large change in signal gain, which can lead to a change in DC offset level. Writing a logic 1 to HP1L_DCS_SYNC initiates a series of DC offset measurements and applies the necessary correction to the HPOUTL output. Writing a logic 1 to HP1R_DCS_SYNC initiates a series of DC offset measurements and applies the necessary correction to the HPOUTR output. The number of DC Servo operations performed is determined by HP1_DCS_SYNC_STEP. A maximum of 127 operations may be selected, though a much lower value will be sufficient in most applications. The DC Servo uses filtering to measure the DC offset in the presence of any audio that may be present; this requires a longer time to perform the correction process than in the Start-Up mode, and means that the DC Servo may be operating for several seconds after the process was initiated. The DC Servo Sync mode described above is supported on the HPOUT DC Servo channels; individual register control is provided for each channel. It is recommended that the DC Servo Sync mode is scheduled whenever a large change in signal gain (eg. >6dB) is applied in the output signal path. Note that the DC Servo Sync mode is not required on the input signal paths as the DC offset in these paths does not change with gain, and only the Start-Up correction is necessary. The DC Servo control fields associated with Sync mode (suitable for use on a signal path that is in active use) are described in Table 82. REGISTER ADDRESS R61 (3Dh) DC Servo 1 R64 (40h) DC Servo 4 BIT LABEL DEFAULT DESCRIPTION 4 HP1L_DCS_SYN C 0 Writing 1 to this bit selects a series of DC offset corrections for HPOUTL 0 HP1R_DCS_SYN C 0 Writing 1 to this bit selects a series of DC offset corrections for HPOUTR 13:7 HP1_DCS_SYNC _STEP [6:0] 10h Number of DC Servo updates to perform in a series event (HPOUTL and HPOUTR) 00h to 0Fh = Reserved 10h = 16 (default) 11h = 17 … 7Fh = 127 Table 82 DC Servo Active Modes 134 Rev 4.4 WM8962 REFERENCE VOLTAGES AND BIAS CONTROL This section describes the analogue reference voltage and bias current controls. It also describes the VMID soft-start circuit for pop suppressed start-up and shut-down. Note that, under the recommended usage conditions of the WM8962, these features will be configured by running the default Start-Up and Shut-Down sequences as described in the “Control Write Sequencer” section. In these cases, the user does not need to set these register fields directly. ANALOGUE REFERENCE AND MASTER BIAS The analogue circuits in the WM8962 require a mid-rail analogue reference voltage, VMID. This reference is generated from AVDD via a programmable resistor chain. The VMID reference generator requires a bias current, which is enabled by STARTUP_BIAS_ENA. Together with the external VMID decoupling capacitor, the programmable VMID resistor chain results in a slow, normal or fast charging characteristic on VMID. This is controlled by the VMID_SEL register, and can be used to optimise the reference for normal operation, low power standby or for fast start-up as described in Table 83. For normal operation, the VMID_SEL field should be set to 01. A soft-start circuit is provided in order to control the switch-on of the VMID reference; this is enabled by setting VMID_RAMP. When the soft-start circuit is enabled prior to enabling VMID_SEL, the VMID reference rises smoothly, without any step change that could otherwise occur. The analogue circuits in the WM8962 require a bias current. The normal bias current is enabled by setting BIAS_ENA. Note that the normal bias current source requires VMID to be enabled also. The analogue inputs to the WM8962 are biased to VMID in normal operation. In order to avoid audible pops caused by a disabled signal path dropping to AGND, the WM8962 can maintain these connections at VMID when the relevant input stage is disabled. This is achieved by connecting a buffered VMID reference to the input or output. The buffered VMID reference is enabled by setting VMID_BUF_ENA. REGISTER ADDRESS R25 (19h) Pwr Mgmt (1) R28 (1Ch) Anti-pop BIT LABEL DEFAULT DESCRIPTION 8:7 VMID_SEL [1:0] 00 VMID Divider Enable and Select 00 = VMID disabled (for OFF mode) 01 = 2 x 50k divider (for normal operation) 10 = 2 x 250k divider (for low power standby) 11 = 2 x 5k divider (for fast start-up) 6 BIAS_ENA 0 Enables the Normal bias current generator (for all analogue functions) 0 = Disabled 1 = Enabled 4 STARTUP_B IAS_ENA 0 Enables the Start-Up bias current generator 0 = Disabled 1 = Enabled 3 VMID_BUF_ ENA 0 VMID Buffer Enable 0 = Disabled 1 = Enabled 2 VMID_RAMP 0 Enables VMID soft ramp-up 0 = Disabled 1 = Enabled Table 83 Reference Voltages and Master Bias Enable INPUT SIGNAL PATH BIAS CONTROL SETTINGS All the analogue circuits of the WM8962 require a bias current. The bias current in the input signal path circuits can be controlled using the register bits described in Table 84. When adjusting the bias settings, there is always a trade-off between performance and power. Selecting a lower bias can be used to reduce power consumption, but may have a marginal impact on audio performance in some usage modes. Selecting a higher bias offers a performance improvement, but also an increase in power consumption. Rev 4.4 135 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R23 (17h) Additional Control (1) 5 ADC_HP 0 ADC Oversampling Ratio 0 = Low Power (typically 64 x fs) 1 = High Performance (typically 128 x fs) R35 (23h) Input bias control 5:3 MIXIN_BIAS 000 Input Boost-Mixer Bias Control 000 = x 2.0 (default) 001 = Reserved 010 = Reserved 011 = x 1.0 100 = x 0.67 101 to 111 = Reserved 2:0 INPGA_BIAS 100 Input PGA Bias Control 000 = x 2.0 001 = Reserved 010 = Reserved 011 = Reserved 100 = x 0.67 (default) 101 to 111 = Reserved Table 84 Input Signal Path Bias Control Settings It is recommended that the input signal path bias control settings are selected only from the supported combinations listed in Table 85. DESCRIPTION ADC_HP MIXIN_BIAS INPGA_BIAS Option 1 0 100 100 Option 2 0 011 100 Option 3 (default) 0 000 100 Option 4 1 000 000 NOTES Lowest power consumption Highest performance Table 85 Recommended Bias Control Settings (Input Signal Path) OUTPUT SIGNAL PATH BIAS CONTROL SETTINGS All the analogue circuits of the WM8962 require a bias current. The bias current in the output signal path circuits can be controlled using the register bits described in Table 86. When adjusting the bias settings, there is always a trade-off between performance and power. Selecting a lower bias can be used to reduce power consumption, but may have a marginal impact on audio performance in some usage modes. Selecting a higher bias offers a performance improvement, but also an increase in power consumption. 136 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R6 (06h) ADC & DAC Control 2 0 DAC_HP 0 DAC Oversampling Ratio 0 = Low Power (typically 64 x fs) 1 = High Performance (typically 128 x fs) R68 (44h) Analogue PGA Bias 2:0 HP_PGAS_BIAS [2:0] 011 Headphone PGA Boost Bias 000 = x 2.0 001 = Reserved 010 = Reserved 011 = x 1.0 (default) 100 to 111 = Reserved Rev 4.4 WM8962 REGISTER ADDRESS BIT R71 (47h) Analogue HP 2 2:0 LABEL HP_BIAS_BOOST [2:0] DEFAULT 011 DESCRIPTION Headphone Driver Boost Bias 000 = x 2.0 001 = Reserved 010 = Reserved 011 = x 1.0 (default) 100 to 111 = Reserved Table 86 Output Signal Path Bias Control Settings It is recommended that the output signal path bias control settings are selected only from the supported combinations listed in Table 87. Note that, for the specified performance in ‘High Performance’ mode, the headphone output secondary PGAs must be set to -7dB attenuation. See “Headphone Output Paths” for details of the associated registers. DESCRIPTION DAC_HP HP_PGAS_BIAS HP_BIAS_BOOST HP1L_VOL, HP1R_VOL Low Power headphone playback mode 0 011 011 XXX High Performance headphone playback mode 1 000 000 000 Table 87 Recommended Bias Control Settings (Output Signal Path) Note that power consumption in the WM8962 can be optimised in real time using the adaptive Charge Pump that provides the supply rails to the headphone driver. The Dynamic control mode of the Charge Pump provides lowest power consumption, and may be selected in Low Power or High Performance headphone playback modes. Note that there are some operating conditions in which the Dynamic control mode should not be selected; these are described in the “Charge Pump” section. DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting DAC data to the WM8962 and outputting ADC data from it. The digital audio interface uses four pins:  ADCDAT: ADC data output  DACDAT: DAC data input  LRCLK: Left/Right data alignment clock  BCLK: Bit clock, for synchronisation The clock signals BCLK and LRCLK can be outputs when the WM8962 operates as a master, or inputs when it is a slave (see “Master and Slave Mode Operation”, below). Four different audio data formats are supported:  Left justified  Right justified  I2S  DSP mode All four of these modes are MSB first. They are described in “Audio Data Formats (Normal Mode)” below. Refer to the “Signal Timing Requirements” section for timing information. Time Division Multiplexing (TDM) is available in all four data format modes. The WM8962 can be programmed to send and receive data in one of two time slots. Rev 4.4 137 WM8962 PCM operation is supported using the DSP mode. MASTER AND SLAVE MODE OPERATION The WM8962 digital audio interface can operate as a master or slave as shown in Figure 37 and Figure 38. BCLK BCLK LRCLK WM8962 LRCLK Processor ADCDAT WM8962 DACDAT ADCDAT Processor DACDAT Figure 37 Master Mode Figure 38 Slave Mode The Audio Interface output control is illustrated above. The MSTR control register determines whether the WM8962 generates the clock signals. The MSTR register field is defined in Table 88. REGISTER ADDRESS BIT R7 (07h) Audio Interface 0 6 LABEL DEFAULT MSTR 0 DESCRIPTION Audio Interface Mode Select 0 = Slave mode 1 = Master mode Table 88 Audio Interface Master/Slave Control OPERATION WITH TDM Time division multiplexing (TDM) allows multiple devices to transfer data simultaneously on the same bus. The WM8962 ADCs and DACs support TDM in master and slave modes for all data formats and word lengths. TDM is enabled and configured using register bits defined in the “Digital Audio Interface Control” section. BCLK BCLK LRCLK WM8962 LRCLK Processor WM8962 ADCDAT DACDAT DACDAT BCLK WM8962 or Similar CODEC LRCLK ADCDAT DACDAT Figure 39 TDM with WM8962 as Master 138 Processor ADCDAT BCLK WM8962 or Similar CODEC LRCLK ADCDAT DACDAT Figure 40 TDM with Other CODEC as Master Rev 4.4 WM8962 BCLK LRCLK WM8962 Processor ADCDAT DACDAT BCLK WM8962 or Similar CODEC LRCLK ADCDAT DACDAT Figure 41 TDM with Processor as Master Note: The WM8962 is a 24-bit device. If the user operates the WM8962 in 32-bit mode then the 8 LSBs will be ignored on the receiving side and not driven on the transmitting side. It is therefore recommended to add a pull-down resistor, if necessary, to the DACDAT line and the ADCDAT line in TDM mode. BCLK FREQUENCY The BCLK frequency is controlled relative to SYSCLK by the BCLK_DIV divider. Internal clock divide and phase control mechanisms ensure that the BCLK and LRCLK edges will occur in a predictable and repeatable position relative to each other and relative to the data for a given combination of DAC/ADC sample rate and BCLK_DIV settings. BCLK_DIV is defined in the “Digital Audio Interface Control” section. See also “Clocking and Sample Rates” section for more information. AUDIO DATA FORMATS (NORMAL MODE) In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition. 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK DACDAT/ ADCDAT 1 MSB 2 3 Input Word Length (WL) n-2 n-1 n 1 2 3 n-2 n-1 n LSB Figure 42 Right Justified Audio Interface (assuming n-bit word length) In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition. Rev 4.4 139 WM8962 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK DACDAT/ ADCDAT 1 2 3 MSB n-2 n-1 n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 43 Left Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK 1 BCLK DACDAT/ ADCDAT 1 2 1 BCLK 3 MSB n-2 n-1 n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 44 I2S Justified Audio Interface (assuming n-bit word length) In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRCLK_INV) following a rising edge of LRCLK. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRCLK output will resemble the frame pulse shown in Figure 45 and Figure 46. In device slave mode, Figure 47 and Figure 48, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse. 1/fs 1/2fs LRCLK 1 BCLK BCLK LEFT CHANNEL DACDAT/ ADCDAT 1 MSB 2 3 n-2 Input Word Length (WL) RIGHT CHANNEL n-1 n 1 2 3 n-2 n-1 n LSB Figure 45 DSP Mode Audio Interface (mode A, LRCLK_INV=0, Master) 140 Rev 4.4 WM8962 1/fs 1/2fs LRCLK BCLK LEFT CHANNEL DACDAT/ ADCDAT 1 2 MSB 3 n-2 RIGHT CHANNEL n-1 n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 46 DSP Mode Audio Interface (mode B, LRCLK_INV=1, Master) 1/fs LRCLK Falling edge can occur anywhere in this area 1 BCLK 1 BCLK BCLK LEFT CHANNEL DACDAT/ ADCDAT 1 2 MSB 3 n-2 RIGHT CHANNEL n-1 n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 47 DSP Mode Audio Interface (mode A, LRCLK_INV=0, Slave) 1/fs LRCLK Falling edge can occur anywhere in this area 1 BCLK 1 BCLK BCLK LEFT CHANNEL DACDAT/ ADCDAT 1 MSB 2 3 n-2 Input Word Length (WL) RIGHT CHANNEL n-1 n 1 2 3 n-2 n-1 n LSB Figure 48 DSP Mode Audio Interface (mode B, LRCLK_INV=1, Slave) PCM operation is supported in DSP interface mode. WM8962 ADC data that is output on the Left Channel will be read as mono PCM data by the receiving equipment. Mono PCM data received by the WM8962 will be treated as Left Channel data. This data may be routed to the Left/Right DACs as described in the “Digital Mixing” section. AUDIO DATA FORMATS (TDM MODE) TDM is supported in master and slave mode and is enabled by register bits AIFADC_TDM_MODE and AIFDAC_TDM_MODE. All audio interface data formats support time division multiplexing (TDM) for ADC and DAC data. Two time slots are available (Slot 0 and Slot 1), selected by register bits AIFADC_TDM_SLOT and AIFDAC_TDM_SLOT which control time slots for the ADC data and the DAC data. Rev 4.4 141 WM8962 When TDM is enabled, the ADCDAT pin will be tri-stated immediately before and immediately after data transmission, to allow another ADC device to drive this signal line for the remainder of the sample period. Note that it is important that two ADC devices do not attempt to drive the data pin simultaneously. A short circuit may occur if the transmission time of the two ADC devices overlap with each other. See “Audio Interface Timing” for details of the ADCDAT output relative to BCLK signal. Note that it is possible to ensure a gap exists between transmissions by setting the transmitted word length to a value higher than the actual length of the data. For example, if 32-bit word length is selected where only 24-bit data is available, then the WM8962 interface will tri-state after transmission of the 24-bit data, ensuring a gap after the WM8962’s TDM slot. When TDM is enabled, BCLK frequency must be high enough to allow data from both time slots to be transferred. The relative timing of Slot 0 and Slot 1 depends upon the selected data format as shown in Figure 49 to Figure 53. 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK DACDAT/ ADCDAT SLOT 0 SLOT 1 SLOT 0 SLOT 1 Figure 49 TDM in Right-Justified Mode 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK DACDAT/ ADCDAT SLOT 0 SLOT 1 SLOT 0 SLOT 1 Figure 50 TDM in Left-Justified Mode 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK 1 BCLK DACDAT/ ADCDAT SLOT 0 1 BCLK SLOT 1 SLOT 0 SLOT 1 Figure 51 TDM in I2S Mode 142 Rev 4.4 WM8962 1/fs LRCLK Falling edge can occur anywhere in this area 1 BCLK 1 BCLK BCLK DACDAT/ ADCDAT SLOT 0 LEFT SLOT 0 RIGHT SLOT 1 LEFT SLOT 1 RIGHT Figure 52 TDM in DSP Mode A 1/fs LRCLK Falling edge can occur anywhere in this area 1 BCLK 1 BCLK BCLK DACDAT/ ADCDAT SLOT 0 LEFT SLOT 0 RIGHT SLOT 1 LEFT SLOT 1 RIGHT Figure 53 TDM in DSP Mode B DIGITAL AUDIO INTERFACE CONTROL The register bits controlling audio data format, word length, left/right channel data configuration and TDM are summarised in Table 89. Rev 4.4 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R5 (05h) ADC & DAC Control 1 6 ADCR_DAT_IN V 0 Right ADC Invert 0 = Right ADC output not inverted 1 = Right ADC output inverted 5 ADCL_DAT_INV 0 Left ADC Invert 0 = Left ADC output not inverted 1 = Left ADC output inverted R6 (06h) ADC & DAC Control 2 6 DACR_DAT_IN V 0 Right DAC Invert 0 = Right DAC input not inverted 1 = Right DAC input inverted 5 DACL_DAT_INV 0 Left DAC Invert 0 = Left DAC input not inverted 1 = Left DAC input inverted R7 (07h) Audio Interface 0 12 AIFDAC_TDM_ MODE 0 DAC TDM Mode Select 0 = Normal DACDAT operation (1 stereo slot) 1 = TDM enabled on DACDAT (2 stereo slots) 11 AIFDAC_TDM_ SLOT 0 DACDAT TDM Slot Select 0 = DACDAT data input on slot 0 1 = DACDAT data input on slot 1 10 AIFADC_TDM_ MODE 0 ADC TDM Mode Select 0 = Normal ADCDAT operation (1 stereo slot) 1 = TDM enabled on ADCDAT (2 stereo slots) 143 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 9 AIFADC_TDM_ SLOT 0 ADCDAT TDM Slot Select 0 = ADCDAT data input on slot 0 1 = ADCDAT data input on slot 1 8 ADC_LRSWAP 0 Swap left/right ADC data on the interface 0 = Normal 1 = ADCDAT channels swapped 7 BCLK_INV 0 BCLK Invert 0 = BCLK not inverted 1 = BCLK inverted 5 DAC_LRSWAP 0 Swap left/right DAC data on the interface 0 = Normal 1 = DACDAT channels swapped 4 LRCLK_INV 0 Right, left and I2S modes – LRCLK polarity 0 = normal LRCLK polarity 1 = invert LRCLK polarity DSP Mode – mode A/B select 0 = MSB is available on 2nd BCLK rising edge after LRCLK rising edge (mode A) 1 = MSB is available on 1st BCLK rising edge after LRCLK rising edge (mode B) 3:2 WL [1:0] 10 Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Note - see “Companding” for the selection of 8-bit mode. 1:0 FMT [1:0] 10 Digital Audio Interface Format 00 = Right justified 01 = Left justified 10 = I2S Format 11 = DSP Mode Table 89 Digital Audio Interface Data Control AUDIO INTERFACE TRI-STATE Register bit AIF_TRI can be used to tri-state the audio interface pins as described in Table 90. All digital audio interface pins will be tri-stated by this function, regardless of the state of other registers which control these pin configurations. REGISTER ADDRESS R24 (18h) Additional Control (2) BIT 3 LABEL AIF_TRI DEFAULT DESCRIPTION 0 Audio Interface Tristate 0 = Audio interface pins operate normally 1 = ADCDAT is tri-stated; BCLK & LRCLK are set as inputs Table 90 Digital Audio Interface Tri-State Control BCLK AND LRCLK CONTROL The audio interface can be programmed to operate in master mode or slave mode using the MSTR register bit. In master mode, the BCLK and LRCLK signals are generated by the WM8962 when any of the ADCs or DACs is enabled. In slave mode, the BCLK and LRCLK clock outputs are disabled by default to allow another digital audio interface to drive these pins. Refer to “Clocking and Sample Rates” for specific operating constraints in this configuration. 144 Rev 4.4 WM8962 REGISTER ADDRESS BIT R7 (07h) Audio Interface 0 6 R8 (08h) Clocking2 3:0 R14 (0Eh) Audio Interface 2 10:0 LABEL DEFAULT MSTR DESCRIPTION 0 Audio Interface Mode Select 0 = Slave mode 1 = Master mode BCLK_DIV 0100 BCLK Rate 0000 = DSPCLK 0001 = Reserved 0010 = DSPCLK / 2 0011 = DSPCLK / 3 0100 = DSPCLK / 4 (default) 0101 = Reserved 0110 = DSPCLK / 6 0111 = DSPCLK / 8 1000 = Reserved 1001 = DSPCLK / 12 1010 = DSPCLK / 16 1011 = DSPCLK / 24 1100 = Reserved 1101 = DSPCLK / 32 1110 = DSPCLK / 32 1111 = DSPCLK / 32 AIF_RATE [10:0] 040h LRCLK Rate LRCLK clock output = BCLK / AIF_RATE Integer (LSB = 1) Valid from 4..2047 Default (040h) = 64 BCLKs per LRCLK Table 91 Digital Audio Interface Clock Control COMPANDING The WM8962 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides as shown in Table 92. REGISTER ADDRESS R9 (09h) Audio Interface 1 BIT LABEL DEFAULT DESCRIPTION 4 DAC_COMP 0 DAC Companding Enable 0 = disabled 1 = enabled 3 DAC_COMPMODE 0 DAC Companding Type 0 = µ-law 1 = A-law 2 ADC_COMP 0 ADC Companding Enable 0 = disabled 1 = enabled 1 ADC_COMPMODE 0 ADC Companding Type 0 = µ-law 1 = A-law Table 92 Companding Control Rev 4.4 145 WM8962 Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: -law (where =255 for the U.S. and Japan): F(x) = ln( 1 + |x|) / ln( 1 + ) -1 ≤ x ≤ 1 A-law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) x ≤ 1/A F(x) = ( 1 + lnA|x|) / (1 + lnA) 1/A ≤ x ≤ 1 The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSBs of data. Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This provides greater precision for low amplitude signals than for high amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quantization. The companded signal is an 8-bit word comprising sign (1 bit), exponent (3 bits) and mantissa (4 bits). 8-bit mode is selected whenever DAC_COMP=1 or ADC_COMP=1. The use of 8-bit data allows samples to be passed using as few as 8 BCLK cycles per LRCLK frame. When using DSP mode B, 8bit data words may be transferred consecutively every 8 BCLK cycles. 8-bit mode (without Companding) may be enabled by setting DAC_COMPMODE=1 ADC_COMPMODE=1, when DAC_COMP=0 and ADC_COMP=0. BIT7 BIT[6:4] BIT[3:0] SIGN EXPONENT MANTISSA or Table 93 8-bit Companded Word Composition u-law Companding 1 120 0.9 Companded Output 0.7 80 0.6 0.5 60 0.4 40 0.3 Normalised Output 0.8 100 0.2 20 0.1 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input Figure 54 µ-Law Companding 146 Rev 4.4 WM8962 A-law Companding 1 120 0.9 Companded Output 0.7 80 0.6 0.5 60 0.4 40 0.3 Normalised Output 0.8 100 0.2 20 0.1 0 0 0 0.2 0.4 0.6 0.8 1 Normalised Input Figure 55 A-Law Companding LOOPBACK Setting the LOOPBACK register bit enables digital loopback. When this bit is set, the ADC digital data output is routed to the DAC digital data input path. The digital audio interface input (DACDAT) is not used when LOOPBACK is enabled. REGISTER ADDRESS R9 (09h) Audio Interface (2) BIT 0 LABEL LOOPBACK DEFAULT DESCRIPTION 0 Digital Loopback Function 0 = No loopback 1 = Loopback enabled (ADC data output is directly input to DAC data input). Table 94 Loopback Control Note: When the digital sidetone is enabled, ADC data will also be added to DAC digital data input path within the Digital Mixing circuit. This applies regardless of whether LOOPBACK is enabled. Rev 4.4 147 WM8962 CLOCKING AND SAMPLE RATES The internal clocks for the WM8962 are all derived from a common internal clock source, SYSCLK. This clock is the reference for the ADCs, DACs, DSP core functions, digital audio interface, Class D switching amplifier, DC servo control and other internal functions. SYSCLK can either be derived directly from MCLK, or may be generated from the Frequency Locked Loop (FLL) or Phase Locked Loop (PLL). Many commonly-used audio sample rates can be derived directly from typical MCLK frequencies; the FLL and PLL provide additional flexibility for a wide range of reference frequencies. To avoid audible glitches, all clock configurations must be set up before enabling playback. The FLL can be used to generate a free-running clock in the absence of an external reference source; see “Free-Running FLL Clock” for further details. See “Internal / External Clock Generation” for further details of the PLL and FLL circuits. The WM8962 supports automatic clocking configuration. The programmable dividers associated with the ADCs, DACs, DSP core functions, Class D switching and DC servo are configured automatically, with values determined from the MCLK_RATE and SAMPLE_RATE fields. The user must also configure the OPCLK (if required), the TOCLK (if required) and the digital audio interface. ADC/DAC oversample rates of 64fs or 128fs are supported (based on a 48kHz sample rate). A 256kHz clock, supporting a number of internal functions, is derived from SYSCLK. The Class D switching amplifier and DC servo control circuits are clocked from SYSCLK. A GPIO Clock, OPCLK, can be derived from SYSCLK and output on a GPIO pin to provide clocking to other devices. This clock is enabled by OPCLK_ENA and controlled by OPCLK_DIV. A slow clock, TOCLK, is used to set the timeout period for volume updates when zero-cross detect is used. This clock is enabled by TOCLK_ENA and controlled by TOCLK_DIV. A de-bounce clock, DBCLK, is used to control the de-bouncing of button/accessory detect GPIO inputs and selected interrupt inputs. This clock is enabled automatically whenever GPIO or interrupt de-bouncing is selected. The de-bounce clock frequency is controlled by DBCLK_DIV. In master mode, BCLK is derived from DSPCLK via a programmable divider set by BCLK_DIV. In master mode, the LRCLK is derived from BCLK via a programmable divider AIF_RATE. In Slave mode, BCLK and LRCLK are inputs to the WM8962, allowing another digitial audio interface to drive these pins. See the “BCLK and LRCLK Control” sub-section for specific operating constraints in this configuration. The control registers associated with Clocking and Sample Rates are shown in Table 97 to Table 102. The overall clocking scheme for the WM8962 is illustrated in Figure 56. 148 Rev 4.4 WM8962 f/N f/N DSPCLK_DIV[1:0] 00 = MCLK 01 = MCLK / 2 10 = MCLK / 4 DSP2CLK (49.152MHz max) DSP Core DSPCLK (24.576MHz max) DSP Core BCLK_DIV[3:0] 0000 = DSPCLK 0001 = Reserved 0010 = DSPCLK/ 2 0011 = DSPCLK/ 3 0100 = DSPCLK/ 4 0101 = Reserved 0110 = DSPCLK/ 6 0111 = DSPCLK/ 8 1000 = Reserved 1001 = DSPCLK/ 12 1010 = DSPCLK/ 16 1011 = DSPCLK/ 24 1100 = Reserved 1101 = DSPCLK/ 32 1110 = DSPCLK/ 32 1111 = DSPCLK/ 32 MASTER MODE CLOCK OUTPUTS f/N f/N LRCLK BCLK AIF_RATE [10:0] BCLK_DIV [3:0] MCLK f/N MCLK_SRC PLL3 DAC f/N MCLK FLL f/N PLL_SYSCLK_DIV 00 = PLL3 / 1 01 = PLL3 / 2 (default) 10 = PLL3 / 4 11 = Reserved SYSCLK_ENA SYSCLK_DIV[1:0] 00 = MCLK 01 = MCLK / 2 10 = MCLK / 4 DACSYS_CLK_DIV [2:0] ADCSYS_CLK_DIV [2:0] f/N MCLK MCLK_SRC selects master clock source (MCLK pin, FLL or PLL3). The PLL3 source, when selected, is divided by PLL_SYSCLK_DIV. The selected source is used to derive SYSCLK, DSPCLK and other clocks automatically. f/N Automatic Clocking Configuration Internal clocks are derived from the master clock source . These are configured using MANUAL_MODE, SAMPLE_RATE, MCLK_RATE, ADC_HP and DAC_HP. DCSCLK_DIV [3:0] f/N f/2 Class D switching clock 256kHz clock to Write Sequencer and other circuits f/N SYSCLK Other internal clocks are derived from SYSCLK. The master clock source is divided by SYSCLK_DIV to derive SYSCLK. The SYSCLK_DIV divider is configured automatically. SYSCLK is enabled by SYSCLK_ENA. TOCLK_ENA F256KCLK_DIV [5:0] f/N ADC / DAC Clocks The ADC clocks are controlled by ADCSYS_CLK_DIV and ADC_HP. The DAC clocks are controlled by DACSYS_CLK_DIV and DAC_HP. The dividers ADCSYS_CLK_DIV and DACSYS_CLK_DIV are configured automatically. Class D Switching Class D switching rate is set by CLASSD_CLK_DIV. The clock frequency is automatically set to around 768kHz. DC Servo clock CLASSD_CLK_DIV [2:0] DSP Clock Clocking for the Digital Audio Interface and many of the DSP functions is derived from DSPCLK. The master clock source is divided by DSPCLK_DIV to derive DSPCLK. The DSPCLK_DIV divider is configured automatically. Clocking for the ReTune, VSS and HD Bass functions is derived from DSP2CLK. DC Servo Clock DC Servo clock is set by DCS_CLK_DIV. The clock frequency is automatically set to around 1.5MHz. ADC f/2 or f/3 SYSCLK (12.288MHz max) DBCLK_DIV [2:0] OPCLK_DIV[2:0] 000 = SYSCLK 001 = SYSCLK / 2 010 = SYSCLK / 3 011 = SYSCLK / 4 100 = SYSCLK / 6 101 = SYSCLK / 8 110 = SYSCLK / 12 111 = SYSCLK / 16 f/N OPCLK_ENA Volume update timeout TOCLK_DIV [2:0] Interrupt de-bounce clock GPIO Clock Output f/N OPCLK_DIV [2:0] 256kHz Clock The 256k clock for internal functions is set automatically by F256KCLK_DIV. OPCLK Output GPIO output clock frequency is set by OPCLK_DIV. TOCLK, DBCLK Control The slow clock for volume update timeout is enabled by TOCLK_ENA; the frequency is controlled by TOCLK_DIV. Clocking for interrupt de-bounce is enabled automatically when required; the frequency is set by DBCLK_DIV. SAMPLE_RATE [2:0] MCLK_RATE [3:0] DAC_HP ADC_HP Automatic DSP Clocking Control In Automatic DSP Clocking Mode, the DAC, ADC, 256kHz, DC Servo and Class D clocks are configured automatically according to SAMPLE_RATE, SYSCLK_RATE, DAC_HP and ADC_HP. Digital Audio Interface Control BCLK rate is set by BCLK_DIV in master mode. BCLK rate must be high enough to support the ADC and DAC sample rates. LRCLK rate is set by AIF_RATE in master mode. Figure 56 SYSCLK and Internal Clocking Scheme SYSCLK CONTROL The MCLK_SRC register is used to select the source for MCLK. The source may be either the MCLK pin, FLL or PLL3. The PLL3 source, when selected, is controlled by the PLL_SYSCLK_DIV divider. The selected source may be adjusted by the programmable divider SYSCLK_DIV; this is configured automatically by the WM8962 to ensure that SYSCLK ALC_LVL 13 ALC_SAT_STS 0 Readback of the ALC saturation status. 0 = ADC signal = ALC_LVL 1 = ADC signal < ALC_LVL but maximum ALC Gain has been reached 12 ALC_PKOVR_S TS 0 Readback of the ALC Peak Limiter Overload status. Set when ADC input signal exceeds -1.16dBFS 11 ALC_NGATE_S TS 0 Readback of the ALC Noise Gate status. 0 = ADC input signal level > ALC_NGATE_THR 1 = ADC input signal level < ALC_NGATE_THR 7 ALC_ZC 0 ALC Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only 6:4 ALC_MINGAIN [2:0] 000 Minimum ALC gain 000 = -23.25dB 001 = -17.25dB 010 = -11.25dB 011 = -5.25dB 100 = +0.75dB 101 = +6.75dB 110 = +12.75dB 111 = +18.75dB 3:0 ALC_HLD [3:0] 0000 ALC Hold time before the gain ramp-up starts 0000 = 0.00ms 0001 = 2.67ms 0010 = 5.33ms 0011 = 10.7ms 0100 = 21.3ms 0101 = 42.7ms 0110 = 85.3ms 0111 = 171ms 1000 = 341ms 1001 = 683ms 1010 = 1.37s 1011 = 2.73s 1100 = 5.46s 1101 = 10.9s 1110 = 21.8s 1111 = 43.7s Register 12h ALC2 216 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT R19 (13h) ALC3 12:10 ALC_NGATE_G AIN [2:0] 111 8 ALC_MODE 0 7:4 ALC_DCY [3:0] 0011 DESCRIPTION Noise Gate Gain level. This is the PGA gain level used within the ALC Noise Gate function. 000 = -23.25dB 001 = -18dB 010 = -12dB 011 = -6dB 100 = 0dB 101 = +6dB 110 = +12dB 111 = +18dB ALC Mode 0 = Normal ALC Mode 1 = Limiter Mode Note that ALCL_ENA and ALCR_ENA must both be set to 0 before changing ALC_MODE, otherwise unexpected behaviour may result. Sets the Gain Decay Rate (measured in time per 1.5dB step). If ALC_MODE = 0 0000 = 0.41ms / step 0001 = 0.82ms / step …doubling with each step to… 1010 = 420ms / step 1011 = 840ms / step 1100 to 1111 = Reserved If ALC_MODE = 1 0000 = 0.082ms / step 0001 = 0.164ms / step …doubling with each step to… 1010 = 83.9ms / step 1011 = 168ms / step 1100 to 1111 = Reserved Note that when 88.2kHz or 96kHz sample rate is selected, the Gain Decay time is defined as for the ALC_MODE=0 case above. 3:0 ALC_ATK [3:0] 0010 Sets the Gain Attack Rate (measured in time per 1.5dB step). If ALC_MODE = 0 0000 = 0.104ms / step 0001 = 0.208ms / step …doubling with each step to… 1010 = 106ms / step 1011 to 1111 = Reserved If ALC_MODE = 1 0000 = 0.020ms / step 0001 = 0.041ms / step …doubling with each step to… 1010 = 21.0ms / step 1011 to 1111 = Reserved Note that when 88.2kHz or 96kHz sample rate is selected, the Gain Attack time is defined as for the ALC_MODE=0 case above. Register 13h ALC3 Rev 4.4 217 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT R20 (14h) Noise Gate 15:12 ALC_NGATE_D CY [3:0] 0011 DESCRIPTION Sets the Noise Gate Gain Decay Rate (time taken to ramp up to the ALC_NGATE_GAIN level), measured in time per 1.5dB step. If ALC_MODE = 0 0000 = 0.41ms / step 0001 = 0.82ms / step …doubling with each step to… 1010 = 420ms / step 1011 = 840ms / step 1100 to 1111 = Reserved If ALC_MODE = 1 0000 = 0.082ms / step 0001 = 0.164ms / step …doubling with each step to… 1010 = 83.9ms / step 1011 = 168ms / step 1100 to 1111 = Reserved Note that when 88.2kHz or 96kHz sample rate is selected, the Noise Gate Gain Decay time is defined as for the ALC_MODE=0 case above. 11:8 ALC_NGATE_A TK [3:0] 0010 Sets the Gain Attack Rate (time taken to ramp down to the ALC_NGATE_GAIN level), measured in time per 1.5dB step. If ALC_MODE = 0 0000 = 0.10ms / step 0001 = 0.21ms / step …doubling with each step to… 1010 = 106ms / step 1011 to 1111 = Reserved If ALC_MODE = 1 0000 = 0.020ms / step 0001 = 0.041ms / step …doubling with each step to… 1010 = 21.0ms / step 1011 to 1111 = Reserved Note that when 88.2kHz or 96kHz sample rate is selected, the Noise Gain Attack time is defined as for the ALC_MODE=0 case above. 218 7:3 ALC_NGATE_T HR [4:0] 0_0000 Noise Gate Threshold. If the input signal falls below this level, the Noise Gate function is triggered. -76.5dB to -30dB in 1.5dB steps. 2:1 ALC_NGATE_M ODE [1:0] 00 Noise gate mode 00 = Hold PGA gain static when noise gate triggers 01 = Mute ADC output immediately when noise gate triggers. 10 = Ramp PGA Gain to ADC_NGATE_GAIN level when Noise Gate triggers. 11 = Reserved 0 ALC_NGATE_E NA 0 Noise Gate function enable 0 = Disable 1 = Enable Rev 4.4 WM8962 Register 14h Noise Gate REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R21 (15h) Left ADC volume 8 ADC_VU 0 ADC Volume Update Writing a 1 to this bit will cause left and right ADC volume to be updated simultaneously 7:0 ADCL_VOL [7:0] 1100_0000 Left ADC Digital Volume 00h = mute 01h = -71.625dB 02h = -71.250dB …0.375dB steps C0h = 0dB (default) … FFh = 23.625dB Register 15h Left ADC volume REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R22 (16h) Right ADC volume 8 ADC_VU 0 ADC Volume Update Writing a 1 to this bit will cause left and right ADC volume to be updated simultaneously 7:0 ADCR_VOL [7:0] 1100_0000 Right ADC Digital Volume 00h = mute 01h = -71.625dB 02h = -71.250dB …0.375dB steps C0h = 0dB (default) … FFh = 23.625dB Register 16h Right ADC volume REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R23 (17h) Additional control(1) 8 THERR_ACT 1 Speaker and Headphone over temperature shutdown enable. 0 = Disabled 1 = Enabled Note that TEMP_ENA_HP or TEMP_ENA_SPK or both must be enabled for Automatic Shutdown to work 5 ADC_HP 0 ADC Oversampling Ratio 0 = Low Power (typically 64 x fs) 1 = High Performance (typically 128 x fs) 0 TOCLK_ENA 0 TOCLK Enable 0 = Disabled 1 = Enabled Register 17h Additional control(1) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R24 (18h) Additional control(2) 3 AIF_TRI 0 Audio Interface Tristate 0 = Audio interface pins operate normally 1 = ADCDAT is tri-stated; BCLK & LRCLK are set as inputs Rev 4.4 219 WM8962 Register 18h Additional control(2) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R25 (19h) Pwr Mgmt (1) 10 DMIC_ENA 0 Enables Digital Microphone mode. 0 = Audio DSP input is from ADC 1 = Audio DSP input is from digital microphone interface Note that, when the digital microphone interface is selected, the ADCL_ENA and ADCR_ENA registers must also be set to enable the left and right digital microphone channels respectively. 9 OPCLK_ENA 0 GPIO Clock Output Enable 0 = Disabled 1 = Enabled 8:7 VMID_SEL [1:0] 00 VMID Divider Enable and Select 00 = VMID disabled (for OFF mode) 01 = 2 x 50k divider (for normal operation) 10 = 2 x 250k divider (for low power standby) 11 = 2 x 5k divider (for fast start-up) 6 BIAS_ENA 0 Enables the Normal bias current generator (for all analogue functions) 0 = Disabled 1 = Enabled 5 INL_ENA 0 Left Input PGA and Mixer Enable. 0 = Disabled 1 = Enabled 4 INR_ENA 0 Right Input PGA and Mixer Enable. 0 = Disabled 1 = Enabled 3 ADCL_ENA 0 Left ADC Enable 0 = Disabled 1 = Enabled 2 ADCR_ENA 0 Right ADC Enable 0 = Disabled 1 = Enabled 1 MICBIAS_ENA 0 Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON Register 19h Pwr Mgmt (1) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R26 (1Ah) Pwr Mgmt (2) 8 DACL_ENA 0 Left DAC Enable 0 = Disabled 1 = Enabled Note that DACL_ENA must be set to 1 when processing left channel data from the DAC or Digital Beep Generator. 7 DACR_ENA 0 Right DAC Enable 0 = Disabled 1 = Enabled Note that DACR_ENA must be set to 1 when processing right channel data from the DAC or Digital Beep Generator. 6 HPOUTL_PGA_ ENA 0 Headphone Left PGA enable 0 = Disabled 1 = Enabled 220 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 5 HPOUTR_PGA_ ENA 0 Headphone Right PGA enable 0 = Disabled 1 = Enabled 4 SPKOUTL_PGA _ENA 0 Speaker Left PGA enable 0 = Disabled 1 = Enabled 3 SPKOUTR_PGA _ENA 0 Speaker Right PGA enable 0 = Disabled 1 = Enabled 1 HPOUTL_PGA_ MUTE 0 HPOUTL_VOL (Left Headphone Output PGA) Mute 0 = Un-mute 1 = Mute 0 HPOUTR_PGA_ MUTE 0 HPOUTR_VOL (Right Headphone Output PGA) Mute 0 = Un-mute 1 = Mute Register 1Ah Pwr Mgmt (2) REGISTER ADDRESS BIT LABEL DEFAULT R27 (1Bh) Additional Control (3) 4 SAMPLE_RATE _INT_MODE 1 2:0 SAMPLE_RATE [2:0] 000 DESCRIPTION Selects the Integer or Fractional value of the SAMPLE_RATE register. 0 = 11.025k, 22.05k, 44.1k or 88.2kHz 1 = 8k, 12k, 16k, 24k, 32k, 48k or 96kHz Selects the Sample Rate (fs) 000 = 44.1kHz, 48kHz 001 = 32kHz 010 = 22.05kHz, 24kHz 011 = 16kHz 100 = 11.025kHz, 12kHz 101 = 8kHz 110 = 88.2kHz, 96kHz 111 = Reserved Register 1Bh Additional Control (3) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R28 (1Ch) Anti-pop 4 STARTUP_BIAS _ENA 0 Enables the Start-Up bias current generator 0 = Disabled 1 = Enabled 3 VMID_BUF_EN A 0 VMID Buffer Enable 0 = Disabled 1 = Enabled 2 VMID_RAMP 0 Enables VMID soft ramp-up 0 = Disabled 1 = Enabled Register 1Ch Anti-pop Rev 4.4 221 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R30 (1Eh) Clocking 3 15:13 DBCLK_DIV [2:0] 000 DBCLK Rate Divider (divides the 256kHz clock; nominal frequency is quoted in brackets) 000 = f / 256 (1kHz) 001 = f / 2048 (125Hz) 010 = f / 4096 (62.5Hz) 011 = f / 8192 (31.2Hz) 100 = f / 16384 (15.6Hz) 101 = f / 32768 (7.8Hz) 110 = f / 64536 (3.9Hz) 111 = f / 131072 (1.95Hz) 12:10 OPCLK_DIV [2:0] 000 GPIO Output Clock Divider 000 = SYSCLK 001 = SYSCLK / 2 010 = SYSCLK / 3 011 = SYSCLK / 4 100 = SYSCLK / 6 101 = SYSCLK / 8 110 = SYSCLK / 12 111 = SYSCLK / 16 000 = SYSCLK / 16 9:7 TOCLK_DIV [2:0] 000 TOCLK Rate Divider (divides the 256kHz clock; nominal frequency is quoted in brackets) 000 = f / 256 (1kHz) 001 = f / 512 (500Hz) 010 = f / 1024 (250Hz) 011 = f / 2048 (125Hz) 100 = f / 4096 (62.5Hz) 101 = f / 8192 (31.2Hz) 110 = f / 16384 (15.6Hz) 111 = f / 32768 (7.8Hz) 6:1 F256KCLK_DIV [5:0] 10_1111 256kHz Clock Divider 0d = SYSCLK 1d = SYSCLK / 2 2d = SYSCLK / 3 …. 63d = SYSCLK / 64 This field is for read-back only; it is set automatically and cannot be adjusted. Protected by security key. Register 1Eh Clocking 3 REGISTER ADDRESS BIT LABEL DEFAULT R31 (1Fh) Input mixer control (1) 3 MIXINL_MUTE 0 Left input boost mixer mute 0 = Un-mute 1 = Mute 2 MIXINR_MUTE 0 Right input boost mixer mute 0 = Un-mute 1 = Mute 1 MIXINL_ENA 0 Left Input Mixer Enable 0 = Disabled 1 = Enabled Note that the Left Input Mixer is also enabled when INL_ENA is set 222 DESCRIPTION Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT 0 MIXINR_ENA 0 DESCRIPTION Right Input Mixer Enable 0 = Disabled 1 = Enabled Note that the Right Input Mixer is also enabled when INR_ENA is set Register 1Fh Input mixer control (1) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R32 (20h) Left input mixer volume 8:6 IN2L_MIXINL_V OL [2:0] 101 Left input IN2L to Left input Boost Mixer Gain 000 = -12dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 5:3 INPGAL_MIXIN L_VOL [2:0] 000 Left input PGA to Left input Boost Mixer Gain 000 = 0dB 001 = +6dB 010 = +13dB 011 = +18dB 100 = +20dB 101 = +24dB 110 = +27dB 111 = +29dB 2:0 IN3L_MIXINL_V OL [2:0] 101 Left input IN3L to Left input Boost Mixer Gain 000 = -12dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Register 20h Left input mixer volume REGISTER ADDRESS BIT LABEL DEFAULT R33 (21h) Right input mixer volume 8:6 IN2R_MIXINR_ VOL [2:0] 101 Right input IN2R to Right input Boost Mixer Gain 000 = -12dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 5:3 INPGAR_MIXIN R_VOL [2:0] 000 Right input PGA to Right input Boost Mixer Gain 000 = 0dB 001 = +6dB 010 = +13dB 011 = +18dB Rev 4.4 DESCRIPTION 223 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 100 = +20dB 101 = +24dB 110 = +27dB 111 = +29dB 2:0 IN3R_MIXINR_ VOL [2:0] 101 Right input IN3R to Right input Boost Mixer Gain 000 = -12dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Register 21h Right input mixer volume REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R34 (22h) Input mixer control (2) 5 IN2L_TO_MIXIN L 0 Left Input IN2L to Left input Boost Mixer Select 0 = Disabled 1 = Enabled 4 IN3L_TO_MIXIN L 0 Left Input IN3L to Left input Boost Mixer Select 0 = Disabled 1 = Enabled 3 INPGAL_TO_MI XINL 1 Left Input PGA to Left input Boost Mixer Select 0 = Disabled 1 = Enabled 2 IN2R_TO_MIXI NR 0 Right input IN2R to Right input Boost Mixer Select 0 = Disabled 1 = Enabled 1 IN3R_TO_MIXI NR 0 Right input IN3R to Right input Boost Mixer Select 0 = Disabled 1 = Enabled 0 INPGAR_TO_MI XINR 1 Right input PGA to Right input Boost Mixer Select 0 = Disabled 1 = Enabled Register 22h Input mixer control (2) REGISTER ADDRESS BIT LABEL DEFAULT R35 (23h) Input bias control 5:3 MIXIN_BIAS [2:0] 000 Input Boost-Mixer Bias Control 000 = x 2.0 (default) 001 = Reserved 010 = Reserved 011 = x 1.0 100 = x 0.67 101 to 111 = Reserved 2:0 INPGA_BIAS [2:0] 100 Input PGA Bias Control 000 = x 2.0 001 = Reserved 010 = Reserved 011 = Reserved 100 = x 0.67 (default) 101 to 111 = Reserved 224 DESCRIPTION Rev 4.4 WM8962 Register 23h Input bias control REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R37 (25h) Left input PGA control 4 INPGAL_ENA 0 Left Input PGA Enable. 0 = Disabled 1 = Enabled Note that the Left Input PGA is also enabled when INL_ENA is set 3 IN1L_TO_INPG AL 1 Selects the IN1L pin as an input to the left PGA 0 = Disabled 1 = Enabled 2 IN2L_TO_INPG AL 0 Selects the IN2L pin as an input to the left PGA 0 = Disabled 1 = Enabled 1 IN3L_TO_INPG AL 0 Selects the IN3L pin as an input to the left PGA 0 = Disabled 1 = Enabled 0 IN4L_TO_INPG AL 0 Selects the IN4L pin as an input to the left PGA 0 = Disabled 1 = Enabled Register 25h Left input PGA control REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R38 (26h) Right input PGA control 4 INPGAR_ENA 0 Right Input PGA Enable 0 = Disabled 1 = Enabled Note that the Right Input PGA is also enabled when INR_ENA is set 3 IN1R_TO_INPG AR 1 Selects the IN1R pin as an input to the right PGA 0 = Disabled 1 = Enabled 2 IN2R_TO_INPG AR 0 Selects the IN2R pin as an input to the right PGA 0 = Disabled 1 = Enabled 1 IN3R_TO_INPG AR 0 Selects the IN3R pin as an input to the right PGA 0 = Disabled 1 = Enabled 0 IN4R_TO_INPG AR 0 Selects the IN4R pin as an input to the right PGA 0 = Disabled 1 = Enabled Register 26h Right input PGA control REGISTER ADDRESS BIT LABEL DEFAULT R40 (28h) SPKOUTL volume 8 SPKOUT_VU 0 Speaker Output PGA Volume Update Writing a 1 to this bit will update SPKOUTL_VOL and SPKOUTR_VOL volumes simultaneously. 7 SPKOUTL_ZC 0 SPKOUTL_VOL (Left Speaker Output PGA) Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled Rev 4.4 DESCRIPTION 225 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT 6:0 SPKOUTL_VOL [6:0] 000_0000 DESCRIPTION Left Speaker Output PGA Volume 000_0000 to 010_1111 = Mute 011_0000 to 011_0101 = -68dB 011_0110 = -67dB …in 1dB steps 111_1001 = 0dB … 111_1111 = +6dB Register 28h SPKOUTL volume REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R41 (29h) SPKOUTR volume 8 SPKOUT_VU 0 Speaker Output PGA Volume Update Writing a 1 to this bit will update SPKOUTL_VOL and SPKOUTR_VOL volumes simultaneously. 7 SPKOUTR_ZC 0 SPKOUTR_VOL (Right Speaker Output PGA) Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled 6:0 SPKOUTR_VOL [6:0] 000_0000 Right Speaker Output PGA Volume 000_0000 to 010_1111 = Mute 011_0000 to 011_0101 = -68dB 011_0110 = -67dB …in 1dB steps 111_1001 = 0dB … 111_1111 = +6dB Register 29h SPKOUTR volume REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R47 (2Fh) Thermal Shutdown Status 3 TEMP_ERR_HP 0 Headphone temperature error status (triggered at 145°C) 0 = Not triggered 1 = Triggered Note that this is a Read Only field 2 TEMP_WARN_ HP 0 Headphone temperature warning status (triggered at 125°C) 0 = Not triggered 1 = Triggered Note that this is a Read Only field 1 TEMP_ERR_SP K 0 Speaker temperature error status (triggered at 145°C) 0 = Not triggered 1 = Triggered Note that this is a Read Only field 0 TEMP_WARN_ SPK 0 Speaker temperature warning status (triggered at 125°C) 0 = Not triggered 1 = Triggered Note that this is a Read Only field Register 2Fh Thermal Shutdown Status 226 Rev 4.4 WM8962 REGISTER ADDRESS R48 (30h) Additional Control (4) BIT LABEL DEFAULT DESCRIPTION Reserved - do not change 15 Reserved 1 14:12 MICDET_THR [2:0] 000 MICBIAS Current Detect Threshold (AVDD = 1.8V) 000 = 64uA 001 = 166uA 010 = 375uA 011 = 475uA 100 = 575uA 101 = 680uA 110 = 885uA 111 = 990uA Note that the value scales with AVDD. The value quoted is correct for AVDD=1.8V 11:10 MICSHORT_TH R [1:0] 00 MICBIAS Short Circuit Threshold (AVDD = 1.8V) 00 = 515uA 01 = 680uA 10 = 1050uA 11 = 1215uA Note that the value scales with AVDD. The value quoted is correct for AVDD=1.8V 9 MICDET_ENA 0 MICBIAS Current and Short Circuit Detect Enable 0 = Disabled 1 = Enabled 7 MICDET_STS 0 MICBIAS Current Detection status 0 = Current Detect threshold not exceeded 1 = Current Detect threshold exceeded 6 MICSHORT_ST S 0 MICBIAS Short Circuit status 0 = Short Circuit threshold not exceeded 1 = Short Circuit threshold exceeded 5 Reserved 1 Reserved - do not change 2 TEMP_ENA_HP 1 Headphone temperature sensor enable 0 = Disabled 1 = Enabled 1 TEMP_ENA_SP K 1 Speaker temperature sensor enable 0 = Disabled 1 = Enabled 0 MICBIAS_LVL 1 Microphone Bias Voltage Control 0 = 5/6 x AVDD (approx.) 1 = 7/6 x AVDD (approx.) Register 30h Additional Control (4) REGISTER ADDRESS BIT LABEL DEFAULT R49 (31h) Class D Control 1 7 SPKOUTR_ENA 0 Right channel class D Speaker Enable 0 = Disabled 1 = Enabled 6 SPKOUTL_ENA 0 Left channel class D Speaker Enable 0 = Disabled 1 = Enabled 4 DAC_MUTE 1 Digital DAC Mute 0 = Un-mute 1 = Mute Note that this bit also exists in R5. Reading or writing to either location has the same effect. Rev 4.4 DESCRIPTION 227 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2 SPKOUT_VU 0 Speaker Output PGA Volume Update Writing a 1 to this bit will update SPKOUTL_VOL and SPKOUTR_VOL volumes simultaneously. 1 SPKOUTL_PGA _MUTE 0 SPKOUTL_VOL (Left Speaker Output PGA) Mute 0 = Un-mute 1 = Mute 0 SPKOUTR_PGA _MUTE 0 SPKOUTR_VOL (Right Speaker Output PGA) Mute 0 = Un-mute 1 = Mute Register 31h Class D Control 1 REGISTER ADDRESS BIT LABEL DEFAULT R51 (33h) Class D Control 2 6 SPK_MONO 0 2:0 CLASSD_VOL [2:0] 011 DESCRIPTION Mono Speaker Configuration enable 0 = Class D drives into 8 ohm loads 1 = Class D drives into a mono 4 ohm load When SPK_MONO is enabled, both speakers output the signal from the left channel. Note that the user must tie the outputs together for mono use AC Speaker Gain Boost. Note that both left and right channels are boosted equally 000 = 1.00x boost (+0dB) 001 = 1.19x boost (+1.5dB) 010 = 1.41x boost (+3.0dB) 011 = 1.68x boost (+4.5dB) 100 = 2.00x boost (+6.0dB) 101 = 2.37x boost (+7.5dB) 110 = 2.81x boost (+9.0dB) 111 = 3.98x boost (+12.0dB) Register 33h Class D Control 2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R56 (38h) Clocking 4 4:1 MCLK_RATE [3:0] 0011 Selects the MCLK / fs ratio. (Note that the MCLK source is selected by MCLK_SRC.) 0000 = 64 0001 = 128 0010 = 192 0011 = 256 (default) 0100 = 384 0101 = 512 0110 = 768 0111 = 1024 1000 = Reserved 1001 = 1536 1010 = 3072 1011 = 6144 1100 to 1111 = Reserved If ADC ReTune, DAC ReTune, DAC HPF, VSS or HD Bass is enabled, then MCLK_RATE must be 512 or higher Register 38h Clocking 4 228 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R57 (39h) DAC DSP Mixing (1) 9 DAC_MONOMI X 0 7:4 ADCR_DAC_SV OL [3:0] 0000 Right ADC Digital Sidetone Volume 0000 = -36dB 0001 = -33dB (… 3dB steps) 1011 = -3dB 11XX = 0dB 3:2 ADC_TO_DACR [1:0] 00 Right DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = No sidetone DAC Mono Mix 0 = Stereo 1 = Mono (Mono mix output on enabled DAC) Mono Mix is only supported when one or other DAC is disabled. When Mono mix is enabled, 6dB attenuation is applied. Register 39h DAC DSP Mixing (1) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R58 (3Ah) DAC DSP Mixing (2) 7:4 ADCL_DAC_SV OL [3:0] 0000 Left ADC Digital Sidetone Volume 0000 = -36dB 0001 = -33dB (… 3dB steps) 1011 = -3dB 11XX = 0dB 3:2 ADC_TO_DACL [1:0] 00 Left DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = No sidetone Register 3Ah DAC DSP Mixing (2) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R60 (3Ch) DC Servo 0 7 INL_DCS_ENA 0 DC Servo enable for Left input signal path 0 = Disabled 1 = Enabled 6 INL_DCS_STAR TUP 0 Writing 1 to this bit selects Start-Up DC Servo mode for Left input signal path 3 INR_DCS_ENA 0 DC Servo enable for Right input signal path 0 = Disabled 1 = Enabled 2 INR_DCS_STA RTUP 0 Writing 1 to this bit selects Start-Up DC Servo mode for Right input signal path Register 3Ch DC Servo 0 Rev 4.4 229 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R61 (3Dh) DC Servo 1 7 HP1L_DCS_EN A 0 DC Servo enable for HPOUTL 0 = Disabled 1 = Enabled 6 HP1L_DCS_ST ARTUP 0 Writing 1 to this bit selects Start-Up DC Servo mode for HPOUTL 4 HP1L_DCS_SY NC 0 Writing 1 to this bit selects a series of DC offset corrections for HPOUTL 3 HP1R_DCS_EN A 0 DC Servo enable for HPOUTR 0 = Disabled 1 = Enabled 2 HP1R_DCS_ST ARTUP 0 Writing 1 to this bit selects Start-Up DC Servo mode for HPOUTR 0 HP1R_DCS_SY NC 0 Writing 1 to this bit selects a series of DC offset corrections for HPOUTR DESCRIPTION Register 3Dh DC Servo 1 REGISTER ADDRESS BIT LABEL DEFAULT R64 (40h) DC Servo 4 13:7 HP1_DCS_SYN C_STEPS [6:0] 001_0000 Number of DC Servo updates to perform in a series event (HPOUTL and HPOUTR) 00h to 0Fh = Reserved 10h = 16 (default) 11h = 17 … 7Fh = 127 Register 40h DC Servo 4 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R66 (42h) DC Servo 6 10 DCS_STARTUP _DONE_INL 0 DC Servo Start-Up Status (Left Input) 0 = Not complete 1 = Complete 9 DCS_STARTUP _DONE_INR 0 DC Servo Start-Up Status (Right Input) 0 = Not complete 1 = Complete 8 DCS_STARTUP _DONE_HP1L 0 DC Servo Start-Up Status (HPOUTL) 0 = Not complete 1 = Complete 7 DCS_STARTUP _DONE_HP1R 0 DC Servo Start-Up Status (HPOUTR) 0 = Not complete 1 = Complete Register 42h DC Servo 6 230 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R68 (44h) Analogue PGA Bias 4 Reserved 1 Reserved - do not change 3 Reserved 1 Reserved - do not change 2:0 HP_PGAS_BIA S [2:0] 011 Headphone PGA Boost Bias 000 = x 2.0 001 = Reserved 010 = Reserved 011 = x 1.0 (default) 100 to 111 = Reserved Register 44h Analogue PGA Bias REGISTER ADDRESS BIT LABEL DEFAULT R69 (45h) Analogue HP 0 7 HP1L_RMV_SH ORT 0 Removes HP1L short 0 = HP1L short enabled 1 = HP1L short removed For pop-free operation, this bit should be set to 1 as the final step in the HP1L Enable sequence. 6 HP1L_ENA_OU TP 0 Enables HP1L output stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set to 1 after the DC offset cancellation has been performed. 5 HP1L_ENA_DL Y 0 Enables HP1L intermediate stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set to 1 after the output signal path has been configured, and before the DC Offset cancellation is scheduled This bit should be set with at least 20us delay after HP1L_ENA. 4 HP1L_ENA 0 Enables HP1L input stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set as the first stage of the HP1L Enable sequence. 3 HP1R_RMV_SH ORT 0 Removes HP1R short 0 = HP1R short enabled 1 = HP1R short removed For pop-free operation, this bit should be set to 1 as the final step in the HP1R Enable sequence. 2 HP1R_ENA_OU TP 0 Enables HP1R output stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set to 1 after the DC offset cancellation has been performed. 1 HP1R_ENA_DL Y 0 Enables HP1R intermediate stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set to 1 after the output signal path has been configured, and before the DC Offset cancellation is scheduled This bit should be set with at least 20us delay after HP1R_ENA. 0 HP1R_ENA 0 Enables HP1R input stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set as the first stage of the HP1R Enable sequence. Rev 4.4 DESCRIPTION 231 WM8962 Register 45h Analogue HP 0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R71 (47h) Analogue HP 2 8:6 HP1L_VOL [2:0] 111 Headphone 1 Left Secondary PGA volume. 000 = -7dB 001 = -6dB 010 = -5dB 011 = -4dB 100 = -3dB 101 = -2dB 110 = -1dB 111 = 0dB (default) 5:3 HP1R_VOL [2:0] 111 Headphone 1 Right Secondary PGA volume. 000 = -7dB 001 = -6dB 010 = -5dB 011 = -4dB 100 = -3dB 101 = -2dB 110 = -1dB 111 = 0dB (default) 2:0 HP_BIAS_BOO ST [2:0] 011 Headphone Driver Boost Bias 000 = x 2.0 001 = Reserved 010 = Reserved 011 = x 1.0 (default) 100 to 111 = Reserved Register 47h Analogue HP 2 REGISTER ADDRESS BIT LABEL DEFAULT R72 (48h) Charge Pump 1 0 CP_ENA 0 DESCRIPTION Enable charge-pump digits 0 = disable 1 = enable Register 48h Charge Pump 1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R82 (52h) Charge Pump B 0 CP_DYN_PWR 0 Enable dynamic charge pump power control 0 = Charge pump controlled by volume register settings (Class G) 1 = Charge pump controlled by real-time audio level (Class W) Class W is recommended for lowest power consumption When selecting CP_DYN_PWR=0, a ‘1’ must be written to the HPOUT_VU bit (Register R2 or R3) to complete the mode change. Register 52h Charge Pump B 232 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R87 (57h) Write Sequencer Control 1 7 WSEQ_AUTOS EQ_ENA 0 Write Sequencer Auto-Sequence Enable (controls the Class D driver via DAC Auto-Mute function) 0 = Disabled 1 = Enabled 5 WSEQ_ENA 0 Write Sequencer Enable. 0 = Disabled 1 = Enabled Register 57h Write Sequencer Control 1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R90 (5Ah) Write Sequencer Control 2 8 WSEQ_ABORT 0 Writing a 1 to this bit aborts the current sequence and returns control of the device back to the serial control interface. 7 WSEQ_START 0 Writing a 1 to this bit starts the write sequencer at the index location selected by WSEQ_START_INDEX. The sequence continues until it reaches an “End of sequence” flag. At the end of the sequence, this bit will be reset by the Write Sequencer. 6:0 WSEQ_START_ INDEX [6:0] 000_0000 Sequence Start Index. This field determines the memory location of the first command in the selected sequence. There are 127 Write Sequencer RAM addresses: 00h = WSEQ_ADDR0 (R4096) 01h = WSEQ_ADDR1 (R4100) 02h = WSEQ_ADDR2 (R4104) …. 7Fh = WSEQ_ADDR127 (R4604) Register 5Ah Write Sequencer Control 2 REGISTER ADDRESS BIT LABEL DEFAULT R93 (5Dh) Write Sequencer Control 3 9:3 WSEQ_CURRE NT_INDEX [6:0] 000_0000 0 WSEQ_BUSY 0 DESCRIPTION Sequence Current Index. This indicates the memory location of the most recently accessed command in the write sequencer memory. Coding is the same as WSEQ_START_INDEX. Sequencer Busy flag (Read Only). 0 = Sequencer idle 1 = Sequencer busy Note: it is not possible to write to non-PLL control registers via the control interface while the Sequencer is Busy. Register 5Dh Write Sequencer Control 3 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R94 (5Eh) Control Interface 6 SPI_CONTRD 0 Enable continuous read mode in SPI (3-wire/4-wire) modes 0 = Disabled 1 = Enabled 5 SPI_4WIRE 0 SPI control mode select 0 = 3-wire using bidirectional SDA 1 = 4-wire using SDOUT Rev 4.4 233 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT 4 SPI_CFG 0 DESCRIPTION SDA/SDOUT pin configuration In 3-wire mode (SPI_4WIRE=0): 0 = SDA output is CMOS 1 = SDA output is Open Drain In 4-wire mode (SPI_4WIRE=1): 0 = SDOUT output is CMOS 1 = SDOUT output is Wired ‘OR’. Note that only GPIO5 can be configured as Wired ‘OR’. This bit has no effect on GPIO2 or GPIO3. Register 5Eh Control Interface REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R99 (63h) Mixer Enables 3 HPMIXL_ENA 0 Left Headphone Mixer Enable 0 = Disabled 1 = Enabled 2 HPMIXR_ENA 0 Right Headphone Mixer Enable 0 = Disabled 1 = Enabled 1 SPKMIXL_ENA 0 Left Speaker Mixer Enable 0 = Disabled 1 = Enabled 0 SPKMIXR_ENA 0 Right Speaker Mixer Enable 0 = Disabled 1 = Enabled Register 63h Mixer Enables REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R100 (64h) Headphone Mixer (1) 7 HPMIXL_TO_H POUTL_PGA 0 Left Headphone PGA Path Select 0 = DACL Output 1 = HPMIXL Output 5 DACL_TO_HPM IXL 0 Left DAC to Left Headphone Mixer select 0 = Disabled 1 = Enabled 4 DACR_TO_HP MIXL 0 Right DAC to Left Headphone Mixer select 0 = Disabled 1 = Enabled 3 MIXINL_TO_HP MIXL 0 Left Input Mixer to Left Headphone Mixer select 0 = Disabled 1 = Enabled 2 MIXINR_TO_HP MIXL 0 Right Input Mixer to Left Headphone Mixer select 0 = Disabled 1 = Enabled 1 IN4L_TO_HPMI XL 0 Input IN4L to Left Headphone Mixer select 0 = Disabled 1 = Enabled 0 IN4R_TO_HPMI XL 0 Input IN4R to Left Headphone Mixer select 0 = Disabled 1 = Enabled Register 64h Headphone Mixer (1) 234 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R101 (65h) Headphone Mixer (2) 7 HPMIXR_TO_H POUTR_PGA 0 Right Headphone PGA Path Select 0 = DACR Output 1 = HPMIXR Output 5 DACL_TO_HPM IXR 0 Left DAC to Right Headphone Mixer select 0 = Disabled 1 = Enabled 4 DACR_TO_HP MIXR 0 Right DAC to Right Headphone Mixer select 0 = Disabled 1 = Enabled 3 MIXINL_TO_HP MIXR 0 Left Input Mixer to Right Headphone Mixer select 0 = Disabled 1 = Enabled 2 MIXINR_TO_HP MIXR 0 Right Input Mixer to Right Headphone Mixer select 0 = Disabled 1 = Enabled 1 IN4L_TO_HPMI XR 0 Input IN4L to Right Headphone Mixer select 0 = Disabled 1 = Enabled 0 IN4R_TO_HPMI XR 0 Input IN4R to Right Headphone Mixer select 0 = Disabled 1 = Enabled Register 65h Headphone Mixer (2) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R102 (66h) Headphone Mixer (3) 8 HPMIXL_MUTE 1 Left Headphone Mixer Mute 0 = Unmuted 1 = Muted 7 MIXINL_HPMIX L_VOL 0 Left Input Mixer to Left Headphone Mixer volume 0 = 0dB 1 = -6dB 6 MIXINR_HPMIX L_VOL 0 Right Input Mixer to Left Headphone Mixer volume 0 = 0dB 1 = -6dB 5:3 IN4L_HPMIXL_ VOL [2:0] 111 Input IN4L to Left Headphone Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 2:0 IN4R_HPMIXL_ VOL [2:0] 111 Input IN4R to Left Headphone Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Register 66h Headphone Mixer (3) Rev 4.4 235 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R103 (67h) Headphone Mixer (4) 8 HPMIXR_MUTE 1 Right Headphone Mixer Mute 0 = Unmuted 1 = Muted 7 MIXINL_HPMIX R_VOL 0 Left Input Mixer to Right Headphone Mixer volume 0 = 0dB 1 = -6dB 6 MIXINR_HPMIX R_VOL 0 Right Input Mixer to Right Headphone Mixer volume 0 = 0dB 1 = -6dB 5:3 IN4L_HPMIXR_ VOL [2:0] 111 Input IN4L to Right Headphone Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 2:0 IN4R_HPMIXR_ VOL [2:0] 111 Input IN4R to Right Headphone Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Register 67h Headphone Mixer (4) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R105 (69h) Speaker Mixer (1) 7 SPKMIXL_TO_S PKOUTL_PGA 0 Left Speaker PGA Path Select 0 = DACL Output 1 = SPKMIXL Output 5 DACL_TO_SPK MIXL 0 Left DAC to Left Speaker Mixer select 0 = Disabled 1 = Enabled 4 DACR_TO_SPK MIXL 0 Right DAC to Left Speaker Mixer select 0 = Disabled 1 = Enabled 3 MIXINL_TO_SP KMIXL 0 Left Input Mixer to Left Speaker Mixer select 0 = Disabled 1 = Enabled 2 MIXINR_TO_SP KMIXL 0 Right Input Mixer to Left Speaker Mixer select 0 = Disabled 1 = Enabled 1 IN4L_TO_SPKM IXL 0 Input IN4L to Left Speaker Mixer select 0 = Disabled 1 = Enabled 0 IN4R_TO_SPK MIXL 0 Input IN4R to Left Speaker Mixer select 0 = Disabled 1 = Enabled Register 69h Speaker Mixer (1) 236 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R106 (6Ah) Speaker Mixer (2) 7 SPKMIXR_TO_ SPKOUTR_PGA 0 Right Speaker PGA Path Select 0 = DACR Output 1 = SPKMIXR Output 5 DACL_TO_SPK MIXR 0 Left DAC to Right Speaker Mixer select 0 = Disabled 1 = Enabled 4 DACR_TO_SPK MIXR 0 Right DAC to Right Speaker Mixer select 0 = Disabled 1 = Enabled 3 MIXINL_TO_SP KMIXR 0 Left Input Mixer to Right Speaker Mixer select 0 = Disabled 1 = Enabled 2 MIXINR_TO_SP KMIXR 0 Right Input Mixer to Right Speaker Mixer select 0 = Disabled 1 = Enabled 1 IN4L_TO_SPKM IXR 0 Input IN4L to Right Speaker Mixer select 0 = Disabled 1 = Enabled 0 IN4R_TO_SPK MIXR 0 Input IN4R to Right Speaker Mixer select 0 = Disabled 1 = Enabled Register 6Ah Speaker Mixer (2) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R107 (6Bh) Speaker Mixer (3) 8 SPKMIXL_MUT E 1 Left Speaker Mixer Mute 0 = Unmuted 1 = Muted 7 MIXINL_SPKMI XL_VOL 0 Left Input Mixer to Left Speaker Mixer volume 0 = 0dB 1 = -6dB 6 MIXINR_SPKMI XL_VOL 0 Right Input Mixer to Left Speaker Mixer volume 0 = 0dB 1 = -6dB 5:3 IN4L_SPKMIXL _VOL [2:0] 111 Input IN4L to Left Speaker Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 2:0 IN4R_SPKMIXL _VOL [2:0] 111 Input IN4R to Left Speaker Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Register 6Bh Speaker Mixer (3) Rev 4.4 237 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R108 (6Ch) Speaker Mixer (4) 8 SPKMIXR_MUT E 1 Right Speaker Mixer Mute 0 = Unmuted 1 = Muted 7 MIXINL_SPKMI XR_VOL 0 Left Input Mixer to Right Speaker Mixer volume 0 = 0dB 1 = -6dB 6 MIXINR_SPKMI XR_VOL 0 Right Input Mixer to Right Speaker Mixer volume 0 = 0dB 1 = -6dB 5:3 IN4L_SPKMIXR _VOL [2:0] 111 Input IN4L to Right Speaker Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 2:0 IN4R_SPKMIXR _VOL [2:0] 111 Input IN4R to Right Speaker Mixer Volume control 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Register 6Ch Speaker Mixer (4) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R109 (6Dh) Speaker Mixer (5) 7 DACL_SPKMIX L_VOL 0 Left DAC to Left Speaker Mixer volume 0 = 0dB 1 = -6dB 6 DACR_SPKMIX L_VOL 0 Right DAC to Left Speaker Mixer volume 0 = 0dB 1 = -6dB 5 DACL_SPKMIX R_VOL 0 Left DAC to Right Speaker Mixer volume 0 = 0dB 1 = -6dB 4 DACR_SPKMIX R_VOL 0 Right DAC to Right Speaker Mixer volume 0 = 0dB 1 = -6dB 1 Reserved 1 Reserved - do not change 0 Reserved 1 Reserved - do not change Register 6Dh Speaker Mixer (5) 238 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R110 (6Eh) Beep Generator (1) 7:4 BEEP_GAIN [3:0] 0000 2:1 BEEP_RATE [1:0] 01 Digital Beep Waveform Control If SAMPLE_RATE_INT_MODE = 1 00 = 500Hz 01 = 1000Hz 10 = 2000Hz 11 = 4000Hz If SAMPLE_RATE_INT_MODE = 0 00 = 499 – 502Hz 01 = 999 – 1003Hz 10 = 1998 – 2005Hz 11 = 3997 – 4009Hz 0 BEEP_ENA 0 Digital Beep Enable 0 = Disabled 1 = Enabled Note that the DAC and associated signal path needs to be enabled when using the digital beep. Digital Beep Volume Control 0000 = mute 0001 = -90dB 0010 = -84dB … (6dB steps) 1111 = -6dB Register 6Eh Beep Generator (1) REGISTER ADDRESS BIT LABEL DEFAULT R115 (73h) Oscillator Trim (3) 4:0 OSC_TRIM_XTI [4:0] 0_0000 DESCRIPTION Trimmed Oscillator XTI capacitance 00h = 8pF 01h = 8.5pF … 0.5pF steps 1Eh = 23pF 1Fh = 23.5pF This field is for read-back only; it is set automatically and cannot be adjusted. Protected by security key. Register 73h Oscillator Trim (3) REGISTER ADDRESS BIT LABEL DEFAULT R116 (74h) Oscillator Trim (4) 4:0 OSC_TRIM_XT O [4:0] 0_0000 DESCRIPTION Trimmed Oscillator XTO capacitance 00h = 8pF 01h = 8.5pF … 0.5pF steps 1Eh = 23pF 1Fh = 23.5pF This field is for read-back only; it is set automatically and cannot be adjusted. Protected by security key. Register 74h Oscillator Trim (4) Rev 4.4 239 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R119 (77h) Oscillator Trim (7) 7:4 XTO_CAP_SEL [3:0] 0000 XTO load capacitance adjustment Two's complement format, LSB = 0.5pF Range is -4.0pF to +3.5pF 3:0 XTI_CAP_SEL [3:0] 0000 XTI load capacitance adjustment Two's complement format, LSB = 0.5pF Range is -4.0pF to +3.5pF Register 77h Oscillator Trim (7) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R124 (7Ch) Analogue Clocking1 6:5 CLKOUT2_SEL [1:0] 00 CLKOUT2 Output Select 00 = PLL2 01 = GPIO2 10 = Internal oscillator 11 = Reserved 4:3 CLKOUT3_SEL [1:0] 10 CLKOUT3 Output Select 00 = PLL3 01 = GPIO3 10 = FLL 11 = Reserved If CLKREG_OVD = 0, then CLKOUT3_SEL = 10 (FLL) and cannot be changed by the Control Interface. If CLKREG_OVD = 1, then CLKOUT3_SEL = 00 (PLL3) by default, but the value can be changed via the Control Interface. 0 CLKOUT5_SEL 1 CLKOUT5 Output Select 0 = Internal oscillator 1 = FLL If CLKREG_OVD = 0, then CLKOUT5_SEL is controlled by the GPIO5 pin. If CLKREG_OVD = 0 and GPIO5 = 0, then CLKOUT5_SEL = 1 (FLL) and cannot be changed by the Control Interface. If CLKREG_OVD = 0 and GPIO5 = 1, then CLKOUT5_SEL = 0 (Oscillator) by default, but the value can be changed via the Control Interface. If CLKREG_OVD = 1 then CLKOUT5_SEL = 0 (Oscillator) by default, but the value can be changed via the Control Interface. DESCRIPTION Register 7Ch Analogue Clocking1 REGISTER ADDRESS BIT LABEL DEFAULT R125 (7Dh) Analogue Clocking2 7 PLL2_OUTDIV 0 PLL2 Output Divider 0 = Divide by 2 1 = Divide by 4 6 PLL3_OUTDIV 1 PLL3 Output Divider 0 = Divide by 2 1 = Divide by 4 240 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT 4:3 PLL_SYSCLK_ DIV [1:0] 01 DESCRIPTION PLL3 to SYSCLK divider 00 = PLL3 / 1 01 = PLL3 / 2 10 = PLL3 / 4 11 = Reserved 2 CLKOUT3_DIV 0 CLKOUT3 Output Divide 0 = Divide by 1 1 = Divide by 2 1 CLKOUT2_DIV 1 CLKOUT2 Output Divide 0 = Divide by 1 1 = Divide by 2 If CLKREG_OVD = 0, then CLKOUT2_DIV = 1 (Divide by 2) and cannot be changed by the Control Interface. If CLKREG_OVD = 1, then CLKOUT2_DIV = 0 by default, but the value can be changed via the Control Interface. 0 CLKOUT5_DIV 1 CLKOUT5 Output Divide 0 = Divide by 1 1 = Divide by 2 If CLKREG_OVD = 0, then CLKOUT5_DIV = 1 (Divide by 2) and cannot be changed by the Control Interface. If CLKREG_OVD = 1, then CLKOUT5_DIV = 0 by default, but the value can be changed via the Control Interface. Register 7Dh Analogue Clocking2 REGISTER ADDRESS BIT LABEL DEFAULT R126 (7Eh) Analogue Clocking3 DESCRIPTION 4 Reserved 1 Reserved - do not change 3 CLKOUT2_OE 1 CLKOUT2 Output Enable 0 = Disabled (tri-state) 1 = Enabled 2 CLKOUT3_OE 1 CLKOUT3 Output Enable 0 = Disabled (tri-state) 1 = Enabled 1 Reserved 1 Reserved - do not change 0 CLKOUT5_OE 1 CLKOUT5 Output Enable 0 = Disabled (tri-state) 1 = Enabled Register 7Eh Analogue Clocking3 REGISTER ADDRESS BIT LABEL R127 (7Fh) PLL Software Reset 15:0 SW_RESET_PL L [15:0] DEFAULT DESCRIPTION 0000_0000 Writing to this register resets all PLL registers to their _0000_000 default state. 0 This affects registers R114 (72h) through to R152 (98h) Register 7Fh PLL Software Reset Rev 4.4 241 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R129 (81h) PLL2 7 OSC_ENA 0 Internal Oscillator Enable 0 = Disabled 1 = Enabled If CLKREG_OVD = 0 and GPIO5 = 0, then OSC_ENA = 0 and cannot be changed by the Control Interface If CLKREG_OVD = 0 and GPIO5 = 1, then OSC_ENA = 1 by default, but the value can be changed via the Control Interface If CLKREG_OVD = 1 then OSC_ENA = 1 by default, but the value can be changed via the Control Interface 5 PLL2_ENA 0 PLL2 Enable 0 = Disabled 1 = Enabled If CLKREG_OVD = 0, then PLL2_ENA = 0 (Disabled) and cannot be changed by the Control Interface. If CLKREG_OVD = 1, then PLL2_ENA = 1 by default, but the value can be changed via the Control Interface. 4 PLL3_ENA 0 PLL3 Enable 0 = Disabled 1 = Enabled If CLKREG_OVD = 0, then PLL3_ENA = 0 (Disabled) and cannot be changed by the Control Interface. If CLKREG_OVD = 1, then PLL3_ENA = 1 by default, but the value can be changed via the Control Interface. 0 Reserved 1 Reserved - do not change LABEL DEFAULT Register 81h PLL2 REGISTER ADDRESS BIT DESCRIPTION R131 (83h) PLL 4 4 Reserved 1 Reserved - do not change 1 PLL_CLK_SRC 0 PLL Clock Source 0 = Internal oscillator 1 = MCLK Note that the SEQ_ENA bit (Register R150, 96h) must be set to 0 when MCLK is selected as the PLL Clock Source. 0 FLL_TO_PLL3 0 PLL3 Clock Source 0 = Selected by PLL_CLK_SRC 1 = FLL Register 83h PLL 4 REGISTER ADDRESS BIT LABEL DEFAULT R136 (88h) PLL 9 6 PLL2_FRAC 1 4:0 PLL2_N [4:0] 0_0111 DESCRIPTION PLL2 Fractional enable 0 = Integer Mode 1 = Fractional Mode (recommended) Integer Multiply for PLL2 (LSB = 1) Register 88h PLL 9 242 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL R137 (89h) PLL 10 7:0 PLL2_K [7:0] DEFAULT DESCRIPTION 0001_1100 Fractional Multiply for PLL2 (MSB = 0.5) This is bits 23:16 of a 24-bit field Register 89h PLL 10 REGISTER ADDRESS BIT LABEL R138 (8Ah) PLL 11 7:0 PLL2_K [7:0] DEFAULT DESCRIPTION 0111_0001 Fractional Multiply for PLL2 (MSB = 0.5) This is bits 15:8 of a 24-bit field Register 8Ah PLL 11 REGISTER ADDRESS BIT LABEL R139 (8Bh) PLL 12 7:0 PLL2_K [7:0] DEFAULT DESCRIPTION 1100_0111 Fractional Multiply for PLL2 (MSB = 0.5) This is bits 7:0 of a 24-bit field Register 8Bh PLL 12 REGISTER ADDRESS BIT LABEL DEFAULT R140 (8Ch) PLL 13 6 PLL3_FRAC 1 4:0 PLL3_N [4:0] 0_0111 DEFAULT DESCRIPTION PLL3 Fractional enable 0 = Integer Mode 1 = Fractional Mode (recommended) Integer Multiply for PLL3 (LSB = 1) Register 8Ch PLL 13 REGISTER ADDRESS BIT LABEL R141 (8Dh) PLL 14 7:0 PLL3_K [7:0] DESCRIPTION 0100_1000 Fractional Multiply for PLL3 (MSB = 0.5) This is bits 23:16 of a 24-bit field Register 8Dh PLL 14 REGISTER ADDRESS BIT LABEL R142 (8Eh) PLL 15 7:0 PLL3_K [7:0] DEFAULT DESCRIPTION 0010_0010 Fractional Multiply for PLL3 (MSB = 0.5) This is bits 15:8 of a 24-bit field Register 8Eh PLL 15 Rev 4.4 243 WM8962 REGISTER ADDRESS BIT LABEL R143 (8Fh) PLL 16 7:0 PLL3_K [7:0] DEFAULT DESCRIPTION 1001_0111 Fractional Multiply for PLL3 (MSB = 0.5) This is bits 7:0 of a 24-bit field Register 8Fh PLL 16 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R150 (96h) PLL DLL 1 SEQ_ENA 1 PLL Control Sequencer Enable 0 = Disabled 1 = Enabled This bit must be set to 0 when MCLK is selected as the PLL Clock Source. 0 Reserved 1 Reserved - do not change Register 96h PLL DLL REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R155 (9Bh) FLL Control (1) 6:5 FLL_REFCLK_S RC [1:0] 00 FLL Clock Source 00 = MCLK 01 = BCLK 10 = Internal oscillator 11 = Reserved 3 Reserved 1 Reserved - do not change 2 FLL_FRAC 1 FLL Fractional Mode enable 0 = Integer Mode 1 = Fractional Mode Fractional Mode (FLL_FRAC=1) is recommended in all cases 1 FLL_OSC_ENA 0 FLL Oscillator enable 0 = Disabled 1 = Enabled (Note that this field is required for free-running FLL modes only) 0 FLL_ENA 0 FLL Enable 0 = Disabled 1 = Enabled Register 9Bh FLL Control (1) 244 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT R156 (9Ch) FLL Control (2) 8:3 FLL_OUTDIV [5:0] 00_0111 1:0 FLL_REFCLK_D IV [1:0] 01 DESCRIPTION FLL FOUT clock ratio 000000 = Reserved 000001 = 2 000010 = 3 000011 = 4 000100 = 5 000101 = 6 … 111110 = 63 111111 = 64 (FOUT = FVCO / FLL_OUTDIV) FLL Clock Reference Divider 00 = MCLK / 1 01 = MCLK / 2 10 = MCLK / 4 11 = Reserved MCLK (or other input reference) must be divided down to 1MHz 011 recommended for FREF < 64kHz Register 9Dh FLL Control (3) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R159 (9Fh) FLL Control (5) 6:1 FLL_FRC_NCO _VAL [5:0] 01_1001 FLL Forced oscillator value Valid range is 000000 to 111111 0x19h (011001) = 12MHz approx (Note that this field is required for free-running FLL modes only) 0 FLL_FRC_NCO 0 FLL Forced control select 0 = Normal 1 = FLL oscillator controlled by FLL_FRC_NCO_VAL (Note that this field is required for free-running FLL modes only) Register 9Fh FLL Control (5) Rev 4.4 245 WM8962 REGISTER ADDRESS BIT LABEL R160 (A0h) FLL Control (6) 15:0 FLL_THETA [15:0] DEFAULT DESCRIPTION 0000_0000 FLL Fractional multiply for FREF. _0001_100 Only valid when FLL_FRAC = 1. 0 This field sets the numerator (multiply) part of the FLL_THETA / FLL_LAMBDA ratio. It is coded as LSB = 1. Register A0h FLL Control (6) REGISTER ADDRESS BIT LABEL R161 (A1h) FLL Control (7) 15:0 FLL_LAMBDA [15:0] DEFAULT DESCRIPTION 0000_0000 FLL Fractional multiply for FREF. _0111_110 Only valid when FLL_FRAC = 1. 1 This field sets the denominator (dividing) part of the FLL_THETA / FLL_LAMBDA ratio. It is coded as LSB = 1. Note that it is required that FLL_LAMBDA > 0 in all cases (Integer and Fractional modes). Register A1h FLL Control (7) REGISTER ADDRESS BIT LABEL R162 (A2h) FLL Control (8) 9:0 FLL_N [9:0] DEFAULT DESCRIPTION 00_0000_1 FLL Integer multiply for FREF 000 (LSB = 1) Register A2h FLL Control (8) REGISTER ADDRESS BIT LABEL DEFAULT R252 (FCh) General test 1 DESCRIPTION 2 Reserved 1 Reserved - do not change 0 AUTO_INC 1 Enables address auto-increment (applies to 2-wire I2C mode only) 0 = Disabled 1 = Enabled Register FCh General test 1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R256 (0100h) DF1 2 DF1_SHARED_ COEFF 0 DF1 Shared Coefficients Enable 0 = Disabled 1 = Enabled 1 DF1_SHARED_ COEFF_SEL 0 DF1 Shared Coefficients Select 0 = Both channels use left coefficients 1 = Both channels use right coefficients 0 DF1_ENA 0 DF1 Enable in ADC path 0 = Disabled 1 = Enabled Register 0100h DF1 246 Rev 4.4 WM8962 REGISTER ADDRESS BIT R257 (0101h) DF2 15:0 LABEL DEFAULT DESCRIPTION DF1_COEFF_L0 0000_0000 DF1 Filter Coefficient Left 0 [15:0] _0000_000 0 Register 0101h DF2 REGISTER ADDRESS BIT R258 (0102h) DF3 15:0 LABEL DEFAULT DESCRIPTION DF1_COEFF_L1 0000_0000 DF1 Filter Coefficient Left 1 [15:0] _0000_000 0 Register 0102h DF3 REGISTER ADDRESS BIT R259 (0103h) DF4 15:0 LABEL DEFAULT DESCRIPTION DF1_COEFF_L2 0000_0000 DF1 Filter Coefficient Left 2 [15:0] _0000_000 0 Register 0103h DF4 REGISTER ADDRESS BIT LABEL R260 (0104h) DF5 15:0 DF1_COEFF_R 0 [15:0] DEFAULT DESCRIPTION 0000_0000 DF1 Filter Coefficient Right 0 _0000_000 0 Register 0104h DF5 REGISTER ADDRESS BIT LABEL R261 (0105h) DF6 15:0 DF1_COEFF_R 1 [15:0] DEFAULT DESCRIPTION 0000_0000 DF1 Filter Coefficient Right 1 _0000_000 0 Register 0105h DF6 REGISTER ADDRESS BIT LABEL R262 (0106h) DF7 15:0 DF1_COEFF_R 2 [15:0] DEFAULT DESCRIPTION 0000_0000 DF1 Filter Coefficient Right 2 _0000_000 0 Register 0106h DF7 Rev 4.4 247 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R264 (0108h) LHPF1 1 LHPF_MODE 0 Low/High-Pass Filter mode select 0 = Low-Pass 1 = High-Pass 0 LHPF_ENA 0 Low/High-Pass Filter 0 = Disable 1 = Enable DEFAULT Register 0108h LHPF1 REGISTER ADDRESS BIT LABEL R265 (0109h) LHPF2 15:0 LHPF_COEFF [15:0] DESCRIPTION 0000_0000 LHPF Coefficient _0000_000 0 Register 0109h LHPF2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R268 (010Ch) THREED1 6 ADC_MONOMI X 0 ADC Monomix enable 0 = Disabled 1 = Enabled Note that THREED_ENA must be disabled for ADC_MONOMIX to be effective. 5 THREED_SIGN _L 0 3D Left Cross mixing polarity (from the right channel to the left) 0 = Positive 1 = Negative 4 THREED_SIGN _R 0 3D Right Cross mixing polarity (from the left channel to the right) 0 = Positive 1 = Negative 2 THREED_LHPF _MODE 0 3D Low/High-Pass filter mode 0 = Low-Pass 1 = High-Pass 1 THREED_LHPF _ENA 0 3D Low/High-Pass filter enable 0 = Disabled 1 = Enabled 0 THREED_ENA 0 3D Surround Sound enable 0 = Disabled 1 = Enabled Note that setting THREED_ENA will cause any ADC_MONOMIX setting to be ignored Register 010Ch THREED1 248 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R269 (010Dh) THREED2 15:11 THREED_FGAI NL [4:0] 0_0000 3D Left Forward Gain 00000 = Mute 00001 = -11.25dB 00010 = -10.875dB (…in steps of -0.375dB) 11110 = -0.375dB 11111 = 0.0dB 10:6 THREED_CGAI NL [4:0] 0_0000 3D Left Cross Gain (from the right channel to the left) 00000 = Mute 00001 = -11.25dB 00010 = -10.875dB (…in steps of -0.375dB) 11110 = -0.375dB 11111 = 0.0dB 5:2 THREED_DELA YL [3:0] 0000 3D Left Filter Delay (measured from the sample rate) 0000 = 0 samples 0001 = 1 samples 0010 = 2 samples 0011 = 3 samples 0100 = 4 samples 0101 = 5 samples 0110 = 6 samples 0111 = 7 samples 1000 = 8 samples 1001 to 1111 = Reserved Register 010Dh THREED2 REGISTER ADDRESS BIT LABEL R270 (010Eh) THREED3 15:0 THREED_LHPF _COEFF [15:0] DEFAULT DESCRIPTION 0000_0000 3D LHPF coefficient _0000_000 0 Register 010Eh THREED3 REGISTER ADDRESS BIT LABEL DEFAULT R271 (010Fh) THREED4 15:11 THREED_FGAI NR [4:0] 0_0000 3D Right Forward Gain 00000 = Mute 00001 = -11.25dB 00010 = -10.875dB (…in steps of -0.375dB) 11110 = -0.375dB 11111 = 0.0dB 10:6 THREED_CGAI NR [4:0] 0_0000 3D Right Cross Gain (from the left channel to the right) 00000 = Mute 00001 = -11.25dB 00010 = -10.875dB (…in steps of -0.375dB) 11110 = -0.375dB 11111 = 0.0dB 5:2 THREED_DELA YR [3:0] 0000 Rev 4.4 DESCRIPTION 3D Filter Delay (measured from the sample rate) 0000 = 0 samples 0001 = 1 samples 0010 = 2 samples 249 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0011 = 3 samples 0100 = 4 samples 0101 = 5 samples 0110 = 6 samples 0111 = 7 samples 1000 = 8 samples 1001 to 1111 = Reserved Register 010Fh THREED4 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R276 (0114h) DRC 1 14:10 DRC_SIG_DET _RMS [4:0] 0_0000 DRC Signal Detect RMS Threshold. This is the RMS signal level for signal detect to be indicated when DRC_SIG_DET_MODE=1. 00000 = -27dB 00001 = -28.5dB …. (1.5dB steps) 11110 = -72dB 11111 = -73.5dB 9:8 DRC_SIG_DET _PK [1:0] 00 DRC Signal Detect Peak Threshold. This is the Peak/RMS ratio, or Crest Factor, level for signal detect to be indicated when DRC_SIG_DET_MODE=0. 00 = 14dB 01 = 20dB 10 = 26dB 11 = 32dB 7 DRC_NG_ENA 0 DRC Noise Gate Enable 0 = Disabled 1 = Enabled 6 DRC_SIG_DET _MODE 0 DRC Signal Detect Mode 0 = Peak threshold mode 1 = RMS threshold mode 5 DRC_SIG_DET 0 DRC Signal Detect Enable 0 = Disabled 1 = Enabled 4 DRC_KNEE2_O P_ENA 0 DRC_KNEE2_OP Enable 0 = Disabled 1 = Enabled 3 DRC_QR 1 DRC Quick-release Enable 0 = Disabled 1 = Enabled 2 DRC_ANTICLIP 1 DRC Anti-clip Enable 0 = Disabled 1 = Enabled 1 DRC_MODE 0 DRC path select 0 = ADC path 1 = DAC path 0 DRC_ENA 0 DRC Enable 0 = Disabled 1 = Enabled Register 0114h DRC 1 250 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R277 (0115h) DRC 2 12:9 DRC_ATK [3:0] 0100 Gain attack rate (seconds/6dB) 0000 = Reserved 0001 = 181us 0010 = 363us 0011 = 726us 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011 = 185.6ms 1100-1111 = Reserved 8:5 DRC_DCY [3:0] 1001 Gain decay rate (seconds/6dB) 0000 = 1.45ms 0001 = 2.9ms 0010 = 5.8ms 0011 = 11.6ms 0100 = 23.25ms 0101 = 46.5ms 0110 = 93ms 0111 = 186ms 1000 = 372ms 1001 = 743ms (default) 1010 = 1.49s 1011 = 2.97s 1100 = 5.94s 1101 = 11.89s 1110 = 23.78s 1111 = 47.56s 4:2 DRC_MINGAIN [2:0] 001 Minimum gain the DRC can use to attenuate audio signals 000 = 0dB 001 = -12dB (default) 010 = -18dB 011 = -24dB 100 = -36dB 101to 111 = Reserved 1:0 DRC_MAXGAIN [1:0] 01 Maximum gain the DRC can use to boost audio signals (dB) 00 = 12dB 01 = 18dB (default) 10 = 24dB 11 = 36dB Register 0115h DRC 2 Rev 4.4 251 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R278 (0116h) DRC 3 15:12 DRC_NG_MING AIN [3:0] 0000 11:10 DRC_QR_THR [1:0] 00 DRC Quick-release threshold (crest factor in dB) 00 = 12dB 01 = 18dB 10 = 24dB 11 = 30dB 9:8 DRC_QR_DCY [1:0] 00 DRC Quick-release decay rate (seconds/6dB) 00 = 0.725ms 01 = 1.45ms 10 = 5.8ms 11 = reserved 7:6 DRC_NG_EXP [1:0] 00 Noise Gate slope 00 = 1 (no expansion) 01 = 2 10 = 4 11 = 8 5:3 DRC_HI_COMP [2:0] 000 Compressor slope (upper region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 (default) 100 = 1/16 101 = 0 (ALC Mode) 110 = Reserved 111 = Reserved 2:0 DRC_LO_COM P [2:0] 000 Compressor slope (lower region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 to 111 = Reserved Minimum gain the DRC can use to attenuate audio signals when the noise gate is active. 0000 = -36dB 0001 = -30dB 0010 = -24dB 0011 = -18dB 0100 = -12dB 0101 = -6dB 0110 = 0dB 0111 = 6dB 1000 = 12dB 1001 = 18dB 1010 = 24dB 1011 = 30dB 1100 to 1111 = Reserved Register 0116h DRC 3 252 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R279 (0117h) DRC 4 10:5 DRC_KNEE_IP [5:0] 00_0000 Input signal level at the Compressor ‘Knee’. 000000 = 0dB 000001 = -0.75dB 000010 = -1.5dB … (-0.75dB steps) 111100 = -45dB 111101 to 111111 = Reserved 4:0 DRC_KNEE_OP [4:0] 0_0000 Output signal at the Compressor ‘Knee’. 00000 = 0dB 00001 = -0.75dB 00010 = -1.5dB … (-0.75dB steps) 11110 = -22.5dB 11111 = Reserved Register 0117h DRC 4 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R280 (0118h) DRC 5 9:5 DRC_KNEE2_IP [4:0] 0_0000 Input signal level at the Noise Gate threshold ‘Knee2’. 00000 = -36dB 00001 = -37.5dB 00010 = -39dB … (-1.5dB steps) 11110 = -81dB 11111 = -82.5dB Only applicable when DRC_NG_ENA = 1. 4:0 DRC_KNEE2_O P [4:0] 0_0000 Output signal at the Noise Gate threshold ‘Knee2’. 00000 = -30dB 00001 = -31.5dB 00010 = -33dB … (-1.5dB steps) 11110 = -75dB 11111 = -76.5dB Only applicable when DRC_KNEE2_OP_ENA = 1. Register 0118h DRC 5 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R285 (011Dh) Tloopback 1 TLB_ENA 0 T-Loopback Enable 0 = Disabled 1 = Enabled 0 TLB_MODE 0 T-Loopback Mode Select 0: Left AIF Output = Left ADC; Right AIF Output = (Left DAC + Right DAC) / 2 1: Left AIF Output = (Left DAC + Right DAC) / 2; Right AIF Output = Right ADC Register 011Dh Tloopback Rev 4.4 253 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R335 (014Fh) EQ1 2 EQ_SHARED_C OEFF 1 5-Band EQ Shared Coefficient enable 0 = Right and Left channels use unique coefficients 1 = Left and right channels share filter coefficients 1 EQ_SHARED_C OEFF_SEL 0 5-Band EQ Shared Coefficient select 0 = Both channels use the left channel filter coefficients 1 = Both channels use the right channel filter coefficients 0 EQ_ENA 0 5-Band EQ Enable 0 = Disabled 1 = Enabled Register 014Fh EQ1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R336 (0150h) EQ2 15:11 EQL_B1_GAIN [4:0] 0_1100 Left Channel Band 1 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved 10:6 EQL_B2_GAIN [4:0] 0_1100 Left Channel Band 2 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved 5:1 EQL_B3_GAIN [4:0] 0_1100 Left Channel Band 3 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved Register 0150h EQ2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R337 (0151h) EQ3 15:11 EQL_B4_GAIN [4:0] 0_1100 Left Channel Band 4 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved 10:6 EQL_B5_GAIN [4:0] 0_1100 Left Channel Band 5 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved Register 0151h EQ3 254 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL R338 (0152h) EQ4 15:0 EQL_B1_A [15:0] DEFAULT DESCRIPTION 0000_1111 5 Band EQ Band 1 coefficient A _1100_101 0 Register 0152h EQ4 REGISTER ADDRESS BIT LABEL R339 (0153h) EQ5 15:0 EQL_B1_B [15:0] DEFAULT DESCRIPTION 0000_0100 5 Band EQ Band 1 coefficient B _0000_000 0 Register 0153h EQ5 REGISTER ADDRESS BIT LABEL R340 (0154h) EQ6 15:0 EQL_B1_PG [15:0] DEFAULT DESCRIPTION 0000_0000 5 Band EQ Band 1 coefficient PG _1101_100 0 Register 0154h EQ6 REGISTER ADDRESS BIT LABEL R341 (0155h) EQ7 15:0 EQL_B2_A [15:0] DEFAULT DESCRIPTION 0001_1110 5 Band EQ Band 2 coefficient A _1011_010 1 Register 0155h EQ7 REGISTER ADDRESS BIT LABEL R342 (0156h) EQ8 15:0 EQL_B2_B [15:0] DEFAULT DESCRIPTION 1111_0001 5 Band EQ Band 2 coefficient B _0100_010 1 Register 0156h EQ8 REGISTER ADDRESS BIT LABEL R343 (0157h) EQ9 15:0 EQL_B2_C [15:0] DEFAULT DESCRIPTION 0000_1011 5 Band EQ Band 2 coefficient C _0111_010 1 Register 0157h EQ9 REGISTER ADDRESS BIT LABEL R344 (0158h) EQ10 15:0 EQL_B2_PG [15:0] DEFAULT DESCRIPTION 0000_0001 5 Band EQ Band 2 coefficient PG _1100_010 1 Register 0158h EQ10 Rev 4.4 255 WM8962 REGISTER ADDRESS BIT LABEL R345 (0159h) EQ11 15:0 EQL_B3_A [15:0] DEFAULT DESCRIPTION 0001_1100 5 Band EQ Band 3 coefficient A _0101_100 0 Register 0159h EQ11 REGISTER ADDRESS BIT LABEL R346 (015Ah) EQ12 15:0 EQL_B3_B [15:0] DEFAULT DESCRIPTION 1111_0011 5 Band EQ Band 3 coefficient B _0111_001 1 Register 015Ah EQ12 REGISTER ADDRESS BIT LABEL R347 (015Bh) EQ13 15:0 EQL_B3_C [15:0] DEFAULT DESCRIPTION 0000_1010 5 Band EQ Band 3 coefficient C _0101_010 0 Register 015Bh EQ13 REGISTER ADDRESS BIT LABEL R348 (015Ch) EQ14 15:0 EQL_B3_PG [15:0] DEFAULT DESCRIPTION 0000_0101 5 Band EQ Band 3 coefficient PG _0101_100 0 Register 015Ch EQ14 REGISTER ADDRESS BIT LABEL R349 (015Dh) EQ15 15:0 EQL_B4_A [15:0] DEFAULT DESCRIPTION 0001_0110 5 Band EQ Band 4 coefficient A _1000_111 0 Register 015Dh EQ15 REGISTER ADDRESS BIT LABEL R350 (015Eh) EQ16 15:0 EQL_B4_B [15:0] DEFAULT DESCRIPTION 1111_1000 5 Band EQ Band 4 coefficient B _0010_100 1 Register 015Eh EQ16 REGISTER ADDRESS BIT LABEL R351 (015Fh) EQ17 15:0 EQL_B4_C [15:0] DEFAULT DESCRIPTION 0000_0111 5 Band EQ Band 4 coefficient C _1010_110 1 Register 015Fh EQ17 256 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL R352 (0160h) EQ18 15:0 EQL_B4_PG [15:0] DEFAULT DESCRIPTION 0001_0001 5 Band EQ Band 2 coefficient PG _0000_001 1 Register 0160h EQ18 REGISTER ADDRESS BIT LABEL R353 (0161h) EQ19 15:0 EQL_B5_A [15:0] DEFAULT DESCRIPTION 0000_0101 5 Band EQ Band 5 coefficient A _0110_010 0 Register 0161h EQ19 REGISTER ADDRESS BIT LABEL R354 (0162h) EQ20 15:0 EQL_B5_B [15:0] DEFAULT DESCRIPTION 0000_0101 5 Band EQ Band 5 coefficient B _0101_100 1 Register 0162h EQ20 REGISTER ADDRESS BIT LABEL R355 (0163h) EQ21 15:0 EQL_B5_PG [15:0] DEFAULT DESCRIPTION 0100_0000 5 Band EQ Band 5 coefficient PG _0000_000 0 Register 0163h EQ21 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R356 (0164h) EQ22 15:11 EQR_B1_GAIN [4:0] 0_1100 Right Channel Band 1 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved 10:6 EQR_B2_GAIN [4:0] 0_1100 Right Channel Band 2 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved 5:1 EQR_B3_GAIN [4:0] 0_1100 Right Channel Band 3 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved Register 0164h EQ22 Rev 4.4 257 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R357 (0165h) EQ23 15:11 EQR_B4_GAIN [4:0] 0_1100 Right Channel Band 4 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved 10:6 EQR_B5_GAIN [4:0] 0_1100 Right Channel Band 5 EQ Gain 0_0000 = -12dB 0_0001 = -11dB …1dB steps to 1_1000 = +12dB 1_1001 to 1_1111 reserved DEFAULT Register 0165h EQ23 REGISTER ADDRESS BIT LABEL R358 (0166h) EQ24 15:0 EQR_B1_A [15:0] DESCRIPTION 0000_1111 5 Band EQ Band 1 coefficient A _1100_101 0 Register 0166h EQ24 REGISTER ADDRESS BIT LABEL R359 (0167h) EQ25 15:0 EQR_B1_B [15:0] DEFAULT DESCRIPTION 0000_0100 5 Band EQ Band 1 coefficient B _0000_000 0 Register 0167h EQ25 REGISTER ADDRESS BIT LABEL R360 (0168h) EQ26 15:0 EQR_B1_PG [15:0] DEFAULT DESCRIPTION 0000_0000 5 Band EQ Band 1 coefficient PG _1101_100 0 Register 0168h EQ26 REGISTER ADDRESS BIT LABEL R361 (0169h) EQ27 15:0 EQR_B2_A [15:0] DEFAULT DESCRIPTION 0001_1110 5 Band EQ Band 2 coefficient A _1011_010 1 Register 0169h EQ27 REGISTER ADDRESS BIT LABEL R362 (016Ah) EQ28 15:0 EQR_B2_B [15:0] DEFAULT DESCRIPTION 1111_0001 5 Band EQ Band 2 coefficient B _0100_010 1 Register 016Ah EQ28 258 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL R363 (016Bh) EQ29 15:0 EQR_B2_C [15:0] DEFAULT DESCRIPTION 0000_1011 5 Band EQ Band 2 coefficient C _0111_010 1 Register 016Bh EQ29 REGISTER ADDRESS BIT LABEL R364 (016Ch) EQ30 15:0 EQR_B2_PG [15:0] DEFAULT DESCRIPTION 0000_0001 5 Band EQ Band 2 coefficient PG _1100_010 1 Register 016Ch EQ30 REGISTER ADDRESS BIT LABEL R365 (016Dh) EQ31 15:0 EQR_B3_A [15:0] DEFAULT DESCRIPTION 0001_1100 5 Band EQ Band 3 coefficient A _0101_100 0 Register 016Dh EQ31 REGISTER ADDRESS BIT LABEL R366 (016Eh) EQ32 15:0 EQR_B3_B [15:0] DEFAULT DESCRIPTION 1111_0011 5 Band EQ Band 3 coefficient B _0111_001 1 Register 016Eh EQ32 REGISTER ADDRESS BIT LABEL R367 (016Fh) EQ33 15:0 EQR_B3_C [15:0] DEFAULT DESCRIPTION 0000_1010 5 Band EQ Band 3 coefficient C _0101_010 0 Register 016Fh EQ33 REGISTER ADDRESS BIT LABEL R368 (0170h) EQ34 15:0 EQR_B3_PG [15:0] DEFAULT DESCRIPTION 0000_0101 5 Band EQ Band 3 coefficient PG _0101_100 0 Register 0170h EQ34 REGISTER ADDRESS BIT LABEL R369 (0171h) EQ35 15:0 EQR_B4_A [15:0] DEFAULT DESCRIPTION 0001_0110 5 Band EQ Band 4 coefficient A _1000_111 0 Register 0171h EQ35 Rev 4.4 259 WM8962 REGISTER ADDRESS BIT LABEL R370 (0172h) EQ36 15:0 EQR_B4_B [15:0] DEFAULT DESCRIPTION 1111_1000 5 Band EQ Band 4 coefficient B _0010_100 1 Register 0172h EQ36 REGISTER ADDRESS BIT LABEL R371 (0173h) EQ37 15:0 EQR_B4_C [15:0] DEFAULT DESCRIPTION 0000_0111 5 Band EQ Band 4 coefficient C _1010_110 1 Register 0173h EQ37 REGISTER ADDRESS BIT LABEL R372 (0174h) EQ38 15:0 EQR_B4_PG [15:0] DEFAULT DESCRIPTION 0001_0001 5 Band EQ Band 2 coefficient PG _0000_001 1 Register 0174h EQ38 REGISTER ADDRESS BIT LABEL R373 (0175h) EQ39 15:0 EQR_B5_A [15:0] DEFAULT DESCRIPTION 0000_0101 5 Band EQ Band 5 coefficient A _0110_010 0 Register 0175h EQ39 REGISTER ADDRESS BIT LABEL R374 (0176h) EQ40 15:0 EQR_B5_B [15:0] DEFAULT DESCRIPTION 0000_0101 5 Band EQ Band 5 coefficient B _0101_100 1 Register 0176h EQ40 REGISTER ADDRESS BIT LABEL R375 (0177h) EQ41 15:0 EQR_B5_PG [15:0] DEFAULT DESCRIPTION 0100_0000 5 Band EQ Band 5 coefficient PG _0000_000 0 Register 0177h EQ41 REGISTER ADDRESS BIT LABEL DEFAULT R513 (0201h) GPIO 2 10 GP2_POL 0 GPIO 2 Polarity 0 = Not inverted 1 = Inverted 6 GP2_LVL 0 GPIO 2 Output Level (when GP2_FN = 00001) 0 = Logic 0 1 = Logic 1 260 DESCRIPTION Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION Note that this is a Write-Only register; the Readback value is undefined. 4:0 GP2_FN [4:0] 0_0000 GPIO 2 Pin Function select 0_0000 = CLKOUT (PLL2 / Oscillator) - see note below 0_0001 = Logic 0 or Logic 1 (depending on GP2_LVL) 0_0010 = SDOUT 0_0011 = IRQ 0_0100 = Temperature shutdown 0_0101 = Reserved 0_0110 = PLL2 Lock 0_0111 = PLL3 Lock 0_1000 = Reserved 0_1001 = FLL Lock 0_1010 = DRC Activity detect 0_1011 = Write Sequencer done 0_1100 = ALC Noise Gate active 0_1101 = ALC Peak Limiter overload 0_1110 = ALC Saturation 0_1111 = ALC level threshold 1_0000 = ALC Level lock 1_0001 = FIFO error indicator 1_0010 = OPCLK 1_0011 = Digital Microphone Output Clock 1_0100 = Reserved 1_0101 = Mic Detect flag 1_0110 = Mic Short Circuit flag 1_0111 to 1_1111 = Reserved Note that PLL2 or the internal oscillator CLKOUT is enabled using CLKOUT2_SEL. Setting GP2_FN = 00h is recommended in this case. DESCRIPTION Register 0201h GPIO 2 REGISTER ADDRESS BIT LABEL DEFAULT R514 (0202h) GPIO 3 10 GP3_POL 0 GPIO 3 Polarity 0 = Not inverted 1 = Inverted 6 GP3_LVL 0 GPIO 3 Output Level (when GP3_FN = 00001) 0 = Logic 0 1 = Logic 1 Note that this is a Write-Only register; the Readback value is undefined. 4:0 GP3_FN [4:0] 0_0000 Rev 4.4 GPIO 3 Pin Function select 0_0000 = CLKOUT (PLL3 / FLL) - see note below 0_0001 = Logic 0 or Logic 1 (depending on GP3_LVL) 0_0010 = SDOUT 0_0011 = IRQ 0_0100 = Temperature shutdown 0_0101 = Reserved 0_0110 = PLL2 Lock 0_0111 = PLL3 Lock 0_1000 = Reserved 0_1001 = FLL Lock 0_1010 = DRC Activity detect 0_1011 = Write Sequencer done 0_1100 = ALC Noise Gate active 261 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0_1101 = ALC Peak Limiter overload 0_1110 = ALC Saturation 0_1111 = ALC level threshold 1_0000 = ALC Level lock 1_0001 = FIFO error indicator 1_0010 = OPCLK 1_0011 = Digital Microphone Output Clock 1_0100 = Reserved 1_0101 = Mic Detect flag 1_0110 = Mic Short Circuit flag 1_0111 to 1_1111 = Reserved Note that PLL3 or FLL CLKOUT is enabled using CLKOUT3_SEL. Setting GP3_FN = 00h is recommended in this case. Register 0202h GPIO 3 REGISTER ADDRESS BIT LABEL DEFAULT R516 (0204h) GPIO 5 15 GP5_DIR 1 GPIO5 Direction 0 = Output 1 = Input 14 GP5_PU 0 13 GP5_PD 0 GPIO5 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled GPIO5 pull-down resistor enable 0 = pull-up disabled 1 = pull-down enabled 10 GP5_POL 0 GPIO5 Polarity 0 = Not inverted 1 = Inverted 9 GP5_OP_CFG 0 8 GP5_DB 1 GPIO5 Output pin configuration 0 = CMOS 1 = Open-drain GPIO5 input de-bounce 0 = Disabled 1 = Enabled 6 GP5_LVL 0 4:0 GP5_FN [4:0] 0_0000 262 DESCRIPTION GPIO 5 Level (when GP5_FN = 00001) 0 = Logic 0 1 = Logic 1 Write to this bit to set the GPIO5 output. Read from this bit to read GPIO input level. Note that, when GPIO5 is configured as an output (GP5_DIR=0), this is a Write-Only register; the Readback value is undefined. GPIO5 Pin Function select 0_0000 = Unused 0_0001 = Logic 0 or Logic 1 (depending on GP5_LVL) 0_0010 = SDOUT 0_0011 = IRQ 0_0100 = Temperature shutdown 0_0101 = Reserved 0_0110 = PLL2 Lock 0_0111 = PLL3 Lock 0_1000 = Reserved 0_1001 = FLL Lock 0_1010 = DRC Activity detect Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0_1011 = Write Sequencer done 0_1100 = ALC Noise Gate active 0_1101 = ALC Peak Limiter overload 0_1110 = ALC Saturation 0_1111 = ALC level threshold 1_0000 = ALC Level lock 1_0001 = FIFO error indicator 1_0010 = OPCLK 1_0011 = Digital Microphone Output Clock 1_0100 = Digital Microphone Input Data 1_0101 = Mic Detect flag 1_0110 = Mic Short Circuit flag 1_0111 to 1_1111 = Reserved Note that GPIO5 functions are only supported when CLKREG_OVD=1. When CLKREG_OVD=0, the contents of Register R516 must not be changed from the default value. Register 0204h GPIO 5 REGISTER ADDRESS BIT LABEL DEFAULT R517 (0205h) GPIO 6 15 GP6_DIR 1 GPIO6 Direction 0 = Output 1 = Input 14 GP6_PU 0 GPIO6 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled 13 GP6_PD 0 GPIO6 pull-down resistor enable 0 = pull-up disabled 1 = pull-down enabled 10 GP6_POL 0 GPIO6 Polarity 0 = Not inverted 1 = Inverted 9 GP6_OP_CFG 0 GPIO6 Output pin configuration 0 = CMOS 1 = Open-drain 8 GP6_DB 1 GPIO6 input de-bounce 0 = Disabled 1 = Enabled 6 GP6_LVL 0 GPIO 6 Level (when GP6_FN = 00001) 0 = Logic 0 1 = Logic 1 Write to this bit to set the GPIO6 output. Read from this bit to read GPIO input level. Note that, when GPIO6 is configured as an output (GP6_DIR=0), this is a Write-Only register; the Readback value is undefined. 4:0 GP6_FN [4:0] 0_0000 Rev 4.4 DESCRIPTION GPIO6 Pin Function select 0_0000 = CSB Input 0_0001 = Logic 0 or Logic 1 (depending on GP6_LVL) 0_0010 = Reserved 0_0011 = IRQ 0_0100 = Temperature shutdown 0_0101 = Reserved 0_0110 = PLL2 Lock 0_0111 = PLL3 Lock 263 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0_1000 = Reserved 0_1001 = FLL Lock 0_1010 = DRC Activity detect 0_1011 = Write Sequencer done 0_1100 = ALC Noise Gate active 0_1101 = ALC Peak Limiter overload 0_1110 = ALC Saturation 0_1111 = ALC level threshold 1_0000 = ALC Level lock 1_0001 = FIFO error indicator 1_0010 = OPCLK 1_0011 = Digital Microphone Output Clock 1_0100 = Digital Microphone Input Data 1_0101 = Mic Detect flag 1_0110 = Mic Short Circuit flag 1_0111 to 1_1111 = Reserved Register 0205h GPIO 6 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R560 (0230h) Interrupt Status 1 5 GP6_EINT 0 GPIO6 IRQ status 0 = GPIO6 IRQ not set 1 = GPIO6 IRQ set Note: cleared when a ‘1’ is written 4 GP5_EINT 0 GPIO5 IRQ status 0 = GPIO5 IRQ not set 1 = GPIO5 IRQ set Note: cleared when a ‘1’ is written Register 0230h Interrupt Status 1 REGISTER ADDRESS BIT LABEL DEFAULT R561 (0231h) Interrupt Status 2 15 MICSCD_EINT 0 Mic Short Circuit Interrupt Status 0 = MICSCD IRQ not set 1 = MICSCD IRQ set Note: cleared when a '1' is written 14 MICD_EINT 0 Mic Detect Interrupt Status 0 = MICD IRQ not set 1 = MICD IRQ set Note: cleared when a '1' is written 13 FIFOS_ERR_EI NT 0 FIFO error IRQ status 0 = FIFO error IRQ not set 1 = FIFO error IRQ set Note: cleared when a ‘1’ is written 12 ALC_LOCK_EIN T 0 ALC level lock IRQ status 0 = ALC level lock IRQ not set 1 = ALC level lock IRQ set Note: cleared when a ‘1’ is written 11 ALC_THRESH_ EINT 0 ALC level threshold IRQ status 0 = ALC level threshold IRQ not set 1 = ALC level threshold IRQ set Note: cleared when a ‘1’ is written 10 ALC_SAT_EINT 0 ALC saturation IRQ status 264 DESCRIPTION Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 = ALC saturation IRQ not set 1 = ALC saturation IRQ set Note: cleared when a ‘1’ is written 9 ALC_PKOVR_EI NT 0 ALC peak overload detector IRQ status 0 = ALC pk. Overload det. IRQ not set 1 = ALC pk. Overload det. IRQ set Note: cleared when a ‘1’ is written 8 ALC_NGATE_EI NT 0 ALC Noise Gate active IRQ status 0 = ALC Noise Gate IRQ not set 1 = ALC Noise Gate IRQ set Note: cleared when a ‘1’ is written 7 WSEQ_DONE_ EINT 0 Write Sequencer done IRQ status 0 = Write Sequencer IRQ not set 1 = Write Sequencer IRQ set Note: cleared when a ‘1’ is written 6 DRC_ACTDET_ EINT 0 DRC Activity IRQ status 0 = DRC Activity IRQ not set 1 = DRC Activity IRQ set Note: cleared when a ‘1’ is written 5 FLL_LOCK_EIN T 0 FLL lock IRQ status 0 = FLL lock IRQ not set 1 = FLL lock IRQ set Note: cleared when a ‘1’ is written 3 PLL3_LOCK_EI NT 0 PLL3 Lock IRQ status 0 = PLL3 Lock IRQ not set 1 = PLL3 Lock IRQ set Note: cleared when a ‘1’ is written 2 PLL2_LOCK_EI NT 0 PLL2 Lock IRQ status 0 = PLL2 Lock IRQ not set 1 = PLL2 Lock IRQ set Note: cleared when a ‘1’ is written 0 TEMP_SHUT_E INT 0 Temperature Shutdown IRQ status 0 = Temperature Shutdown IRQ not set 1 = Temperature Shutdown IRQ set Note: cleared when a ‘1’ is written Register 0231h Interrupt Status 2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R568 (0238h) Interrupt Status 1 Mask 5 IM_GP6_EINT 1 Interrupt mask for GPIO6 0 = Not masked 1 = Masked 4 IM_GP5_EINT 1 Interrupt mask for GPIO5 0 = Not masked 1 = Masked Register 0238h Interrupt Status 1 Mask Rev 4.4 265 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R569 (0239h) Interrupt Status 2 Mask 15 IM_MICSCD_EI NT 1 Interrupt mask for Mic Short Circuit 0 = Not masked 1 = Masked 14 IM_MICD_EINT 1 Interrupt mask for Mic Detect 0 = Not masked 1 = Masked 13 IM_FIFOS_ERR _EINT 1 Interrupt mask for FIFOS Error 0 = Not masked 1 = Masked 12 IM_ALC_LOCK_ EINT 1 Interrupt mask for ALC Lock 0 = Not masked 1 = Masked 11 IM_ALC_THRE SH_EINT 1 Interrupt mask for ALC Threshold 0 = Not masked 1 = Masked 10 IM_ALC_SAT_E INT 1 Interrupt mask for ALC Saturation 0 = Not masked 1 = Masked 9 IM_ALC_PKOV R_EINT 1 Interrupt mask for ALC Peak Detector overload 0 = Not masked 1 = Masked 8 IM_ALC_NGAT E_EINT 1 Interrupt mask for ALC Noise Gate active 0 = Not masked 1 = Masked 7 IM_WSEQ_DON E_EINT 1 Interrupt mask for Write Sequencer done 0 = Not masked 1 = Masked 6 IM_DRC_ACTD ET_EINT 1 Interrupt mask for DRC Activity detect 0 = Not masked 1 = Masked 5 IM_FLL_LOCK_ EINT 1 Interrupt mask for FLL Lock 0 = Not masked 1 = Masked 4 Reserved 1 Reserved - do not change 3 IM_PLL3_LOCK _EINT 1 Interrupt mask for PLL3 Lock 0 = Not masked 1 = Masked 2 IM_PLL2_LOCK _EINT 1 Interrupt mask for PLL2 Lock 0 = Not masked 1 = Masked 1 Reserved 1 Reserved - do not change 0 IM_TEMP_SHU T_EINT 1 Interrupt mask for Temperature Shutdown 0 = Not masked 1 = Masked Register 0239h Interrupt Status 2 Mask REGISTER ADDRESS BIT LABEL DEFAULT R576 (0240h) Interrupt Control 0 IRQ_POL 0 DESCRIPTION Interrupt Output polarity 0 = Active high 1 = Active low Register 0240h Interrupt Control 266 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R584 (0248h) IRQ Debounce 5 FLL_LOCK_DB 1 Debounce Enable on FLL Lock 0 = Disabled 1 = Enabled 4 Reserved 1 Reserved - do not change 3 PLL3_LOCK_D B 1 Debounce Enable on PLL3 Lock 0 = Disabled 1 = Enabled 2 PLL2_LOCK_D B 1 Debounce Enable on PLL2 Lock 0 = Disabled 1 = Enabled 1 Reserved 1 Reserved - do not change 0 TEMP_SHUT_D B 1 Debounce Enable on Temperature Shutdown 0 = Disabled 1 = Enabled Register 0248h IRQ Debounce REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R586 (024Ah) MICINT Source Pol 15 MICSCD_IRQ_P OL 0 Mic Short Circuit Interrupt Polarity 0 = Active high (IRQ asserted when MICSHORT_THR is exceeded) 1 = Active low (IRQ asserted when MICSHORT_THR not exceeded) 14 MICD_IRQ_POL 0 Mic Detect Interrupt Polarity 0 = Active high (IRQ asserted when MICDET_THR is exceeded) 1 = Active low (IRQ asserted when MICDET_THR not exceeded) Register 024Ah MICINT Source Pol REGISTER ADDRESS BIT LABEL DEFAULT R768 (0300h) DSP2 Power Management 0 DSP2_ENA 0 DESCRIPTION DSP2 Audio Processor Enable. 0 = Disabled 1 = Enabled This bit must be set before any of ADC ReTune, DAC ReTune, DAC HPF, VSS or HDBass is enabled. It must remain set whenever any of these functions is enabled. Register 0300h DSP2 Power Management Rev 4.4 267 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1037 (040Dh) DSP2_ExecC ontrol 5 DSP2_STOPC 0 [No description available] 4 DSP2_STOPS 0 [No description available] 3 DSP2_STOPI 0 [No description available] 2 DSP2_STOP 0 Stop the DSP2 audio processor. Writing a 1 to this bit will cause the DSP2 processor to stop processing audio data. 1 DSP2_RUNR 0 Start the DSP2 audio processor Writing a 1 to this bit will cause the DSP2 processor to start processing audio data 0 DSP2_RUN 0 [No description available] Register 040Dh DSP2_ExecControl REGISTER ADDRESS BIT LABEL R4096 (1000h) Write Sequencer 0 13:0 WSEQ_ADDR0 [13:0] DEFAULT DESCRIPTION 00_0000_0 Control Register Address to be written to in this sequence 001_1100 step. Register 1000h Write Sequencer 0 REGISTER ADDRESS BIT LABEL R4097 (1001h) Write Sequencer 1 7:0 WSEQ_DATA0 [7:0] DEFAULT DESCRIPTION 0000_0011 Data to be written in this sequence step. When the data width is less than 8 bits, then one or more of the MSBs of WSEQ_DATAn are ignored. It is recommended that unused bits be set to 0. Register 1001h Write Sequencer 1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4098 (1002h) Write Sequencer 2 10:8 WSEQ_DATA_ WIDTH0 [2:0] 001 Width of the data block written in this sequence step. 000 = 1 bit 001 = 2 bits 010 = 3 bits 011 = 4 bits 100 = 5 bits 101 = 6 bits 110 = 7 bits 111 = 8 bits 3:0 WSEQ_DATA_S TART0 [3:0] 0011 Bit position of the LSB of the data block written in this sequence step. 0000 = Bit 0 … 1111 = Bit 15 Register 1002h Write Sequencer 2 268 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT R4099 (1003h) Write Sequencer 3 8 WSEQ_EOS0 0 3:0 WSEQ_DELAY0 [3:0] 0000 DESCRIPTION End of Sequence flag. This bit indicates whether the Control Write Sequencer should stop after executing this step. 0 = Not end of sequence 1 = End of sequence (Stop the sequencer after this step). Time delay after executing this step. Total time per step (including execution) = k × (2^WSEQ_DELAY + 8) k = 62.5µs (SAMPLE_RATE_INT_MODE = 1) k = 68.1µs (SAMPLE_RATE_INT_MODE = 0) Register 1003h Write Sequencer 3 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION [Write Sequencer Control Registers] R4100 (1004h) Write Sequencer 4 To R4607 (11FFh) Write Sequencer 511 Register 1004h Write Sequencer 4 to Register 11FFh Write Sequencer 511 REGISTER ADDRESS BIT LABEL DEFAULT R16384 (4000h) RETUNEAD C_SHARED_ COEFF_1 7 ADC_RETUNE_ SCV 0 DESCRIPTION ADC ReTune Coefficient sharing 0 = Left and Right channels each use unique coefficients 1 = Both channels use the Right Channel coefficients [ADC ReTune Control Registers] 6:0 Register 4000h RETUNEADC_SHARED_COEFF_1 REGISTER ADDRESS BIT R16385 (4001h) RETUNEAD C_SHARED_ COEFF_0 15:0 LABEL DEFAULT DESCRIPTION [ADC ReTune Control Registers] Register 4001h RETUNEADC_SHARED_COEFF_0 Rev 4.4 269 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT R16386 (4002h) RETUNEDA C_SHARED_ COEFF_1 7 DAC_RETUNE_ SCV 0 DESCRIPTION DAC ReTune Coefficient sharing 0 = Left and Right channels each use unique coefficients 1 = Both channels use the Right Channel coefficients [DAC ReTune Control Registers] 6:0 Register 4002h RETUNEDAC_SHARED_COEFF_1 REGISTER ADDRESS BIT R16387 (4003h) RETUNEDA C_SHARED_ COEFF_0 15:0 LABEL DEFAULT DESCRIPTION [DAC ReTune Control Registers] Register 4003h RETUNEDAC_SHARED_COEFF_0 REGISTER ADDRESS BIT LABEL R16388 (4004h) SOUNDSTA GE_ENABLE S_1 7:0 SOUNDSTAGE _ENABLES_23_ 16 [7:0] DEFAULT DESCRIPTION 0000_0000 [No description available] Register 4004h SOUNDSTAGE_ENABLES_1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R16389 (4005h) SOUNDSTA GE_ENABLE S_0 15:6 SOUNDSTAGE _ENABLES_15_ 06 [9:0] 5 RTN_ADC_ENA 0 ADC ReTune enable 0 = Disabled 1 = Enabled 4 RTN_DAC_ENA 0 DAC ReTune enable 0 = Disabled 1 = Enabled 3 HDBASS_ENA 0 HD Bass enable 0 = HD Bass disabled 1 = HD Bass enabled 2 HPF2_ENA 0 High-Pass Filter (HPF2) enable 0 = Disabled 1 = Enabled 1 HPF1_ENA 0 High-Pass Filter (HPF1) enable 0 = Disabled 1 = Enabled 0 VSS_ENA 0 Virtual Surround Sound (VSS) enable 0 = Disabled 1 = Enabled 00_0000_0 [No description available] 000 Register 4005h SOUNDSTAGE_ENABLES_0 270 Rev 4.4 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION [HD Bass Control Registers] R16896 (4200h) HDBASS_AI _0 To R16925 (421Dh) HDBASS_PG _0 Register 4201h HDBASS_AI_0 to Register 421Dh HDBASS_PG_0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION [DAC High Pass Filter Control Registers] R17408 (4400h) HPF_C_1 To R17409 (4401h) HPF_C_0 Register 4400h HPF_C_1 to Register 4401h HPF_C_0 REGISTER ADDRESS R17920 (4600h) ADCL_RETU NE_C1_1 BIT LABEL DEFAULT DESCRIPTION [ADC ReTune Control Registers] To R19007 (4A3Fh) ADCR_RETU NE_C32_0 Register 4600h ADCL_RETUNE_C1_1 to Register 4A3Fh ADCR_RETUNE_C32_0 Rev 4.4 271 WM8962 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION [DAC ReTune Control Registers] R19456 (4C00h) DACL_RETU NE_C1_1 To R20543 (503Fh) DACR_RETU NE_C32_0 Register 4C00h DACL_RETUNE_C1_1 to Register 503Fh DACR_RETUNE_C32_0 REGISTER ADDRESS R20992 (5200h) VSS_XHD2_ 1 BIT LABEL DEFAULT DESCRIPTION [VSS Control Registers] To R21139 (5293h) VSS_XTS32 _0 Register 5200h VSS_XHD2_1 to Register 5293h VSS_XTS32_0 272 Rev 4.4 WM8962 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Filter Passband 0.454 fs -3dB Passband Ripple 0.5 fs f < 0.454 fs +/- 0.05 Stopband dB 0.546 fs Stopband Attenuation f > 0.546 fs -60 dB DAC Normal Filter Passband 0.454 fs -6dB Passband Ripple 0.5 fs f < 0.454 fs +/- 0.05 Stopband dB 0.546 fs Stopband Attenuation 0.546 fs < f < 30 fs -50 dB DAC Sloping Stopband Filter Passband 0.454 fs -9dB Passband Ripple 0.5 fs f < 0.25 fs +/- 0.05 0.25 fs < f < 0.454 fs +/- 1 Stopband 1 0.546 fs Stopband 1 Attenuation f > 0.546 fs 0.7 fs -60 Stopband 2 dB 0.7 fs Stopband 2 Attenuation f > 0.7 fs 1.4 fs -85 Stopband 3 dB dB 1.4 fs Stopband 3 Attenuation 1.4 fs < f < 30fs DAC FILTERS -53 dB ADC FILTERS Mode Group Delay Mode Group Delay Normal 16.5 / fs Normal 15 / fs Sloping Stopband 18 / fs TERMINOLOGY 1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple – any variation of the frequency response in the pass-band region Rev 4.4 273 WM8962 DAC FILTER RESPONSES This series of plots shows the filter response for the entire DAC channel for different signal rates. The full path, has a nominal gain of 3.01dB (1V input, 1.414V output), this means that the highest nodes in the 48kHz case are at 47.5dB (rather than below the 50dB specification). Sample Rate (kHz) Sloping Stop-band MCLK recommended rate for DAC only playback (CODEC mode) (Hz) 8 Yes 3072000 (3072000) 11.025 Yes 2822400 (2822400) 12 Yes 3072000 (3072000) 16 Yes 2048000 (6144000) 22.05 Yes 2822400 (5644800) 24 Yes 3072000 (6144000) 32 No 2048000 (8192000) 44.1 No 2822400 (11289600) 48 No 3072000 (12288000) Table 132 Recommended Filter Configurations for Supported Sample Rates Figure 73 DAC Filter Response 8k Sampling Rate Figure 74 DAC Filter Response for 11.025k Sample Rate Figure 75 DAC Filter Response for 12k Sample Rate Figure 76 DAC Filter Response for 16k Sample Rate 274 Rev 4.4 WM8962 Figure 77 DAC Filter Response 22.05k Sample Rate Figure 78 DAC Playback Filter Response for 24k Sample Rate Figure 79 DAC Playback Filter Response for 32k Sample Figure 80 DAC Playback Filter Response for 44.1k Sample Rate Rate Figure 81 DAC Playback Filter Response for 48k Sample Figure 82 DAC Playback Filter Passband Ripple for 44.1k Rate Sample Rate (MCLK=11.2896MHZ) Rev 4.4 275 WM8962 ADC FILTER RESPONSES Figure 83 ADC Digital Filter Frequency Response (128OSR) Figure 84 ADC Digital Filter Passband Ripple (128OSR) 276 Rev 4.4 WM8962 ADC HIGH PASS FILTER RESPONSES Figure 85 ADC Digital High Pass Filter Frequency Response (48kHz, Hi-Fi Mode, ADC_HPF_CUT[1:0]=00) -2.3338m -8.3373 -16.672 -25.007 -33.342 -41.677 -50.012 -58.347 -66.682 -75.017 -83.352 2 5.0248 hpf_response.res MAGNITUDE(dB) 12.624 31.716 79.683 200.19 502.96 1.2636k 3.1747k 7.9761k 20.039k hpf_response2.res MAGNITUDE(dB) hpf_response2.res#1 MAGNITUDE(dB) Figure 86 ADC Digital High Pass Filter Ripple (48kHz, Voice Mode, ADC_HPF_CUT=01, 10 and 11) Rev 4.4 277 WM8962 DE-EMPHASIS FILTER RESPONSES MAGNITUDE(dB) MAGNITUDE(dB) 0.3 0 -1 0.25 0 5000 10000 15000 20000 0.2 -2 0.15 -3 0.1 -4 0.05 0 -5 -0.05 -6 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 -0.1 -7 -0.15 Frequency (Hz) -8 -9 -10 Frequency (Hz) Figure 87 De-Emphasis Digital Filter Response (32kHz) Figure 88 De-Emphasis Error (32kHz) MAGNITUDE(dB) MAGNITUDE(dB) 0.2 0 -1 0 5000 10000 15000 20000 25000 0.15 -2 -3 0.1 -4 0.05 -5 -6 0 -7 0 -8 5000 10000 15000 20000 25000 -0.05 -9 -0.1 -10 Frequency (Hz) Frequency (Hz) Figure 89 De-Emphasis Digital Filter Response (44.1kHz) Figure 90 De-Emphasis Error (44.1kHz) MAGNITUDE(dB) MAGNITUDE(dB) 0.15 0 0 5000 10000 15000 20000 25000 30000 -2 0.1 -4 0.05 -6 0 -8 -0.05 -10 -0.1 0 10000 15000 20000 25000 30000 -0.15 -12 Frequency (Hz) Figure 91 De-Emphasis Digital Filter Response (48kHz) 278 5000 Frequency (Hz) Figure 92 De-Emphasis Error (48kHz) Rev 4.4 WM8962 APPLICATIONS INFORMATION ANALOGUE INPUT PATHS The WM8962 provides up to 8 analogue audio input paths. Each of these inputs is referenced to the internal DC reference, VMID. A DC blocking capacitor is required for each analogue input pin used in the target application. The choice of capacitor is determined by the filter that is formed between that capacitor and the impedance of the input pin. The circuit is illustrated in Figure 93. Input C R Fc = - eg. 1F 1 2 p RC PGA To input boost mixer Fc = high pass 3dB cut-off frequency + VMID Figure 93 Audio Input Path DC Blocking Capacitor In accordance with the WM8962 input pin resistance, it is recommended that a 1F capacitance will give good results in most cases. Note that the input impedance, R, changes with the PGA gain setting, as described in the “Electrical Characteristics”. A single capacitor is required for line or microphone input connection. Tantalum electrolytic capacitors are particularly suitable as they offer high stability in a small package size. Ceramic equivalents are a cost effective alternative to the superior tantalum packages, but care must be taken to ensure the desired capacitance is maintained at the AVDD operating voltage. Also, ceramic capacitors may show microphonic effects, where vibrations and mechanical conditions give rise to electrical signals. This is particularly problematic for microphone input paths where a large signal gain is required. The external connections for electret condenser microphones, incorporating the WM8962 microphone bias circuit, are shown later in the “Microphone Bias Circuit” section below. MICROPHONE BIAS CIRCUIT The WM8962 is designed to interface easily with analogue microphones. An electret condenser microphone (ECM) requires a bias current; this can be provided by the MICBIAS output on the WM8962. An electret condenser microphone may be connected in single-ended configuration, as illustrated in Figure 94. A decoupling capacitor is required on the MICBIAS output. A suitable capacitor must be connected whenever the MICBIAS output is enabled. A current-limiting resistor is also required for the ECM; the resistance should be chosen according to the minimum operating impedance of the microphone and MICBIAS voltage so that the maximum bias current of the WM8962 is not exceeded. A 2.2k current-limiting resistor is recommended; this provides compatibility with a wide range of microphone components. Note that the MICBIAS output can also be used to power an analogue silicon microphone. In this case, the MICBIAS connects directly to the VDD pin of the microphone - a current-limiting resistor is not required in this case. Rev 4.4 279 WM8962 MICBIAS 1F 2.2k IN1L, IN4L, IN1R, IN4R - MIC To input boost mixer PGA + VMID Figure 94 Single Ended Microphone Connection Additional filtering of the MICBIAS output, to reduce noise and interference, may be implemented using the configuration illustrated in Figure 95. 1k MICBIAS 22F 1.2k IN1L, IN4L, IN1R, IN4R - MIC PGA To input boost mixer + VMID Figure 95 Microphone Connection, with MICBIAS filter components 280 Rev 4.4 WM8962 CHARGE PUMP COMPONENTS The WM8962 incorporates a Charge Pump circuit, which generates the CPVOUTP and CPVOUTN supply rails for the ground-referenced headphone drivers. Decoupling capacitors are required on each of the Charge Pump outputs. A fly-back capacitor is also required. The recommended Charge Pump capacitors for WM8962 are detailed below in Table 133. DESCRIPTION CPVOUTP decoupling CAPACITOR Required capacitance is 2.0F at 2V. Suitable component typically 4.7F. CPVOUTN decoupling Required capacitance is 2.0F at 2V. Suitable component typically 4.7F. Charge Pump fly-back (connect between C1CA and C1CB) Required capacitance is 1.0F at 2V. Suitable component typically 2.2F. Table 133 Charge Pump External Capacitors Ceramic capacitors are recommended for these Charge Pump requirements. Note that, due to the wide tolerance of many types of ceramic capacitors, care must be taken to ensure that the selected components provide the required capacitance across the required temperature and voltage ranges in the intended application. Ceramic capacitors with X5R dielectric are recommended. The positioning of the Charge Pump capacitors is important, particularly the fly-back capacitors. These capacitors should be placed as close as possible to the WM8962. Rev 4.4 281 WM8962 PLLVDD MICVDD SPKVDD2 SPKVDD1 CPVDD DBVDD AVDD DCVDD RECOMMENDED EXTERNAL COMPONENTS DIAGRAM AGND DGND CPGND AVDD SPKGND1 DCVDD SPKGND2 DBVDD PLLGND CPVDD SPKVDD1 SPKVDD2 VMIDC MICVDD 4.7F PLLVDD 4.7F 0.1F 0.1F 2.2F 4.7F 4.7F 4.7F 4.7F MICBIAS 1.0F SDA SCLK Control Interface MCLK/XTI CIFMODE Crystal Oscillator XTO CS/GPIO6 24MHz WM8962 BCLK LRCLK Audio Interface DACDAT ADCDAT GPIO / External Clocking HPOUTFB Headset HPOUTR HPOUTL 0.1F 0.1F 20 20 CLKOUT2/GPIO2 CLKOUT3/GPIO3 (Note: HPOUTFB ground connection close to headset jack) GPIO5 Note that GPIO5 must be in a defined state (logic ‘0’ or logic ‘1’) during start-up; it must not be left floating. CLKOUT5 1F 1F 1F 1F Analogue Audio (Mic / Line) Inputs 1F 1F IN1L SPKOUTLN IN1R SPKOUTLP IN2L SPKOUTRN IN2R SPKOUTRP Loudspeaker Loudspeaker IN3L IN3R CPCA 2.2F CPCB 1F 1F IN4L CPVOUTN IN4R CPVOUTP 2.2F 2.2F Note that the optimum input capacitance will vary according to the required frequency response and the applicable input impedance. Figure 96 WM8962 Recommended External Components 282 Rev 4.4 WM8962 Notes: 1. Power Supply Decoupling Capacitors X5R ceramic capacitor is recommended for the power supply decoupling capacitors. The decoupling capacitors on VMIDC, MICBIAS, CPVOUTP and CPVOUTN should be as close to the WM8962 as possible. 2. Charge Pump Capacitors Specific recommendations for Charge Pumpe capacitors are provided in Table 134. Note that two different recommendations are provided for CPVOUTP and CPVOUTN; either of these components is suitable, depending upon size requirements and availability. The positioning of the flyback capacitor is very important - this should be as close to the WM8962 as possible. It is important to select a suitable capacitor type for the Charge Pump. Note that the capacitance may vary with DC voltage; care is required to ensure that required capacitance is achieved at the applicable operating voltage, as specified in Figure 96. The capacitor datasheet should be consulted for this information. COMPONENT REQUIRED CAPACITANCE VALUE  1F at 2VDC 2.2F Kemet C0402C225M9PAC 2.2F 4.7F Charge Pump Flyback (CPCA to CPCB) CPVOUTN decoupling, CPVOUTP decoupling  2F at 2VDC PART NUMBER VOLTAGE TYPE SIZE 6.3v X5R 0402 MuRata GRM188R61A225KE34D 10v X5R 0603 MuRata GRM155R60J475M_EIA 6.3v X5R 0402 Table 134 Charge Pump Capacitors 3. Zobel Networks The Zobel network shown in Figure 96 is required on HPOUTL and HPOUTR whenever that output is enabled. Stability of these ground-referenced outputs across all process corners cannot be guaranteed without the Zobel network components. (Note that, if any ground-referenced output pin is not required, the Zobel network components can be omitted from the output pin, and the pin can be left floating.) The Zobel network requirement is detailed further in the applications note WAN_0212 “Class W Headphone Impedance Compensation”. Zobel networks should be positioned reasonably close to the WM8962. 4. Crystal Oscillator The WM8962 supports device clocking from either a digital clock source (compatible with timing and voltage threshold requirements) or from a crystal oscillator. 5. PLLGND Connection The AGND and PLLGND pins must be tied together as close as possible to the WM8962. Rev 4.4 283 WM8962 PCB LAYOUT CONSIDERATIONS Poor PCB layout will degrade the performance and be a contributory factor in EMI, ground bounce and resistive voltage losses. All external components should be placed as close to the WM8962 device as possible, with current loop areas kept as small as possible. The following layout priorities should be observed. (All these components should be as close to the WM8962 as possible; item 1. Is the highest priority). 284 1. Crystal 2. Charge pump capacitors 3. AVDD, DCVDD, DBVDD decoupling 4. VMIDC, MICBIAS decoupling 5. Other decoupling 6. Zobel network components 7. CLKOUTn termination resistors Rev 4.4 WM8962 MIC DETECTION SEQUENCE USING MICBIAS CURRENT This section details an example sequence which summarises how the host processor can configure and detect the events supported by the MICBIAS current detect function (see “MICBIAS Current Detect”):  Mic insertion/removal  Hook switch press/release Figure 97 shows an example of how the MICBIAS current flow varies versus time, during mic insertion and hook switch events. The Y axis is annotated with the Mic detection thresholds, and the X axis is annotated with the stages of an example sequence as detailed in Table 135, to illustrate how the host processor can implement mic insertion and hook switch detection. The sequence assumes that the microphone insertion and hook switch detection functions are monitored by polling the interrupt flags using the control interface. Note that the maximum mechanical bounce times for mic insertion and removal must be fully understood by the software programmer. A GPIO pin could be used as an alternative mechanism to monitor the MICBIAS detection functions. This enables the host processor to detect mechanical bounce at any time. Example plot of MICBIAS Current versus time (1) Step (2) (3) (4) (5) (6) (7) (8) (9) (10) MICBIAS Current Mic inserted TSHORT Hook switch pressed Mic Hook Switch Threshold TDET TDET Hysteresis TSHORT Mic Detect Threshold Step (1) (2) (3) (4) (5) (6) (7) (8) Time (9) (10) Mic Detect Interrupt MICD_EINT Mic Detect Interrupt Polarity MICD_IRQ_POL MICSCD_EINT Mic Short Interrupt Mic Short Interrupt Polarity Read the Mic detect interrupt HOST PROCESSOR flag. If high, can then set MICD_IRQ_POL to 1, but only if mechanical bounce phase has finished. Clear MICD_EINT by writing ‘1’. MICSCD_IRQ_POL Read the Hook switch interrupt flag. If high, can immediately set MICSCD_IRQ_POL to 1. Clear MICSCD_EINT by writing ‘1’. Read the Mic detect interrupt flag. If high, can then clear MICD_IRQ_POL to 0, but only if mechanical bounce phase has finished. Clear MICD_EINT by writing ‘1’. Read the Hook switch interrupt flag. If high, can immediately clear MICSCD_IRQ_POL to 0. Clear MICSCD_EINT by writing ‘1’. Figure 97 Mic Insert and Hook Switch Detect: Example MICBIAS Current Plot STEP Rev 4.4 DETAILS 285 WM8962 1 Mic not inserted. To detect mic insertion, Host processor must initialise interrupts and clear MICD_IRQ_POL = 0. At every step, the host processor should poll the interrupt status register. Note that Mic Insertion de-bounce circuitry is automatically enabled. 2 Mechanical bounce of jack socket during Mic insertion. Host processor may already detect a mic insertion interrupt (MICD_EINT) during this step. Once detected, the host processor can set MICD_IRQ_POL = 1 and then clear the interrupt, unless mechanical bounce can last longer than the shortest possible TDET, in which case the host processor should wait until step 3. 3 Mic fully inserted. If not already set, the host processor must now set MICD_IRQ_POL = 1. If not already cleared, the host processor must now clear the MICD_EINT interrupt. To detect Hook switch press, the host processor must clear MICSCD_IRQ_POL = 0. At this step, the diagram shows no AC current swing, due to a very low ambient noise level. 4 Mic fully inserted. Diagram shows AC current swing due to high levels of background noise (such as wind). 5 Mechanical bounce during hook switch press. The hook switch interrupt is unlikely to be set during this step, because 10 successive samples of the MICBIAS current exceeding the hook switch threshold have not yet been sampled. Note that Hook Switch de-bounce circuitry is automatically enabled. 6 Hook switch is fully pressed down. After TSHORT, 10 successive samples of the MICBIAS current exceeding the hook switch threshold have been detected, hence a hook switch interrupt (MISCD_EINT) will be generated. Once detected, the host processor can immediately set MICSCD_IRQ_POL = 1 and then clear the MICSCD_EINT interrupt. 7 Mechanical bounce during hook switch release. The hook switch interrupt is unlikely to be set during this step, because 10 successive samples of the MICBIAS current lower than the hook switch threshold have not yet been sampled. 8 Hook switch fully released. After TSHORT, 10 successive samples of the MICBIAS current lower than the hook switch threshold have been detected, hence a hook switch interrupt (MICSCD_EINT) will be generated. Once detected, the host processor can immediately clear MICSCD_IRQ_POL = 0 and then clear the MICSCD_EINT interrupt. 9 Mechanical bounce of jack socket during Mic removal. Host processor may already detect a mic removal interrupt (MICD_EINT) during this step. Once detected, the host processor can clear MICD_IRQ_POL = 0 and then clear the interrupt, unless mechanical bounce can last longer than the shortest possible TDET, in which case the host processor should wait until step 10. 10 Mic fully removed. If not already cleared, the host processor must now clear MICD_IRQ_POL = 0. If not already cleared, the host processor must now clear the MICD_EINT interrupt. Table 135 Mic Insert and Hook Switch Detect: Example Sequence Alternatively, utilising a GPIO pin to monitor the MICBIAS current detect functionality permits the host processor to monitor the steady state of microphone detection or hook switch press functions. Because the GPIO shows the steady state condition, software de-bounce may be easier to implement in the host processor, dependant on the processor performance characteristics, hence use of the GPIO is likely to simplify the rejection of mechanical bounce. Changes of state in the GPIO pin are also subject to the time delays tDET and tSHORT. 286 Rev 4.4 WM8962 PACKAGE DIMENSIONS PACKAGE DIAGRAM FOR DEVICES MARKED KBC B: 49 BALL W-CSP PACKAGE 3.594 X 3.984 X 0.7mm BODY, 0.50 mm BALL PITCH DM075.B 6 D DETAIL 1 A 2 7 A2 3 4 5 6 2 1 A A1 CORNER 4 B C e E1 D E 5 E F G 2X e DETAIL 2 2X D1 0.10 Z 0.10 Z TOP VIEW BOTTOM VIEW f1 SOLDER BALL f2 bbb Z h 1 Z A1 DETAIL 2 Symbols A A1 A2 D D1 E E1 e MIN 0.650 0.219 0.431 3.564 3.954 f1 0.297 f2 0.492 h Dimensions (mm) NOM MAX 0.7 0.750 0.269 0.244 0.456 0.481 3.594 3.624 3.00 BSC 3.984 4.014 3.00 BSC 0.50 BSC NOTE 5 0.314 BSC NOTES: 1. PRIMARY DATUM -Z- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 2. THIS DIMENSION INCLUDES STAND-OFF HEIGHT ‘A1’ AND BACKSIDE COATING. 3. A1 CORNER IS IDENTIFIED BY INK/LASER MARK ON TOP PACKAGE. 4. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY. 5. ‘e’ REPRESENTS THE BASIC SOLDER BALL GRID PITCH. 6. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 7. FOLLOWS JEDEC DESIGN GUIDE MO-211-C. Rev 4.4 287 WM8962 PACKAGE DIAGRAM FOR DEVICES MARKED BCA HN8 B: 49 BALL W-CSP PACKAGE 3.594 X 3.984 X 0.7mm BODY, 0.50 mm BALL PITCH DM112.B 6 A D DETAIL 1 A 2 7 A2 3 4 5 6 2 1 A A1 CORNER 4 B C e E1 D E 5 E F G 2X ddd e DETAIL 2 M Z AB 2X D1 aaa B bbb A TOP VIEW B BOTTOM VIEW f1 SOLDER BALL f2 bbb Z h 1 Z ccc Z A1 DETAIL 2 Symbols A A1 A2 D D1 E E1 e MIN 0.661 0.207 0.443 3.569 3.959 f1 0.297 f2 0.492 h aaa 0.264 bbb ccc ddd Dimensions (mm) NOM MAX 0.700 0.739 0.281 0.244 0.456 0.469 3.594 3.619 3.00 BSC 3.984 4.009 3.00 BSC 0.50 BSC 0.314 0.025 0.060 NOTE 5 0.364 0.030 0.015 NOTES: 1. PRIMARY DATUM -Z- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 2. THIS DIMENSION INCLUDES STAND-OFF HEIGHT ‘A1’ AND BACKSIDE COATING. 3. A1 CORNER IS IDENTIFIED BY INK/LASER MARK ON TOP PACKAGE. 4. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY. 5. ‘e’ REPRESENTS THE BASIC SOLDER BALL GRID PITCH. 6. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 7. FOLLOWS JEDEC DESIGN GUIDE MO-211-C. 288 Rev 4.4 WM8962 IMPORTANT NOTICE Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic group (collectively either “Cirrus” or “Cirrus Logic”) are sold subject to Cirrus’s terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Cirrus to verify that the information is current and complete. Testing and other quality control techniques are utilized to the extent Cirrus deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. Cirrus is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Cirrus products. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). 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Rev 4.4 289 WM8962 REVISION HISTORY DATE REV 9 Nov 09 0.1 First draft for internal review 25 Nov09 1.0 Draft Release 26 Nov09 1.1 Page 1 (left side) – Changed ‘…and one EFS F are…’ to ‘…and one EFS Frequency Synthesiser are…’ Page 1 (left side) – Removed ‘providing 1W per channel into 8 ohms’ from penultimate paragraph Page 1 (right side) – added the word ‘analogue’ to first bullet on mic interface Page 7 – Pin description changed from CS/GPIO2 to CS/GPIO6 Page 8 – F3 was in bold font – changed to normal font Page 27 – Line Input Connection had omitted ‘IN1’ from the list of inputs – ‘IN1, ‘ was added to ‘IN2, IN3 and IN4…’ Page 88 – SPKMIXx_TO_SPKOUTx_PGA register descriptions moved from Table 66 to Tables 64 (left) and 65 (right) Pge 129 – Reinserted short paragraph starting ‘Note that the frequency synthesiser can be used to generate free –running…’ Page 131/132 – Descriptions of register in Table 97 (FLL_OUTDIV) changed from ‘divide’ to ratio and in Table 98 (FLL_FRATIO) from ‘multiply’ to ‘ratio’. Register descriptions also changed to ‘ratio’ in Table 99 Register Controls Page 137/138 – Registers GP2_FN and GP3_FN, value 0_0000 descriptions changed from ‘PLLn CLKOUT’ to ‘CLKOUT’ Replaced most occurrences of ‘EFS Frequency Synthesiser’ with ‘FLL’ throughout the document Page 122 Table 88 Automatic Clocking Configuration Control – Changed description of ADC_HP in this table to be the same as the description used in Table 24 ADC Oversampling Ratio on page 50 Page 83 – Table 61 DAC Oversampling Control – Changed description of DAC_HP to be similar style to ADC_HP descriptions used elsewhere Page 122 Table 88 Automatic Clocking Configuration Control – Changed description of DAC_HP in this table to be the same as the description used in Table 61 DAC Oversampling Ratio on page 83 Page 137 Table 103 ‘GPIO Control’: GP2_FN – note at the bottom of the description now reads ‘Note that PLL2 or the internal oscillator CLKOUT is enabled…’ Page 138 Table 103 ‘GPIO Control’: GP3_FN – note at the bottom of the description now reads ‘Note that PLL3 or FLL CLKOUT is enabled…’ 22 Dec09 1.2 Page 52 Table 26 ADC High-Pass Filter – added ‘This field is for readback only; it is set automatically by the WM8962’ to description Page 68 Table 43 Digital Sidetone Control – The table wrongly described the register bits of ADC_TO_DACR as 1:0; this was changed to register bits 3:2 Page 84 – Figure 29 Output Signal Paths - Modified the diagram to show 'DAC_MUTERATE' instead of 'DAC_MUTE_RATE' (two occurrences) Page 165 Table of Register 06h ADC and DAC Control2 – added ‘This field is for read-back only; it is set automatically by the WM8962’ to description 290 PAGE CHANGED BY Page 27 – added a note (two places on the page) clarifying automatic switching of IN1L/R (used for capacitor connection) when any of IN2L/R or IN3L/R are used for mic input 14 Jan 10 12 April 10 DESCRIPTION OF CHANGES 2.0 Page 138 Fig 56 updated to show Microphone Short Interrupt and Microphone Detect Interrupt Rev 4.4 WM8962 DATE REV DESCRIPTION OF CHANGES May 2010 2.0 Default value of CHIP_REV and PLL_REVISION code deleted Clocking registers with variable defaults defined (depending upon PLLVDD3), new register CLKREG_OVD added Change to default PLL1 spread spectrum rate SW_RESET amended to control non-PLL registers only. New register SW_RESET_PLL added to reset PLL registers MICBIAS current detection features added DRC Decay times updated Write Sequencer updated to allow register access to PLL registers whilst sequencer is running FLL integer mode descriptions added Update to incorrect register value FLL_LAMBDA Crystal oscillator loading capacitor trim control registers added CLKOUTn Output Enable registers and Divide by 2 registers added Update to incorrect register address for “Write Sequencer Control 2” (R90) Beep generator registers moved Digital filter characteristics added Added analogue input IN4 to Headphone path, with all associated mixer functions Updated minimum clocking requirements for DSP2 BIAS_LVL register deleted Noted that Class W Charge Pump mode not recommended when using DSP functions Added definition of HP1_DCS_SYNC_STEP register to control number of measurements in DC Servo series event Added DSP control registers and control sequence requirements for DSP enable / disable / update / readback Amended clocking diagram and BCLK_DIV to show BCLK generated from DSPCLK Minimum supply voltages updated Write Sequencer register defaults updated in Table 113 Updated HPOUT_VU description Updated InxL_TO_INPGAL, InxR_TO_INPGAR descriptions ALC_PKOVR_STS level amended to -1.16dBFS Amended definition of TEMP_ENA_SPK Amended definition of ADCL_DAC_SVOL and ADCR_DAC_SVOL Updated Audio Interface Timing spec (ADCDAT propagation delay and LRCLK set-up time) Added confirmation that Mic Detect and Interrupts are supported using free-running FLL in the absence of an external clock Example PLL settings described for 12MHz & 24.576MHz output External components drawing updated, removing crystal loading caps External components (PCB layout) recommendations added 10/11/10 2.1 Clock generation block diagram updated to include FLL_OUTDIV and PLLn_OUTDIV. “Further Headphone Control and Pop Suppression” section moved to start of the Headphone Output Paths section, and re-titled as “Headphone Signal Paths Enable”. Added sub-section title “Analogue Reference and Master Bias” within the “Reference voltages and Master Bias” section. Updated illustration of mono/speaker connections. Removed REG_SYNC register (described as “Reserved - do not change”). Updates to clarify SYSCLK_ENA requirements for register access with/without clocking. Noted the register addressing is 15-bit (not 16-bit) in SPI modes. Clarified requirement that MICVDD must be at least 300mV greater than Vmicbias. Rev 4.4 PAGE CHANGED BY 291 WM8962 DATE REV DESCRIPTION OF CHANGES 10/11/10 2.1 SYSCLK_RATE renamed as MCLK_RATE SYSCLK_SRC renamed as MCLK_SRC MCLKDIV renamed as SYSCLK_DIV Clocking schematic updated, adding DSP2CLK MCLK_RATE definition updated (1408fs deleted, 3072fs/6144fs added) Description of ADCSYS_CLK_DIV and DACSYS_CLK_DIV edited to simply refer to deriving the ‘most suitable SYSCLK / fs ratio’ Additional detail provided on supported SYSCLK configurations. DAC Clocking Control and ADC Clocking Control sections added. Digital Microphone interface section updated, including supported clocking configurations. Block diagram updated to include DAC path HPF. Digital Mixing diagram updated to show DSP Signal Enhancements. DAC HPF description moved from HD Bass into a new section, between DRC and VSS. Descriptive text added to all DSP Signal Enhancement functions. Clarification to the GCD function description for FLL fractional mode. DSP2 registers added to Register Table and Register by Address section. GPn_LVL registers described as Write-Only as outputs; the readback value is undefined. Additional cross-referencing to “Interrupts” added in Micbias Current Detect description. Moved “PLL Reference Select” into PLL section, and “FLL Reference Select” into FLL section. Analogue input resistance characteristics updated. Added requirements that GPIO5 must be in a defined logic state during start-up. DC servo / offset characteristics updated to +/-1.4mV. MICDET_THR and MICSHORT_THR definitions updated. Additional requirements defined for selecting MCLK as PLL Clock Source. OSC_TRIM_XTI and OSC_TRIM_XTO definitions updated. ADC_BIAS register deleted. ADC_HP default value updated. INPGA_BIAS definition and default value updated. MIXIN_BIAS definition updated. Relative performance of each of the input signal paths described. Digital Microphone Interface timing specification added. Timing specifications amended as “applicable across all Recommended Operating Conditions”. Correction to I2C Register Read illustration. 292 PAGE CHANGED BY Rev 4.4 WM8962 DATE REV 25/01/11 3.0 DAC to Headphone Channel Separation updated. Crosstalk definition re-named as Channel Separation definition. Added clarification to the GP2_FN = 0 and GP3_FN = 0 settings. Digital Sidetone registers ADC_TO_DACR and ADC_TO_DACL updated. DRC Signal Detect registers DRC_SIG_DET_RMS, DRC_SIG_DET_PK and DRC_SIG_DET_MODE updated. TOCLK, DBCLK and Interrupt de-bounce functions updated - DBCLK is enabled automatically whenever de-bounce is selected; TOCLK_ENA no longer enables the DBCLK. Specific control sequence described for disabling all DSP sound enhancements. Updated ‘Multiple Push Button Detection’ section with note that mic/line audio input path cannot be supported at the same as DC measurement via the same PGA. DMICCLK duty cycle specification added. INL, INR, HPOUTL and HPOUTR PGA descriptions updated to note that the PGA Mute functions are controlled by the respective Volume Update (_VU) registers. 25/01/11 3.0 CLKOUTn output impedance added to Electrical Characteristics. IN4 to Headphone path characteristics added. Recommended Input Signal Path bias settings defined (4 options). Electrical Characteristics updated for each of the specified input path bias options. Removed ALC_NGATE_MODE = 11 setting. Updated definition of WSEQ_DELAY and all sequencer timing information. Added requirement that FLL_LAMBDA must be non-zero in all cases. Headphone output Low Power / High Performance modes defined, with applicable bias settings. Crystal oscillator start-up time added. Noted that PLL start-up is inclusive of oscillator start-up. Noted that AGND / PLLGND must be tied together as close as possible to the device. Output PGA descriptions updated; gain is -68dB for codes 011_0000 through to 011_0101. Amendments to DRC_SIG_DET_RMS, DRC_SIG_DET_PK and DRC_NG_MINGAIN registers. Additional requirements defined for setting CP_DYN_PWR=0. Sound Enhancement control sequences updated. Noted the DAC HPF cannot be enabled on its own; another enhancement must be enabled. Power consumption data added. Correction to SPI_CFG register. In 4-wire mode, only SDOUT on GPIO5 can be configured as Wired ‘OR’; SDOUT on GPIO2 or GPIO3 will always be CMOS. PLL Reset described in Power On Reset section. Recommended operating conditions note that operation is possible without PLLVDD. Updated clocking constraints - DRC is not supported below 192fs. Additional requirements defined for AIF Slave mode relating to BCLK/LRCLK stopping. Input PGA boost definition updated (+30dB setting becomes +29dB). Amendment in ALC Attack/Decay definition - varies with ALC_MODE (not ALC_LVL_MODE). 25/01/11 3.0 Electrical Characteristics updated, Record power consumption added on front page. 25/01/11 3.0 Up-issued to Rev 3.0 Rev 4.4 DESCRIPTION OF CHANGES PAGE CHANGED BY 293 WM8962 DATE REV DESCRIPTION OF CHANGES 22/11/11 3.2 Block diagram updated - duplicate SPKVDD1 / SPKGND1 pins deleted. Minor updates to ALC description. Updated recommended components description for Charge Pump & MICBIAS. Digital Filter Characteristics updated. External components drawing updated. ALC Attack/Decay timing descriptions updated. Speaker output path PSRR figures updated. Control sequence added to configure IN4L or IN4R for push-button detection function. Additional description provided for configuring the CLKOUT/GPIO pins as GPIO functions. Additional description provided for clocking registers controlled by GPIO5 / CLKREG_OVD. Updates to MCLK / Sample rate feature availability tables. 13/03/12 3.2 MICBIAS Current Detection thresholds updated 25/05/12 3.2 Update to comments regarding MICBIAS filtering components 23/08/12 3.3 Package Diagram DM112A added 30/08/12 4.0 Product status updated to Production Data Updates to the Electrical Characteristics. Updated ADC oversampling rate description. 04/04/13 4.1 Noted that I2C addresses 94h and D2h are reserved, and must not be used on the same bus as WM8962. 22/05/13 4.2 Additions to the recommended DSP control sequences. Correction to the inconsistent descriptions of the SPKOUTL/R_PGA_MUTE bits. 08/01/14 4.2 Part number WM8962ECS/R added. Heading ‘Package Diagram for Devices Marked BCA’ updated to ’Package Diagram for Devices Marked BCA HN8’ 30/01/14 4.2 Additional requirements for writing 24-bit DSP configuration registers. Digital Core block diagram updated, consistent with ADC Enhancements functions (Second Order Filter is included within ADC Enhancements). 70, 184 92 22/07/14 4.3 Correction to control sequence for multiple push-button detection. DF1 filter as input to DRC is deleted. 43 82, 84 PH 27/05/15 4.3 Ordering Information (Reel Quantity) updated Package Drawings DM075.B and DM112.B incorporated 7 288, 289 PH 09/09/16 4.4 Ordering Information (Reel Quantity) updated Multiple-button detect function deleted 7 43-44 PH 294 PAGE CHANGED BY 70, 73-74 120 7 289 Rev 4.4