WM8974CGEFL/RV

WM8974 Mono CODEC with Speaker Driver DESCRIPTION FEATURES The WM8974 is a low power, high quality mono CODEC designed for portable applications such as Digital Still Camera or Digital Voice Recorder. Mono CODEC:  Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz  DAC SNR 98dB, THD -84dB (‘A’-weighted @ 8 – 48ks/s)  ADC SNR 94dB, THD -83dB (‘A’-weighted @ 8 – 48ks/s)  On-chip Headphone/Speaker Driver with ‘cap-less’ connect - 40mW output power into 16 / 3.3V SPKVDD - BTL speaker drive 0.9W into 8 / 5V SPKVDD  Additional MONO Line output  Multiple analogue or ‘Aux’ inputs, plus analogue bypass path Mic Preamps:  Differential or single end Microphone Interface - Programmable preamp gain - Psuedo-differential inputs with common mode rejection - Programmable ALC / Noise Gate in ADC path  Low-noise bias supplied for electret microphones The device integrates support for a differential or single ended mic, and includes drivers for speakers or headphone, and mono line output. External component requirements are reduced as no separate microphone or headphone amplifiers are required. Advanced Sigma Delta Converters are used along with digital decimation and interpolation filters to give high quality audio at sample rates from 8 to 48ks/s. Additional digital filtering options are available in the ADC path, to cater for application filtering such as ‘wind noise reduction’, plus an advanced mixed signal ALC function with noise gate is provided. The digital audio interface supports A-law and -law companding. An on-chip PLL is provided to generate the required Master Clock from an external reference clock. The PLL clock can also be output if required elsewhere in the system. The WM8974 operates at supply voltages from 2.5 to 3.6V, although the digital supplies can operate at voltages down to 1.71V to save power. The speaker and mono outputs use a separate supply of up to 5V which enables increased output power if required. Different sections of the chip can also be powered down under software control by way of the selectable two or three wire control interface. WM8974 is supplied in a very small 4x4mm QFN package, offering high levels of functionality in minimum board area, with high thermal performance. DCVDD DBVDD DGND OTHER FEATURES  5 band EQ (record or playback path)  Digital Playback Limiter  Programmable ADC High-Pass Filter (wind noise reduction)  Programmable ADC Notch Filter  On-chip PLL  Low power, low voltage - 2.5V to 3.6V (digital: 1.71V to 3.6V) - power consumption 0.3, less than 0.1 for 50k/500k BOOSTEN 0.2 INPPGAEN 0.2 ADCEN x64 (ADCOSR=0)=>2.6, x128 (ADCOSR=1)=>4.9 MONOEN 0.2 SPKPEN 1mA from SPKVDD + 0.2mA from AVDD in 5V mode SPKNEN 1mA from SPKVDD + 0.2mA from AVDD in 5V mode MONOMIXEN 0.2 SPKMIXEN 0.2 DACEN x64 (DACOSR=0)=>1.8, x128(DACOSR=1)=>1.9 Table 62 AVDD Supply Current 64 Rev 4.7 WM8974 REGISTER MAP ADDR B[15:9] REGISTER NAME B8 B7 B6 B5 B4 B3 B2 B1 B0 DEF’T VAL (HEX) DEC HEX Software reset 0 00 Software Reset 1 01 Power manage’t BUFDCOP 1 EN 2 02 Power manage’t 2 3 03 0 AUXEN PLLEN MICBEN BIASEN BUFIOEN 0 0 0 0 BOOSTEN 0 INPPGAEN 0 ADCEN 000 Power manage’t 3 0 MONOEN SPKNEN SPKPEN 0 MONO SPK 0 DACEN 000 MIXEN MIXEN 0 050 4 04 Audio Interface BCP FRAMEP WL 5 05 Companding ctrl 0 0 6 06 Clock Gen ctrl CLKSEL 7 07 Additional ctrl 0 0 0 8 08 GPIO 0 0 0 OPCLKDIV GPIOPOL 10 0A DAC Control 0 0 DACMU DEEMPH DACOSR 0 VMIDSEL FMT DACLRSW ADCLRSW AP AP 0 DAC_COMP ADC_COMP 0 0 MCLKDIV BCLKDIV LOOPBACK 000 0 SR 000 MS 140 SLOWCLK 000 EN GPIOSEL 000 AMUTE 0 DACPOL 0 0 ADCPOL 000 128 11 0B DAC digital Vol 14 0E ADC Control 0 HPFEN DACVOL HPFAPP HPFCUT 0FF ADCOSR 100 128 15 0F ADC Digital Vol 0 18 12 EQ1 – low shelf EQMODE 0 EQ1C ADCVOL EQ1G 12C 19 13 EQ2 – peak 1 EQ2BW 0 EQ2C EQ2G 02C 20 14 EQ3 – peak 2 EQ3BW 0 EQ3C EQ3G 02C 21 15 EQ4 – peak 3 EQ4BW 0 EQ4C EQ4G 02C 22 16 EQ5 – high shelf 0 0 EQ5C EQ5G 02C 24 18 DAC Limiter 1 LIMEN 25 19 DAC Limiter 2 0 0 27 1B Notch Filter 1 NFU NFEN NFA0[13:7] 000 28 1C Notch Filter 2 NFU 0 NFA0[6:0] 000 29 1D Notch Filter 3 NFU 0 NFA1[13:7] 000 30 1E Notch Filter 4 NFU 0 NFA1[6:0] 32 20 ALC control 1 ALCSEL 0 33 21 ALC control 2 ALCZC ALCHLD ALCLVL 00B 34 22 ALC control 3 ALCMODE ALCDCY ALCATK 032 35 23 Noise Gate 0 0 0 0 0 36 24 PLL N 0 0 0 0 PLLPRE 0FF LIMDCY LIMLVL 0 LIMATK 032 LIMBOOST 000 000 ALCMAX ALCMIN NGEN 038 NGTH 000 PLLN[3:0] 008 SCALE 0 0 0 PLLK[23:18] 37 25 PLL K 1 38 26 PLL K 2 PLLK[17:9] 39 27 PLL K 3 PLLK[8:0] 40 28 Attenuation ctrl 44 2C Input ctrl 45 2D 0 0 0 MBVSEL 0 0 0 0 AUXMODE 0 0 0 ADC Boost ctrl 31 Output ctrl Rev 4.7 0 PGABOOST 2F 49 0E9 0 0 47 093 0 INP PGA gain ctrl INPPGAZC INPPGA 00C MONOATT SPKATTN N 0 000 003 AUX2 MICN2 MICP2 INPPGA INPPGA INPPGA INPPGAVOL 010 MUTE MICP2BOOSTVOL 0 0 0 0 MONO AUX2BOOSTVOL SPK TSDEN 000 VROI 002 65 WM8974 REGISTER NAME ADDR B[15:9] B8 B7 B6 B5 B4 B3 B2 B1 B0 DEF’T VAL (HEX) DEC HEX 50 32 SPK mixer ctrl 0 0 0 54 36 SPK volume ctrl 0 SPKZC SPKMUTE 56 38 MONO mixer ctrl 0 0 MONO AUX2SPK BOOST BOOST 0 0 0 BYP2SPK DAC2SPK SPKVOL 0 0 0 MUTE 000 039 AUX2 BYP2 DAC2 MONO MONO MONO 000 REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as "Reserved" should not be changed from the default. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 0 (00h) [8:0] RESET N/A Software reset Resetting the Chip 1 (01h) 8 BUFDCOPEN 0 Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration. Analogue Outputs 0=Buffer disabled 1=Buffer enabled (required for 1.5x gain boost) 7 6 AUXEN 0 Reserved 0 Auxiliary input buffer enable Auxiliary Inputs 0 = OFF 1 = ON 5 PLLEN 0 PLL enable 0=PLL off 1=PLL on 4 MICBEN 0 Microphone Bias Enable 0 = OFF (high impedance output) Master Clock and Phase Locked Loop (PLL) Microphone Biasing Circuit 1 = ON 3 BIASEN 0 Analogue amplifier bias control 0=Disabled Power Management 1=Enabled 2 BUFIOEN 0 Unused input/output tie off buffer enable 0=Disabled Enabling the Outputs 1=Enabled 1:0 VMIDSEL 00 Reference string impedance to VMID pin: 00=off (open circuit) Power Management 01=50kΩ 10=500kΩ 11=5kΩ 2 (02h) 8:5 4 BOOSTEN 0000 Reserved 0 Input BOOST enable Input Boost 0 = Boost stage OFF 1 = Boost stage ON 3 2 INPPGAEN 0 Reserved 0 Input microphone PGA enable Input Signal Path 0 = disabled 1 = enabled 1 66 0 Reserved Rev 4.7 WM8974 REGISTER ADDRESS BIT 0 LABEL ADCEN DEFAULT 0 DESCRIPTION ADC Enable Control 0 = ADC disabled 1 = ADC enabled 3 (03h) 8 7 MONOEN 0 Reserved 0 MONOOUT enable REFER TO Analogue to Digital Converter (ADC) Analogue Outputs 0 = disabled 1 = enabled 6 SPKNEN 0 SPKOUTN enable Analogue Outputs 0 = disabled 1 = enabled 5 SPKPEN 0 SPKOUTP enable Analogue Outputs 0 = disabled 1 = enabled 4 3 MONOMIXEN 0 Reserved 0 Mono Mixer Enable Analogue Outputs 0 = disabled 1 = enabled 2 SPKMIXEN 0 Speaker Mixer Enable Analogue Outputs 0 = disabled 1 = enabled 1 0 DACEN 0 Reserved 0 DAC enable Analogue Outputs 0 = DAC disabled 1 = DAC enabled 4 (04h) 8 BCP 0 BCLK polarity 0=normal Digital Audio Interfaces 1=inverted 7 FRAMEP 0 Frame clock polarity 0=normal Digital Audio Interfaces 1=inverted DSP Mode control 1 = Reserved 0 = Configures the interface so that MSB is available on 2nd BCLK rising edge after FRAME rising edge 6:5 WL 10 Word length 00=16 bits Digital Audio Interfaces 01=20 bits 10=24 bits 11=32 bits 4:3 FMT 10 Audio interface Data Format Select: 00=Right Justified Digital Audio Interfaces 01=Left Justified 10=I2S format 11= DSP/PCM mode 2 DACLRSWAP 0 Controls whether DAC data appears in ‘right’ or ‘left’ phases of FRAME clock: Digital Audio Interfaces 0=DAC data appear in ‘left’ phase of FRAME 1=DAC data appears in ‘right’ phase of FRAME 1 ADCLRSWAP 0 Controls whether ADC data appears in ‘right’ or ‘left’ phases of FRAME clock: Digital Audio Interfaces 0=ADC data appear in ‘left’ phase of FRAME 1=ADC data appears in ‘right’ phase of FRAME 0 Rev 4.7 0 Reserved 67 WM8974 REGISTER ADDRESS 5 (05h) BIT LABEL 8:5 4:3 DAC_COMP DEFAULT DESCRIPTION 0000 Reserved 00 DAC companding 00=off REFER TO Digital Audio Interfaces 01=reserved 10=µ-law 11=A-law 2:1 ADC_COMP 00 ADC companding 00=off Digital Audio Interfaces 01=reserved 10=µ-law 11=A-law 0 LOOPBACK 0 Digital loopback function 0=No loopback Digital Audio Interfaces 1=Loopback enabled, ADC data output is fed directly into DAC data input. 6 (06h) 8 CLKSEL 1 7:5 MCLKDIV 010 Controls the source of the clock for all internal operation: Digital Audio Interfaces 0=MCLK 1=PLL output Sets the scaling for either the MCLK or PLL clock output Digital Audio (under control of CLKSEL) Interfaces 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 4:2 BCLKDIV 000 Configures the BCLK and FRAME output frequency, for use when the chip is master over BCLK. Digital Audio Interfaces 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved 1 0 MS 0 Reserved 0 Sets the chip to be master over FRAME and BCLK 0=BCLK and FRAME clock are inputs Digital Audio Interfaces 1=BCLK and FRAME clock are outputs generated by the WM8974 (MASTER) 7 (07h) 8:4 3:1 SR 00000 Reserved 000 Approximate sample rate (configures the coefficients for Audio Sample the internal digital filters): Rates 000=48kHz 001=32kHz 010=24kHz 011=16kHz 100=12kHz 101=8kHz 110-111=reserved 68 Rev 4.7 WM8974 REGISTER ADDRESS BIT LABEL 0 8 (08h) 8:6 5:4 OPCLKDIV DEFAULT DESCRIPTION 0 Reserved 000 Reserved 00 PLL Output clock division ratio 00=divide by 1 REFER TO General Purpose Input Output 01=divide by 2 10=divide by 3 11=divide by 4 3 GPIOPOL 0 GPIO Polarity invert 0=Non inverted General Purpose Input Output 1=Inverted 2:0 GPIOSEL 000 CSB/GPIO pin function select: 000=CSB input General Purpose Input Output 001= Jack insert detect 010=Temp ok 011=Automute active 100=PLL clk o/p 101=PLL lock 110=Reserved 111=Reserved 9 (09h) 8:0 10 (0Ah) 8:7 6 Reserved DACMU 00 Reserved 0 DAC soft mute enable 0 = DACMU disabled Output Signal Path 1 = DACMU enabled 5:4 DEEMPH 00 De-Emphasis Control 00 = No de-emphasis Output Signal Path 01 = 32kHz sample rate 10 = 44.1kHz sample rate 11 = 48kHz sample rate 3 DACOSR128 0 DAC oversample rate select 0 = 64x (lowest power) Power Management 1 = 128x (best SNR) 2 AMUTE 0 DAC automute enable 0 = automute disabled Output Signal Path 1 = automute enabled 1 0 DACPOL 0 Reserved 0 DAC Polarity Invert 0 = No inversion Output Signal Path 1 = DAC output inverted 11 (0Bh) 8 7:0 DACVOL 0 Reserved 11111111 DAC Digital Volume Control 0000 0000 = Digital Mute Output Signal Path 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB 12 (0Ch) 8:0 13 (0Dh) 8:0 14 (0Eh) 8 Reserved Reserved HPFEN 1 High-Pass Filter Enable 0=disabled 1=enabled Rev 4.7 Analogue to Digital Converter (ADC) 69 WM8974 REGISTER ADDRESS BIT 7 LABEL HPFAPP DEFAULT 0 DESCRIPTION Select audio mode or application mode 0=Audio mode (1st order, fc = ~3.7Hz) 1=Application mode (2nd order, fc = HPFCUT) 6:4 HPFCUT 000 Application mode cut-off frequency See Table 11 for details. 3 ADCOSR128 0 ADC oversample rate select 0 = 64x (lowest power) REFER TO Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Power Management 1 = 128x (best SNR) 2:1 0 ADCPOL 00 Reserved 0 ADC Polarity 0=normal 1=inverted 15 (0Fh) 8 7:0 ADCVOL 0 Reserved 11111111 ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB 16 (10h) 8:0 Reserved 17 (11h) 8:0 Reserved 18 (12h) 8 EQMODE 1 0 = Equaliser applied to ADC path 1 = Equaliser applied to DAC path 7 6:5 EQ1C 0 Reserved 01 EQ Band 1 Cut-off Frequency: 00=80Hz Output Signal Path Output Signal Path 01=105Hz 10=135Hz 11=175Hz 19 (13h) 4:0 EQ1G 01100 EQ Band 1 Gain Control. See Table 35 for details. Output Signal Path 8 EQ2BW 0 Band 2 Bandwidth Control Output Signal Path 0=narrow bandwidth 1=wide bandwidth 7 6:5 EQ2C 0 Reserved 01 Band 2 Centre Frequency: 00=230Hz Output Signal Path 01=300Hz 10=385Hz 11=500Hz 20 (14h) 4:0 EQ2G 01100 Band 2 Gain Control. See Table 35 for details. Output Signal Path 8 EQ3BW 0 Band 3 Bandwidth Control Output Signal Path 0=narrow bandwidth 1=wide bandwidth 7 6:5 EQ3C 0 Reserved 01 Band 3 Centre Frequency: 00=650Hz Output Signal Path 01=850Hz 10=1.1kHz 11=1.4kHz 70 Rev 4.7 WM8974 REGISTER ADDRESS 21 (15h) BIT LABEL DEFAULT DESCRIPTION REFER TO 4:0 EQ3G 01100 Band 3 Gain Control. See Table 35 for details. Output Signal Path 8 EQ4BW 0 Band 4 Bandwidth Control Output Signal Path 0=narrow bandwidth 1=wide bandwidth 7 6:5 EQ4C 0 Reserved 01 Band 4 Centre Frequency: 00=1.8kHz Output Signal Path 01=2.4kHz 10=3.2kHz 11=4.1kHz 4:0 22 (16h) EQ4G 8:7 6:5 EQ5C 01100 Band 4 Gain Control. See Table 35 for details. 00 Reserved 01 Band 5 Cut-off Frequency: 00=5.3kHz Output Signal Path Output Signal Path 01=6.9kHz 10=9kHz 11=11.7kHz 24 (18h) 4:0 EQ5G 01100 Band 5 Gain Control. See Table 35 for details. Output Signal Path 8 LIMEN 0 Enable the DAC digital limiter: Output Signal Path 0=disabled 1=enabled 7:4 LIMDCY 0011 DAC Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with Output Signal Path sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 1011 to 1111=1.536s 3:0 LIMATK 0010 DAC Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate. Output Signal Path 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms Rev 4.7 71 WM8974 REGISTER ADDRESS 25 (19h) BIT LABEL 8:7 6:4 LIMLVL DEFAULT DESCRIPTION 00 Reserved 000 DAC Limiter Programmable signal threshold level (determines level at which the limiter starts to operate) REFER TO Output Signal Path 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB 3:0 LIMBOOST 0000 DAC Limiter volume boost (can be used as a standalone volume boost when LIMEN=0): Output Signal Path 0000=0dB 0001=+1dB 0010=+2dB … (1dB steps) 1011=+11dB 1100=+12dB 1101 to 1111=reserved 27 (1Bh) 8 NFU 0 Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Analogue to Digital Converter (ADC) 7 NFEN 0 Notch filter enable: Analogue to Digital Converter (ADC) 0=Disabled 1=Enabled 28 (1Ch) 6:0 NFA0[13:7] 0000000 Notch Filter a0 coefficient, bits [13:7] Analogue to Digital Converter (ADC) 8 NFU 0 Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Analogue to Digital Converter (ADC) 7 29 (1Dh) 0 Reserved 6:0 NFA0[6:0] 0000000 Notch Filter a0 coefficient, bits [6:0] Analogue to Digital Converter (ADC) 8 NFU 0 Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Analogue to Digital Converter (ADC) 7 30 (1Eh) 0 Reserved 6:0 NFA1[13:7] 0000000 Notch Filter a1 coefficient, bits [13:7] Analogue to Digital Converter (ADC) 8 NFU 0 Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Analogue to Digital Converter (ADC) 7 32 (20h) 0 Reserved 6:0 NFA1[6:0] 0000000 Notch Filter a1 coefficient, bits [6:0] Analogue to Digital Converter (ADC) 8 ALCSEL 0 ALC function select: Input Limiter / Automatic Level Control (ALC) 0=ALC off (PGA gain set by INPPGAVOL register bits) 1=ALC on (ALC controls PGA gain) 7:6 72 Reserved Rev 4.7 WM8974 REGISTER ADDRESS BIT 5:3 LABEL ALCMAX DEFAULT 111 DESCRIPTION REFER TO Set Maximum Gain of PGA when using ALC: 111=+35.25dB 110=+29.25dB Input Limiter / Automatic Level Control (ALC) 101=+23.25dB 100=+17.25dB 011=+11.25dB 010=+5.25dB 001=-0.75dB 000=-6.75dB 2:0 ALCMIN 000 Set minimum gain of PGA when using ALC: 000=-12dB 001=-6dB Input Limiter / Automatic Level Control (ALC) 010=0dB 011=+6dB 100=+12dB 101=+18dB 110=+24dB 111=+30dB 33 (21h) 8 ALCZC 0 ALC zero cross detection. Input Limiter / Automatic Level Control (ALC) 0 = disabled 1 = enabled 7:4 ALCHLD 000 ALC hold time before gain is increased. Input Limiter / Automatic Level Control (ALC) 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms … (time doubles with every step) 1111 = 43.691s 3:0 ALCLVL 1011 ALC target – sets signal level at ADC input Input Limiter / Automatic Level Control (ALC) 0000 = -28.5dB FS 0001 = -27.0dB FS … (1.5dB steps) 1110 = -7.5dB FS 1111 = -6dB FS 34 (22h) 8 ALCMODE 0 Determines the ALC mode of operation: Input Limiter / Automatic Level Control (ALC) 0=ALC mode 1=Limiter mode. 7:4 ALCDCY 0011 Decay (gain ramp-up) time (ALCMODE =0) Per step Per 6dB 0000 410us 3.3ms Input Limiter / 90% of range Automatic Level Control (ALC) 24ms 0001 820us 6.6ms 48ms 0010 1.64ms 13.1ms 192ms … (time doubles with every step) 1010 or higher 0011 420ms 3.36s 24.576s Decay (gain ramp-up) time (ALCMODE =1) Per step Per 6dB 90% of range 0000 90.8us 726.4us 5.26ms 0001 181.6us 1.453ms 10.53ms 0010 363.2us 2.905ms 21.06ms … (time doubles with every step) 1010 Rev 4.7 93ms 744ms 5.39s 73 WM8974 REGISTER ADDRESS BIT 3:0 LABEL ALCATK DEFAULT 0010 DESCRIPTION REFER TO ALC attack (gain ramp-down) time (ALCMODE = 0) Per step Per 6dB 90% of range 0000 104us 832us 6ms 0001 208us 1.664ms 12ms 0010 416us 3.328ms 24.1ms Input Limiter / Automatic Level Control (ALC) … (time doubles with every step) 1010 or higher 0010 106ms 852ms 6.18s ALC attack (gain ramp-down) time (ALCMODE = 1) Per step Per 6dB 90% of range 0000 22.7us 182.4us 1.31ms 0001 45.4us 363.2us 2.62ms 0010 90.8us 726.4us 5.26ms … (time doubles with every step) 1010 35 (23h) 8:4 3 NGEN 23.2ms 186ms 00000 Reserved 0 ALC Noise gate function enable 1.348s 1 = enable 0 = disable 2:0 NGTH 000 ALC Noise gate threshold: 000=-39dB 001=-45dB Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC) 010=-51db … (6dB steps) 111=-81dB 36 (24h) 8:5 4 0000 PLLPRESCALE 0 Reserved 0 = MCLK input not divided (default) 1 = Divide MCLK by 2 before input PLL 3:0 37 (25h) PLLN[3:0] 8:6 1000 Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. 000 Reserved Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) 5:0 PLLK[23:18] 001100 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 38 (26h) 8:0 PLLK[17:9] 010010011 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 39 (27h) 8:0 PLLK[8:0] 011101001 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 40 (28h) 8:3 000000 Reserved 0 Attenuation control for bypass path (output of input boost stage) to mono mixer input 2 MONOATTN Analogue Outputs 0 = 0dB 1 = -10dB 1 SPKATTN 0 Attenuation control for bypass path (output of input boost stage) to speaker mixer input Analogue Outputs 0 = 0dB 1 = -10dB 0 74 0 Reserved Rev 4.7 WM8974 REGISTER ADDRESS 44 (2Ch) BIT 8 LABEL MBVSEL DEFAULT 0 DESCRIPTION Microphone Bias Voltage Control REFER TO Input Signal Path 0 = 0.9 x AVDD 1 = 0.75 x AVDD 7:4 3 AUXMODE 0000 Reserved 0 Auxiliary Input Mode Input Signal Path 0 = inverting buffer 1 = mixer (on-chip input resistor bypassed) 2 AUX2INPPGA 0 Select AUX amplifier output as input PGA signal source. Input Signal Path 0=AUX not connected to input PGA 1=AUX connected to input PGA amplifier negative terminal. 1 MICN2INPPGA 1 Connect MICN to input PGA negative terminal. Input Signal Path 0=MICN not connected to input PGA 1=MICN connected to input PGA amplifier negative terminal. 0 MICP2INPPGA 1 Connect input PGA amplifier positive terminal to MICP or VMID. Input Signal Path 0 = input PGA amplifier positive terminal connected to VMID 1 = input PGA amplifier positive terminal connected to MICP through variable resistor string 45 (2Dh) 8 7 INPPGAZC 0 Reserved 0 Input PGA zero cross enable: Input Signal Path 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. 6 INPPGAMUTE 0 Mute control for input PGA: Input Signal Path 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). 5:0 INPPGAVOL 010000 Input PGA volume Input Signal Path 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB 47 (2Fh) 8 PGABOOST 0 Input Boost Input Signal Path 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. 7 6:4 0 MICP2BOOSTVOL 000 Reserved Controls the MICP pin to the input boost stage (NB, when using this path set MICP2INPPGA=0): Input Signal Path 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage … 111=+6dB gain through boost stage 3 Rev 4.7 0 Reserved 75 WM8974 REGISTER ADDRESS BIT 2:0 LABEL DEFAULT AUX2BOOSTVOL 000 DESCRIPTION Controls the auxiliary amplifier to the input boost stage: REFER TO Input Signal Path 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage … 111=+6dB gain through boost stage 49 (31h) 8:4 3 MONOBOOST 00000 Reserved 0 Mono output boost stage control (see Table 37 for details) Analogue Outputs 0=No boost (output is inverting buffer) 1=1.5x gain boost 2 SPKBOOST 0 Speaker output boost stage control (see Table 37 for details) Analogue Outputs 0=No boost (outputs are inverting buffers) 1 = 1.5x gain boost 1 TSDEN 1 Thermal Shutdown Enable Output Switch 0 : thermal shutdown disabled 1 : thermal shutdown enabled 0 VROI 0 VREF (AVDD/2 or 1.5xAVDD/2) to analogue output resistance Analogue Outputs 0: approx 1k 1: approx 30 k 50 (32h) 8:6 5 AUX2SPK 000 Reserved 0 Output of auxiliary amplifier to speaker mixer input Analogue Outputs 0 = not selected 1 = selected 4:2 1 BYP2SPK 000 Reserved 0 Bypass path (output of input boost stage) to speaker mixer input Analogue Outputs 0 = not selected 1 = selected 0 DAC2SPK 0 Output of DAC to speaker mixer input Analogue Outputs 0 = not selected 1 = selected 54 (36h) 8 7 SPKZC 0 Speaker Volume control zero cross enable: Analogue Outputs 1 = Change gain on zero cross only 0 = Change gain immediately 6 SPKMUTE 0 Speaker output mute enable Analogue Outputs 0=Speaker output enabled 1=Speaker output muted (VMIDOP) 5:0 SPKVOL 111001 Speaker Volume Adjust Analogue Outputs 111111 = +6dB 111110 = +5dB … (1.0 dB steps) 111001=0dB … 000000=-57dB 56 (38h) 76 8:7 0 Reserved Rev 4.7 WM8974 REGISTER ADDRESS BIT 6 LABEL MONOMUTE DEFAULT 0 DESCRIPTION MONOOUT Mute Control REFER TO Analogue Outputs 0=No mute 1=Output muted. During mute the mono output will output VMID which can be used as a DC reference for a headphone out. 5:3 2 AUX2MONO 0 Reserved 0 Output of Auxiliary amplifier to mono mixer input: Analogue Outputs 0 = not selected 1 = selected 1 BYP2MONO 0 Bypass path (output of input boost stage) to mono mixer Analogue Outputs input 0 = non selected 1 = selected 0 DAC2MONO 0 Output of DAC to mono mixer input Analogue Outputs 0 = not selected 1 = selected Rev 4.7 77 WM8974 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Filter Passband +/- 0.025dB 0 -6dB 0.454fs 0.5fs Passband Ripple +/- 0.025 Stopband Stopband Attenuation dB 0.546fs f > 0.546fs -60 Group Delay dB 21/fs ADC High-Pass Filter High-Pass Filter Corner Frequency -3dB 3.7 -0.5dB 10.4 -0.1dB 21.6 Hz DAC Filter Passband +/- 0.035dB 0 -6dB 0.454fs 0.5fs Passband Ripple +/-0.035 Stopband Stopband Attenuation dB 0.546fs f > 0.546fs -80 Group Delay dB 29/fs Table 63 Digital Filter Characteristics TERMINOLOGY 1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple – any variation of the frequency response in the pass-band region 3. Note that this delay applies only to the filters and does not include additional delays through other digital circuits. See Table 64 for the total delay. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Path Group Delay Total Delay (ADC analogue input to digital audio interface output) EQ disabled 26/fs 28/fs 30/fs EQ enabled 27/fs 29/fs 31/fs EQ disabled 34/fs 36/fs 38/fs EQ enabled 35/fs 37/fs 39/fs DAC Path Group Delay Total Delay (Audio interface input to DAC analogue output) Table 64 Total Group Delay Notes: 1. 78 Wind noise filter is disabled. Rev 4.7 WM8974 DAC FILTER RESPONSES 0.2 0 0.15 0.1 Response (dB) Response (dB) -20 -40 -60 -80 0.05 0 -0.05 -0.1 -100 -0.15 -120 -0.2 0 0.5 1 1.5 2 2.5 3 0 0.1 Frequency (Fs) 0.2 0.3 0.4 0.5 Frequency (Fs) Figure 37 DAC Digital Filter Ripple Figure 36 DAC Digital Filter Frequency Response ADC FILTER RESPONSES 0.2 0 0.15 0.1 Response (dB) Response (dB) -20 -40 -60 -80 0.05 0 -0.05 -0.1 -100 -0.15 -0.2 -120 0 0.5 1 1.5 2 Frequency (Fs) Figure 38 ADC Digital Filter Frequency Response Rev 4.7 2.5 3 0 0.1 0.2 0.3 0.4 0.5 Frequency (Fs) Figure 39 ADC Digital Filter Ripple 79 WM8974 DE-EMPHASIS FILTER RESPONSES 0 0.30 -1 0.25 -2 0.20 Response (dB) Response (dB) -3 -4 -5 -6 -7 0.15 0.10 0.05 0.00 -8 -0.05 -9 -0.10 -10 -0.15 0 2000 4000 6000 8000 10000 12000 14000 16000 0 2000 4000 Frequency (Hz) 6000 8000 10000 12000 14000 16000 Frequency (Hz) Figure 40 De-emphasis Frequency Response (32kHz) Figure 41 De-emphasis Error (32kHz) 0.10 0 -1 0.05 -2 Response (dB) Response (dB) -3 -4 -5 -6 -7 -8 0.00 -0.05 -0.10 -0.15 -9 -0.20 -10 0 5000 10000 15000 0 20000 5000 Frequency (Hz) 15000 20000 Figure 43 De-emphasis Error (44.1kHz) 0 0.10 -1 0.08 -2 0.06 -3 0.04 Response (dB) Response (dB) Figure 42 De-emphasis Frequency Response (44.1kHz) -4 -5 -6 -7 0.02 0.00 -0.02 -0.04 -8 -0.06 -9 -0.08 -10 -0.10 0 5000 10000 15000 20000 Frequency (Hz) Figure 44 De-emphasis Frequency Response (48kHz) 80 10000 Frequency (Hz) 0 5000 10000 15000 20000 Frequency (Hz) Figure 45 De-emphasis Error (48kHz) Rev 4.7 WM8974 HIGH-PASS FILTER The WM8974 has a selectable digital high-pass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1st order IIR with a cut-off of around 3.7Hz. In applications mode the filter is a 2nd order high-pass filter with a selectable cut-off frequency. 5 10 0 0 -5 -10 -15 Response (dB) Response (dB) -10 -20 -25 -30 -35 -20 -30 -40 -40 0 5 10 15 20 25 30 35 40 45 -50 Frequency (Hz) -60 0 200 400 600 800 1000 1200 Frequency (Hz) Figure 46 ADC High-pass Filter Response, HPFAPP=0 Figure 47 ADC High-pass Filter Responses (48kHz), HPFAPP=1, all cut-off settings shown. 10 10 0 0 -10 -10 Response (dB) -20 Response (dB) -20 -30 -40 -30 -40 -50 -60 -50 -70 -60 -80 -70 -90 0 -80 200 400 600 800 1000 1200 Frequency (Hz) 0 200 400 600 800 1000 1200 Frequency (Hz) Figure 48 ADC High-pass Filter Responses (24kHz), Figure 49 ADC High-pass Filter Responses (12kHz), HPFAPP=1, all cut-off settings shown. HPFAPP=1, all cut-off settings shown. Rev 4.7 81 WM8974 5-BAND EQUALISER 15 15 10 10 5 5 Magnitude (dB) Magnitude (dB) The WM8974 has a 5-band equaliser which can be applied to either the ADC path or the DAC path. The plots from Figure 50 to Figure 63 show the frequency responses of each filter with a sampling frequency of 48kHz, firstly showing the different cut-off/centre frequencies with a gain of 12dB, and secondly a sweep of the gain from -12dB to +12dB for the lowest cut-off/centre frequency of each filter. 0 -5 -5 -10 -10 -15 -1 10 0 10 1 10 2 10 Frequency (Hz) 3 10 4 10 -15 -1 10 5 10 Figure 50 EQ Band 1 – Low Frequency Shelf Filter Cut-offs 15 15 10 10 5 5 0 -5 -10 -10 0 10 1 10 2 10 Frequency (Hz) 3 10 4 10 5 10 1 10 2 10 Frequency (Hz) 3 10 4 10 5 10 0 -5 -15 -1 10 0 10 Figure 51 EQ Band 1 – Gains for Lowest Cut-off Frequency Magnitude (dB) Magnitude (dB) 0 -15 -1 10 0 10 1 10 2 10 Frequency (Hz) 3 10 4 10 5 10 Figure 52 EQ Band 2 – Peak Filter Centre Frequencies, Figure 53 EQ Band 2 – Peak Filter Gains for Lowest Cut-off EQ2BW=0 Frequency, EQ2BW=0 15 10 Magnitude (dB) 5 0 -5 -10 -15 -2 10 -1 10 0 10 1 10 Frequency (Hz) 2 10 3 10 4 10 Figure 54 EQ Band 2 – EQ2BW=0, EQ2BW=1 82 Rev 4.7 15 15 10 10 5 5 Magnitude (dB) Magnitude (dB) WM8974 0 0 -5 -5 -10 -10 -15 -1 10 Figure 55 0 10 1 10 2 10 Frequency (Hz) 3 10 4 10 5 10 EQ Band 3 – Peak Filter Centre Frequencies, EQ3BW=0 -15 -1 10 0 10 1 10 2 10 Frequency (Hz) 3 10 4 10 5 10 Figure 56 EQ Band 3 – Peak Filter Gains for Lowest Cut-off Frequency, EQ3BW=0 15 10 Magnitude (dB) 5 0 -5 -10 -15 -2 10 Figure 57 Rev 4.7 -1 10 0 10 1 10 Frequency (Hz) 2 10 3 10 4 10 EQ Band 3 – EQ3BW=0, EQ3BW=1 83 15 15 10 10 5 5 Magnitude (dB) Magnitude (dB) WM8974 0 0 -5 -5 -10 -10 -15 -1 10 Figure 58 0 10 1 10 2 10 Frequency (Hz) 3 10 4 10 -15 -1 10 5 10 EQ Band 4 – Peak Filter Centre Frequencies, EQ3BW=0 Figure 59 0 10 1 10 2 10 Frequency (Hz) 3 10 4 10 5 10 EQ Band 4 – Peak Filter Gains for Lowest Cut-off Frequency, EQ4BW=0 15 10 Magnitude (dB) 5 0 -5 -10 -15 -2 10 1 10 Frequency (Hz) 2 10 3 10 4 10 EQ Band 4 – EQ3BW=0, EQ3BW=1 15 15 10 10 5 5 0 0 -5 -5 -10 -10 -15 -1 10 Figure 61 84 0 10 Magnitude (dB) Magnitude (dB) Figure 60 -1 10 0 10 1 10 2 10 Frequency (Hz) 3 10 4 10 5 10 -15 -1 10 EQ Band 5 – High Frequency Shelf Filter Cut-offs Figure 62 0 10 1 10 2 10 Frequency (Hz) 3 10 4 10 5 10 EQ Band 5 – Gains for Lowest Cut-off Frequency Rev 4.7 WM8974 Figure 63 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with 12dB gain. The red traces show the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EQxBW=0 for the peak filters. 20 15 Magnitude (dB) 10 5 0 -5 -10 -15 -1 10 Figure 63 Rev 4.7 0 10 1 10 2 10 Frequency (Hz) 3 10 4 10 5 10 Cumulative Frequency Boost/Cut 85 WM8974 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 64 86 Recommended External Components Rev 4.7 WM8974 PACKAGE DIAGRAM FL: 24 PIN QFN PLASTIC PACKAGE 4 X 4 X 0.9 mm BODY, 0.50 mm LEAD PITCH DETAIL 1 D2 19 DM102.C D 24 1 18 EXPOSED GROUND 6 PADDLE INDEX AREA (D/2 X E/2) 4 E2 E SEE DETAIL 2 13 6 2X 12 b7 e 1 bbb M C A B 2X aaa C aaa C TOP VIEW BOTTOM VIEW ccc C DETAIL 1 DETAIL 2 A 0.08 C 45° A1 SIDE VIEW C SEATING PLANE M DETAIL 3 M L 5 Datum 1 A3 0.30mm EXPOSED GROUND PADDLE Terminal Tip e/2 e W Exposed lead T A3 G H Half etch tie bar b DETAIL 3 Symbols A A1 A3 b D D2 E E2 e G H L T W MIN 0.80 0 0.20 2.40 2.40 0.35 Dimensions (mm) NOM MAX NOTE 0.85 0.90 0.035 0.05 0.203 REF 1 0.25 0.30 4.00 BSC 2.50 4.00 BSC 2.50 0.50 BSC 0.20 0.10 0.40 0.103 0.15 2.60 2 2.60 2 0.45 Tolerances of Form and Position aaa bbb ccc REF: 0.10 0.10 0.10 JEDEC, MO-220, VARIATION VGGD-8. NOTES: 1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC, MO-220, VARIATION VGGD-8. 3. ALL DIMENSIONS ARE IN MILLIMETRES. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002. 5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. 7. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. Rev 4.7 87 WM8974 IMPORTANT NOTICE Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. For the purposes of our terms and conditions of sale, "Preliminary" or "Advanced" datasheets are non-final datasheets that include but are not limited to datasheets marked as “Target”, “Advance”, “Product Preview”, “Preliminary Technical Data” and/or “Pre-production.” Products provided with any such datasheet are therefore subject to relevant terms and conditions associated with "Preliminary" or "Advanced" designations. The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic group (collectively either “Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. Cirrus Logic is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Cirrus Logic products. Use of Cirrus Logic products may entail a choice between many different modes of operation, some or all of which may require action by the user, and some or all of which may be optional. Nothing in these materials should be interpreted as instructions or suggestions to choose one mode over another. Likewise, description of a single mode should not be interpreted as a suggestion that other modes should not be used or that they would not be suitable for operation. Features and operations described herein are for illustrative purposes only. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS LOGIC PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS LOGIC PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS LOGIC DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS LOGIC PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS LOGIC PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS LOGIC, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. This document is the property of Cirrus Logic and by furnishing this information, Cirrus Logic grants no license, express or implied, under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Any provision or publication of any third party’s products or services does not constitute Cirrus Logic’s approval, license, warranty or endorsement thereof. Cirrus Logic gives consent for copies to be made of the information contained herein only for use within your organization with respect to Cirrus Logic integrated circuits or other products of Cirrus Logic, and only if the reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices and conditions (including this notice). This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. This document and its information is provided “AS IS” without warranty of any kind (express or implied). All statutory warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus Logic for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design, and SoundClear are among the trademarks of Cirrus Logic. Other brand and product names may be trademarks or service marks of their respective owners. Copyright © 2004–2016 Cirrus Logic, Inc. All rights reserved. 88 Rev 4.7 WM8974 REVISION HISTORY DATE REV ORIGINATOR CHANGES 26/09/11 4.6 JMacD Order codes changed from WM8974GEFL/V and WM8974GEFL/RV to WM8974CGEFL/V and WM8974CGEFL/RV to reflect change to copper wire bonding. 26/09/11 4.6 JMacD Package diagram updated to DM102.C 12/08/16 4.7 PH Rev 4.7 MICBIAS voltage (MBVSEL=1) updated to 0.75 x AVDD. 89