WM8978CGEFL/RV

w WM8978 Stereo CODEC with Speaker Driver DESCRIPTION FEATURES The WM8978 is a low power, high quality stereo CODEC designed for portable applications such as multimedia phone, digital still camera or digital camcorder. Stereo CODEC:  DAC SNR 98dB, THD -84dB (‘A’ weighted @ 48kHz)  ADC SNR 95dB, THD -84dB (‘A’ weighted @ 48kHz)  On-chip Headphone Driver with ‘capless’ option 40mW per channel into 16 / 3.3V SPKVDD  1W output power into 8 BTL speaker / 5V SPKVDD Capable of driving piezo speakers Stereo speaker drive configuration Mic Preamps:  Stereo Differential or mono microphone Interfaces Programmable preamp gain Psuedo differential inputs with common mode rejection Programmable ALC / Noise Gate in ADC path  Low-noise bias supplied for electret microphones Other Features:  Enhanced 3-D function for improved stereo separation  Digital playback limiter  5-band Equaliser (record or playback)  Programmable ADC High Pass Filter (wind noise reduction)  Programmable ADC Notch Filter  Aux inputs for stereo analogue input signals or ‘beep’  On-chip PLL supporting 12, 13, 19.2MHz and other clocks  Support for 8, 11.025, 12, 16, 22.05, 24, 32, 44.1 and 48kHz sample rates  Low power, low voltage 2.5V to 3.6V (digital: 1.71V to 3.6V)  5x5mm 32-lead QFN package The device integrates preamps for stereo differential mics, and includes drivers for speakers, headphone and differential or stereo line output. External component requirements are reduced as no separate microphone or headphone amplifiers are required. Advanced on-chip digital signal processing includes a 5-band equaliser, a mixed signal Automatic Level Control for the microphone or line input through the ADC as well as a purely digital limiter function for record or playback. Additional digital filtering options are available in the ADC path, to cater for application filtering such as ‘wind noise reduction’. The WM8978 digital audio interface can operate as a master or a slave. An internal PLL can generate all required audio clocks for the CODEC from common reference clock frequencies, such as 12MHz and 13MHz. The WM8978 operates at analogue supply voltages from 2.5V to 3.3V, although the digital core can operate at voltages down to 1.71V to save power. The speaker outputs and OUT3/4 line outputs can run from a 5V supply if increased output power is required. Individual sections of the chip can also be powered down under software control. APPLICATIONS BLOCK DIAGRAM   WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Stereo Camcorder or DSC Multimedia Phone Production Data, October 2011, Rev 4.5 Copyright 2011 Wolfson Microelectronics plc WM8978 Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1  BLOCK DIAGRAM ................................................................................................ 1  FEATURES ............................................................................................................ 1  APPLICATIONS..................................................................................................... 1  TABLE OF CONTENTS ......................................................................................... 2  PIN CONFIGURATION .......................................................................................... 4  ORDERING INFORMATION .................................................................................. 4  PIN DESCRIPTION ................................................................................................ 5  ABSOLUTE MAXIMUM RATINGS ........................................................................ 6  RECOMMENDED OPERATING CONDITIONS ..................................................... 6  ELECTRICAL CHARACTERISTICS ..................................................................... 7  TERMINOLOGY ............................................................................................................ 10  SPEAKER OUTPUT THD VERSUS POWER ...................................................... 11  POWER CONSUMPTION .................................................................................... 12  AUDIO PATHS OVERVIEW ................................................................................ 14  SIGNAL TIMING REQUIREMENTS .................................................................... 15  SYSTEM CLOCK TIMING ............................................................................................. 15  AUDIO INTERFACE TIMING – MASTER MODE .......................................................... 15  AUDIO INTERFACE TIMING – SLAVE MODE ............................................................. 16  CONTROL INTERFACE TIMING – 3-WIRE MODE ...................................................... 17  CONTROL INTERFACE TIMING – 2-WIRE MODE ...................................................... 18  INTERNAL POWER ON RESET CIRCUIT .......................................................... 19  DEVICE DESCRIPTION ...................................................................................... 21  INTRODUCTION ........................................................................................................... 21  INPUT SIGNAL PATH ................................................................................................... 23  ANALOGUE TO DIGITAL CONVERTER (ADC) ........................................................... 30  INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)............................................ 36  OUTPUT SIGNAL PATH ............................................................................................... 47  3D STEREO ENHANCEMENT ...................................................................................... 54  ANALOGUE OUTPUTS ................................................................................................. 54  DIGITAL AUDIO INTERFACES ..................................................................................... 70  AUDIO SAMPLE RATES ............................................................................................... 75  MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ................................................ 75  LOOPBACK ................................................................................................................... 77  COMPANDING .............................................................................................................. 77  GENERAL PURPOSE INPUT/OUTPUT........................................................................ 79  OUTPUT SWITCHING (JACK DETECT)....................................................................... 80  CONTROL INTERFACE ................................................................................................ 82  RESETTING THE CHIP ................................................................................................ 83  POWER SUPPLIES....................................................................................................... 83  RECOMMENDED POWER UP/DOWN SEQUENCE .................................................... 83  POWER MANAGEMENT .............................................................................................. 88  REGISTER MAP .................................................................................................. 89  REGISTER BITS BY ADDRESS ................................................................................... 91  DIGITAL FILTER CHARACTERISTICS ............................................................ 108  TERMINOLOGY .......................................................................................................... 108  DAC FILTER RESPONSES ........................................................................................ 109  ADC FILTER RESPONSES ........................................................................................ 109  HIGHPASS FILTER ..................................................................................................... 110  w PD, Rev 4.5, October 2011 2 Production Data WM8978 5-BAND EQUALISER .................................................................................................. 111  APPLICATION INFORMATION ......................................................................... 115  RECOMMENDED EXTERNAL COMPONENTS ......................................................... 115  PACKAGE DIAGRAM ....................................................................................... 116  IMPORTANT NOTICE ....................................................................................... 117  ADDRESS ................................................................................................................... 117  REVISION HISTORY ......................................................................................... 118  w PD, Rev 4.5, October 2011 3 WM8978 Production Data PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8978CGEFL/V -40C to +100C 32-lead QFN (5 x 5 mm) (Pb-free) MSL3 260 C WM8978CGEFL/RV -40C to +100C 32-lead QFN (5 x 5 mm) (Pb-free, tape and reel) MSL3 260 C o o Note: Reel quantity = 3,500 w PD, Rev 4.5, October 2011 4 WM8978 Production Data PIN DESCRIPTION PIN NAME TYPE 1 LIP Analogue input Left Mic Pre-amp positive input DESCRIPTION 2 LIN Analogue input Left Mic Pre-amp negative input 3 L2/GPIO2 Analogue input Left channel line input/secondary mic pre-amp positive input/GPIO2 pin 4 RIP Analogue input Right Mic Pre-amp positive input 5 RIN Analogue input Right Mic Pre-amp negative input 6 R2/GPIO3 Analogue input Right channel line input/secondary mic pre-amp positive input/GPIO3 pin 7 LRC Digital Input / Output 8 BCLK Digital Input / Output 9 ADCDAT Digital Output 10 DACDAT Digital Input 11 MCLK Digital Input 12 DGND Supply 13 DCVDD Supply Digital core logic supply 14 DBVDD Supply Digital buffer (I/O) supply 15 CSB/GPIO1 Digital Input / Output 16 SCLK Digital Input 17 SDIN Digital Input / Output 18 MODE Digital Input 19 AUXL Analogue input Left Auxillary input 20 AUXR Analogue input Right Auxillary input 21 OUT4 Analogue Output Buffered midrail Headphone pseudo-ground, or Right line output or MONO mix output 22 OUT3 Analogue Output Buffered midrail Headphone pseudo-ground, or Left line output 23 ROUT2 Analogue Output Second right output, or BTL speaker driver positive output 24 SPKGND Supply 25 LOUT2 Analogue Output 26 SPKVDD Supply 27 VMID Reference DAC and ADC Sample Rate Clock Digital Audio Port Clock ADC Digital Audio Data Output DAC Digital Audio Data Input Master Clock Input Digital ground 3-Wire Control Interface Chip Select / GPIO1 pin 3-Wire Control Interface Clock Input / 2-Wire Control Interface Clock Input 3-Wire Control Interface Data Input / 2-Wire Control Interface Data Input Control Interface Selection Speaker ground (feeds speaker amp and OUT3/OUT4) Second left output, or BTL speaker driver negative output Speaker supply (feed speaker amp only) Decoupling for ADC and DAC reference voltage 28 AGND Supply 29 ROUT1 Analogue Output Headphone or Line Output Right 30 LOUT1 Analogue Output Headphone or Line Output Left 31 AVDD Supply 32 MICBIAS Analogue Output Analogue ground (feeds ADC and DAC) Analogue supply (feeds ADC and DAC) Microphone Bias Note: It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB. Refer to the application note WAN_0118 on “Guidelines on How to Use QFN Packages and Create Associated PCB Footprints”. w PD, Rev 4.5, October 2011 5 WM8978 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at