WM8988
Stereo CODEC for Portable Audio Applications
DESCRIPTION
FEATURES
The WM8988 is a low power, high quality stereo CODEC
designed for portable digital audio applications.
The device integrates complete interfaces to 2 stereo
headphone or line out ports. External component
requirements are drastically reduced as no separate
headphone amplifiers are required. Advanced on-chip digital
signal processing performs graphic equaliser, 3-D sound
enhancement and automatic level control for the
microphone or line input.
The WM8988 can operate as a master or a slave, with
various master clock frequencies including 12 or 24MHz for
USB devices, or standard 256fs rates like 12.288MHz and
24.576MHz. Different audio sample rates such as 96kHz,
48kHz, 44.1kHz are generated directly from the master
clock without the need for an external PLL.
The WM8988 operates at supply voltages down to 1.8V,
although the digital core can operate at voltages down to
1.42V to save power, and the maximum for all supplies is
3.6 Volts. Different sections of the chip can also be powered
down under software control.
The WM8988 is supplied in a very small and thin 4x4mm
COL package, ideal for use in hand-held and portable
systems.
DAC SNR 100dB (‘A’ weighted), THD –90dB at 48kHz, 3.3V
ADC SNR 93dB (‘A’ weighted), THD -81dB at 48kHz, 3.3V
Programmable ALC / Noise Gate
2x On-chip Headphone Drivers
- >40mW output power on 16 / 3.3V
- THD –80dB at 20mW, SNR 90dB with 16 load
Digital Graphic Equaliser
Low Power
- 7mW stereo playback (1.8V / 1.5V supplies)
- 14mW record and playback (1.8V / 1.5V supplies)
Low Supply Voltages
- Analogue 1.8V to 3.6V
- Digital core: 1.42V to 3.6V
- Digital I/O: 1.8V to 3.6V
256fs / 384fs or USB master clock rates: 12MHz, 24MHz
Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48,
88.2, 96kHz generated internally from master clock
4x4mm COL package
APPLICATIONS
Portable Multimedia players
Multimedia handsets
Handheld gaming
BLOCK DIAGRAM
DGND
M
U
X
M
U
X
WM8988
PGA
+ MIC
BOOST
M
U
X
LEFT
LD2LO MIXER
VOLUME
DIGITAL
MONO MIX
LOUT1
(headphone / line output
LOUT1VOL
DIGITAL
FILTERS
GRAPHIC
EQUALISER
HPCOM
BASS
BOOST
ADC
PGA
+ MIC
BOOST
RIGHT
LD2RO MIXER
DAC
LI2RO
ROUT1
RD2RO
DC MEASUREMENT
M
U
X
HPVDD
LI2LO
RI2LO
DAC
DIGITAL
FILTERS
ANALOGUE
MONO MIX
RINSEL
RINPUT2
RINPUT1
HPGND
RD2LO
ADC
LINSEL
DIFF.
INPUT
L1-R1 OR
L2-R2
DBVDD
LMIXSEL
DC MEASUREMENT
LINPUT1
LINPUT2
DCVDD
RI2RO
ROUT1VOL
(headphone / line output
LOUT2VOL
LOUT2
(headphone / line output
RMIXSEL
LCOM
50K
AUDIO
INTERFACE
50K
CLOCK
CIRCUITRY
CONTROL
INTERFACE
http://www.cirrus.com
ROUT2
(headphone / line output
MODE
SCLK
SDIN
CSB
MCLK
BCLK
ADCDAT
LRC
DACDAT
VREF
VMID
AVDD
AGND
ROUT2VOL
Copyright Cirrus Logic, Inc., 2008–2016
(All Rights Reserved)
Rev 4.2
DEC ‘16
WM8988
TABLE OF CONTENTS
DESCRIPTION ................................................................................................................ 1
FEATURES ..................................................................................................................... 1
APPLICATIONS.............................................................................................................. 1
BLOCK DIAGRAM ......................................................................................................... 1
TABLE OF CONTENTS .................................................................................................. 2
PIN CONFIGURATION ................................................................................................... 3
ORDERING INFORMATION ........................................................................................... 3
PIN DESCRIPTION ......................................................................................................... 4
ABSOLUTE MAXIMUM RATINGS ................................................................................. 5
RECOMMENDED OPERATING CONDITIONS .............................................................. 5
ELECTRICAL CHARACTERISTICS .............................................................................. 6
POWER CONSUMPTION ............................................................................................. 10
SIGNAL TIMING REQUIREMENTS ............................................................................. 11
SYSTEM CLOCK TIMING ........................................................................................................ 11
AUDIO INTERFACE TIMING – MASTER MODE .................................................................... 12
AUDIO INTERFACE TIMING – SLAVE MODE ........................................................................ 13
CONTROL INTERFACE TIMING – 3-WIRE MODE ................................................................. 14
CONTROL INTERFACE TIMING – 2-WIRE MODE ................................................................. 15
INTERNAL POWER ON RESET CIRCUIT ................................................................... 16
DEVICE DESCRIPTION ............................................................................................... 17
INTRODUCTION ...................................................................................................................... 17
INPUT SIGNAL PATH .............................................................................................................. 17
AUTOMATIC LEVEL CONTROL (ALC) ................................................................................... 23
OUTPUT SIGNAL PATH .......................................................................................................... 27
ANALOGUE OUTPUTS ........................................................................................................... 32
ENABLING THE OUTPUTS ..................................................................................................... 34
THERMAL SHUTDOWN .......................................................................................................... 34
DIGITAL AUDIO INTERFACE .................................................................................................. 35
AUDIO INTERFACE CONTROL .............................................................................................. 38
CLOCKING AND SAMPLE RATES.......................................................................................... 40
CONTROL INTERFACE........................................................................................................... 42
POWER SUPPLIES ................................................................................................................. 44
POWER MANAGEMENT ......................................................................................................... 44
REGISTER MAP ........................................................................................................... 47
DIGITAL FILTER CHARACTERISTICS ....................................................................... 48
TERMINOLOGY ....................................................................................................................... 48
DAC FILTER RESPONSES ..................................................................................................... 49
ADC FILTER RESPONSES ..................................................................................................... 50
DE-EMPHASIS FILTER RESPONSES .................................................................................... 51
HIGHPASS FILTER ................................................................................................................. 52
APPLICATIONS INFORMATION ................................................................................. 53
RECOMMENDED EXTERNAL COMPONENTS ...................................................................... 53
LINE INPUT CONFIGURATION............................................................................................... 54
HEADPHONE OUTPUT CONFIGURATION ............................................................................ 54
LINE OUTPUT CONFIGURATION........................................................................................... 54
MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS.................................................... 55
POWER MANAGEMENT EXAMPLES ..................................................................................... 55
2
Rev 4.2
WM8988
PACKAGE DIMENSIONS ............................................................................................. 56
IMPORTANT NOTICE .................................................................................................. 57
REVISION HISTORY .................................................................................................... 58
LINPUT1
RINPUT1
LINPUT2
27
CSB
SDIN
28
MODE
SCLK
PIN CONFIGURATION
26
25
24
23
22
MCLK
1
21
RINPUT2
DCVDD
2
20
VMID
DBVDD
3
19
VREF
18
AGND
WM8988 –
Top View
7
LOUT2
LRC
8
9
10
11
12
13
14
ROUT2
HPVDD
15
LOUT1
6
DACDAT
HPGND
AVDD
16
ROUT1
17
LCOM
5
HPCOM
4
BCLK
ADCDAT
DGND
ORDERING INFORMATION
ORDER CODE
WM8988LGECN/V
TEMPERATURE
RANGE
-25°C to +85°C
PACKAGE
MOISTURE
SENSITIVITY LEVEL
PEAK SOLDERING
TEMPERATURE
28-lead COL QFN
MSL3
260°C
MSL3
260°C
(4x4x0.55mm, lead-free)
WM8988LGECN/RV
-25°C to +85°C
28-lead COL QFN
(4x4x0.55mm, lead-free)
Tape and reel
Note:
Reel quantity = 3,500
Rev 4.2
3
WM8988
PIN DESCRIPTION
PIN NO
4
NAME
TYPE
DESCRIPTION
1
MCLK
Digital Input
Master Clock
2
DCVDD
Supply
Digital Core Supply
3
DBVDD
Supply
Digital Buffer (I/O) Supply
4
DGND
Supply
Digital Ground (return path for both DCVDD and DBVDD)
5
BCLK
Digital Input / Output
Audio Interface Bit Clock
6
DACDAT
Digital Input
DAC Digital Audio Data
7
LRC
Digital Input / Output
Audio Interface Left / Right Clock
8
ADCDAT
Digital Output
ADC Digital Audio Data
9
HPCOM
Analogue Input
LOUT1 and ROUT1 common mode feedback
10
LCOM
Analogue Input
LOUT2 and ROUT2 common mode feedback
11
ROUT1
Analogue Output
Right Output 1 (Line or Headphone)
12
LOUT1
Analogue Output
Left Output 1 (Line or Headphone)
13
HPGND
Supply
Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2)
14
ROUT2
Analogue Output
Right Output 1 (Line or Headphone )
15
LOUT2
Analogue Output
Left Output 1 (Line or Headphone)
16
HPVDD
Supply
Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2, MONOUT)
17
AVDD
Supply
Analogue Supply
18
AGND
Supply
Analogue Ground (return path for AVDD)
19
VREF
Analogue Output
Reference Voltage Decoupling Capacitor
20
VMID
Analogue Output
Midrail Voltage Decoupling Capacitor
21
RINPUT2
Analogue Input
Right Channel Input 2
22
LINPUT2
Analogue Input
Left Channel Input 2
23
RINPUT1
Analogue Input
Right Channel Input 1
24
LINPUT1
Analogue Input
Left Channel Input 1
25
MODE
Digital Input
Control Interface Selection
26
CSB
Digital Input
Chip Select / Device Address Selection
27
28
SDIN
SCLK
Digital Input/Output
Digital Input
Control Interface Data Input / 2-wire Acknowledge output
Control Interface Clock Input
Rev 4.2
WM8988
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or
beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Cirrus Logic tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at 0.584fs
-50
dB
DAC Filter Type 1 (USB mode, 272fs or Normal mode operation)
Passband
+/- 0.03dB
0
-6dB
0.4535fs
0.5fs
Passband Ripple
+/- 0.03
Stopband
dB
0.5465fs
Stopband Attenuation
f > 0.5465fs
-50
dB
Table 43 Digital Filter Characteristics
DAC FILTERS
ADC FILTERS
Mode
Group Delay
Mode
Group Delay
0 (250 USB)
11/fs
0 (250 USB)
13/fs
1 (256/272)
16/fs
1 (256/272)
23/fs
2 (250 USB, 96k mode)
4/fs
2 (250 USB, 96k mode)
4/fs
3 (256/272, 88.2/96k mode)
3/fs
3 (256/272, 88.2/96k mode)
5/fs
Table 44 ADC/DAC Digital Filters Group Delay
TERMINOLOGY
1.
Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band)
2.
Pass-band Ripple – any variation of the frequency response in the pass-band region
48
Rev 4.2
WM8988
DAC FILTER RESPONSES
Figure 21 DAC Digital Filter Frequency Response – Type 0 Figure 22 DAC Digital Filter Ripple – Type 0
Figure 23 DAC Digital Filter Frequency Response – Type 1 Figure 24 DAC Digital Filter Ripple – Type 1
Figure 25 DAC Digital Filter Frequency Response – Type 2 Figure 26 DAC Digital Filter Ripple – Type 2
Rev 4.2
49
WM8988
Figure 27 DAC Digital Filter Frequency Response – Type 3 Figure 28 DAC Digital Filter Ripple – Type 3
ADC FILTER RESPONSES
Figure 29 ADC Digital Filter Frequency Response – Type 0
Figure 30 ADC Digital Filter Ripple – Type 0
Figure 31 ADC Digital Filter Frequency Response – Type 1
Figure 32 ADC Digital Filter Ripple – Type 1
50
Rev 4.2
WM8988
Figure 33 ADC Digital Filter Frequency Response – Type 2
Figure 34 ADC Digital Filter Ripple – Type 2
Figure 35 ADC Digital Filter Frequency Response – Type 2
Figure 36 ADC Digital Filter Ripple – Type 3
DE-EMPHASIS FILTER RESPONSES
Figure 37 De-emphasis Frequency Response (32kHz)
Rev 4.2
Figure 38 De-emphasis Error (32kHz)
51
WM8988
Figure 39 De-emphasis Frequency Response (44.1kHz)
Figure 40 De-emphasis Error (44.1kHz)
Figure 41 De-emphasis Frequency Response (48kHz)
Figure 42 De-emphasis Error (48kHz)
HIGHPASS FILTER
The WM8988 has a selectable digital highpass filter in the ADC filter path to remove DC offsets. The filter response is characterised
by the following polynomial:
H(z) =
1 - z-1
1 - 0.9995z-1
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Figure 43 ADC Highpass Filter Response
52
Rev 4.2
WM8988
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
DVDD
AVDD
DGND
DBVDD
DCVDD
HPGND
AGND
GND
AVDD
HPVDD
C1 C2 0.1uF
0.1uF
GND
GND
C4
C3
4.7uF
220uF
+ C14
LOUT1
4.7uF
+
ROUT1
GND
+
MCLK
HPCOM
16 OR 32 OHM
HEADPHONES
C15
220uF
C20
4.7uF
BCLK
AUDIO
INTERFACE
(I2S/LJ/RJ/DSP)
LRC
DACDAT
ADCDAT
GND
WM8988
+
LOUT2
HIGH for 3-wire
LOW for 2-wire
+
ROUT2
CONTROL
INTERFACE
(2 OR 3-WIRE)
CSB
SDIN
SCLK
Lineout
C23
10uF
+
LCOM
C22
10uF
MODE
C21
4.7uF
C7
1uF
C8
1uF
C9
1uF
C10
1uF
LINPUT1
GND
RINPUT1
LINPUT2
RINPUT2
VREF
+ C19
VMID
+ C17
4.7uF
4.7uF
GND
GND
Layout Notes:
1. C1 to C4, C17, C19, C20 and C21 should be as close to the relative WM8988 connecting pin as possible.
2. For capacitors C7 to C10, C14, C15, C22 and C23 it is recommended that low ESR components are used.
3. HPCOM and LCOM should be connected to GND at the connector.
Figure 44 Recommended External Components Diagram
Rev 4.2
53
WM8988
LINE INPUT CONFIGURATION
When LINPUT1/RINPUT1 or LINPUT2/RINPUT2 are used as line inputs, the microphone boost and
ALC functions should normally be disabled.
In order to avoid clipping, the user must ensure that the input signal does not exceed AVDD. This may
require a potential divider circuit in some applications. It is also recommended to remove RF
interference picked up on any cables using a simple first-order RC filter, as high-frequency
components in the input signal may otherwise cause aliasing distortion in the audio band. AC signals
with no DC bias should be fed to the WM8988 through a DC blocking capacitor, e.g. 1F.
HEADPHONE OUTPUT CONFIGURATION
Analogue outputs LOUT1/ROUT1 and LOUT2/ROUT2, can drive a 16 or 32 headphone load, as
shown in Figure 45.
LOUT1/2
C1 220uF
ROUT1/2
WM8988
HPCOM/
LCOM
C3 4.7uF
C2 220uF
HPGND = 0V
Figure 45 Recommended Headphone Output Configurations
The DC blocking capacitors C1 and C2 and the load resistance together determine the lower cut-off
frequency, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance
values will diminish the bass response. Assuming a 16 Ohm load and C1, C2 = 220F:
fc = 1 / 2 RLC1 = 1 / (2 x 16 x 220F) = 45 Hz
LINE OUTPUT CONFIGURATION
The analogue outputs, LOUT1/ROUT1 and LOUT2/ROUT2, can be used as line outputs.
Recommended external components are shown below.
C1
10uF
LINE-OUT
SOCKET
(LEFT)
LOUT1/2
C3
WM8988
4.7uF
ROUT1/2
C2
10uF
GND
LINE-OUT
SOCKET
(RIGHT)
Figure 46 Recommended Circuit for Line Output
The DC blocking capacitors and the load resistance together determine the lower cut-off frequency, fc.
Assuming a 10 kΩ load and C1, C2 = 1F:
fc = 1 / 2 (RL+R1) C1 = 1 / (2 x 10.1k x 1F) = 16 Hz
Increasing the capacitance lowers fc, improving the bass response. Smaller values of C1 and C2 will
diminish the bass response. The function of R1 and R2 is to protect the line outputs from damage
when used improperly.
54
Rev 4.2
WM8988
MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS
To minimize any pop or click noise when the system is powered up or down, the following procedures
are recommended.
POWER UP
Switch on power supplies. By default the WM8988 is in Standby Mode, the DAC is digitally muted and
the Audio Interface, Line outputs and Headphone outputs are all OFF (DACMU = 1 Power
Management registers 1 and 2 are all zeros).
Enable Vmid and VREF.
Enable DACs as required
Enable line and / or headphone output buffers as required.
Set DACMU = 0 to soft-un-mute the audio DACs.
POWER DOWN
Set DACMU = 1 to soft-mute the audio DACs.
Disable all output buffers.
Switch off the power supplies.
POWER MANAGEMENT EXAMPLES
AINL/R
POWER MANAGEMENT (1)
VREF
OPERATION MODE
PGAs
POWER MANAGEMENT (2)
ADCs
PGL PGR ADL
DACs
Output Buffers
ADR
MBI
DAL
DAR
LO1
RO1
LO2
RO2
Stereo Headphone Playback
1
0
0
0
0
0
0
1
1
1
1
0
0
Stereo Line-in Record
1
1
1
1
1
1
0
0
0
0
0
0
0
Stereo Microphone Record
1
1
1
1
1
1
1
0
0
0
0
0
0
Mono Microphone Record
1
1
1
0
1
0
1
0
0
0
0
0
0
Stereo Line-in to Headphone Out
1
1
0
0
0
0
0
0
0
1
1
0
0
Table 45 Register Settings for Power Management
Rev 4.2
55
WM8988
PACKAGE DIMENSIONS
DM050.D
FL: 28 PIN COL QFN PLASTIC PACKAGE 4 X 4 X 0.55 mm BODY, 0.45 mm LEAD PITCH
DETAIL 1
D
28
22
21
1
INDEX AREA
(D/2 X E/2)
4
A
E
SEE DETAIL 2
15
7
2X
8
14
1
bbb M C A B
b
e
2X
aaa C
aaa C
TOP VIEW
BOTTOM VIEW
DETAIL 1
DETAIL 2
A
0.08 C
A1
SIDE VIEW
C
5
PIN 1
IDENTIFICATION
0.150MM SQUARE
L
Datum
L1
0.275MM
DETAIL 2
SEATING PLANE
0.275MM
1
ccc C
A3
Terminal
Tip
e/2
e
R
W
T
A3
H
G
b
Exposed lead
DETAIL 2
Symbols
A
A1
A3
b
D
E
e
G
H
L
L1
T
W
MIN
0.500
0
0.180
3.950
3.950
Dimensions (mm)
NOM
MAX
0.550
0.600
0.035
0.050
0.152 REF
0.230
4.000
4.000
0.450 BSC
0.200 REF
0.075 REF
0.400 REF
0.000 REF
0.077 REF
0.150 REF
0.280
4.050
4.050
NOTE
1
5
Tolerances of Form and Position
aaa
bbb
ccc
REF:
0.100
0.100
0.100
JEDEC, MO-220
NOTES:
1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP.
2. ALL DIMENSIONS ARE IN MILLIMETRES.
3. COPLANARITY APPLIES TO THE TERMINALS.
4. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.
5. DEPENDING ON THE METHOD OF LEAD TERMINATION AT THE EDGE OF THE PACKAGE, PULL BACK (L1) MAY BE PRESENT.
6. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
56
Rev 4.2
WM8988
IMPORTANT NOTICE
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com.
For the purposes of our terms and conditions of sale, "Preliminary" or "Advanced" datasheets are non-final datasheets that include
but are not limited to datasheets marked as “Target”, “Advance”, “Product Preview”, “Preliminary Technical Data” and/or “Preproduction.” Products provided with any such datasheet are therefore subject to relevant terms and conditions associated with
"Preliminary" or "Advanced" designations. The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.;
and other companies in the Cirrus Logic group (collectively either “Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms
and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and
limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right to make changes to its
products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest
version of relevant information from Cirrus Logic to verify that the information is current and complete. Testing and other quality
control techniques are utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not
necessarily performed. In order to minimize risks associated with customer applications, the customer must use adequate design
and operating safeguards to minimize inherent or procedural hazards. Cirrus Logic is not liable for applications assistance or
customer product design. The customer is solely responsible for its selection and use of Cirrus Logic products. Use of Cirrus Logic
products may entail a choice between many different modes of operation, some or all of which may require action by the user, and
some or all of which may be optional. Nothing in these materials should be interpreted as instructions or suggestions to choose one
mode over another. Likewise, description of a single mode should not be interpreted as a suggestion that other modes should not be
used or that they would not be suitable for operation. Features and operations described herein are for illustrative purposes only.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL
INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS LOGIC PRODUCTS
ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY,
AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL
APPLICATIONS. INCLUSION OF CIRRUS LOGIC PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT
THE CUSTOMER’S RISK AND CIRRUS LOGIC DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR
IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE,
WITH REGARD TO ANY CIRRUS LOGIC PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR
CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS LOGIC PRODUCTS IN CRITICAL APPLICATIONS,
CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS LOGIC, ITS OFFICERS, DIRECTORS, EMPLOYEES,
DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT
MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
This document is the property of Cirrus Logic and by furnishing this information, Cirrus Logic grants no license, express or implied,
under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Any provision or
publication of any third party’s products or services does not constitute Cirrus Logic’s approval, license, warranty or endorsement
thereof. Cirrus Logic gives consent for copies to be made of the information contained herein only for use within your organization
with respect to Cirrus Logic integrated circuits or other products of Cirrus Logic, and only if the reproduction is without alteration and
is accompanied by all associated copyright, proprietary and other notices and conditions (including this notice). This consent does
not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for
resale. This document and its information is provided “AS IS” without warranty of any kind (express or implied). All statutory
warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus Logic for the use of
information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents
or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design, and SoundClear are among the trademarks of
Cirrus Logic. Other brand and product names may be trademarks or service marks of their respective owners.
Copyright © 2008–2016 Cirrus Logic, Inc. All rights reserved.
Rev 4.2
57
WM8988
REVISION HISTORY
DATE
RELEASE
01/05/08
3.0
WM8988 datasheet created
26/09/08
4.0
Product Status updated to Production Data
all
18/10/13
4.1
Package Diagram updated: Reference removed to exposed heat sink slug
55
20/12/16
4.2
Package Drawing updated (POD 050.D)
56
58
DESCRIPTION OF CHANGES
PAGES
Rev 4.2
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