CPC7581MATR

Not for New Designs CPC7581 Line Card Access Switch Features • Small 16-pin SOIC or DFN package • DFN package printed-circuit board footprint is 60 percent smaller than the SOIC version, 40 percent smaller than fourth generation EMR solutions. • Monolithic IC reliability • Low, matched RON • Eliminates the need for zero-cross switching • Flexible switch timing for transition from ringing mode to idle/talk mode. • Clean, bounce-free switching • Tertiary protection consisting of integrated current limiting, thermal shutdown for SLIC protection • 5 V operation with power consumption < 10 mW • Intelligent battery monitor • Latched logic-level inputs, no external drive circuitry required • SOIC package pin-compatible with Legerity product Description The CPC7581 is a monolithic solid-state four-pole switch in a 16-pin package. It provides the necessary functions to replace a 2-Form-C electromechanical relay on traditional analog and integrated voice and data (IVD) line cards found in central office, access, and PBX equipment. The CPC7581 contains solid-state switches for tip and ring lead line break and ringing injection/ringing return. The device requires only a +5 V supply and offers break-before-make and make-before-break operation using logic-level inputs. The CPC7581xA versions include an SCR that provides protection to the SLIC and subsequent circuitry during a fault condition. The CPC7581xC versions are functionally identical to the CPC7581xA versions, but with higher SCR hold current. Applications • • • • • • • • Central office (CO) Digital Loop Carrier (DLC) PBX Systems Digitally Added Main Line (DAML) Hybrid Fiber Coax (HFC) Fiber in the Loop (FITL) Pair Gain System Channel Banks Ordering Information CPC7581 part numbers are specified as shown here: B - 16-pin SOIC delivered 50/Tube, 1000/Reel M - 16-pin DFN delivered 52/Tube, 1000/Reel CPC7581 x x xx TR - Add for Tape & Reel Version A - With Protection SCR B - Without Protection SCR C - With Protection SCR and higher SCR hold current Figure 1. CPC7581 Block Diagram +5 Vdc 6 TRING 7 VDD Tip Secondary Protection TLINE 3 X SW3 SW1 CPC7581 2 TBAT X SLIC RLINE 14 SW2 15 RBAT SCR and Trip Circuit (CPC7581xA/C) VREF Switch Control Logic L A T C H 8 TSD Ring X X SW4 10 11 INRINGING LATCH 12 300Ω (min.) 1 FGND 16 VBAT 9 DGND VBAT RINGING Pb RoHS 2002/95/EC e3 1 DS-CPC7581-R05 www.clare.com CPC7581 1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Switch Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.1 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.2 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.3 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 Additional Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9 Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 4 4 4 5 5 6 7 8 9 9 2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1 Make-Before-Break Operation Logic Table (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 Break-Before-Make Operation Logic Table (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 TSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.7 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.8 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.8.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.8.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.9 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 DFN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Printed-Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 DFN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 DFN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 14 15 15 15 16 16 16 17 17 17 17 2 www.clare.com R05 CPC7581 1. Specifications 1.1 Package Pinout CPC7581 FGND TBAT TLINE NC NC T RINGING 1 16 VBAT 1.2 Pinout Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name FGND TBAT TLINE NC NC TRINGING VDD TSD DGND INRINGING LATCH RRINGING NC RLINE RBAT VBAT Description Fault ground Tip lead of the SLIC Tip lead of the line side No connection No connection Ringing generator return +5 V supply Temperature shutdown pin Digital ground Logic control input Data latch enable control input Ringing generator source No connection Ring lead of the line side Ring lead of the SLIC Battery supply 2 3 4 5 6 7 8 15 RBAT 14 RLINE 13 NC 12 RRINGING 11 LATCH 10 9 INRINGING DGND VDD TSD R05 www.clare.com 3 CPC7581 1.3 Absolute Maximum Ratings Parameter +5 V power supply (VDD) Battery Supply DGND to FGND Separation Logic input voltage Logic input to switch output isolation Switch open-contact isolation (SW1, SW2, SW3) Switch open-contact isolation (SW4) Operating relative humidity Operating temperature Storage temperature Minimum Maximum -0.3 -5 -0.3 5 -40 -40 7 -85 +5 VDD + 0.3 320 320 465 95 +110 +150 Unit V V V V V V V % °C °C Specifications cover the operating temperature range TA = -40°C to +85°C. Also, unless otherwise specified all testing is performed with VDD = +5Vdc, logic low input voltage is 0Vdc and logic high input voltage is +5Vdc. 1.4 ESD Rating ESD Rating (Human Body Model) 1000 V 1.5 General Conditions Unless otherwise specified, minimum and maximum values are production testing requirements. Typical values are characteristic of the device at 25°C and are the result of engineering evaluations. They are provided for informational purposes only and are not part of the manufacturing testing requirements. Absolute maximum electrical ratings are at 25°C. Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and affect its reliability. 4 www.clare.com R05 CPC7581 1.6 Switch Specifications 1.6.1 Break Switches, SW1 and SW2 Parameter Off-state leakage current +25° C +85° C -40° C RON +25° C +85° C -40° C RON match DC current limit +25° C +85° C -40° C Dynamic current limit (t ≤ 0.5 μs) Break switches on, all other switches off, apply ±1 kV at 10x1000 μs pulse, with appropriate protection in place. VSW (TLINE, RLINE) = ±320 V, logic inputs = gnd VSW (TLINE, RLINE) = ±330 V, logic inputs = gnd VSW (TLINE, RLINE) = ±310 V, logic inputs = gnd ISW VSW (on) = ±10 V ISW 80 300 160 400 2.5 425 A mA ISW = ±10 mA, ±40 mA, RBAT and TBAT = -2 V Per on-resistance test condition of SW1, SW2. Magnitude RON SW1-RON SW2 14.5 RON 20.5 10.5 Δ RON 0.15 28 0.8 Ω VSW (differential) = -320 V to gnd VSW (differential) = +260 V to -60 V VSW (differential) = -330 V to gnd VSW (differential) = +270 V to -60 V VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V ISW 0.1 0.3 0.1 1 μA Conditions Symbol Minimum Typical Maximum Unit Logic input to switch output isolation +25° C +85° C -40° C dv/dt sensitivity 0.1 0.3 0.1 200 V/μs 1 μA R05 www.clare.com 5 CPC7581 1.6.2 Ringing Return Switch, SW3 Parameter Off-state leakage current +25° C +85° C -40° C RON +25° C +85° C -40° C DC current limit +25° C +85° C -40° C Dynamic current limit (t ≤ 0.5 μs) Ringing switches on, all other switches off, apply ±1 kV at 10x1000 μs pulse, with appropriate protection in place. VSW (TRINGING, TLINE) = ±320 V, logic inputs = gnd VSW (TRINGING, TLINE) = ±330 V, logic inputs = gnd VSW (TRINGING, TLINE) = ±310 V, logic inputs = gnd ISW VSW (on) = ±10 V ISW 70 135 85 210 2.5 A mA ISW (on) = ±0 mA, ±10 mA RON 60 85 45 100 Ω VSW (differential) = -320 V to gnd VSW (differential) = +260 V to -60 V VSW (differential) = -330 V to gnd VSW (differential) = +270 V to -60 V VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V ISW 0.1 0.3 0.1 1 μA Conditions Symbol Minimum Typical Maximum Unit Logic input to switch output isolation +25° C +85° C -40° C dv/dt sensitivity 0.1 0.3 0.1 200 V/μs 1 μA 6 www.clare.com R05 CPC7581 1.6.3 Ringing Switch, SW4 Parameter Off-state leakage current +25° C +85° C -40° C On Voltage VSW (differential) = -255 V to +210 V VSW (differential) = +255 V to -210 V VSW (differential) = -270 V to +210 V VSW (differential) = +270 V to -210 V VSW (differential) = -245 V to +210 V VSW (differential) = +245 V to -210 V ISW (on) = ± 1 mA IRINGING ISW IRINGING RON 0.1 300 10 0.25 150 2 15 mA mA A μA Ω ISW 0.05 0.1 0.05 1.5 3 V 1 μA Conditions Symbol Minimum Typical Maximum Unit Ringing generator current to ground during VDD = 5 V, INRINGING = 0 ringing On steady-state current* Inputs set for ringing mode Surge current* Release current RON Logic input to switch output isolation +25° C +85° C -40° C dv/dt sensitivity VSW (RRINGING, RLINE) = ±320 V, logic inputs = gnd VSW (RRINGING, RLINE) = ±330 V, logic inputs = gnd VSW (RRINGING, RLINE) = ±310 V, logic inputs = gnd Ringing switches on, all other switches off, apply ±1 kV at 10x1000 μs pulse, with appropriate protection in place. ISW (on) = ±70 mA, ±80 mA 0.1 ISW 0.3 0.1 200 V/μs 1 μA *Secondary protection and ringing source current limiting must prevent exceeding this parameter. R05 www.clare.com 7 CPC7581 1.7 Additional Electrical Characteristics Parameter Digital input characteristics Input low voltage Input high voltage Input leakage current (high) Input leakage current (low) Voltage Requirements VDD VBAT1 1 Conditions VDD = 5.5 V, VBAT = -75 V, VIH = 5 V VDD = 5.5 V, VBAT = -75 V, VIL = 0 V Symbol VIL VIH IIH IIL Minimum 3.5 - Typical 2.2 2.3 0.1 0.1 Maximum 1.5 1 Unit V μA 1 - VDD VBAT 4.5 -19 5.0 -48 5.5 -72 V V VBAT is used only for internal protection circuitry. If VBAT goes more positive than -10 V, the device will enter the all-off state and will remain in the all-off state until the battery goes more negative than -15 V Power requirements Power consumption in talk and all-off states Power consumption in ringing state VDD current in talk and all-off states VDD current in ringing state VBAT current in any state Shutdown activation temperature Shutdown circuit hysteresis VDD = 5 V, VBAT = -48 V VDD = 5 V, VBAT = -48 V, measure IDD and IBAT P 6.5 IDD IBAT 1.3 0.1 2.0 10 μA 1.1 10 2.0 mA 5.5 10 mW Temperature Shutdown Requirements (temperature shutdown flag is active low) 110 10 25 125 150 °C Temperature shutdown requirements are not production tested, but rather guaranteed by design. 8 www.clare.com R05 CPC7581 1.8 Protection Circuitry Electrical Specifications Parameter Conditions Symbol Minimum Typical Maximum Unit Parameters Related to the Diodes in the Diode Bridge Voltage drop at Apply ± dc current limit of break continuous current (50/ switches 60 Hz) Voltage drop at surge current Surge current Apply ± dynamic current limit of break switches T=+25°C Trigger current T=+85°C ITRIG Forward Voltage Forward Voltage 2.1 5 3 V - Parameters Related to the Protection SCR 60 (CPC7581xA) 70 (CPC7581xC) 35 (CPC7581xA) 40 (CPC7581xC) 110 (CPC7581xA) 135 (CPC7581xC) 70 60 (CPC7581xA) (CPC7581xA) 115 110 (CPC7581xC) (CPC7581xC) VBAT -4 -3 -5 VBAT -2 1.0 V μA V V * A - mA T=+25°C Hold current T=+85°C VTBAT or VRBAT IVBAT VTBAT or VRBATIHOLD Gate trigger voltage IGATE = ITRIGGER** Reverse leakage current VBAT = -48 V On-state voltage 0.5 A, t = 0.5 μs 2.0 A, t = 0.5 μs *Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place. **VBAT must be capable of sourcing ITRIGGER for the internal SCR to activate. 1.9 Truth Table State Talk Ringing Latched All-Off 1 INRINGING 0 1 X X Latch 0 1 X TSD Break Switches On Off Ringing Switches Off On Z1 0 Unchanged Off Off Z = High Impedance. Because TSD has an internal pull up at this pin, it should be controlled with an open-collector or open-drain type device. R05 www.clare.com 9 CPC7581 2. Functional Description 2.1 Introduction The CPC7581 has three states: • Talk. Line break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open. • Ringing. Ringing switches SW3 and SW4 closed, line break switches SW1 and SW2 open. • All-off. All switches open. See “Truth Table” on page 9 for more information. The CPC7581 offers break-before-make and make-before-break switching from the ringing state to the talk state with simple logic-level input control. Solid-state switch construction means no impulse noise is generated when switching during ring cadence or ring trip, eliminating the need for external zero-cross switching circuitry. State control is via logic-level input so no additional driver circuitry is required. The line break switches SW1 and SW2 are linear switches that have exceptionally low RON and excellent matching characteristics. The ringing switch SW4 has a breakdown voltage rating of 465V @ 25°C. This is sufficiently high, with proper protection, to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ringing generator). Integrated into the CPC7581 is a over voltage clamping circuit, active current limiting, and a thermal shutdown mechanism to provide protection to the SLIC device during a fault condition. Positive and negative surges are reduced by the current limiting circuitry and hazardous potentials are steered to ground via diodes and, in CPC7581xA and CPC7581xC parts, an integrated SCR. Power-cross potentials are also reduced by the current limiting and thermal shutdown circuits. To protect the CPC7581 from an overvoltage fault condition, the use of a secondary protector is required. The secondary protector must limit the voltage seen at the tip and ring terminals to a level below the maximum breakdown voltage of the switches. To minimize the stress on the solid-state contacts, use of a foldback or crowbar type secondary protector is recommended. With proper selection of the secondary protector, a line card using the CPC7581 will meet all relevant ITU, LSSGR, TIA/EIA and IEC protection requirements. The CPC7581 operates from a +5 V supply only. This gives the device extremely low idle and active power consumption and allows use with virtually any range of battery voltage. Battery voltage is also used by the CPC7581 as a reference for the integrated protection circuit. In the event of a loss of battery voltage, the CPC7581 enters the all-off state. 2.2 Switch Logic The CPC7581 provides, when switching from the ringing state to the talk state, the ability to control the release timing of the ringing switches SW3 and SW4 relative to the state of the line break switches SW1 and SW2 using simple logic-level input. This is called make-before-break or break-before-make operation. When the line break switch contacts (SW1 and SW2) are closed (or made) before the ringing switch contacts (SW3 and SW4) are opened (or broken), this is called make-before-break operation. Break-before-make operation occurs when the ringing contacts (SW3 and SW4) are opened (broken) before the line break contacts (SW1 and SW2) are closed (made). To use make-before-break ringing switch release timing, de-assert INRINGING during ringing. This causes the operational sequence shown in “MakeBefore-Break Operation Logic Table (Ringing to Talk Transition)” on page 11 to occur. 10 www.clare.com R05 CPC7581 2.2.1 Make-Before-Break Operation Logic Table (Ringing to Talk Transition) Break Switches Off Ringing Return Switch (SW3) On Ringing Switch (SW4) On State INRINGING 1 Latch TSD Timing Ringing MakeBeforeBreak Talk SW4 waiting for next zero-current crossing to turn off. Maximum time is one-half of the ringing cycle. In this transition state, current that is limited to the dc break switch current limit value will be sourced from the ring node of the SLIC. Zero-cross current has occurred 0 0 Z On Off On 0 On Off Off To use break-before-make ringing switch release timing, assert TSD during ringing. This causes the operational sequence shown in “Break-Before-Make Operation Logic Table (Ringing to Talk Transition)” on page 11 to occur. 2.2.2 Break-Before-Make Operation Logic Table (Ringing to Talk Transition) Break Switches Off Off Off On Ringing Return Switch (SW3) On Off Off Off Ringing Switch (SW4) On On Off Off State INRINGING 1 1 1 0 Latch TSD Z Timing Ringing All-off All-off Talk Hold this state for one-half of the ringing cycle. SW4 waiting for zero current to turn off. Zero current has occurred. SW4 has opened Release break switches 0 0 Z Logic states and explanations are given in “Truth Table” on page 9. affected by the LATCH input and the TSD input will override state control. 2.3 Data Latch The CPC7581 has an integrated data latch. The latch operation is controlled by logic-level input pin 11 (LATCH). The data input of the latch is pin 10 (INRINGING), while the output of the data latch is an internal node used for state control. When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly through to state control. A change in input will be reflected in a change is switch state. When the LATCH control pin is at logic 1, the data latch is active and a change in input control will not affect switch state. The switches will remain in the position they were in when the LATCH changed from logic 0 to logic 1 and will not respond to changes in input as long as the latch is at logic 1. The TSD input is not tied to the data latch. Therefore, TSD is not 2.4 TSD The thermal shutdown mechanism activates when the device die temperature reaches a minimum of 110° C, placing the device in the all-off state regardless of logic input. During thermal shutdown mode, pin 8 (TSD) will read a nominal 0 V. Normal output of TSD is typically equal to VDD. If presented with a short duration transient such as a lightning event, the thermal shutdown feature will typically not activate. But in an extended power-cross event, the device temperature will rise and the thermal shutdown will activate forcing the switches to the all-off state. At this point the current measured through the break switches (SW1 and SW2) will drop to zero. Once the device enters thermal shutdown it will remain in the all-off state until the temperature of the device drops below the de-activation level of the thermal shutdown circuit. This permits the device to 11 R05 www.clare.com CPC7581 return to normal operation. If the transient has not passed, current will flow at the value allowed by the dynamic DC current limiting of the switches and heating will begin again, reactivating the thermal shutdown mechanism. This cycle of entering and exiting the thermal shutdown mode will continue as long as the fault condition persists. If the magnitude of the fault condition is great enough, the external secondary protector could activate and shunt all current to ground. The TSD pin is a pull-up current source with a nominal value of 300 μA biased from VDD. For applications using low-voltage logic devices (lower than VDD), Clare recommends the use of an open-drain type output to control TSD. This avoids sinking the TSD bias current to ground during normal operation when the all-off state is not required. prevents a fault-induced overvoltage event at the TBAT or RBAT nodes. 2.7 Battery Voltage Monitor The CPC7581 also uses the VBAT voltage to monitor battery voltage. If system battery voltage is lost, the CPC7581 immediately enters the all-off state. It remains in this state until the battery voltage is restored. The device also enters the all-off state if the system battery voltage goes more positive than –10 V, and remains in the all-off state until the battery voltage goes more negative than –15 V. This battery monitor feature draws a small current from the battery (less than 1 μA typical) and adds slightly to the device’s overall power dissipation. Due to the nature of the internal protection circuitry, the VBAT pin can be biased via potentials applied to TBAT or RBAT. This allows the CPC7581 switches to operate, but offers no transient protection. The supply voltage applied to VBAT should therefor be the same supply voltage applied to the line driver device. 2.5 Ringing Switch Zero-Cross Current Turn Off After the application of a logic input to turn SW4 off, the ringing switch is designed to delay the change in state until the next zero-crossing. Once on, the switch requires a zero-current cross to turn off, and therefore should not be used to switch a pure DC signal. The switch will remain in the on state no matter the logic input until the next zero crossing. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing switches. See Clare application note AN-144, Impulse Noise Benefits of Line Card Access Switches for more information. The attributes of ringing switch SW4 may make it possible to eliminate the need for a zero-cross switching scheme. A minimum impedance of 300 Ω in series with the ring generator is recommended. 2.8 Protection 2.8.1 Diode Bridge/SCR The CPC7581 uses a combination of current limited break switches, a diode bridge/SCR clamping circuit, and a thermal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line transient events such as lightning. During a positive transient condition, the fault current is conducted through the diode bridge to ground via FGND. Voltage is clamped to a diode drop above ground. During a negative transient of 2 to 4 V more negative than the battery, the SCR conducts and faults are shunted to FGND via the SCR or the diode bridge. In order for the SCR to crowbar (or foldback), the on voltage (see “Protection Circuitry Electrical Specifications” on page 9) of the SCR must be less negative than the battery reference voltage. If the battery voltage is less negative than the SCR on voltage, or if the VBAT supply is unable to source the trigger current, the SCR will not crowbar. For power induction or power-cross fault conditions, the positive cycle of the transient is clamped to a diode drop above ground and the fault current directed to ground. The negative cycle of the transient will cause the SCR to conduct when the voltage exceeds the R05 2.6 Power Supplies Both a +5 V supply and battery voltage are connected to the CPC7581. CPC7581 switch state control is powered exclusively by the +5 V supply. As a result, the CPC7581 exhibits extremely low power dissipation during both active and all-off states. The battery voltage is not used for switch control but rather as a supply for the integrated secondary protection circuitry. The integrated SCR is designed to trigger when pin 2 (TBAT) or pin 15 (RBAT) drops 2 to 4 V below the voltage on pin 16 (VBAT). This trigger 12 www.clare.com CPC7581 battery reference voltage by two to four volts, steering the current to ground. Note: The CPC7581xB does not contain the protection SCR. 2.9 External Protection Elements The CPC7581 requires only overvoltage secondary protection on the loop side of the device. The integrated protection feature described above negates the need for protection on the other (usually SLIC) side. The secondary protector limits voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7581. A foldback or crowbar type protector is recommended to minimize stresses on the device. Consult Clare’s application note, AN-100, “Designing Surge and Power Fault Protection Circuits for Solid State Subscriber Line Interfaces” for equations related to the specifications of external secondary protectors, fused resistors and PTCs. 2.8.2 Current Limiting function If a lightning strike transient occurs when the device in the talk state, the current is passed along the line to the integrated protection circuitry and limited by the dynamic current limit response of break switches SW1 and SW2. When a 1000V 10x1000 μs pulse (GR-1089-CORE lightning) is applied to the line though a properly clamped external protector, the current seen through the break switches will be a pulse with a typical magnitude of 2.5 A and a duration of less than 0.5 μs. If a power-cross fault occurs with the device in the talk state, the current is passed though the break switches SW1 and SW2 on to the integrated protection circuit and is limited by the dynamic DC current limit response of the two break switches. The DC current limit, specified over temperature, is between 80 mA and 425 mA, and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to power cross fault, the measured current through the break switches (SW1 and SW2) will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will enter the all-off state. R05 www.clare.com 13 CPC7581 3. Manufacturing Information 3.1 Mechanical Dimensions 3.1.1 SOIC 10.211 ± 0.254 (0.402 ± 0.010) NOTES: 1. Coplanarity = 0.1016 (0.004) max. 2. Leadframe thickness does not include solder plating (1000 microinch maximum). PIN 16 10.312 ± 0.381 (0.406 ± 0.015) 7.493 ± 0.127 (0.295 ± 0.005) DIMENSIONS mm (inches) 1.270 TYP (0.050 TYP) 0.406 ± 0.076 (0.016 ± 0.003) 0.254 MIN / 0.737 MAX X 45° (0.010 MIN / 0.029 MAX X 45°) PIN 1 2.337 ± 0.051 (0.092 ± 0.002) 2.540 ± 0.152 (0.100 ± 0.006) 0.649 ± 0.102 (0.026 ± 0.004) 0.203 ± 0.102 (0.008 ± 0.004) 0.889 ± 0.178 (0.035 ± 0.007) 0.2311 MIN / 0.3175 MAX (0.0091 MIN / 0.0125 MAX) 3.1.2 DFN 7.00 ± 0.25 (0.276 ± 0.01) 6.00 ± 0.25 (0.236 ± 0.01) INDEX AREA 0.90 ± 0.10 (0.035 ± 0.004) TOP VIEW 0.02, + 0.03, - 0.02 (0.0008, + 0.0012, - 0.0008) 1 SIDE VIEW 0.30 ± 0.05 (0.012 ± 0.002) SEATING PLANE 0.20 (0.008) EXPOSED METALLIC PAD 4.25 ± 0.05 (0.167 ± 0.002) Terminal Tip 0.80 (0.032) 16 6.00 ± 0.05 (0.236 ± 0.002) BOTTOM VIEW Dimensions mm (inch) 0.55 ± 0.10 (0.022 ± 0.004) 14 www.clare.com R05 CPC7581 3.2 Printed-Circuit Board Layout 3.2.1 SOIC 1.27 (0.050) 9.40 (0.370) 2.00 (0.079) 0.60 (0.024) DIMENSIONS mm (inches) 3.2.2 DFN 0.35 (0.014) 1.05 (0.041) 5.80 (0.228) 0.80 (0.031) DIMENSIONS mm (inches) As the metallic pad on the bottom of the DFN package is connected to the substrate of the die, Clare recommends that no printed circuit board traces or vias be placed under this area. R05 www.clare.com 15 CPC7581 3.3 Tape and Reel Packaging 3.3.1 SOIC Tape and Reel Packaging for 16-Pin SOIC Package 330.2 Dia (13.00 Dia) Top Cover Tape Thickness 0.102 Max (0.004 Max) Top Cover Tape P=12.00 (0.47) A0=10.90 + 0.15 (0.429 + 0.010) Dimensions mm (inches) Pin 1 B0=10.70 + 0.15 (0.421 + 0.01) W=16.00 + 0.30 (0.630 + 0.010) K0=3.20 + 0.15 (0.193 + 0.01) K1=2.70 + 0.15 (0.106 + 0.01) Embossed Carrier User Direction of Feed Embossment NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2 3.3.2 DFN 330.2 Dia (13.00 Dia) Top Cover Tape Thickness 0.102 Max (0.004 Max) Pin 1 W=16.00 + 0.30 (0.630 + 0.012) B0=7.24 + 0.10 (0.285 + 0.004) Embossed Carrier K0=1.61 + 0.10 (0.063 + 0.004) P=12.00 + 0.10 (0.472 + 0.004) A0=6.24 + 0.10 (0.246 + 0.004) User Direction of Feed Embossment Dimensions mm (inches) NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2 16 www.clare.com R05 CPC7581 3.4 Soldering 3.4.1 Moisture Reflow Sensitivity Clare has characterized the moisture reflow sensitivity for this product using IPC/JEDEC standard J-STD-020. Moisture uptake from atmospheric humidity occurs by diffusion. During the solder reflow process, in which the component is attached to the PCB, the whole body of the component is exposed to high process temperatures. The combination of moisture uptake and high reflow soldering temperatures may lead to moisture induced delamination and cracking of the component. To prevent this, this component must be handled in accordance with IPC/JEDEC standard J-STD-033 per the labeled moisture sensitivity level (MSL), level 1 for the SOIC package, and level 3 for the DFN package. 3.4.2 Reflow Profile For proper assembly, this component must be processed in accordance with the current revision of IPC/JEDEC standard J-STD-020. Failure to follow the recommended guidelines may cause permanent damage to the device resulting in impaired performance and/or a reduced lifetime expectancy. 3.5 Washing Clare does not recommend ultrasonic cleaning of this part. Pb RoHS 2002/95/EC e3 For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC7581-R05 © Copyright 2009, Clare, Inc. All rights reserved. Printed in USA. 10/14/09 17 www.clare.com