M-8888-01P

M-8888 DTMF Transceiver Features CMOS technology · Advancedand increased noisefor low power consumption immunity Complete DTMF transmitter/receiver in a single · chip · Standard 8051, 8086/8 microprocessor port · Central office quality and performance guard time · Adjustable tone burst mode Automatic · Call progress mode · Single +5 Volt power supply · 20-pin DIP and SOIC packages · 2 MHz microprocessor port operation · Inexpensive 3.58 MHz crystal · Applications Description The M-8888 is a complete DTMF Transmitter Receiver that features adjustable guard time, automatic tone burst mode, call progress mode, and a fully compatible 8051, 8086/8 microprocessor interface. The receiver portion is based on the industry standard M-8870 DTMF Receiver, while the transmitter uses a switched-capacitor digital-to-analog converter for lowdistortion, highly accurate DTMF signaling. Tone bursts can be transmitted with precise timing by making use of the automatic tone burst mode. To analyze call progress tones, a call progress filter can be selected by an external microprocessor. · Paging systems · Repeater systems/mobile radio · Interconnect dialers · PBX systems · Computer systems · Fax machines · Pay telephone · Credit card verification Ordering Information Part # Description M-8888-01P M-8888-01SM M-8888-01T 20-pin plastic DIP 20-pin plastic SOIC 20-pin plastic SOIC,Tape and Reel Pin Connections Block Diagram DS-M8888-R1 www.clare.com 1 M-8888 Single-Ended Input Configuration Differential Input Configuration Functional Description M-8888 functions consist of a high-performance DTMF receiver with an internal gain setting amplifier and a DTMF generator that contains a tone burst counter for generating precise tone bursts and pauses. The call progress mode, when selected, allows the detection of call progress tones. A standard 8051, 8086/8 series microprocessor interface allows access to an internal status register, two control registers, and two data registers. Input Configuration The input arrangement consists of a differential input operational amplifier and bias sources (VREF) for biasPin Functions Name IN+ INGS VREF VSS OSC1 OSC2 TONE WR CS RS0 RD IRQ /CP Description Noninverting op-amp input. Inverting op-amp input. Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference voltage output. Nominally VDD/2 is used to bias inputs at mid-rail. Negative power supply input. DTMF clock/oscillator input. Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Dual tone multifrequency (DTMF) output. Write input. A low on this pin when CS is low enables data transfer from the microprocessor. TTL compatible. Chip select. TTL input (CS = 0 to select the chip). Register select input. See Internal Register Functions on page 7. TTL compatible. Read input. A low on this pin when CS is low enables data transfer to the microprocessor. TTL compatible.. Interrupt request to microprocessor (open-drain output). Also, when call progress (CP) mode has been selected and interrupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Timing Diagrams on page 11. Microprocessor data bus. TTL compatible. Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. Positive power supply input. ing the amplifier inputs at VDD/2. Provisions are made for the connection of a feedback resistor to the op-amp output (GS) for gain adjustment. In a single-ended configuration, the input pins should be connected as shown in the Single-Ended Input Configuration above. Differential Input Configuration above shows the necessary connections for a differential input configuration. Receiver Section The low and high group tones are separated by applying the DTMF signal to the inputs of two sixth-order D0-D3 ESt St/GT VDD 2 www.clare.com Rev. 1 M-8888 switched capacitor bandpass filters with bandwidths that correspond to the low and high group frequencies listed in the Tone Encoding/Decoding below. The low group filter incorporates notches at 350 and 440 Hz, providing excellent dial tone rejection. Each filter output is followed by a single-order switched capacitor filter that smoothes the signals prior to limiting. Limiting is performed by high-gain comparators with hysteresis to prevent detection of unwanted low-level signals. The comparator outputs provide full-rail logic swings at the incoming DTMF signal frequencies. A decoder employs digital counting techniques to determine the frequencies of the incoming tones, and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals (such as voice), while tolerating small deviations in frequency. The algorithm provides an optimum combination of immunity to talkoff with tolerance to interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (referred to as signal condition), the early steering (ESt) output goes to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state. Basic Steering Circuit by an external RC time constant driven by ESt. A logic high on ESt causes VC (see the Basic Steering Circuit above) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt remains high) for the validation period (tGTP), VC reaches the threshold (VTSt) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see the Tone Encoding/Decoding on left) into the receive data register. At this point the StGT output is activated and drives VC to VDD. StGT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag goes high, signaling that a received tone pair has been registered. It is possible to monitor the status of the delayed steering flag by checking the appropriate bit in the status register. If interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering flag is active. The contents of the output latch are updated on an active delayed steering transition. This data is presented to the 4-bit bidirectional data bus when the receive data register is read. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropout) too short to be considered a valid pause. This capability, together with the ability to select the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. Guard Time Adjustment: The simple steering circuit shown in the Basic Steering Circuit above is adequate for most applications. Component values are chosen according to the formula: tREC = tDP + tGTP TID = tDA + tGTA 3 Tone Encoding/Decoding FLOW 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 FHIGH 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 Digit 1 2 3 4 5 6 7 8 9 0 * # A B C D D3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 = logic low, 1 = logic high Steering Circuit: Before a decoded tone pair is registered, the receiver checks for a valid signal duration (referred to as “character recognition condition”). This check is performed Rev. 1 www.clare.com M-8888 Guard Time Adjustment Call Progress Response The value of tDP is a device parameter and tREC is the minimum signal duration to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most applications, leaving R1 to be selected by the designer. Different steering arrangements may be used to select independently the guard times for tone present (tGTP) and tone absent (tGTA). This may be necessary to meet system specifications that place both accept and reject limits on both tone duration and interdigit pause. Guard time adjustment also allows the designer to tailor system parameters such as talkoff and noise immunity. Increasing tREC improves talkoff performance since it reduces the probability that tones simulated by speech will maintain signal condition long enough to be registered. Alternatively, a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone dropouts are required. Design information for guard time adjustment is shown in the Guard Time Adjustment above. Call Progress Filter A call progress (CP) mode can be selected, allowing the detection of various tones that identify the progress of a telephone call on the network. The call progress tone input and DTMF input are common; however, call progress tones can only be detected when the CP mode has been selected. DTMF signals cannot be detected if the CP mode has been selected (see the Actual Frequencies vs Standard Requirements on page 5). The Call Progress Response above indicates the useful detect bandwidth of the call progress filter. Frequencies presented to the input (IN+ and IN-) that are within the accept bandwidth limits of the filter are hard-limited by a high-gain comparator with the IRQ/CP pin serving as the output. The square wave output obtained from the schmitt trigger can be ana4 yzed by a microprocessor or counter arrangement to determine the nature of the call progress tone being detected. Frequencies in the reject area will not be detected, and consequently there will be no activity on IRQ/CP as a result of these frequencies. DTMF Generator The DTMF transmitter used in the M-8888 is capable of generating all 16 standard DTMF tone pairs with low distortion and high accuracy. All frequencies are derived from an external 3.58 MHz crystal. The sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable dividers and switched capacitor digital-to-analog converters. The row and column tones are mixed and filtered, providing a DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the encoding format shown in the Tone Encoding/Decoding Table on page 3 must be written to the transmit data register. Note that this is the same as the receiver output code. The individual tones that are generated (fLOW and fHIGH) are referred to as low-group and high-group tones. Typically, the highgroup to low-group amplitude ratio (twist) is 2 dB to compensate for high-group attenuation on long loops. Operation: During write operations to the transmit data register, 4bit data on the bus is latched and converted to a 2 of 8 code for use by the programmable divider circuitry to specify a time segment length that will ultimately determine the tone frequency. The number of time segments is fixed at 32, but the frequency is varied by varying the segment length. When the divider reaches the appropriate count as determined by the input code, a reset pulse is issued and the counter starts again. Rev. 1 www.clare.com M-8888 either by the application or by any of the existing exchange transmitter specifications. Standard DTMF signal timing can be accomplished by making use of the burst mode. The transmitter is capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 ms ± 1 ms, a standard interval for autodialer and central office applications. After the burst/pause has been issued, the appropriate bit is set in the status register, indicating that the transmitter is ready for more data. The timing described in the previous paragraph is available when the DTMF mode has been selected. However, when call progress (CP) mode is selected, a secondary burst/pause time is available that extends this interval to 102 ms ± 2 ms. The extended interval is useful when precise tone bursts of longer than 51 ms duration and 51 ms pause are desired. Note that when CP mode and burst mode have been selected, DTMF tones may be transmitted only and not received. In applications where a nonstandard burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses when the burst mode is disabled by enabling and disabling the transmitter. The M-8888 is initialized on powerup sequence with DTMF mode and burst mode selected. Single-Tone Generation: A single-tone mode is available whereby individual tones from the low group or high group can be generated. This mode can be used for DTMF test equipment applications, acknowledgment tone generation, and distortion measurements. Refer to the Control Register B Description below for details. The divider output clocks another counter that addresses the sinewave lookup ROM. The lookup table contains codes used by the switched capacitor D/A converter to obtain discrete and highly accurate DC voltage levels. Two identical circuits are used to produce row and column tones, which are then mixed using a low-noise summing amplifier. The oscillator described needs no startup time as in other DTMF generators, since the crystal oscillator is running continuously, thus providing a high degree of tone burst accuracy. When there is no tone output signal, the TONE pin assumes a DC level of 2.5 volts (typically). A bandwidth limiting filter is incorporated to attenuate distortion products above 4 KHz. Burst Mode: Certain telephony applications require that generated DTMF signals be of a specific duration, determined Actual Frequencies vs Standard Requirements Active Cell L1 L2 L3 L4 H1 H2 H3 H4 Output Frequency(Hz) Specified Actual 697 770 852 941 1209 1336 1447 1633 699.1 766.2 847.4 948.0 1215.9 1331.7 1471.9 1645.0 % Error + 0.30 - 0.49 - 0.54 + 0.74 + 0.57 - 0.32 - 0.35 + 0.73 Control Register A Description Bit b0 Name TOUT Function Tone output Mode control Description A logic 1 enables the tone output. This function can be implemented in either the burst mode or nonburst mode. In DTMF mode (logic 0), the device is capable of generating and receiving DTMF signals. When the call progress (CP) mode is selected (logic 1), a 6th-order bandpass filter is enabled to allow call progress tones to be detected. Call progress tones within the specified bandwidth will be presented at the IRQ/CP pin in rectangular wave format if the IRQ bit has been enabled (b2 = 1). Also, when the CP mode and burst mode have both been selected, the transmitter will issue DTMF signals with a burst and pause of 102 ms (typ) duration. This signal duration is twice that obtained from the DTMF transmitter, if DTMF mode had been selected. Note that DTMF signals cannot be decoded when the CP mode has been selected. A logic 1 enables the interrupt mode. When this mode is active and the DTMF mode has been selected (b1 = 0), the IRQ/CP pin will pull to a logic 0 condition when either (1) a valid DTMF signal has been received and has been present for the guard time or (2) the transmitter is ready for more data (burst mode only). A logic 1 selects control register B on the next write cycle to the control register address. Subsequent write cycles to the control register are directed back to control register A. b1 CP/DTMF b2 IRQ Interrupt enable b3 Rev. 1 RSEL Register select www.clare.com 5 M-8888 Distortion Calculations: The M-8888 is capable of producing precise tone bursts with minimal error in frequency (see the Actual Frequecies vs Standard Requirements on page 5). The internal summing amplifier is followed by a firstorder low-pass switched capacitor filter to minimize harmonic components and intermodulation products. The total harmonic distortion for a single tone can be calculated using Equation 1, (see Equations on page 7), which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency expressed as a percentage. The Fourier components of the tone output correspond to V2f... Vnf as measured on the output waveform. The total harmonic distortion for a dual tone can be calculated using Equation 2, (see Equations on page 7). VL and VH correspond to the low-group and high-group amplitude, respectively, and V2IMD is the sum of all the intermodulation components. The internal switched capacitor filter following the D/A converter keeps distortion products down to a very low level. DTMF Clock Circuit The internal clock circuit is completed with the addition of a standard 3.579545 MHz television color burst crystal. A number of M-8888 devices can be connected as shown in the Common Crystal Connection on page 7 using only one crystal. Microprocessor Interface The M-8888 uses a microprocessor interface that allows precise control of transmitter and receiver functions. Five internal registers are associated with the microprocessor interface, which can be subdivided into three categories: data transfer, transceiver control, and transceiver status. Two registers are associated with data transfer operations. The receive data register, a read-only register, contains the output code of the last valid DTMF tone pair to be decoded. The data entered in the transmit data register determines which tone pair is to be generated (see the Tone Encoding/Decoding Table on page 3). Data can only be written to the transmit data register. Transceiver control is accomplished with two control registers (and CRB) that occupy the same address space. A write operation to CRB can be executed by setting the appropriate bit in CRA. The following write operation to the same address will then be directed to CRB, and subsequent write cycles will then be redirected to CRA. Internal reset circuitry clears the control registers on powerup; however, as a precautionary measure, the initialization software should include a routine to clear the registers. Refer to the Actual Frequencies vs Standard Requirements Table on page 5 and the Control Register A Description below for details on the control registers. The IRQ/CP pin can be programmed to provide an interrupt request signal on validation of DTMF signals, or when the transmitter is ready for more data (burst mode only). The IRQ/CP pin is configured as an open-drain output device and as such requires a pullup resistor (see the Single-Ended Input Configuration on page 2). Control Register B Description Bit b0 Name BURST Function Burst mode Description b1 TEST b2 S/D b3 C/R A logic 0 enables the burst mode. When this mode is selected, data corresponding to the desired DTMF tone pair can be written to the transmit data register, resulting in a tone burst of a specific duration (see the 12 AC Characteristics on page 9). Subsequently, a pause of the same duration is induced. Immediately following the pause, the status register is updated indicating that the transmit data register is ready for further instructions, and an interrupt will be generated if the interrupt mode has been enabled. Additionally, if call progress (CP) mode has bee enabled, the burst and pause duration is increased by a factor of two. When the burst mode is not selected (logic 1), tone bursts of any desired duration may be generated. Test mode By enabling the test mode (logic 1), the IRQ/CP pin will present the delayed steering (inverted) signal from the DTMF receiver. Refer to the Timing Diagrams on page 11 (b3 waveform) for details concerning the output waveform.DTMF mode must be selected (CRA b1=0) before test mode can be implemented. Single/dual tone A logic 0 will allow DTMF signals to be produced. If single-tone generation is enabled generation (logic 1), either now or column tones (low or high group) can be generated depending on the state of b3 in control register B. Column/row tones When used in conjunction with b2 (above), the transmitter can be made to generate single-row or single-column frequencies. A logic 0 will select row frequencies and a logic 1 will select column frequencies. 6 www.clare.com Rev. 1 M-8888 Common Crystal Connection Internal Register Functions RS0 0 0 1 1 RD 1 0 1 0 WR 0 1 0 1 Function Write to transmitter Read from receiver Write to control register Read from status register CRA Bit Positions Equations b3 RSEL b2 IRQ b1 CP/DTMF b0 TOUT CRB Bit Positions b3 C/R b2 S/D b1 TEST b0 BURST Application Circuit (Single-Ended Input) Staus Register Description Bit b0 b1 b2 b3 IRQ Transmit data register empty (burst mode only) Receive data register full. Delayed Steering Name Status Flag Set Interrupt has occurred. Bit one (b1) and/or bit 2 (b2) is set.status register is read. Pause duration has terminated and transmitter is ready for new data. Valid data is in the receive data register. Set on valid detection of the absence of a DTMF signal. Status Flag Cleared Interrupt is inactive. Cleared after Cleared after status register is read or when not in burst mode. Cleared after status register is read. Cleared on detection of a valid DTMF signal. Rev. 1 www.clare.com 7 M-8888 Absolute Maximum Ratings Parameter Power supply voltage (VDD - VSS) Voltage on any pin Current on any pin Operating temperature Storage temperature Symbol VDD Vdc IDD TA TS Value + 6.0 V max VSS -0.3 V to VDD + 0.3V 10 mA max -40°C to +85°C -65°C to +150°C Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and effect its reliability. Note: Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied. DC Characteristics Parameter Operating supply voltage Operating supply current Power consumption Inputs High-level input voltage, OSC1 Low-level input voltage, OSC1 Input impedance (@ 1 KHz), IN+, INSteering threshold voltage Outputs High-level output voltage (no load), OSC2 Low-level output voltage (no load), OSC2 Output leakage current (VOH = 2.4V), IRQ VREF output voltage (no load) VREF output resistance Data Bus Low-level input voltage High-level input voltage Low-level output voltage (IOL = 1.6 mA) High-level output voltage (IOH = 400 µA) Input leakage current (VIN = 0.4 to 2.4 V) Symbol VDD IDD PO VIHO VILO RIN VTSt VOHO VOLO IOZ VREF ROR VIL VIH VOL VOH IIZ Min 4.75 3.5 2.2 VDD - 0.1V 2.4 2.0 2.4 - Typ* 5.0 10 50 10 2.3 1.0 - Max 5.25 15 78.75 1.5 2.5 0.1 10.0 2.7 1.0 0.8 0.4 10.0 Units V mA mW V V MΩ V V V µA V kΩ V V V V µA All voltages referenced to VSS unless otherwise noted. VDD = 5.0 V ± 5%; fC = 3.579545 MHz; TA = -40°C to +85°C unless otherwise noted. *Typical values are for use as design aids only, and are not guaranteed or subject to production testing. 8 www.clare.com Rev. 1 M-8888 AC Characteristics Parameter Receive signal conditions Valid input signal levels (each tone of composite signal; Notes 1, 2, 3, 5, 6, 9) Positive twist accept (Notes 2, 3, 6, 9) Negative twist accept (Notes 2, 3, 6, 9) Frequency deviation accept (Notes 2, 3, 5, 9) Frequency deviation reject (Notes 2, 3, 5) Third tone tolerance (Notes 2, 3, 4, 5, 9, 10) Noise tolerance (Notes 2, 3, 4, 5, 7, 9, 10) Dial tone tolerance (Notes 2, 3, 4, 5, 8, 9, 11) Call progress Lower frequency (@ -25 dBm) accept Upper frequency (@ -25 dBm) accept Lower frequency (@ -25 dBm) reject Upper frequency (@ -25 dBm) reject Receive timing Tone present detect time Tone absent detect time Tone duration accept (the Timing Diagrams on page 10) Tone duration reject (the Timing Diagrams on page 10) Interdigit pause accept (the Timing Diagrams on page 10) Interdigit pause reject (the Timing Diagrams on page 10) Delay St to b3 Delay St to RXO-RX3 Transmit timing Tone burst duration (DTMF mode) Tone pause duration (DTMF mode) Tone burst duration (extended, call progress mode) Tone pause duration (extended, call progress mode) Tone output High group output level (RL = 10 KΩ) Low group output level (RL = 10 KΩ) Pre-emphasis (RL = 10 KΩ) Output distortion (RL = 10 kΩ, 3.4 KHz bandwidth) Frequency deviation (f = 3.5795 MHz) Output load resistance Microprocessor interface RD, WR low pulse width RD, WR high pulse width RD, WR rise and fall time Address hold time Address setup time Data hold time (read) RD to valid data delay (200 pF load) Data setup time (write) Data hold time (write) Input capacitance, D0-D3 Output capacitance, IRQ /CP fLA fHA fLR fHR tDP tDA tREC tREC tID tDO tPStb3 tPStRX tBST tPS tBSTE tPSE VHOUT VLOUT dBP THD fD RLT tCL tCH tR, tF tAH tAS tDHR tDDR tDSW tDHW CIN C/OUT -29 27.5 ± 1.5% ± 2 Hz ± 3.5% 5 0.5 20 20 50 50 100 100 -6.1 -8.1 0 10 200 180 10 23 22 45 10 -16 -12 +22 320 510 290 540 11 4 13 8 2 -25 ± 0.7 5 5 +1 869 6 6 14 8.5 40 40 52 52 104 104 -2.1 -4.1 3 ± 1.5 50 25 150 dBm mVRMS dB dB Nom. Nom. dB dB dB Hz Hz Hz Hz ms ms ms ms ms ms µs µs ms ms ms ms dBm dBm dB dB % kΩ ns ns ns ns ns ns ns ns ns pF pF Symbol Min Typ* Max Units Rev. 1 www.clare.com 9 M-8888 AC Characteristics (Continued) Parameter DTMF Clock Crystal clock frequency Clock input rise time (external clock) Clock input fall time (external clock) Clock input duty cycle (external clock) Capacitive load, OSC2 fC tLHCL tHLCL DCCL CLO 3.5759 40 3.5795 50 3.5831 110 100 60 30 MHz ns ns % pF Symbol Min Typ* Max Units Voltages referenced to VSS unless otherwise noted. VDD = 5.0V ± 5%; VSS = 0 V; fC = 3.579545 MHz; TA = -40°C to +85°C *Typical values are for use as design aids only and are not guaranteed or subject to production testing. Notes: 1. dBm = decibels above or below a reference power of 1 mW into a 600 Ω load. 2. Digit sequence consists of all 16 DTMF tones. 3. Tone duration = 40 ms. Tone pause = 40 ms. 4. Nominal DTMF frequencies are used. 5. Both tones in the composite signal have an equal amplitude. 6. The tone pair is deviated by ± 1.5% ± 2 Hz. 7. Bandwidth limited (3 kHz) Gaussian noise. 8. The precise dial tone frequencies are 350 and 440 Hz (± 2%). 9. For an error rate of less than 1 in 10,000. 10. Referenced to the lowest amplitude tone in the DTMF signal. 11. Referenced to the minimum valid accept level. Electrical Characteristics - Gain Setting Amplifier Parameter Input leakage current (VSS ≤ VIN ≤ VDD) Input resistance Input offset voltage Power supply rejection (1 KHz) Common mode rejection (-3.0 V≤ VIN ≤ 3.0V) DC open-loop voltage gain Unity gain bandwidth Output voltage swing (RL ≥ 100 KΩ to VSS) Maximum capcitive load, GS Maximum resistive load, GS Common mode range (no load) Symbol IIN RIN VOS PSRR CMRR AVOL BW VO CL RL VCM Min - Typ* 100 10 25 60 60 65 1.5 4.5 100 50 3.0 Max - Units nA MΩ mV dB dB dB MHz VPP pF kΩ VPP All voltages referenced to VSS unless otherwise noted. VDD = 5.0V ± 5%; VSS = 0 V; fC = 3.579545 MHz; TA = -40°C to +85°C *Typical values are for use as design aids only, and are not guaranteed or subject to production testing. Timing Diagrams 10 www.clare.com Rev. 1 M-8888 Test Loads Timing Diagrams Rev. 1 www.clare.com 11 M-8888 Explanation of Events (A) Tone bursts detected, tone duration invalid, RX Data Register not updated. (B) Tone #n detected, tone duration valid, tone decoded and latched in RX Data Register. (C) End of tone #n detected, tone absent duration valid, RX Data Register remain latched until next valid tone. (D) Tone #n + 1 detected, tone duration valid, tone decoded and latched in RX Data Register. (E) Acceptable dropout of tone #n + 1, tone absent duration invalid, RX Data Register remain latched. (F) End of tone #n + 1 detected, tone absent duration valid, RX Data Register remain latched until next valid tone. Explanation of Symbols VIN ESt St/GT RX0-RX3 b3 b2 IRQ /CP tREC tREC tID tDO tDP tDA tGTP tGTA DTMF composite input signal. Early steering output. Indicates detection of valid tone frequencies. Steering input/guard time output. Drives external RC timing circuit. 4-bit decoded data in receive data register. Delayed steering output. Indicates that valid frequencies have been present/absent for the required guard time, thus constituting a valid DTMF signal. Output enable (input). A low level shifts Q1 - Q4 to its high impedance state. Interrupt is active indicating that new data is in the RX data register. The interrupt is cleared after the status register is ready. Maximum DTMF signal duration not detected as valid. Minimum DTMF signal duration required for valid recognition. Minimum time between valid DTMF signals. Maximum allowable dropout during valid DTMF signal. Time to detect the presence of valid DTMF signals. Time to detect the absence of valid DTMF signals. Guard time, tone present. Guard time, tone absent. 12 www.clare.com Rev. 1 M-8888 Package Dimensions Tolerances Inches Metric (mm) Min Max Min Max A A1 b b2 C D E E1 e ec L .210 .015 .014 .022 .045 .070 .008 .014 .980 1.060 .300 .325 .240 .280 .100 BSC 0° 15° .115 .150 5.33 .38 .36 .56 1.14 1.78 .20 .36 24.89 26.92 7.62 8.26 6.10 7.11 2.54 BSC 0° 15° 2.92 3.81 Tolerances Inches Metric (mm) Min Max Min Max A A1 b D E e H L .093 .104 .004 .012 .013 .020 .496 .512 .291 .299 .050 BSC .394 .419 .016 .050 2.35 2.65 .10 .30 .33 .51 12.60 13.00 7.39 7.59 1.27 BSC 10.00 10.65 .40 1.27 Dimensions mm (inches) Rev. 1 www.clare.com 13 Worldwide Sales Offices CLARE LOCATIONS Clare Headquarters 78 Cherry Hill Drive Beverly, MA 01915 Tel: 1-978-524-6700 Fax: 1-978-524-4900 Toll Free: 1-800-27-CLARE Clare Switch Division 4315 N. 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Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-M8888-R1 ©Copyright 2001, Clare, Inc. All rights reserved. Printed in USA. 7/26/01