CM6530N

CM6530N USB Audio Chip DESCRIPTION FEATURES The CM6530N is a low power USB 2.0 audio controller builds in 8051 for flexible applications. Accompany with ultra low power codec makes it suitable for low power headset, notebook/mobile docking and microphone applications. The internal 8051 can also be developed to different applications, such as Android Phone Accessories with special functions, such as HID buttons or LED control. The CM6530N is compatible with USB Audio Class 1.0 and USB 2.0 full-speed, Thus it can plug and play without additional software installation on the major operation systems. The I2S support 8~96 KHz sampling rate and 16/24bits resolution.  USB 2.0 full-speed compliant The CM6530N also integrates 512K Byte flash (Including 32KB F/W programming size) and just requires few passive components to make a finish product. Thus it can save the total BOM cost and PCB area can be smaller.  USB Audio Class 1.0 compliant  USB Human Interface Device (HID) Class 1.1 compliant  Two (2) channel I2S for audio output interface  Two (2) channel I2S for audio input interface  Supports Digital Microphone Interface  Built-in S/PDIF Input/output Interface  Supports USB suspend/resume/reset functions  Supports control, interrupt, bulk, and isochronous data transfers  Embedded 1T 8051 with 32K Byte SRAM and 512K Byte Flash (Including 32K Byte F/W programming size)  Integrated Tricolors PWM LED driver  Master/Slave hardware I2C/SPI/UART control interface for external audio devices or FLASH access  On chip watchdog timer  Support crystal and crystal-less mode BLOCK DIAGRAM 5 Band EQ Mux 2 Channel I2S In SPDIF In 2 Channel Digital MIC in Control Bus USB Interface 32K SRAM Internal 12M Hz Crystal MCU with 512K Byte Flash 4K ROM 5 Band EQ 2 Channel I2S Out SPDIF Out GPIO x 18 PWM LED X 3 Uart, I2C, SPI Page 1 / 47 www.cmedia.com.tw Copyright© C-Media Electronics Inc. CM6530N USB Audio Chip Release notes Revision 1.0 Page 2 / 47 Date 2016/12/15 Description First release. www.cmedia.com.tw Copyright© C-Media Electronics Inc. CM6530N USB Audio Chip TABLE OF CONTENTS Release notes .................................................................................................................................................. 2 TABLE OF CONTENTS ..................................................................................................................................... 3 1 Description and overview .......................................................................................................................... 6 2 Features ...................................................................................................................................................... 6 2.1 USB compliance ........................................................................................................................ 6 2.2 Integrated 8051 micro-processor ............................................................................................... 6 2.3 Control interface ........................................................................................................................ 6 2.4 General ....................................................................................................................................... 7 2.5 Audio I/O ................................................................................................................................... 7 3 4 5 Applications ............................................................................................................................................... 7 Pin assignment ........................................................................................................................................... 8 4.1 CM6530N Pin-out diagram........................................................................................................ 8 4.2 Pin description ........................................................................................................................... 9 Function description................................................................................................................................. 12 5.1 Playback Equalizer................................................................................................................... 12 5.1.1 5-band equalizer ............................................................................................................... 12 5.1.2 Four (4) Preset EQ Mode ................................................................................................. 14 5.2 Recording Equalizer................................................................................................................. 15 5.3 HID function ............................................................................................................................ 15 5.3.1 HID interrupt in................................................................................................................ 15 5.3.2 HID get_input_report ....................................................................................................... 16 5.3.3 HID set_output_report ..................................................................................................... 17 5.4 Vendor command definition ..................................................................................................... 18 5.4.1 Vender command read...................................................................................................... 18 5.4.2 Vender command write .................................................................................................... 18 5.4.3 USB vendor requests........................................................................................................ 18 5.4.4 Simple process of firmware update.................................................................................. 19 2 5.5 I S Control description ............................................................................................................. 20 5.5.1 I2S Interface setting .......................................................................................................... 20 5.5.2 Basic of I2S bus ................................................................................................................ 20 5.5.3 Left justified mode ........................................................................................................... 21 5.5.4 I2S Mode .......................................................................................................................... 21 5.5.5 I2S MCLK/BCLK/LRCK ratio and format for CM6530N .............................................. 22 5.5.6 I2S output enable setting and data stream path ................................................................ 23 5.5.7 Slave Mode Playback and Record ................................................................................... 23 5.6 SPDIF control description........................................................................................................ 24 5.6.1 SPDIF frame description.................................................................................................. 24 Page 3 / 47 www.cmedia.com.tw Copyright© C-Media Electronics Inc. CM6530N USB Audio Chip 5.6.2 5.7 5.8 SPDIF out channel status ................................................................................................. 26 Digital microphone .................................................................................................................. 27 I2C interface ............................................................................................................................. 28 5.8.1 I2C master mode ............................................................................................................... 28 5.8.2 I2C-master read with clk_sync mode .............................................................................. 29 5.8.3 I2C master device address and control register ................................................................ 29 5.8.4 I2C master memory address pointer (map) register ......................................................... 29 5.8.5 I2C master memory address pointer (map2) register ....................................................... 29 5.8.6 I2C master data register .................................................................................................... 29 5.8.7 I2C Master Control and Status Register 0 ........................................................................ 30 5.8.8 I2C master control and status register 1 ........................................................................... 30 5.8.9 5.8.10 5.8.11 I2C master download control and status register.............................................................. 30 I2C master clock period setting register ........................................................................... 31 I2C slave mode ................................................................................................................. 32 5.8.12 I2C slave data register ...................................................................................................... 32 5.8.13 I2C slave status register .................................................................................................... 32 5.8.14 I2C slave memory address pointer (map) register ............................................................ 33 5.8.15 I2C slave status register .................................................................................................... 33 5.9 SPI interface ............................................................................................................................. 35 5.9.1 SPI Registers Descriptions ............................................................................................... 35 5.9.2 SPI Control Register 0 ..................................................................................................... 35 5.9.3 SPI control register 1 ....................................................................................................... 36 5.9.4 SPI interrupt ..................................................................................................................... 36 5.9.5 SPI Control Register 3 ..................................................................................................... 37 5.10 GPIO ........................................................................................................................................ 38 5.10.1 GPO data register ............................................................................................................. 38 5.10.2 GPI data register .............................................................................................................. 38 5.10.3 GPIO direction control register ........................................................................................ 38 5.10.4 GPIO interrupt enable mask register................................................................................ 38 5.10.5 GPIO debouncing register................................................................................................ 38 5.10.6 GPI remote choose ........................................................................................................... 38 5.10.7 GPIO pull-up/down .......................................................................................................... 39 5.11 5.12 5.13 6 Arbitrary sine-tone generator ................................................................................................... 41 Tri-colored led control setting.................................................................................................. 42 Reset ......................................................................................................................................... 43 5.13.1 Watchdog reset timer ....................................................................................................... 43 Electrical characteristics .......................................................................................................................... 44 6.1 Absolute maximum ratings ...................................................................................................... 44 6.2 Recommended operation conditions ........................................................................................ 44 Page 4 / 47 www.cmedia.com.tw Copyright© C-Media Electronics Inc. CM6530N USB Audio Chip 6.3 7 Power consumption .................................................................................................................. 44 6.4 DC characteristics .................................................................................................................... 45 6.5 USB transceiver ....................................................................................................................... 45 Package dimension................................................................................................................................... 45 7.1 Package Dimension of CM6530N ........................................................................................... 46 Page 5 / 47 www.cmedia.com.tw Copyright© C-Media Electronics Inc. CM6530N USB Audio Chip 1 Description and overview The CM6530N is a low power USB 2.0 audio controller builds in 8051 for flexible applications. Accompany with ultra low power codec makes it suitable for low power headset, notebook/mobile docking and microphone applications. The internal 8051 can also be developed to different applications, such as Android Phone accessories with special functions, such as HID buttons or LED control. The CM6530N is compatible with USB Audio Class 1.0 and USB 2.0 full-speed, Thus it can plug and play without additional software installation on the major operation systems. The I2S support 8~96 KHz sampling rate and 16/24bits resolution. The CM6530N also integrates 512K Byte flash (Including 32KB F/W programming size) and just requires few passive components to make a finish product. Thus it can save the total BOM cost and PCB area can be smaller. 2 Features 2.1 USB compliance  USB 2.0 full-speed compliant  USB Audio Class 1.0 compliant  USB Human Interface Device (HID) Class 1.1 compliant  Supports USB suspend/resume/reset functions  Supports control, interrupt, bulk, and isochronous data transfers  Support Synchronous and Asynchronous audio data synchronization 2.2 Integrated 8051 micro-processor  Embedded 8051 micro-processor to handle the command/protocol transactions  Embedded 512K Byte SPI Flash(Including 32KB F/W programming size)  32K Byte RAM for firmware extension and plug-in  HID interrupts/buttons/functions can be implemented via firmware codes  Provides maximum hardware configuration flexibility with firmware code upgrade  VID/PID/Product String can be programmed by firmware 2.3 Control interface  Master/Slave I2C control interface, bus speed supports 100 and 400kbit/s  One 4-wire SPI mater / slave interface, bus speed supports from 150k to 12Mbit/s  Twelve (12) GPIO pins and firmware programmable.  JTAG debug interface  GPIOs are configured as HID key and LED indicators  Tri-color PWM LED Driver Page 6 / 47 www.cmedia.com.tw Copyright© C-Media Electronics Inc. CM6530N USB Audio Chip 2.4 General  CM6530N can auto detect and switch to crystal mode or none crystal mode. The power consumption for crystal mode is 8mA lower than non-crystal mode.  Single 5V power supply (embedded 5V to 1.8V regulator for digital core, 5V to 3.3V regulator for digital IO, 5V to 3.6V regulator for analog codec)  3.3V digital I/O pads with 5V tolerance  Industrial standard QFN-48 package (6.5mm x 5mm) 2.5 Audio I/O  Playback Stream:  I2S interface  Sample Rates: 8K/11.025K/16K/22.05K/32K/44.1K/48/88.2/96KHz  Supported Bit Length: 16/24 bits  S/PDIF transmitter  Sample Rates: 44.1K/48K/88.2K/96KHz  Supported Bit Length: 16/24 bits  Recording Stream:  I2S interface Sample Rates: 8K/11.025K/16K/22.05K/32K/44.1K/48K/96KHz  Supported Bit Length: 16/24 bits.  S/PDIF receiver  Sample Rates: 44.1K/48K/88.2K/96KHz  Supported Bit Length: 16/24 bits **Note: CM6530N is a USB 2.0 full-speed audio device. Since there is a bandwidth limitation, CM6530N cannot support 96 KHz/24bits for playback and capture streams simultaneously. The possible combinations are shown below: Playback Stereo, 96KHz/24bits Audio Format 3 Stereo, 48kHz/24bits or below Mono, 96KHz/24bits or below Capture Stereo, 48kHz/24bits or below Mono, 96KHz/24bits or below Stereo, 96KHz/24bits Applications  Low power USB Headset  Low power Notebook/Ultrabook Docking  Low power Android Phone/Tablet Docking  USB DAC, Headphone amplify  Low power USB Microphone Page 7 / 47 www.cmedia.com.tw Copyright© C-Media Electronics Inc. CM6530N USB Audio Chip 4 Pin assignment ADC_LRCK GPIO_3 SPDIF_I GPIO_5 SPDIF_O GPIO_4 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_21 DAC_LRCK DAC_DOUT 4.1 CM6530N Pin-out diagram 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 39 23 40 22 41 21 42 20 43 CM6530N 19 44 18 45 17 46 16 47 48 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AVDD50 DAC_MCLK DAC_BCLK VSS VSS USB_DP USB_DM DVDD50 VSS DVDD18 GPIO_2 GPIO_1 GPIO_0 GPIO_16 PDSW GPIO15 TEST GPIO_14 GPIO_13 I2C_SCLK I2C_SDAT XTAL_I XTAL_O DVDD33 ADC_DIN ADC_BCLK ADC_MCLK GPIO_7 GPIO_6 NC SPI_MISO SPI_MOSI SPI_CS0 SPI_SCK Page 8 / 47 www.cmedia.com.tw Copyright© C-Media Electronics Inc. CM6530N USB Audio Chip 4.2 Pin description Pin # Symbol I/O Description Clock 13 12 XTAL_O XTAL_I AO AI 12MHz crystal oscillator output 12MHz crystal oscillator input USB2.0 BUS Interface 19 18 USB_DP USB_DM AIO AIO USB 2.0 data plus (USB D+ signal) USB 2.0 data minus (USB D- signal) Power/Ground 14 15 17 24 16 20 21 DVDD33 DVDD18 DVDD50 AVDD50 VSS VSS VSS AO AO PWR PWR GND GND GND 23 DAC_MCLK DIO 22 DAC_BCLK DIO 25 DAC_DOUT DO 26 DAC_LRCK DIO 38 ADC_ LRCK DIO 39 ADC_ DIN DI 40 ADC_ BCLK DIO 41 ADC_ MCLK DIO 34 SPDIF_O DO 36 SPDIF_I DI Regulator 3.3V output, drive capacity 10mA Regulator 1.8V output, no current drive capacity 5V digital power for 5/3.3/1.8V regulator 5V analog power for 4.2/3.6V regulator Digital Ground Digital Ground Digital Ground Two (2)-channel I2S DAC Output Interface I2S out master clock Programmable 3.3V output buffer I2S out bit clock Programmable 3.3V bidirectional buffer Internal default pull-down I2S out serial data output Programmable 3.3V output buffer I2S out left/right clock Programmable 3.3V bidirectional buffer Internal default pull-down Two (2)-channel I2S ADC Input Interface I2S in left/right clock Programmable 3.3V bidirectional buffer Internal default pull-down I2S in serial data input Programmable 3.3V input buffer, Schmitt trigger Internal default pull-down I2S in bit clock Programmable 3.3V bidirectional buffer Internal default pull-down I2S in master clock Programmable 3.3V output buffer S/PDIF I/O S/PDIF transmitter SPDIF_O is an output buffer with 8mA Tri-state S/PDIF Receiver SPDIF_O is an input buffer with 8mA Tri-state GPIO 3 Page 9 / 47 GPIO_0 DIO General purpose input/output (default Volume Up button). 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input (JTAG-TCK) www.cmedia.com.tw Copyright© C-Media Electronics Inc. CM6530N USB Audio Chip 2 GPIO_1 DIO 1 GPIO_2 DIO 37 GPIO_3 DIO 33 GPIO_4 DIO 35 GPIO_5 DIO 43 GPIO_6 DIO 42 GPIO_7 DIO 32 GPIO_8 DIO 31 GPIO_9 DIO 30 GPIO_10 DIO 29 GPIO_11 DIO 28 GPIO_12 DIO 9 GPIO_13 DIO 8 GPIO_14 DIO Page 10 / 47 General purpose input/output (default Volume Down button). 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input (JTAG-TMS) General purpose input/output (default Play Mute button). 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input (JTAG-TDI) General purpose input/output (default Rec Mute button). 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input. Programmable 2 in 1 I/O interface. GPIO/PWM select by firmware. General purpose input/output (default PWM LED Blue). 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input. Programmable 2 in 1 I/O interface. GPIO/PWM select by firmware. General purpose input/output (default PWM LED Green). 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input. Programmable 2 in 1 I/O interface. GPIO/PWM select by firmware. General purpose input/output (default PWM LED Red). 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input (JTAG-TRST) General purpose input/output (JTAG-TDO). 3.3V I/O, 5V tolerance, There are 4 kinds of preset EQ, GPIO7 and 8 bidirectional buffer with 8mA are used to determine in which mode. The driving current, default EQ combinations are shown below. disable and weak pull-up for GPIO[8:7]=0,0: Normal mode input. GPIO[8:7]=0,1: Gaming mode General purpose input/output GPIO[8:7]=1,0: Communication mode 3.3V I/O, 5V tolerance, GPIO[8:7]=1,1: Movie mode bidirectional buffer with 8mA EQ function can enable via configuration driving current, Default EQ tool or firmware. disable and weak pull-up for input. General purpose input/output (default Rec Clip Indicator). 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input. Programmable 3 in 1 I/O interface. GPIO/Digital MIC Clock (DMIC_CLK)/ UART_RX select by firmware. GPIO (Default MIC Jack Detect): 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input. Programmable 3 in 1 I/O interface. GPIO/Digital MIC Data (DMIC_DAT)/ UART_TX select by firmware. GPIO (Default Headphone Jack Detect): 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input. General purpose input/output (default Rec Mute button). 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input. General purpose input/output (default Rec Mute button). 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input. General purpose input/output (default Rec Mute button). 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input. www.cmedia.com.tw Copyright© C-Media Electronics Inc. CM6530N USB Audio Chip 9 GPIO_15 DIO 4 GPIO_16 DIO 27 GPIO_21 DIO 45 SPI_MISO DIO 46 SPI_MOSI DIO 47 SPI_CS0 DIO 48 SPI_SCK DIO 11 I2C_SDAT DIO 10 I2C_SCLK DIO 5 PDSW DO 7 TEST DI 44 NC N.C. General purpose input/output (default Rec Mute button). 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input. General purpose input/output (default Rec Mute button). 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input. General purpose input/output (default Rec Mute button). 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input. 4-Wire SPI Serial Bus SPI data master in/slave out, 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, default weak pull-down for input. SPI data master out/slave in, 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, default weak pull-down for input. SPI chip select, 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input. SPI clock, 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, default weak pull-down for input. 2-Wire Serial Bus (I2C) 2-wire serial data, 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input. 2-wire serial clock, 3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current, Default weak pull-up for input. Miscellaneous Power Down Switch is an output buffer with 8mA Tri-state output. Normal mode: 0 Suspend mode: 1 The TEST pin is used for IC test, another one is in the instance when F/W crashes or USB was not recognized, set TEST pin to 3.3V before USB connect can force MCU into boot loader mode and be able to update F/W via configuration tool, default weak pull-down for input. 1: Boot loader mode 0 : Normal operation No Connection. **Note1: GPIOs, I2C, SPI, SPDIF, PDSW, NC, RESETN pins can be left floating if not in use. **Note2: Suggest connect TEST pin to GND by default setting. Page 11 / 47 www.cmedia.com.tw Copyright© C-Media Electronics Inc. CM6530N USB Audio Chip 5 Function description 5.1 Playback Equalizer 5.1.1 5-band equalizer CM6530N has integrated five (5)-band hardware digital equalizer (EQ) engine inside the chips to fulfill various application usages. It provides up to four (4)-preset modes on client’s product design for different user scenarios including default/music, movies, gaming and communication modes. Clients could also change the gain parameters for each of the preset application EQ mode via embedded FLASH coding. Also, the EQ engine could also be utilized for compensating and fine-tuning the headphone driver for Sound Pressure Level (SPL) performance to a specific preference. In this case, clients could fully customize all EQ coefficients such as center frequency, gain values, and bandwidth to one optimized frequency response curve and setting in terms of the headphone driver and housing’s acoustics characteristics, also via embedded FLASH programming. Digital Equalizer Digital PCM Attenuation PCM (5-Band Fc, Gain, Digital-Analog PCM Bandwidth, OPA Gain) -Converter Analog Analog Analog Gain Gain The EQ engine contains five (5) frequency bands (Fc) of digital filters to conduct transfer functions of the frequency response over the audio band. It allows maximum +-12dB digital gain (Gain) for each band with 0.5dB adjustment per step. Each filter will have its bandwidth (BW) factor between 0 and 1.0. Fc: Center Frequency, F1~F5, 20