CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
DESCRIPTION
FEATURES
The CM6533/CM6533N/CM6533X1/CM6533DH is a
USB 2.0 audio chip built-in 8051 for flexible
applications. With integrated Tri-Colors PWM LED
driver and two (2)-channel ADC/DAC and S/PDIF
interface that makes it suitable for headset,
docking, speaker and microphone applications.
The internal 8051 can also be developed to a lot of
different applications, such as Microsoft™ Lync /
Skype/VoIP device, Android Phone or Tablet/Slate
docking device. The CM6533 /CM6533N /CM6533X1
/CM6533DH is compatible with USB Audio Class 1.0
and USB 2.0 Full-Speed, thus it can plug & play
without any additional software installation on
major operating systems. The internal DAC and
ADC support from 8 ~ 96 KHz sampling rate and
16/24 bits resolution.
USB 2.0 Full-Speed compliant
The CM6533/CM6533N/CM6533X1/CM6533DH
integrates equalizer on both playback and
recording paths to compensate the frequency
response of microphone and headphone.
Embedded 1T 8051 with 32K Byte SRAM and 256K Byte
flash(Including 32KB F/W programming size)
The CM6533/CM6533N/CM6533X1/CM6533DH also
integrates 256K Byte flash (Including 32KB F/W
programming size) and crystal but requires few
passive components to make a finish product.
Thus, it can save the total BOM cost and PCB area
can be smaller.
Master/Slave H/W I2C/SPI/UART control interface for
external audio devices or FLASH access
USB Audio Class 1.0 compliant
USB Human Interface Device (HID) Class 1.11 compliant
Two (2)-channel DAC for audio output interface
Two (2)-channel ADC for audio input interface
Supports Digital Microphone interface
Built-in S/PDIF transmitter
Built-in Equalizer on both playback and recording paths
Built-in AGC (Auto Gain Control) on recording path
Supports dual tone generator
Supports USB suspend/resume/reset functions
Supports control, interrupt, bulk, and isochronous data
transfers
Supports OMTP and CTIA auto switch on a 4-pole jack
Integrated Tri-Colors PWM LED driver
Supports embedded oscillator without external crystal
Built-in 30mW @ R=32 headphone amplifier
On chip watchdog timer
BLOCK DIAGRAM
Analog Gain
-18 ~ 45dB
(1dB/step)
Digital Gain
-16 ~ 12dB
(1dB/step)
AGC
USB
Interface
ADC
Mux
Microphone In
5-Band EQ
Analog Gain
-30 ~ 33dB
(1dB/step)
Control Bus
32KB SRAM
+12dB
Internal Clock
ROM(4KB)
MCU with
256KB Flash
Digital Gain
-62 ~ 0dB
(1dB/step)
DAC
Analog Gain
-15 ~ 32dB
(1dB/step)
Analog Gain
-44 ~ 0dB (1dB/step)
Speaker/
Heaphone
5-Band EQ
SPDIF Out
GPIO x 12
PWM LED X 3
Uart, I2C, SPI
Page 1 / 60
Rev.1.7
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
Release Notes
Revision
1.0
1.1
Date
2014/07/08
2014/08/05
1.2
2014/09/18
1.3
2014/09/19
1.4
2015/3/30
1.5
2015/08/07
1.6
2015/10/29
1.7
2018/08/27
Page 2 / 60
Rev.1.7
Description
First release.
Modify F/W volume setting table(CH2.6).
1. Modify Pin descriptions.
2. Modify Pin out diagram.
1. Modify MIC_SWOUT to AO pin.
2. Modify power consumption for 12MHz MCU Clock.
3. Modify Reset diagram of CH6.13.
4. Separate CM6533/CM6533X1/CM6533DH Pin out diagram.
5. Modify flash description: 256K Byte flash(Including 32KB F/W programming
size).
1. Remove Microphone input impedance chart.
2. Add Xear and Dolby software function descriptions.(CH7,CH8)
3. Modify Operating ambient temperature to -15~70 oC.
4. Modify CH5.1 CH5.2 USB Topology chart.
5. Modify Block Diagram (Page1).
6. Add Cap-less cross talk performance.
7. Add CM6533N QFN Package.
1. Modify CH6.7 Digital microphone descriptions.
1. Modify I2C Using Example.
2. Modify SPI Using Example.
3. Modify TEST pin description.
1. Modify UART TX/RX pin description
2. Correct I2C timing diagram.
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
TABLE OF CONTENTS
Release Notes .................................................................................................. 2
TABLE OF CONTENTS........................................................................................... 3
1 Description and Overview ............................................................................... 6
2 Features.................................................................................................... 6
2.1
USB Compliance ................................................................................ 6
2.2
Integrated 8051 Microprocessor ............................................................. 6
2.3
Control Interface .............................................................................. 6
2.4
General .......................................................................................... 6
2.5
Audio I/O........................................................................................ 7
3
4
5
6
2.6
General Firmware Volume Setting Value ................................................... 8
2.7
CM6533/CM6533N/CM6533X1/CM6533DH Compared Table .............................. 8
Applications ............................................................................................... 9
Pin Assignment ...........................................................................................10
4.1
CM6533 Pin-out Diagram (LQFP48) .........................................................10
4.2
CM6533N Pin-out Diagram (QFN48) ........................................................11
4.3
CM6533X1 Pin-out Diagram (LQFP48) ......................................................12
4.4
CM6533DH Pin-out Diagram (LQFP48) ......................................................13
4.5
Pin Description ................................................................................14
4.6
Pin Circuit Diagrams ..........................................................................17
USB Audio Topology ......................................................................................18
5.1
CM6533N/CM6533 Headset Topology .......................................................18
5.2
CM6533X1/CM6533DH Headset Topology ..................................................19
Function Description ....................................................................................20
6.1
Playback Equalizer ...........................................................................20
6.1.1
5-band equalizer ........................................................................20
6.1.2
Four (4) Preset EQ Mode................................................................22
6.2
Recording Equalizer ..........................................................................23
6.3
Recording AGC.................................................................................23
6.4
HID Function ...................................................................................25
6.4.1
HID Interrupt in ..........................................................................25
6.4.2
HID get_input_report ...................................................................26
6.4.3
HID set_output_report ..................................................................27
6.5
Vendor Command Definition ................................................................28
6.5.1
Vendor Command Read .................................................................28
6.5.2
Vendor Command Write ................................................................28
6.5.3
USB Vendor Requests....................................................................28
6.5.4
Simple Process of Firmware Update ..................................................29
Page 3 / 60
Rev.1.7
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6.6
SPDIF Control Description ...................................................................29
6.6.1
SPDIF Frame Description ...............................................................29
6.6.2
SPDIF Out Channel Status ..............................................................31
6.7
Digital Microphone ............................................................................32
6.8
I2C Interface...................................................................................33
6.8.1
I2C Master Mode .........................................................................33
6.8.2
I2C-Master Read with clk_sync mode .................................................34
6.8.3
I2C Master Device Address and Control Register ....................................34
6.8.4
I2C Master Memory Address Pointer (MAP) Register ................................34
6.8.5
I2C Master Memory Address Pointer (MAP2) Register ...............................34
6.8.6
I2C Master Data Register ...............................................................35
6.8.7
I2C Master Control and Status Register 0 ............................................35
6.8.8
6.8.9
6.8.10
6.8.11
6.8.12
6.8.13
6.8.14
6.8.15
6.9
SPI
6.9.1
I2C Master Control and Status Register 1 ............................................35
I2C Master Download Control and Status Register ..................................36
I2C Master Clock Period Setting Register ............................................37
I2C Slave Mode ...........................................................................38
I2C Slave Data Register .................................................................38
I2C Slave Status Register ...............................................................38
I2C Slave Memory Address Pointer(MAP) Register...................................39
I2C Slave Status Register ...............................................................39
Interface ...................................................................................41
SPI Registers Descriptions ..............................................................41
6.9.2
SPI Control Register 0 ...................................................................41
6.9.3
SPI Control Register 1 ...................................................................42
6.9.4
SPI Interrupt .............................................................................42
6.9.5
SPI Control Register 3 ...................................................................43
6.10
GPIO ............................................................................................44
6.10.1 GPO Data Register .......................................................................44
6.10.2 GPI Data Register ........................................................................44
6.10.3 GPIO Direction Control Register .......................................................44
6.10.4 GPIO Interrupt Enable Mask Register .................................................44
6.10.5 GPIO Debouncing Register .............................................................44
7
6.10.6 GPI Remote Choose .....................................................................45
6.10.7 GPIO Pull-up/Down .....................................................................45
6.11
Arbitrary Sine-tone Generator ..............................................................47
6.12
Tri-Colored LED Control Setting ............................................................48
6.13
Reset ............................................................................................49
6.13.1 Watchdog Reset Timer ..................................................................49
CM6533X1 Xear™ Sound Processing....................................................................50
7.1
Xear™ Surround Headphone .................................................................50
Page 4 / 60
Rev.1.7
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
7.2
8
9
Xear™ Software 10 Band Equalizer .........................................................50
7.3
Xear™ Audio Brilliant .........................................................................50
7.4
Xear™ Dynamic Bass ..........................................................................50
7.5
Xear™ Voice Clarity ...........................................................................50
7.6
Xear™ Smart Volume .........................................................................50
7.7
Xear™ Surround Max ..........................................................................50
7.8
Xear™ Magic Voice ............................................................................50
7.9
Xear™ Environmental Noise Cancellation .................................................51
CM6533DH Dolby® and Xear™ Sound Processing ....................................................51
8.1
Dolby® Headphone v2 ........................................................................51
8.2
Dolby® Pro Logic IIx ..........................................................................51
8.3
Xear™ Environment Effect ...................................................................51
8.4
Xear™ Software 10 Band Equalizer .........................................................51
8.5
Xear™ Magic Voice ............................................................................51
Electrical Characteristics ...............................................................................52
9.1
Absolute Maximum Ratings ..................................................................52
9.2
Recommended Operation Conditions ......................................................52
9.3
Power Consumption ..........................................................................52
9.4
DC Characteristics ............................................................................52
9.5
Analog Audio ...................................................................................53
9.6
USB Transceiver ...............................................................................53
9.7
Microphone Bias ...............................................................................53
10
Audio Performance .................................................................................54
10.1
DAC Audio Quality ............................................................................54
10.2
ADC Audio Quality ............................................................................55
10.3
Analog Monitoring / Sidetone (A-A ) Path Audio Quality ................................56
11
Package Dimension .................................................................................57
11.1
Package Dimension of CM6533/6533X1/6533DH .........................................58
11.2
Package Dimension of CM6533N ............................................................59
Page 5 / 60
Rev.1.7
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
1 Description and Overview
The CM6533/CM6533N/CM6533X1/CM6533DH is a USB 2.0 audio chip built-in 8051 for flexible applications. With
integrated Tri-Colors PWM LED driver and two (2)-channel ADC/DAC and S/PDIF interface makes it suitable for
headset, docking, speaker and microphone applications. The internal 8051 can also be developed to a lot of different
applications, such as Microsoft™ Lync/Skype/VoIP device, Android Phone or Tablet/Slate docking device. The
CM6533/CM6533N/CM6533X1/CM6533DH is compatible with USB Audio Class 1.0 and USB 2.0 Full-Speed, thus it can
plug & play without any additional software installation on major operating systems. The internal DAC and ADC
support from 8 ~ 96 KHz sampling rate and 16/24 bits resolution. The hardware of CM6533, CM6533N, CM6533X1 and
CM6533DH are all the same and they only differ in firmware and software.
The CM6533/CM6533N/CM6533X1/CM6533DH integrates equalizer on both playback and recording paths to
compensate the frequency response of microphone and headphone.
The CM6533/CM6533N/CM6533X1/CM6533DH also integrates 256K Byte flash(Including 32KB F/W programming size)
and crystal but requires few passive components to make a finish product. Thus, it can save the total BOM cost and
PCB area can be smaller.
2 Features
2.1 USB Compliance
USB 2.0 Full-Speed compliant
USB Audio Class 1.0 compliant
USB Human Interface Device (HID) Class 1.1 compliant
Supports USB suspend/resume/reset functions
Supports control, interrupt, bulk, and isochronous data transfers and overview
2.2 Integrated 8051 Microprocessor
Embedded 8051 micro-processor to handle the command/protocol transactions
Embedded 256K Byte SPI Flash(Including 32KB F/W programming size)
32K Byte RAM for firmware extension and plug-in
HID interrupts/buttons/functions can be implemented via firmware codes
Provides maximum hardware configured flexibility with firmware code upgrade
VID/PID/Product String can program by firmware
2.3 Control Interface
Master/Slave I2C control interface, bus speed supports 100 and 400kbit/s
One 4-wire SPI mater/slave interface, bus speed supports from 150k to 12Mbit/s
12 GPIO pins and firmware programmable
JTAG debug interface
GPIOs are configured as HID key and LED indicators
Tri-Colors PWM LED Driver
2.4 General
Crystal-less (embedded crystal function)
Page 6 / 60
Rev.1.7
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
Single 5V power supply (embedded 5V to 1.8V regulator for digital core, 5V to 3.3V regulator for digital IO, 5V to
3.6V regulator for analog codec)
3.3V digital I/O pads with 5V tolerance
Industrial standard LQFP-48 package (7x7mm)
2.5 Audio I/O
Playback Stream:
Speaker/Headphone
Sample Rates: 8K/11.025K/16K/22.05K/32K/44.1K/48K/88.2K/96KHz
Supports Bit Length: 16/24bits
Speaker Gain Range (Analog) is -44 ~ 0dB, 1dB/step
DAC Gain Range (Digital) is -62 ~ 0dB, 1dB/step
S/PDIF transmitter
Sample Rates: 44.1K/48K/88.2K/96KHz
Supports Bit Length: 16/24 bits
Recording Stream:
Microphone
Sample Rates: 8K/11.025K/16K/22.05K/32K/44.1K/48K/88.2k/96KHz
Supports Bit Length: 16/24 bits
Microphone gain range (Analog) is -18 ~ 45dB, 1dB/step
ADC gain range (Digital) is -16 ~ 12dB, 1dB/step
Stereo Mixer
Mix stereo playback stream and stereo microphone
Stereo Mixer gain range is -30 ~ 33dB, 1dB/step
A-A path Stream:
Microphone to playback A-A path
Mix mono microphone input to stereo playback both L/R channel
The Microphone A-A path gain range is -15 ~ 32dB, 1dB/step
**Note 1: A-A path means Analog to Analog Mixer path
**Note 2:
CM6533/CM6533N/CM6533X1/CM6533DH is a USB 2.0 Full Speed audio device. Since bandwidth limitation,
CM6533/CM6533N/CM6533X1/CM6533DH cannot support 96KHz/24bits for playback and capture streams
simultaneously. The possible combinations are shown below:
Playback
Stereo, 96KHz/24bits
Audio Format
Page 7 / 60
Rev.1.7
Stereo, 48kHz/24bits or below
Mono, 96KHz/24bits or below
Capture
Stereo, 48kHz/24bits or below
Mono, 96KHz/24bits or below
96KHz/24bits
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
2.6 General Firmware Volume Setting Value
The CM6533/CM6533N/CM6533X1/CM6533DH is a MCU base USB Audio Device; the default topology is different from
its hardware capability.
Please refer to chapter 5.1 and 5.2 for the CM6533/CM6533N/CM6533X1/CM6533DH default topology while below the
gain volume range.
Device
Speaker
Microphone in recording Volume
Microphone A-A path (playback)
Minimum
-45dB(Mute)
0dB
-15dB(Mute)
Maximum
0dB
+30dB
+22dB
Default
-10dB
+20dB
0dB
dB/Step
1dB
1dB
1dB
2.7 CM6533/CM6533N/CM6533X1/CM6533DH Compared Table
The pin out of CM6533, CM6533N, CM6533X1 and CM6533DH are all the same and they only differ in firmware,
software and package.
Package
Firmware
Jack Detection
Xear™ Surround HP
Dolby® Headphone
Software
CM6533N
QFN48
Optional Jack
Detection
●
---
CM6533
LQFP48
Optional Jack
Detection
●
---
CM6533X1
LQFP48
CM6533DH
LQFP48
--
--
-●
--●
For the detailed firmware and software information, please refer to its corresponding spec.
Software Functions:
CM6533X1 Xear™ Sound Processing
Xear™ Surround Headphone
Xear™ Software 10 Band Equalizer
Xear™ Audio Brilliant
Xear™ Dynamic Bass
Xear™ Voice Clarity
Xear™ Smart Volume
Xear™ Surround Max
Xear™ Magic Voice
Xear™ Environmental Noise Cancellation
CM6533DH Dolby® and Xear™ Sound Processing
Dolby® Headphone v2
Dolby Pro Logic® IIx
Xear™ Environment Effect
Xear™ Software 10 Band Equalizer
Xear™ Magic Voice
Page 8 / 60
Rev.1.7
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
3 Applications
USB Headset/Gaming Headset
Microsoft™ Lync/Skype VoIP Headset
Notebook/Netbook Docking
Android Phone/Slate Docking
USB Speaker
USB Microphone
Page 9 / 60
Rev.1.7
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
4 Pin Assignment
SPDIF_O
GPIO_8
GPIO_9
GPIO_10
GPIO_11
AV36_DAR
LOUTR
AGND_DAR
LOCOM
AGND_DAL
LOUTL
AV36_DAL
4.1 CM6533 Pin-out Diagram (LQFP48)
AV42_DA
AVDD50
AVDD36
AGND
MBIASR_SLEEVE
MICR_RING2
MIC_SWOUT
VAG
MBIASL
MICL
VOLADJ
AGND
GPIO_0
PDSW
TEST
I2C_SCLK
I2C_SDAT
VSS
USB_DP
USB_DM
DVDD33
DVDD18
DVDD50
VSS
GPIO_5
GPIO_4
GPIO_3
GPIO_7
GPIO_6
VSS
SPI_MISO
SPI_MOSI
SPI_CS0
SPI_SCK
GPIO_2
GPIO_1
36 35 34 33 32 31 30 29 28 27 26 25
37
24
23
38
22
39
21
40
41
20
42
19
CM6533
43
18
44
17
45
16
46
15
47
14
48
13
10
11
12
1 2 3 4 5 6 7 8 9
Page 10 / 60
Rev.1.7
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
SPDIF_O
GPIO_8
GPIO_9
GPIO_10
GPIO_11
AV36_DAR
LOUTR
AGND_DAR
LOCOM
AGND_DAL
LOUTL
AV36_DAL
4.2 CM6533N Pin-out Diagram (QFN48)
AV42_DA
AVDD50
AVDD36
AGND
MBIASR_SLEEVE
MICR_RING2
MIC_SWOUT
VAG
MBIASL
MICL
VOLADJ
AGND
GPIO_0
PDSW
TEST
I2C_SCLK
I2C_SDAT
VSS
USB_DP
USB_DM
DVDD33
DVDD18
DVDD50
VSS
GPIO_5
GPIO_4
GPIO_3
GPIO_7
GPIO_6
VSS
SPI_MISO
SPI_MOSI
SPI_CS0
SPI_SCK
GPIO_2
GPIO_1
36 35 34 33 32 31 30 29 28 27 26 25
37
24
23
38
22
39
21
40
41
20
42
19
CM6533N
43
18
44
17
45
16
46
15
47
14
48
13
10
11
12
1 2 3 4 5 6 7 8 9
Page 11 / 60
Rev.1.7
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
SPDIF_O
GPIO_8
GPIO_9
GPIO_10
GPIO_11
AV36_DAR
LOUTR
AGND_DAR
LOCOM
AGND_DAL
LOUTL
AV36_DAL
4.3 CM6533X1 Pin-out Diagram (LQFP48)
AV42_DA
AVDD50
AVDD36
AGND
MBIASR_SLEEVE
MICR_RING2
MIC_SWOUT
VAG
MBIASL
MICL
VOLADJ
AGND
GPIO_0
PDSW
TEST
I2C_SCLK
I2C_SDAT
VSS
USB_DP
USB_DM
DVDD33
DVDD18
DVDD50
VSS
GPIO_5
GPIO_4
GPIO_3
GPIO_7
GPIO_6
VSS
SPI_MISO
SPI_MOSI
SPI_CS0
SPI_SCK
GPIO_2
GPIO_1
36 35 34 33 32 31 30 29 28 27 26 25
37
24
23
38
22
39
21
40
41
20
42
19
CM6533X1
43
18
44
17
45
16
46
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
Page 12 / 60
Rev.1.7
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
SPDIF_O
GPIO_8
GPIO_9
GPIO_10
GPIO_11
AV36_DAR
LOUTR
AGND_DAR
LOCOM
AGND_DAL
LOUTL
AV36_DAL
4.4 CM6533DH Pin-out Diagram (LQFP48)
AV42_DA
AVDD50
AVDD36
AGND
MBIASR_SLEEVE
MICR_RING2
MIC_SWOUT
VAG
MBIASL
MICL
VOLADJ
AGND
GPIO_0
PDSW
TEST
I2C_SCLK
I2C_SDAT
VSS
USB_DP
USB_DM
DVDD33
DVDD18
DVDD50
VSS
GPIO_5
GPIO_4
GPIO_3
GPIO_7
GPIO_6
VSS
SPI_MISO
SPI_MOSI
SPI_CS0
SPI_SCK
GPIO_2
GPIO_1
36 35 34 33 32 31 30 29 28 27 26 25
37
24
23
38
22
39
21
40
41
20
42
19
CM6533DH
43
18
44
17
45
16
46
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
Page 13 / 60
Rev.1.7
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
4.5 Pin Description
Pin #
Symbol
I/O
7
8
USB_DP
USB_DM
AIO
AIO
9
10
11
22
23
24
25
31
6
12
42
13
21
27
29
DVDD33
DVDD18
DVDD50
AVDD36
AVDD50
AV42_DA
AV36_DAL
AV36_DAR
VSS
VSS
VSS
AGND
AGND
AGND_DAL
AGND_DAR
AO
AO
PWR
AO
PWR
AO
AO
AO
GND
GND
GND
GND
GND
GND
GND
18
MIC_SWOUT
AO
15
19
16
20
17
26
MICL
MICR_RING2
MBIASL
MBIASR_SLEEVE
VAG
LOUTL
AI
AI
AO
AO
AO
AO
28
LOCOM
AO
30
LOUTR
AO
14
VOLADJ
AI
36
SPDIF_O
DO
1
GPIO_0
DIO
48
GPIO_1
DIO
47
GPIO_2
DIO
Page 14 / 60
Rev.1.7
Description
USB2.0 BUS Interface
USB 2.0 data positive (USB D+ signal).
USB 2.0 data negative (USB D- signal).
Power/Ground
Regulator 3.3V output, drive capacity 10mA.
Regulator 1.8V output, no current drive capacity.
5V digital power for 5/3.3/1.8V regulator.
Analog 3.6V regulator for ADC, no current drive capacity.
5V analog power for 4.2/3.6V regulator.
Analog 4.2V regulator for Analog 3.6V regulator, no current drive capacity.
Analog 3.6V regulator for DAC left channel, no current drive capacity.
Analog 3.6V regulator for DAC right channel, no current drive capacity.
Digital Ground.
Digital Ground.
Digital Ground.
Analog Ground.
Analog Ground.
Analog Ground.
Analog Ground.
Audio Interface
Combo jack detect and auto switch, detect combo jack type and switch to
MICR_RING2 or MBIASR_SLEEVE.
Microphone in left channel.
Microphone in right channel or combo jack Ring2 pin input.
Microphone bias (2.75V) for Left channel.
Microphone bias (2.75V) for Right channel or combo jack Sleeve pin input.
Voltage reference cap filter.
Line out left channel.
Line out common reference for cap-less connection.
Suggested connections:
Cap-less: 10uF
None use: floating
Line out right channel.
Analog control voltage input for playback volume control.
SAR ADC digital input range:
SARAD
000000:Maxium------27.3mV
111111:Minium-------1.75V
(27.3mV/1step)
S/PDIF I/O
S/PDIF transmitter
SPDIF_O is an output buffer with 8mA Tri-state.
GPIO
General purpose input/output (default Volume Up button).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input. (JTAG-TCK)
General purpose input/output (default Volume Down button).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input. (JTAG-TMS)
General purpose input/output (default Play Mute button).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input. (JTAG-TDI)
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
39
GPIO_3
DIO
38
GPIO_4
DIO
37
GPIO_5
DIO
41
GPIO_6
DIO
40
GPIO_7
DIO
35
GPIO_8
DIO
34
GPIO_9
DIO
33
GPIO_10
DIO
32
GPIO_11
DIO
43
SPI_MISO
DIO
44
SPI_MOSI
DIO
45
SPI_CS0
DIO
46
SPI_SCK
DIO
5
I2C_SDAT
DIO
Page 15 / 60
Rev.1.7
General purpose input/output (default Rec Mute button).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
Programmable 2 in 1 I/O interface. GPIO / PWM select by firmware.
General purpose input/output (default PWM LED Blue).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
Programmable 2 in 1 I/O interface. GPIO / PWM select by firmware.
General purpose input/output (default PWM LED Green).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
Programmable 2 in 1 I/O interface. GPIO / PWM select by firmware.
General purpose input/output (default PWM LED Red).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input. (JTAG-TRST)
General purpose input/output
There are 4 kinds of preset EQ, GPIO7
(JTAG-TDO).
and 8 are used to determine in which
3.3V I/O, 5V tolerance,
mode. The combinations are shown
bidirectional buffer with 8mA
below.
driving current, Default EQ disable GPIO[8:7]=0,0: Normal mode
and weak pull-up for input.
GPIO[8:7]=0,1: Gaming mode
GPIO[8:7]=1,0: Communication mode
General purpose input/output
GPIO[8:7]=1,1: Movie mode
3.3V I/O, 5V tolerance,
EQ function can enable via configuration
bidirectional buffer with 8mA
driving current, Default EQ disable tool or firmware.
and weak pull-up for input.
General purpose input/output (default Rec Clip Indicator).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
Programmable 3 in 1 I/O interface. GPIO / Digital MIC Clock (DMIC_CLK) /
UART_RX select by firmware.
GPIO (Default MIC Jack Detect):
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
Programmable 3 in 1 I/O interface. GPIO / Digital MIC Data (DMIC_DAT) /
UART_TX select by firmware.
GPIO (Default Headphone Jack Detect):
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
4-Wire SPI Serial Bus
SPI data master in/slave out,
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-down for input.
SPI data master out/slave in,
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-down for input.
SPI chip select,
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
SPI clock,
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-down for input.
2-Wire Serial Bus (I2C)
2-wire serial data,
3.3V I/O, 5V tolerant, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
www.cmedia.com.tw
Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
4
I2C_SCLK
DIO
2
PDSW
DO
3
TEST
DI
2-wire serial clock,
3.3V I/O, 5V tolerant, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
Miscellaneous
Power Down Switch is an output buffer with 8mA Tri-state output.
Normal mode: 0
Suspend mode: 1
The TEST pin is used for IC test, another one is in the situation when F/W
was crash or USB was not recognized, Set TEST pin to 3.3V before USB
connect can force MCU into boot loader mode and able to update F/W via
configuration tool, Default weak pull-down for input.
1: Boot loader mode
0: Normal operation
**Note1: GPIOs, I2C, SPI, SPDIF, MIC_SWOUT, MICL, MICR_RING2, MBIASL, MBIASR_SLEEVE, VAG, LOUTL, LOCOM,
LOUTR, VOLADJ, PDSW pins can be left floating if not in use.
**Note2: Suggest connect TEST pin to GND by default setting.
Page 16 / 60
Rev.1.7
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
4.6 Pin Circuit Diagrams
VAG, MIC_BAIS
VAG
AGND
VSS
Analog input pins LINE, MIC
ADC
AGND
Output pins LOUTL, LOUTR
LOUT_n
AGND
Output pins LOUTL, LOUTR
VDD
VREG
VSS
Page 17 / 60
Rev.1.7
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
5 USB Audio Topology
5.1 CM6533N/CM6533 Headset Topology
USB
Streaming
Interface #1
01
Mute Control
Volume Control
-45dB(Mute) ~ 0dB
Mixer
08
05
IT
03
OT
Speaker
2CH Out
07
02
Microphone
2CH In
Mute Control
Volume Control
0dB ~ 30dB
Mute Control
Volume Control
-15dB(Mute) ~ 22dB
04
06
IT
OT
USB Streaming
Interface #2
USB Interfaces List
Interface Description
Endpoint
Interface 0
Audio Control Interface
Interface 1
Audio Stream Interface for Playback
0x01
Interface 2
Audio Stream Interface for Record
0x82
Interface 3
HID Interface
0x87(Interrupt In 16 bytes)
Audio Stream Interfaces’ Alternate Setting List
Interface 1
(Speaker)
Interface 2
(MIC In)
Page 18 / 60
Rev.1.7
Alt 1
2CH, 16Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 2
2CH, 24Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 3
2CH, 16Bits PCM
88.2K,96K
Alt 4
2CH, 24Bits PCM
88.2K,96K
Alt 1
2CH, 16Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 2
2CH, 24Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 3
2CH, 16Bits PCM
88.2K,96K
Alt 4
2CH, 24Bits PCM
88.2K,96K
www.cmedia.com.tw
Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
5.2 CM6533X1/CM6533DH Headset Topology
USB
Streaming
Interface #1
01
Mute Control
Volume Control
-45dB(Mute) ~ 0dB
Mixer
08
05
IT
03
OT
Speaker
2CH Out
07
02
Microphone
2CH In
Mute Control
Volume Control
0dB ~ 30dB
Mute Control
Volume Control
-15dB(Mute) ~ 22dB
04
06
IT
OT
USB Streaming
Interface #2
USB Interfaces List
Interface Description
Endpoint
Interface 0
Audio Control Interface
Interface 1
Audio Stream Interface for Playback
0x01
Interface 2
Audio Stream Interface for Record
0x82
Interface 3
HID Interface
0x87 (Interrupt In 16 bytes)
Audio Stream Interfaces’ Alternate Setting List
Interface 1
(Speaker)
Interface 2
(MIC In)
Page 19 / 60
Rev.1.7
Alt 1
2CH, 16Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 2
2CH, 24Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 3
2CH, 16Bits PCM
88.2K,96K
Alt 4
2CH, 24Bits PCM
88.2K,96K
Alt 5
2CH, 16Bits AC3
44.1K,48K
Alt 1
2CH, 16Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 2
2CH, 24Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 3
2CH, 16Bits PCM
88.2K,96K
Alt 4
2CH, 24Bits PCM
88.2K,96K
www.cmedia.com.tw
Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6 Function Description
6.1 Playback Equalizer
6.1.1 5-band equalizer
CM6533/CM6533N/CM6533X1/CM6533DH has integrated five (5)-band hardware digital equalizer (EQ) engine inside
the chips to fulfill various application usages. It provides up to four (4)-preset modes on client’s product design for
different user scenarios including default/music, movies, gaming and communication modes. Clients could also
change the gain parameters for each of the preset application EQ mode via embedded FLASH coding. Also, the EQ
engine could also be utilized for compensating and fine-tuning the headphone driver for Sound Pressure Level (SPL)
performance to a specific preference. In this case, clients could fully customize all EQ coefficients such as center
frequency, gain values, and bandwidth to one optimized frequency response curve and setting in terms of the
headphone driver and housing’s acoustics characteristics, also via embedded FLASH programming.
Digital Equalizer
Digital
PCM
Attenuation
PCM
(5-Band Fc, Gain,
Digital-Analog
PCM
Bandwidth, OPA Gain)
-Converter
Analog
Analog
Analog
Gain
Gain
The EQ engine contains five (5) frequency bands (Fc) of digital filters to conduct transfer functions of the frequency
response over the audio band. It allows maximum +-12dB digital gain (Gain) for each band with 0.5dB adjustment per
step. Each filter will have its bandwidth (BW) factor between 0 and 1.0.
Fc: Center Frequency, F1~F5, 20
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