CMI8788

OxygenTMHD CMI8788 High Performance PCI Audio Processor Data Sheet v0.6 2005/09/12 C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 NOTICES THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, DOCUMENT OR SAMPLE. ALL RIGHTS RESERVED. NO PART OF THIS DOCUMENT MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS, ELECTRONIC OR MECHANICAL, INCLUDING INFORMATION STORAGE AND RETRIEVAL SYSTEMS, WITHOUT PERMISSION IN WRITING FROM THE C-MEDIA ELECTRONICS, INC. Third-party brands and names are the property of their respective owners. Dolby® logo is the trademark of Dolby Lab. DTS® logo is the trademark of DTS Lab. Copyright 2004-2005 © C-Media Electronics Inc. C-Media Electronics, Inc. 6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan 106, R.O.C. TEL: 886-2-8773-1100 http://www.cmedia.com.tw For detailed product information, please contact sales@cmedia.com.tw FAX: 886-2-8773-2211 1 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 Contents 0. 1. Revision History......................................................................................... 4 Features and software description ...................................................... 5 1.1 1.2 1.3 1.4 Hardware Features ............................................................................. 5 Software Features............................................................................... 6 General Description ........................................................................... 7 Application......................................................................................... 8 2. 3. Block Diagram............................................................................................ 9 Pin Assignment ........................................................................................... 10 3.1 3.2 Pinout Diagram .................................................................................. 10 Pin Descriptio n................................................................................... 11 Maximum Ratings.............................................................................. 16 Recommended Operation Conditions ................................................ 16 Power consumption............................................................................ 16 DC Characteristics ............................................................................. 17 EEPROM AC Timing Characteristics................................................ 17 4.5.1 I2 S SIGNAL TIMING.................................................................. 17 4.5.2 CONTROL INTERFACE TIMING - 3 - WIRE MODE............. 17 4.5.3 CONTROL INTERFACE TIMING - 2 - WIRE MODE............. 20 4.5.4 EEPROM INTERFACE TIMING ............................................... 21 4.5.5 EEPROM AC Timing Characteristics ......................................... 22 4.5.6 AC-LINK TIMING CHARACTERISTICS ................................ 23 Package Dimension............................................................................ 27 4. Electrical Characteristics ....................................................................... 16 4.1 4.2 4.3 4.4 4.5 5. Mechanical Specifications ...................................................................... 27 5.1 2 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 List of Figures Figure 1. Block Diagram of OxygenT MHD CMI8788 ...................................................... 9 Figure 2. Pinout Diagram of OxygenT MHD CMI8788 ................................................... 10 3 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 0. Revision History Date 2005/03/15 2005/04/18 2005/07/22 2005/9/12 Rev. 0.1 0.2 0.5 0.6 Preliminary vision Release Note Modify S/W features Edit for readability Modify S/W features 4 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 1. Features and General Description 1.1 Hardware Features n n n n n n n n n n n n n n n n n n n n n n PCI 2.2 interface with bus mastering and burst modes Only one 24.576MHz oscillator is needed 4 synchronous I2 S output data stream pairs within 1 flexible output DMA Programmable channel routing mechanism among the 4 I2 S output pairs 4 synchronous I2 S input data stream pairs spread in 3 input DMA’ (for Dolby s pro-audio applications) Optionally, a multi-channel AC- link can support 2 AC97 codecs Programmable HW monitoring routing from I2 S inputs to outputs All I2 S I/O pairs support 32-bit PCM data transfer and adjustable sample rate (up to 192KHz) Integrated 192k/24-bit S/PDIF transmitter with 1 dedicated S/PDIF OUT DMA Integrated 192k/24-bit S/PDIF receiver in recording DMA S/PDIF IN supports digital loopback path for switching between optical and RCA connections 48k/16-bit front panel DMA for AC97 codec 2-wire master serial bus or 4-wire SPI (Serial Peripheral Interface) bus to control I2 S codecs 2-wire slave serial bus to communicate with microcontroller unit (MCU) Interrupt pin to inform external MCU to retrieve the data from the system driver One MPU-401 MIDI UART port EEPROM control interface 6 GPI phone jack detection pins Advanced device-sensing technology indicates whether a speaker or a headphone is plugged in the jack 9 direct-access GPIO pins 3 bonding-option bits for 8 identification possibilites 128-pin LQFP thin high-quality package 5 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 1.2 Software Features n n n n n n n n n n n n n n DTS® Interactive – a real-time 5.1 channel encoder that takes 2 or more channels and encodes them into a DTS bit stream. DTS® NeoPC - an up- mix matrix that turns any 2 channel aud io into 7.1 channel surround sound Dolby® Digital Live (AC-3) real-time 5.1 channel encoding bit-stream to facilitate the connection with CE AV receiver Dolby® Pro-Logic IIx surround processor, spreading stereo audio into 7.1 channel surround sound Renowned Dolby® Headphone technology, conveying 5.1 surround and 3D gaming audio over stereo headphones The latest Dolby® Virtual Speaker solution, creating amazing virtual surround sound from a generic two-speaker configuration C-Media FlexBassTM – configurable LFE channel crossover frequency (from 50 to 250Hz) C-Media Magic VoiceT M, a popular feature for disguising voice in online chatting C-Media Xear 3D™ 7.1 Virtual Speaker Shifter technology C-Media’s unique Karaoke functions: Microphone Echo, Key-shifting Individual 10-band EQ for each channel 27 global reverberation environments Play3D demo program Supports most industrial standards of 3D sound for PC gaming, including EAX™ 1.0&2.0, A3D™ 1.0, and DirectSound™ n Support 7.1 CH digital audio playback for WinXP, 2K, ME, 98SE (Microsoft® DirectX V.9.0 and above is required) n Linux driver available (without Dolby® and DTS ® technologies) 6 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 1.3 General Description The CMI8788 is a high quality PCI 32-bit multi-channel audio processor that can be built into home audio electronics or personal computers to provide high fidelity sound playback and processing. It supports up to 12 output channels and 8 input channels. The 12 output channels are composed of 3 playback DMA’ which are multi-channel DMA s, (32 bits, 8 channels, 192k), S/PDIF DMA (32 bits, 2 channels, 192k), and front panel DMA (16 bits, 2 channels, 48k). The 8 input channels are spread across 3 recording DMA’ (32 bits, 192k) - recording A, B, and C DMA’ The architecture of recording is s s. a unique point of CMI8788 that enables very flexible recording options for the user. The details of the recording mode selection will be explained in the later sections. The CMI8788 is compatible with all the popular codecs, from I2 S codecs with over 120dB quality to the usual AC97 codecs. This ability gives customers the flexibility to design their products exactly the way they want them. The I2 S, AC-Link, 2-wire master bus, and SPI interfaces are used to transfer audio data and control data between the CMI8788 and codecs. To facilitate the connection with existing home audio electronics, the CMI8788 has incorporated the S/PDIF transmitter and receiver with 192k sampling rate. An EEPROM interface is built for the CMI8788 in connection with the EEPROM to store and retrieve the non-evaporable data for customer applications, such as board configuration, sub- vendor and sub-system IDs of the PCI configuration, or any dynamic data that customers want to restore at the next power-on. The CMI8788 has an independent 2-wire slave bus to communicate with the micro control unit (MCU). This interface is used as a medium for the system driver and the MCU to exchange data. One of the applications of the 2-wire slave bus is to transmit the control data from the remote controller to the system driver. The MPU-401 MIDI UART is also integrated in the CMI8788. There are six GPI phone jack detect pins in CMI8788, which can be used to distinguish if a cable is plugged in the phone jack. The re are 9 GPIO pins on the chip, however some of them are shared with other functions. The C-Media’s unique device sensing technology is imple mented in CMI8788, which can indicate whether a speaker or a headphone is plugged in the jack. Then according to this information, the system driver can decide to turn on the C-Media’ X-ear 3D audio technology if appropriate. s 7 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 1.4 Applications n n n n n n n n Pro-sumer high-quality PCI sound card for retailer market Consumer sound card powered by Dolby® and DTS ® technologies PC-based media center Professional PC musician application High-end motherboard requiring top audio quality Audio up-sell for PC systems Bundle selling with high-profile VGA cards General purpose multi- channel I/O 8 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 2. Block Diagram Figure 1. Block Diagram of OxygenTMHD CMI8788 9 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 3. Pin Assignment 3.1 Pinout Diagram Figure 2. Pinout Diagram of OxygenTMHD CMI8788 10 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 3.2 Pin Descriptions The following table gives the pin descriptions for the OxygenT MHD CMI8788. Some of the pins perform multiple functions, so for the sake of consistency, a pin may be listed more than once in the table. The abbreviations used in the pin description table are expla ined below. DI: digital input signal DO: digital output signal DIO: digital bidirectional signal AI: analog input PU: pull- up with 75KΩ resistor PD: pull-down with 75KΩ resistor #: low active signal Table 3.1 Pin description table of OxygenTMHD CMI8788 Symbol XRST XCLK33 XIDSEL XGNT# Pin No. 119 120 5 121 Type PCI Bus Interface DI DI DI DI PCI Bus Reset. PCI Bus clock, 33MHz. Description PCI Initialization Device Select. This is the chip select during PCI configuration access. PCI Bus Grant. When active, PCI bus master is granted to CMI8788. XREQ# XAD[31:0] 122 1-3, 7-11, 13-15, 25, 27, 28-31, 33, 35-38, 40-44, 123-126, 128 4, 16, 24, 34 17 21 18 20 DIO DIO PCI Bus Master Request. When active, the CMI8788 is requesting to become a bus master. PCI Address / Data Bus XCB#[3:0] XFRAME# XDEVSEL# XIRDY# XTRDY# DIO DIO DIO DIO DIO PCI Bus Command / Byte Enable PCI Cycle Frame. It is driven by the current master to indicate the beginning and duration of an access PCI Device Select. When active, indicates that the driving device has decoded its address as the target of the current access. PCI Initiator Ready. When active, indicates that the initiator can complete the current data phase of the transaction. PCI Target Ready. When active, indicates the target device can complete the current data phase of the transaction. 11 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 XSTOP# XPAR XINTA# 22 23 118 DIO DIO DIO PCI Stop. When active, indicates that the target is requesting that the master stop the current transaction. PCI Parity. It is even parity across XAD[31:0] and XCB#[3:0]. PCI Interrupt Request A. MPU-401 MIDI UART Interface XTXD 54 DIO, PU M P-401 MIDI transmitter (output). It is also used as XGPIO5~8 and I2S ADC 3 configuration (input, 0: GPIO5~8, 1: I2S ADC 3) at the rising edge of XRST. DI, PU MPU401 MIDI receiver. XRXD 55 I2S Interface XDAC_MCLK XDAC_LRCK XDAC_BCLK XDAC_SDOUT0 XDAC_SDOUT1 XDAC_SDOUT2 XDAC_SDOUT3 XADC1_MCLK XADC1_LRCK XADC1_BCLK XADC1_SDIN XAC97_SDI1/ XADC1_SDIN1 XADC2_MCLK XADC2_LRCK XADC2_BCLK XADC2_SDIN XGPIO5/ XADC3_MCLK XGPIO6/ XADC3_BCLK XGPIO7/ XADC3_LRCK XGPIO8/ XADC3_SDIN 94 95 96 97 98 82 83 84 85 86 87 88 90 91 92 93 58 DO DIO DIO DO DO DO DO DO DIO DIO I2S DAC master clock output. I2S DAC Left/Right sample clock. I2S DAC bit clock. I2S DAC channel 0,channel 1 serial data output. I2S DAC channel 2,channel 3 serial data output. I2S DAC channel 4,channel 5 serial data output. I2S DAC channel 6,channel 7 serial data output. I2S ADC 1 and I2S ADC 4 master clock output. I2S ADC 1 Left/Right sample clock. I2S ADC 1 bit clock. DI, PU I2S ADC 1 serial data input. DI, PD I2S ADC 1 serial data input 1. This pin is shared with AC97 serial data input 1, and determined by XSPI_DOUT/XA1 input configuration at the rising edge of XRST. DO DIO DIO I2S ADC 2 master clock output. I2S ADC 2 Left/Right sample clock. I2S ADC 2 bit clock. DI, PU I2S ADC 2 serial data input. DIO, PD I2S ADC 3 master clock output. This pin is shared with XGPIO5, which is determined by XTXD input configuration at the rising edge of XRST. DIO, PD I2S ADC 3 bit clock. This pin is shared with XGPIO6, which is determined by XTXD input configuration at the rising edge of XRST. DIO, PD I2S ADC 2 Left/Right sample clock. This pin is shared with XGPIO7, which is determined by XTXD input configuration at the rising edge of XRST. DIO, PD GPIO8, default input. This pin is shared with XADC3_SDIN, which determined by XTXD input configuration at the rising edge of XRST. 99 100 101 AC-Link Interface 12 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 XAC97_BCLK XAC97_SDI0 XAC97_SDI1/ XADC1_SDIN1 XAC97_SYNC XAC97_SDO0 XAC97_SDO1 XAC97_RST0 XAC97_RST1 XAC97_MCLK 63 62 58 DI, PU AC97 serial clock input8 DI, PD AC97 serial data input 0 DI, PD AC97 serial data input 1. This pin is shared with XADC1_SDIN1, and determined by XSPI_DOUT/XA1 input configuration at the rising edge of XRST. DO DO DO DO DO DO AC97 frame synchronization. AC97 serial data output 0. AC97 serial data output 1. AC97 codec reset 0. AC97 codec reset 1. AC97 master clock 24.5760M for AC97 codec. 61 64 59 60 57 65 Serial Port Interface XSPI_DIN/ XMSDA XSPI_CLK/ XMSCL XSPI_DOUT/ XA1 73 74 75 DIO, PU SPI data input. This pin is shared with 2-wire master serial data. DIO, PU SPI clock output. This pin is shared with 2-wire master serial clock. DIO, PU SPI data output. This pin is shared with 2-wire Codec address A1. It is also used as XAC97_SDI1 and XADC1_SDIN1 configuration at the rising edge of XRST (input, 1: XAC97_SDI1, 0: XADC1_SDIN1). DIO, PU SPI chip enable, which select the codec #0 to be controlled. It is shared with I2C Codec address A0. It is also used as XGPIO3~4 and SSCL/SSDA configuration (input, 1: GPIO3~4, 0: SSCL/SSDA) at the rising edge of XRST. DIO, PU SPI chip enable, which select the codec #1 to be controlled (output). It is shared with codec ID 0 configuration (input) at the rising edge of XRST. DIO, PU SPI chip enable, which select the codec #2 to be controlled (output). It is shared with codec ID 1 configuration (input) at the rising edge of XRST. DIO, PU SPI chip enable, which select the codec #3 to be controlled (output). It is shared with codec ID 2 configuration (input) at the rising edge of XRST. SPI chip enable, which select the codec #4 to be controlled. It is DO shared with EEPROM serial clock. SPI chip enable, which select the codec #5 to be controlled. It is DO shared with EEPROM serial data out. XSPI_CEN0/ XA0 77 XSPI_CEN1/ XCID0 XSPI_CEN2/ XCID1 XSPI_CEN3/ XCID2 XSPI_CEN4/ XEESK XSPI_CEN5/ XEEDO XMSDA/ XSPI_DIN XMSCL/ XSPI_CLK XA1/ XSPI_DOUT 78 79 80 68 69 2-Wire Master Serial Bus 73 74 75 DIO, PU 2-wire serial bus data. This pin is shared with SPI data input. DIO, PU 2-wire serial bus clock. This pin is shared with SPI clock output. DIO, PU 2-wire serial bus codec address A1. This pin is shared with SPI data output. It is also used as XAC97_SDI1 and XADC1_SDIN1 configuration at the rising edge of XRST (input, 1: XAC97_SDI1, 13 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 0: XADC1_SDIN1). DIO, PU 2-wire serial bus codec address A0. This pin is shared with SPI chip enable, which select the codec #0 to be controlled. It is also used as XGPIO3~4 and SSCL/SSDA configuration (input, 1: GPIO3~4, 0: SSCL/SSDA) at the rising edge of XRST. XA0/ XSPI_CEN0 77 2-Wire Slave Serial Bus XSSCL/ XGPIO3 XSSDA/ XGPIO4 XMCU_INT XSLAVE_RDY/ XGPIO1 52 53 72 50 DIO, PU 2-wire serial bus clock. This pin is shared with XGPIO3. DIO, PU 2-wire serial bus data. This pin is shared with XGPIO4. DO Interrupt output for external Micro Control Unit (MCU). DIO, PD 2-wire serial bus data ready. This pin is shared with XGPIO1. S/PDIF Interface XSPDIFI XSPDIFO 107 116 DI DO S/PDIF receiver. S/PDIF transmitter. EEPROM Interface XEECS 67 DIO, PD EEPROM chip enable (output). It is also used as power on EEPROM CS delay configuration (input, 0: no delay, 1: delay 1 clock) at the rising edge of XRST EEPROM serial clock. This pin is shared with SPI chip enable, DO which select the codec #4 to be controlled DI, PU EEPROM serial data in DO EEPROM serial data out. This pin is shared with SPI chip enable, which select the codec #5 to be controlled XEESK/ XSPI_CEN4 XEEDI XEEDO/ XSPI_CEN5 68 66 69 Jack Detect GPI Interface XGPI0 XGPI1 XGPI2 XGPI3 XGPI4 XGPI5 108 109 110 111 112 113 DI, PD JACK A detection input DI, PD JACK B detection input DI, PD JACK C detection input DI, PD JACK D detection input DI, PD JACK E detection input DI, PD JACK F detection input GPIO Interface XGPIO0 XGPIO1/ XSLAVE_RDY XGPIO2 XGPIO3/XSSCL XGPIO4/XSSDA XGPIO5/ XADC3_MCLK 49 50 51 52 53 98 DIO, PD GPIO0, default output Low. DIO, PD GPIO1, default output Low. This pin is shared with I2C Slave data ready. DIO, PD GPIO2, default input. DIO, PU GPIO3, default output Low. This pin is shared with I2C Slave serial clock. DIO, PU GPIO4, default input. This pin is shared with I2C Slave serial data DIO, PD GPIO5, default output Low. This pin is shared with XADC3_MCLK, which determined by XTXD input configuration 14 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 at the rising edge of XRST. DIO, PD GPIO6, default input. This pin is shared with XADC3_BCLK, which determined by XTXD input configuration at the rising edge of XRST. DIO, PD GPIO7, default output Low. This pin is shared with XADC3_LRCK, which determined by XTXD input configuration at the rising edge of XRST. DIO, PD GPIO8, default input. This pin is shared with XADC3_SDIN, which determined by XTXD input configuration at the rising edge of XRST. XGPIO6/ XADC3_BCLK XGPIO7/ XADC3_LRCK XGPIO8/ XADC3_SDIN 99 100 101 Headphone Sensing Interface XHPD_E/ XTEST XHPD_IN XHPD_R1 XHPD_R2 104 105 106 103 DIO, PD Head phone detect enable. This pin is shared with test mode selection at the rising edge of XRST AI AI AI Head phone voltage input Head phone reference resistor 1 Head phone reference resistor 2 Miscellaneous XTAL1 XTAL2 XRSTO XPWDN DVDD 46 47 71 115 6, 19, 32, 45, 56, 76, 89, 117 12, 26, 39, 48, 70, 81, 102, 114 DI DO DO DO 24.576Mhz OSC input OSC output External Codec reset, can be programmed as Active Low or High with Register 0x50-bit 2 Power Down output pin, Active Low, default High 3.3V power input DGND Ground 15 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 4. Electrical Characteristics 4.1 Maximum Ratings Test Conditions DVDD = 3.3V, DGND =0V,TA=+25o C Parameter Storge temperature Operating ambient temperature DC supply voltage I/O pin voltage Power dissipation Symbol Min -55 0 3.0 GND Typ 25 3.3 0.15 Max 150 75 3.6 VDD Units o o C C V V W 4.2 Recommended Operation Conditions Test Conditions DVDD = 3.3V, DGND =0V,TA=+25o C Parameter Input voltage range Output voltage range Symbol Min VDD-0.3 0 Typ VDD Max VDD+0.3 VDD Units V V 4.3 Power consumption Test Conditions DVDD = 3.3V, DGND =0V,TA=+25o C Parameter Supply current : power up Supply current : power down Symbol Min Typ 40 10 Max Units mA uA 16 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 4.4 DC Characteristics Test Conditions DVDD = 3.3V, DGND =0V,TA=+25o C Parameter Input voltage range Output voltage range High level input voltage Low level input voltage High level output voitage Low level output voltage Input leakage current Output leakage current Output buffer driver current SPDIF transmit output driver current Symbol Vin Vout Vih Vil Voh Vol Iil Iol - Min VDD-0.3 0 0.7VDD 2.4 Typ VDD - Max VDD+0.3 VDD 0.3VDD 0.4 10 10 - Units V V V V V V uA uA mA mA -10 -10 - 8 8 4.5 AC Timing Characteristics 4.5.1 I2S SIGNAL TIMING 1. SYSTEM CLOCK TIMING System Clock Timing Diagram Test Conditions DVDD = 3.3V, DGND =0V,TA=+25o C,fs=96KHz,MCLK=512fs,24 bit data,unless otherwise stated System Clock Timing Parameters 17 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 Parameter MCLK clock cycle time MCLK pulse width high MCLK pulse width high MCLK duty cycle Symbol tmclk tmclkh tmclkl Min 20 10 10 40 Typ 50 Max 60 Units ns ns ns % 2. AUDIO INTERFACE TIMING Audio Interface Timing Diagram Test Conditions DVDD = 3.3V, DGND =0V,TA=+25o C,fs=96KHz,MCLK=512fs,24 bit data,unless otherwise stated Audio Interface Timing Parameters Parameter LRCK propagation delay from BCLK falling edge SDOUT propagation delay from BCLK falling edge Tdd 5 ns Symbol Tdl Min 5 Typ Max Units ns 18 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 4.5.2 CONTROL INTERFACE TIMING - 3 - WIRE MODE Control Interface Timing -3- Wire Diagram Note: latch data at XSPI_CEN clock low mode , XSPI_CEN clock can be low or high mode Test Conditions DVDD = 3.3V, DGND =0V,TA=+25o C,SPI clock 160 ns,unless otherwise stated Control Interface Timing -3- Wire Parameters Parameter XSPI_CLK rising edge to XSPI_CEN rising edge XSPI_CLK pulse cycle time XSPI_CLK pulse width low XSPI_CLK pulse width high XSPI_DOUT to XSPI_CLK set-up time XSPI_DOUT to XSPI_CLK hold time XSPI_CEN rising to SCLK rising Tscy Tscl Tsch Tdsu Tdho Tcss 160 80 80 40 40 40 ns ns ns ns ns ns Symbol Tscs Min 120 Typ Max Units ns 19 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 4.5.3 CONTROL INTERFACE TIMING - 2 - WIRE MODE Control Interface Timing -2- Wire Diagram Test Conditions DVDD = 3.3V, DGND =0V,TA=+25o C,2 wire,Fast speed mode,unless otherwise stated Control Interface Timing -2- Wire Parameters Parameter XMSCL frequency XMSCL pulse width low XMSCL pulse width high Hold time (start condition) Set-up time (start condition) Data set-up time XMSDI,XMSCL rise time XMSDI,XMSCL fall time Set-up time (stop condition) Data hold time t1 t2 t3 t4 t5 t6 t7 t8 t9 Symbol Min 400 650 1.3 650 650 650 100 100 650 650 Typ Max Units KHz ns us ns ns ns ns ns ns ns Note: test parameters at 2 wire,Fast speed mode 20 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 4.5.4 EEPROM INTERFACE TIMING EEPROM Interface Timing Diagram Test Conditions DVDD = 3.3V, DGND =0V,TA=+25o C,unless otherwise stated EEPROM Interface Timing Parameters Parameter XEESK clock frequency XEESK high time XEESK low time XEECS setup time XEEDI setup time XEECS hold time XEEDI hold time Output delay to “1” Output delay to “0” XEECS to status valid XEECS to XEEDO in high impedance Symbol tsk tskh tskl tcss tdis tcsh tdih tpd1 tpd0 tsv tdf Min 555 900 900 900 900 900 2 900 30 30 30 Typ Max Units KHz ns ns ns ns ns ns ns ns ns ns 21 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 4.5.5 EEPROM AC Timing Characteristics Symbol f sk tskh tskl tcss tcsh tdis tdih tpd0 tpd1 t sv tdf Description SK Clock Frequency SK High Time SK Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to “0” Output Delay to “1” CS to Status Valid CS to DO High Impedance Min 0 500 500 100 0 200 200 Max 0.5 Units MHz ns ns ns ns ns ns ns ns ns ns 500 500 500 200 22 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 4.5.6 AC-LINK TIMING CHARACTERISTICS Test Conditions DVDD = 3.3V, DGND =0V,TA=+25o C ,unless otherwise stated 1 . COLD RESET Cold Reset Timing Diagram Cold Reset Timing Parameters Parameter XAC97_RST active low pulse width XAC97_RST inactive to XAC97_BCLK startup delay Symbol Trst_low Trst2clk Min 1.7 168 Typ Max Units us ns # denotes active low. 23 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 2 . WARM RESET Warm Reset Diagram Warm Reset Parameters Parameter XAC97_SYNC active high pulse width XAC97_SYNC inactive to XAC97_BCLK startup delay Symbol Tsync_high Tsync2clk Min 1.2 168 Typ Max Units us ns 3 . AC-LINK CLOCKS BIT_CLK to SYNC Timing Diagram 24 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 BIT_CLK to SYNC Timing Parameters Parameter XAC97_BCLK frequency XAC97_BCLK period XAC97_BCLK output jitter XAC97_BCLK high pulsewidth (note 1) XAC97_BCLK low pulse width (note 1) XAC97_SYNC frequency XAC97_SYNC period XAC97_SYNC high pulse width XAC97_SYNC low_pulse width Tsync_period Tsync_high Tsync_low Tclk_high Tclk_low Tclk_period Symbol Min 12.288 81.4 750 40.7 40.7 48.0 20.8 1.3 19.5 Typ Max Units M Hz ns ps ns ns kHz us us us Note: W orst case duty cycle restricted to 45/55. 4 . DATA SETUP AND HOLD Data Setup and Hold diagram Data Setup and Hold Parameters Parameter Setup to falling edge of Hold from falling edge of XAC97_BCLK XAC97_BCLK Symbol Tsetup Thold Min 30 30 Typ Max Units ns ns Note: Setup and hold time parameters for SDATA_IN are with respect to the AC ‘97 Controller. 25 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 5 . SIGNAL RISING AND FALLING TIMES Signal Rising and Falling Times Diagram Signal Rising and Falling time Parameters Parameter XAC97_BCLK rising time XAC97_BCLK falling time XAC97_SYNC rising time XAC97_SYNC falling time XAC97_SDI rising time XAC97_SDI falling time XAC97_SDO rising time XAC97_SDO falling time Symbol Triseclk Tfallclk Trisesync Tfallsync Trisedin Tfalldin Trisedout Tfalldout Min 6 6 6 6 6 6 6 6 Typ Max Units ns ns ns ns ns ns ns ns 26 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 5. Mechanical Specification 5.1 Package Dimension 27 C-MEDIA CONFIDENTIAL C-Media High Performance PCI Audi o Controller OxygenTM HD CMI8788 Datasheet v0 .6 - End of Datasheet - C-Media Electronics, Inc. 6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan 106, R.O.C. TEL: 886-2-8773-1100 http://www.cmedia.com.tw For detailed product information, please contact sales@cmedia.com.tw FAX: 886-2-8773-2211 28 C-MEDIA CONFIDENTIAL