CMX654D4

CMX654 V23 Transmit Modulator D/654/3 June 1998 Advance Information Features Applications • 1200bits/sec, V23 Transmit Modulator • Caller ID generation for: • 3.0V to 5.5V Supply: 1mA typical at 3V • ISDN Terminal Adapters • Zero Power Mode: 1µA typical • Wireless Local Loop System • 1200bits/sec Tx Data Retiming • ISDN PABX Applications • 3.58MHz Xtal/Clock Rate • Pair-Gain Systems • Meets ITU and ETSI Specifications • Public Switched Telephone Networks • 16 Pin SOIC and DIP Packages • Trunk Exchanges 1.1 Brief Description The CMX654 is a low power CMOS integrated circuit for the transmission of asynchronous 1200bits/sec data in accordance with ITU, V.23 and ETSI specifications. The device incorporates an optional Tx data retiming function. The device can be operated so that only the mark or space tone is produced. The CMX654 may be used in a wide range of telephone telemetry systems. With a low voltage requirement of 3.0V it is suitable for both portable terminal and line powered applications. A very low current 'sleep' mode (1µA typ.) and operating current of 1mA typ. mean the device is ideal for line powered applications. A 3.58MHz standard Xtal/Clock rate is required and the device operates from a 3.0 to 5.5V supply. Both SOIC (D4) and Plastic DIL (P3) 16-pin package types are available.  1998 Consumer Microcircuits Limited V.23 Transmit Modulator CMX654 CONTENTS Section Page 1.1 Brief Description ............................................................................................ 1 1.2 Block Diagram ................................................................................................ 3 1.3 Signal List ....................................................................................................... 3 1.4 External Components .................................................................................... 5 1.5 General Description ....................................................................................... 5 1.5.1 Xtal Osc and Clock Dividers............................................................. 5 1.5.2 Mode Control Logic .......................................................................... 6 1.5.3 FSK Modulator and Transmit Filter .................................................. 6 1.5.4 Tx Data Retiming.............................................................................. 7 1.6 Application Notes........................................................................................... 8 1.6.1 Line Interface.................................................................................... 8 1.7 Performance Specification ............................................................................ 9 1.7.1 Electrical Performance ..................................................................... 9 1.7.2 Packaging....................................................................................... 12  1998 Consumer Microcircuits Limited 2 D/654/3 V.23 Transmit Modulator 1.2 CMX654 Block Diagram Figure 1 Block Diagram 1.3 Signal List CMX654 D4/P3 Signal Description Pin No. Name Type 1 XTALN O/P The output of the on-chip Xtal oscillator inverter. 2 XTAL/CLOCK I/P The input to the on-chip Xtal oscillator inverter. 3 M0 I/P A logic level input for setting the mode of the device. See Section 1.5.2. 4 M1 I/P A logic level input for setting the mode of the device. See Section 1.5.2. 5 - - 6 - N/C No connection, do not connect to this pin. 7 TXOP O/P The output of the FSK generator. 8 VSS Power The negative supply rail (ground).  1998 Consumer Microcircuits Limited Connect to VSS 3 D/654/3 V.23 Transmit Modulator CMX654 CMX654 D4/P3 Signal Description Pin No. Name Type 9 VBIAS O/P 10 - - 11 TXD I/P A logic level input for either the raw input to the FSK Modulator or data to be re-timed depending on the state of the M0, M1 and CLK inputs. See Section 1.5.3. 12 CLK I/P A logic level input which may be used to clock data bits into the Tx FSK Data Retiming block. 13 - N/C No connection, do not connect to this pin. 14 - N/C No connection, do not connect to this pin. 15 RDYN O/P "Ready for Tx data transfer" output of the onchip data retiming circuit. This open-drain active low output may be used as an Interrupt Request/Wake-up input to the associated µC. An external pull-up resistor should be connected between this output and VDD. 16 VDD Power The positive supply rail. Levels and thresholds within the device are proportional to this voltage. Should be decoupled to VSS by a capacitor mounted close to the device pins. Notes: I/P = O/P = N/C = Internally generated bias voltage, held at VDD/2 when the device is not in 'Zero-Power' mode. Should be decoupled to VSS by a capacitor mounted close to the device pins. Connect to VDD. Input Output No Connection VDD and VBIAS decoupling are very important. It is recommended that the decoupling capacitors are placed so that connections between them and the device pins are as short as practicable.  1998 Consumer Microcircuits Limited 4 D/654/3 V.23 Transmit Modulator 1.4 CMX654 External Components R1 X1 100kΩ 3.579545MHz C1, C2 C3 C4 18pF 0.1µF 0.1µF Resistors ±5%, capacitors ±10% unless otherwise stated. Figure 2 Recommended External Components for Typical Application 1.5 General Description 1.5.1 Xtal Osc and Clock Dividers Frequency and timing accuracy of the CMX654 is determined by a 3.579545MHz clock present at the XTAL/CLOCK pin. This may be generated by the on-chip oscillator inverter using the external components C1, C2 and X1 of Figure 2, or may be supplied from an external source to the XTAL/CLOCK input. If supplied from an external source, C1, C2 and X1 should not be fitted. The on-chip oscillator is turned off in the 'Zero-Power' mode. If the clock is provided by an external source which is not always running, then the 'Zero-Power' mode must be set when the clock is not available. Failure to observe this rule may cause a significant rise in the supply current drawn by CMX654 as well as generating undefined states of the RDYN output.  1998 Consumer Microcircuits Limited 5 D/654/3 V.23 Transmit Modulator 1.5.2 CMX654 Mode Control Logic The CMX654's operating mode is determined by the logic levels applied to the M0 and M1 input pins: M1 0 1 1 M0 1 0 1 Data Retime[1] Tx - Tx Mode 1200bits/sec off 'Zero-Power' [1] If enabled. In the 'Zero-Power' mode, power is removed from all internal circuitry. When leaving 'Zero-Power' mode there must be a delay of 20ms before any Tx data is passed to the device to allow the bias level, filters and oscillator to stabilise. On applying power to the device the mode must be set to 'ZP', i.e. M0=1, M1=1, until VDD has stabilised. 1.5.3 FSK Modulator and Transmit Filter These blocks produce a tone according to the TXD, M0 and M1 inputs as shown in the table below, assuming data retiming is not being used: M1 1 1 0 Note: [1] M0 1 0 1 TXD = '0' TXD = '1' 0Hz[1] 2100Hz 1300Hz TXOP held at approx VDD/2. When modulated at the appropriate baud rates, the Transmit Filter and associated external components (see Section 1.6.1) limit the FSK out of band energy sent to the line in accordance with Figure 3 assuming that the signal on the line is at -6dBm or less. Figure 3 Tx limits  1998 Consumer Microcircuits Limited 6 D/654/3 V.23 Transmit Modulator 1.5.4 CMX654 Tx Data Retiming The Data Retiming block, when enabled in 1200bits/sec transmit mode, requires the controlling µC to load 1 bit at a time into the device by a pulse applied to the CLK input. The timing of this pulse is not critical and it may easily be generated by a simple software loop. This facility removes the need for a UART in the µC without incurring an excessive software overhead. The Tx re-timing circuit consists of two 1-bit registers in series, the input of the first is connected to the TXD pin and the output of the second feeds the FSK modulator. The second register is clocked by an internally generated 1200Hz signal and when this occurs the CLK input is sampled. If the CLK input is high the TXD pin directly controls the FSK modulator, if the CLK input is low the FSK modulator is controlled by the output of the second register and the RDYN pin is pulled low. The RDYN output is reset by a high level on the CLK input pin. A low to high change on the CLK input pin will latch the data from the TXD input pin into the first register ready for transfer to the second register when the internal 1200Hz signal next occurs. So to use the retiming option the CLK input should be held low until the RDYN output is pulled low. When the RDYN pin goes low the next data bit should be applied at the TXD input and the CLK input pulled high and then low within the time limits set out in Figure 6. To ensure synchronisation between the controlling device and the CMX654 when entering Tx retiming mode, the TXD pin must be held at a constant logic level from when the CLK pin is first pulled low to the end of loading in the second retimed bit. Similarly when exiting Tx retiming mode the TXD pin should be held at the same logic level as the last retimed bit for at least 2 bit times after the CLK line is pulled high. If the data retiming facility is not required, the CLK input to the CMX654 should be kept high at all times. The asynchronous data to the FSK modulator will then be connected directly to the TXD input pin. This is illustrated in Figure 5.  1998 Consumer Microcircuits Limited 7 D/654/3 V.23 Transmit Modulator CMX654 1.6 Application Notes 1.6.1 Line Interface The signals on the telephone line are not suitable for direct connection to the CMX654. A Line Interface circuit is necessary to: • Provide high voltage and dc isolation • Provide the low impedance drive necessary for the line • Filter the Tx and Rx signals R3 R6 See below 100kΩ C5 C7 22µF (±20%) 330pF Resistors ±1%, capacitors ±10% unless otherwise stated. Figure 4 Line Interface Circuit Notes: • • • The component(s) 'Z' between points B and C should match the line impedance. Device A1 must be able to drive 'Z' and the line. R3: The levels in dB (relative to a 775mV rms signal) at 'A', 'B' and 'C' in the line interface circuit are: 'A' = 20Log(VDD/5) 'B' = 'A' + 20Log(100kΩ/R3) 'C' = 'B' - 6 VDD 3.3V 5.0V 'A' -3.6dB 0dB  1998 Consumer Microcircuits Limited R3 100kΩ 150kΩ 'B' -3.6dB -3.5dB 8 'C' -9.6dB -9.5dB D/654/3 V.23 Transmit Modulator 1.7 Performance Specification 1.7.1 Electrical Performance CMX654 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Min. -0.3 -0.3 -30 -20 Max. 7.0 VDD + 0.3 +30 +20 Units V V mA mA D4 Package Total Allowable Power Dissipation at Tamb = 25°C ... Derating Storage Temperature Operating Temperature Min. Max. 800 13 +125 +85 Units mW mW/°C °C °C P3 Package Total Allowable Power Dissipation at Tamb = 25°C ... Derating Storage Temperature Operating Temperature Min. Max. 800 13 +125 +85 Units mW mW/°C °C °C Max. 5.5 +85 3.583125 Units V °C MHz Supply (VDD - VSS) Voltage on any pin to VSS Current into or out of VDD and VSS pins Current into or out of any other pin -55 -40 -55 -40 Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply (VDD - VSS) Operating Temperature Xtal Frequency Notes: 1 Min. 3.0 -40 3.575965 1. A Xtal frequency of 3.579545MHz ±0.1% is required for correct FSK operation.  1998 Consumer Microcircuits Limited 9 D/654/3 V.23 Transmit Modulator CMX654 Operating Characteristics For the following conditions unless otherwise specified: VDD = 3.0V at Tamb = 25°C and VDD = 3.3V to 5.5V at Tamb = -40 to +85°C, Xtal Frequency = 3.579545MHz ± 0.1% 0dBV corresponds to 1.0Vrms 0dBm corresponds to 775mVrms into 600Ω. DC Parameters IDD (M0='1', M1='1') IDD (M0 or M1='0') at VDD = 3.0V IDD (M0 or M1='0') at VDD= 5.0V Notes Min. Typ. Max. Units 1, 2 1 1 - 1 1.0 1.7 1.25 2.5 µA mA mA 70% -1.0 - 30% +1.0 VDD VDD µA VDD-0.4 - - 0.4 1.0 V V µA 1194 - 1206 Baud -1.0 -2.0 0 0 +1.0 +2.0 dB dB 0 1297 2097 1200 - 1212 1303 2103 Baud Hz Hz 100 100 - - ns ns Logic '1' Input Level Logic '0' Input Level Logic Input Leakage Current (Vin = 0 to VDD), Excluding XTAL/CLOCK Input Output Logic '1' Level (lOH = 360µA) Output Logic '0' Level (lOL = 360µA) RDYN O/P 'off' State Current (Vout = VDD) FSK Retiming Tx Data Rate FSK Modulator TXOP Level Twist (Mark Level WRT Space Level) 3 Tx 1200bits/sec (M1='0', M0='1'). Bit Rate Mark (Logical 1) Frequency Space (Logical 0) Frequency XTAL/CLOCK Input 'High' Pulse Width 'Low' Pulse Width Notes: 4 4 1. At 25°C, not including any current drawn from the CMX654 pins by external circuitry other than X1, C1 and C2. 2. TXD and CLK inputs at VSS, M0 and M1 inputs at VDD. 3. Relative to 775mVrms at VDD= 5.0V for load resistances greater than 40kΩ. 4. Timing for an external input to the XTAL/CLOCK pin. Data and Mode Timing  1998 Consumer Microcircuits Limited Min. 10 Typ. Max. Units D/654/3 V.23 Transmit Modulator CMX654 Delay to reliable data at TXOP after ZP to Tx mode change Data Retiming Disabled (reference Figure 5) Tx Data Delay (TXD to TXOP) Data Retiming Enabled (reference Figure 6) Td = Internal CMX654 delay Tchi = CLK High time Tr = RDY low to CLK going low Ts = Data Set-up time Th = Data Hold time - - 20.0 ms - 0.1 - ms 1.0 1.0 1.0 - 1.0 800 - µs µs µs µs µs Note: M0 and M1 are preset and stable. FLO and FHI are the two FSK signalling frequencies. Figure 5 TXD to TXOP Delay Time Figure 6 FSK Operation with Tx Data Retiming  1998 Consumer Microcircuits Limited 11 D/654/3 V.23 Transmit Modulator 1.7.2 CMX654 Packaging Figure 7 16-pin SOIC (D4) Mechanical Outline: Order as part no. CMX654D4 Figure 8 16-pin DIL (P3) Mechanical Outline: Order as part no. CMX654P3 Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed. 1 WHEATON ROAD WITHAM - ESSEX CM8 3TD - ENGLAND Telephone: +44 1376 513833 Telefax: +44 1376 518247 e-mail: sales@cmlmicro.co.uk http://www.cmlmicro.co.uk CML Microcircuits COMMUNICATION SEMICONDUCTORS CML Product Data In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached. Company contact information is as below: CML Microcircuits (UK)Ltd CML Microcircuits (USA) Inc. CML Microcircuits (Singapore)PteLtd COMMUNICATION SEMICONDUCTORS COMMUNICATION SEMICONDUCTORS COMMUNICATION SEMICONDUCTORS Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com 4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com D/CML (D)/1 February 2002