CMX624D2

CML Microcircuits COMMUNICA TION SEMICONDUCTORS D/624/7 September 2003 CMX624 V.23 / Bell 202 Modem Applications • Telephone Telemetry Systems • Remote Utility Meter Reading • Security Systems/Cash Terminals • Industrial Control Systems • Pay-Phones • Cable TV Set-Top Boxes Features • V.23 / Bell 202 Compatible Modem • Integrated DTMF Encoder • Call Progress Tone Detection • Line Reversal and Ring Detector • Low Power Operation (2.7V) • Part of the CMX6x4 Modem Series 1.1 Brief Description The CMX624 V.23 / Bell 202 modem is intended for use in any telephone based information and telemetry system with low power requirements. Using FSK signalling, fast call set-up times and robust error resistant transmission can be implemented by efficient low power circuits. The circuit can operate at 1200bps full duplex over a 4-wire circuit or 1200 bps plus low speed data over a 2-wire circuit. Flexible line driver and receive hybrid circuitry are integrated on chip requiring only passive external components to build a 2- or 4wire interface. A low impedance pull down output is provided for a hook relay. Control of the device is via a simple high speed serial bus; this allows easy interfacing to a host µController. The data transmitted and received by the modem is also transferred over the same high speed serial bus. On-chip programmable Tx and Rx UARTs allow asynchronous data to be simultaneously encoded and decoded. Either UART may be disabled to allow 8-bit raw data to be received or transmitted. Any repetitive 8-bit data pattern can be sent without the controller having to reload data every 8 bits. All 16 DTMF combinations are available along with a single tone 'melody' mode. The ringing, 2100Hz, call progress and data detectors included on the CMX624 make the set-up of a telephone call a simple matter for the host µController. In many data collection and telemetry systems low power consumption is important. The CMX624 features a 'Zero Power' standby mode. Whilst in standby the ring detector continues to operate and will supply the host µController with an interrupt when line reversal or ringing is detected. The CMX624 can operate on a supply voltage between 3.0V and 5.5V across the full temperature range of -40°C to +85°C. The CMX624 is pin compatible with the CMX644A V22 and Bell 212A modem also from CML.  2003 CML Microsystems Plc V23 / Bell 202 Modem CMX624 CONTENTS Section 1.1 1.2 1.3 1.4 1.5 Page Brief Description ..................................................................................... 1 Block Diagram ......................................................................................... 3 Signal List ................................................................................................ 4 External Components ............................................................................. 6 General Description ................................................................................ 6 1.5.1 Xtal Osc and Clock Dividers ..................................................... 6 1.5.2 Rx Input Amplifier ...................................................................... 7 1.5.3 Receive Filter and Equaliser ..................................................... 7 1.5.4 FSK Demodulator....................................................................... 8 1.5.5 Rx Energy Detector.................................................................... 8 1.5.6 FSK / DTMF Modulator .............................................................. 8 1.5.7 Transmit Filter ............................................................................ 9 1.5.8 Transmit Output Buffer ........................................................... 10 1.5.9 Ring Signal Detector................................................................ 10 1.5.10 Tx/Rx UART .............................................................................. 11 1.5.11 ‘C-BUS’ Interface...................................................................... 13 1.5.12 ‘C-BUS’ Registers .................................................................... 14 Application Notes.................................................................................. 15 1.6.1 Line Interface............................................................................ 15 1.6.2 Ring Detector Interface............................................................ 17 Performance Specification................................................................... 19 1.7.1 Electrical Performance ............................................................ 19 1.7.2 Packaging ................................................................................. 24 1.6 1.7  2003 CML Microsystems Plc 2 D/624/7 V23 / Bell 202 Modem CMX624 1.2 Block Diagram Figure 1 Block Diagram  2003 CML Microsystems Plc 3 D/624/7 V23 / Bell 202 Modem CMX624 1.3 Signal List Signal Description CMX624 D2/D5/P4 Pin No. 1 2 Name XTALN XTAL/CLOCK Type O/P I/P The output of the on-chip Xtal oscillator inverter. The input to the oscillator inverter from the Xtal circuit or external clock source. The ‘C-BUS’ serial clock input from the µC. See Section 1.5.11 The ‘C-BUS’ serial data input from the µC. A 3-state ‘C-BUS’ serial data output to the µC. This output is high impedance when not sending data to the µC. The ‘C-BUS’ transfer control input provided by the µC. A ‘wire-ORable’ output for connection to a µC Interrupt Request input. This output is pulled down to Vss when active and is high impedance when inactive. An external pullup resistor is required. The Tx analogue signal output. The output of the line driving amplifier. The inverting input to the line driver amplifier. The inverted output of the line driving amplifier. The negative supply rail (ground). Internally generated bias voltage of VDD/2, except when the device is in ‘Zero Power’ mode when VBIAS will discharge to VSS. Should be decoupled to VSS by a capacitor mounted close to the device pins. Relay drive open drain output. This output is pulled down to VSS when active and is high impedance when inactive. The non-inverting input to the Rx input amplifier. 3 SERIAL CLOCK COMMAND DATA REPLY DATA I/P 4 5 I/P T/S 6 CSN I/P 7 IRQN O/P 8 9 10 11 12 13 TOP TXO TXN TXON VSS VBIAS O/P O/P I/P O/P Power O/P 14 RLYDRV O/P 15 RXP I/P  2003 CML Microsystems Plc 4 D/624/7 V23 / Bell 202 Modem CMX624 CMX624 D2/D5/P4 Pin No. 16 17 18 Signal Description Name RXN RXO RT Type I/P O/P BI The inverting input to the Rx input amplifier. The output of the Rx input amplifier. Open drain output and Schmitt trigger input forming part of the Ring Signal detector. Schmitt trigger input to the Ring Signal Detector. No connection should be made to this pin. No connection should be made to this pin. No connection should be made to this pin if the printed circuit board is to be used for CMX624 only. If the board is also to be used for CMX644A, a capacitor should be connected as shown in Figure 2. No connection should be made to this pin if the printed circuit board is to be used for CMX624 only. If the board is also to be used for CMX644A, a capacitor should be connected as shown in Figure 2. The positive supply rail. Levels and thresholds within the device are proportional to this voltage. Should be decoupled to VSS by a capacitor mounted close to the device pins. 19 20 21 22 RD - I/P NC NC NC 23 - I/P 24 VDD Power Notes: I/P O/P BI T/S NC = = = = = Input Output Bidirectional 3-state Output No Connection This device is capable of detecting and decoding small amplitude signals. To achieve this VDD and VBIAS decoupling and protecting the receive path from extraneous in-band signals are very important. It is recommended that the printed circuit board is laid out with a ground plane in the CMX624 area to provide a low impedance connection between the VSS pin and the VDD and VBIAS decoupling capacitors.  2003 CML Microsystems Plc 5 D/624/7 V23 / Bell 202 Modem CMX624 1.4 External Components R1 X1 100kΩ 3.579545MHz C1, C2 C3, C4 C5 18pF 0.1µF * Resistors ±5%, capacitors ±10% unless otherwise stated. * This component is only required for compatibility with CMX644A, see CMX644A Data Sheet for further details. Figure 2 Recommended External Components for Typical Application 1.5 General Description The CMX624 contains a V.23/Bell 202 compatible FSK modem capable of duplex operation at 1200/75 or 1200/150 bps over a 2-wire line or 1200/1200 bps over a 4-wire line, a flexible FSK data UART, a receive FSK or Call Progress Tone energy detector, a 2100Hz detector, a DTMF generator, a Tx line driving buffer amplifier, a telephone line Ringing Signal or Line Voltage Reversal detector and a 3.579545MHz Xtal oscillator. These functions are all controlled over a ‘C-BUS’ serial µC interface which also carries the transmit and receive FSK modem data. 1.5.1 Xtal Osc and Clock Dividers Frequency and timing accuracy of the CMX624 is determined by a 3.579545MHz clock present at the XTAL/CLOCK pin. This may be generated by the on-chip oscillator inverter using the external components C1, C2 and X1 of Figure 2, or may be supplied from an external source to the XTAL/CLOCK input. If the clock is supplied from an external source, C1, C2 and X1 should not be fitted. The on-chip oscillator is turned off in the 'Zero-Power' mode. If the clock is provided by an external source which is not always running, then the 'Zero-Power' mode must be set when the clock is not available. Failure to observe this rule may cause a rise in the supply current drawn by CMX624.  2003 CML Microsystems Plc 6 D/624/7 V23 / Bell 202 Modem CMX624 1.5.2 Rx Input Amplifier This amplifier, with suitable external components, is used to adjust the received signal to the correct amplitude for the FSK receiver and Energy Detect circuits and may also form part of a 2-wire or 4-wire hybrid circuit; see Section 1.6.1. 1.5.3 Receive Filter and Equaliser This block includes a bandpass filter whose characteristics are set by bits 4 and 5 of the FSK MODE Register according to the receive operating mode (Call Progress, 75/150bps FSK or 1200bps FSK). It is used to attenuate out of band noise and interfering signals, especially the locally generated transmit FSK signal which could otherwise interfere with the received FSK signal when the modem is operating in 2-wire duplex mode. When receiving 1200bps FSK data an optional equaliser section, enabled by setting bit 6 of the FSK MODE Register, compensates for one-half of the ETS Test Line 1 characteristics shown in Figure 3b. 0 -10 dB -20 1200bps 75/150 bps Call Progress -30 -40 100 1000 Hz 10000 Figure 3a Rx Frequency Responses with Line Interface, see section 1.6.1 (equaliser disabled) 5 4 3 dB ms 2 dB wrt 800Hz ms wrt 1700Hz 1 0 0 500 1000 1500 2000 Hz 2500 3000 3500 4000 Figure 3b ETS 300 114 Test Line 1 Characteristics (Normalised)  2003 CML Microsystems Plc 7 D/624/7 V23 / Bell 202 Modem CMX624 1.5.4 FSK Demodulator This block is enabled when bits 1 and 5 of the FSK MODE Register are set to ‘1’, and converts the 75, 150 or 1200 bps FSK input signal to a binary received data signal which is sent to the Rx UART block. Note that in the absence of a valid FSK signal, the demodulator may falsely interpret speech or other extraneous signals as data. 1.5.5 Rx Energy and 2100Hz Detector The function of this block is controlled by Bits 4 and 5 of the FSK MODE Register and Bit 0 of the TX TONES Register. When Bit 0 of the TX TONES Register and Bits 4 and 5 of the FSK MODE Register are set to ‘1’ this block will measure the frequency and amplitude of the incoming signal. When a signal of 2100Hz is present of sufficient amplitude and time Bit 4 of the FLAGS Register is set high. See Section 1.7.1 for amplitude, time and frequency limits. When Bit 0 of the TX TONES Register is set to ‘0’ this block compares the level of the signal at the output of the Receive Filter against an internal threshold and may be used as a FSK level detector or a simple Call Progress Signal detector according to the settings of bits 4 and 5 of the FSK MODE Register, which affect the Receive Filter pass band as described in Section 1.5.3. The required register settings are summarised in the table below: TX TONES Reg Bit 0 0 0 0 1 FSK MODE Reg Bit 5 0 1 1 1 Bit 4 0 0 1 1 Detection Mode Call Progress 75 / 150 bps FSK 1200 bps FSK 2100 Hz Bit 4 of the FLAGS Register is set to ‘1’ by the output of this block when the received level has exceeded the threshold for sufficient time. Amplitude and time hysteresis are used to reduce chattering in marginal conditions. See Section 1.7.1 for definitions of Teon and Teoff Figure 4 Rx Energy Detector Timing 1.5.6 FSK / DTMF Modulator W hen bit 7 of the TX TONES Register is set to ‘0’ then this block generates FSK signals as determined by bits 0 and 1 of the FSK MODE Register and the Tx data bits from the UART block as shown in the tables below: V.23 mode (bit 7 of SETUP register = ‘0’): FSK MODE Reg Bit 1 0 1 1 Bit 0 x 0 1 FSK / DTMF Modulator block output (Bit 7 of TX TONES = ‘0’) Disabled (o/p held at VDD / 2) 75bps FSK 1200bps FSK FSK Signal Frequency ‘0’ (Space) 450Hz 2100Hz ‘1’ (Mark) 390Hz 1300Hz  2003 CML Microsystems Plc 8 D/624/7 V23 / Bell 202 Modem CMX624 Bell 202 mode (bit 7 of SETUP register = ‘1’): FSK MODE Reg Bit 1 Bit 0 0 1 1 x 0 1 FSK / DTMF Modulator block output (Bit 7 of TX TONES = ‘0’) Disabled (o/p held at VDD / 2) 150bps FSK 1200bps FSK FSK Signal Frequency ‘0’ (Space) ‘1’ (Mark) 487Hz 2200Hz 387Hz 1200Hz W hen bit 7 of the TX TONES Register is set to ‘1’, the block generates DTMF tone pairs or single tones from the DTMF range as shown in the table below. Bit 6 of the TX TONES Register is then used to enable or disable the block’s output to the Tx filter. TX DATA Register Bits 0-3 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1.5.7 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DTMF Tone Pairs (TX TONES Register Bit 4 = ‘0’) Lower Upper Keypad Frequency (Hz) Frequency (Hz) Legend 941 1633 D 697 1209 1 697 1336 2 697 1477 3 770 1209 4 770 1336 5 770 1477 6 852 1209 7 852 1336 8 852 1477 9 941 1336 0 941 1209 * 941 1477 # 697 1633 A 770 1633 B 852 1633 C Single Tone (Bit 4 = ‘1’) Single Tone Frequency (Hz) 1633 1209 1336 1477 1209 1336 1477 1209 852 852 941 941 941 697 770 852 Transmit Filter This stage attenuates out of band signals present at the output of the FSK/DTMF modulator and also includes a programmable 3dB level switch, selected by bit 2 of the FSK MODE Register. The nominal output levels at the TOP pin when VDD = 5.0V are as shown below. FSK MODE Register bit 2 0 (low level) 1 (high level) 0dB = 775mVrms FSK Signal -6dB -3dB DTMF Tone (Low group) -5dB -2dB DTMF Tone (High group) -3dB 0dB These levels are proportional to VDD, and the actual transmit signal levels present on the 2- or 4-wire line will depend on the external circuitry as described in Section 1.6.1. Using the external components recommended in Section 1.6.1 for a nominal FSK transmit level of -9dBm, DTMF tone levels of -8dBm and -6dBm, then the out of band energy sent to the line will be within the limits shown in Figure 5 for both FSK and DTMF signals.  2003 CML Microsystems Plc 9 D/624/7 V23 / Bell 202 Modem CMX624 0 -10 Bell 202 -20 -30 dBm -40 -50 -60 -70 10 100 1000 Hz 10000 100000 V23 Figure 5 Maximum Out of Band Tx Line Energy Limits 1.5.8 Transmit Output Buffer This buffer amplifier, connected to the TXN, TXO and TXON pins, is intended for use as a Tx line driver as shown in Section 1.6.1. Two symmetrical outputs are provided for use with a balanced load to give sufficient Tx line signal levels even at low VDD. If this is not required the TXON output can be disabled. If the buffer is used as a balanced line driver, then bit 6 of the SETUP Register should be set to ‘1’ (TXON output enabled). Setting bit 6 to ‘0’ disables the TXON output and the buffer draws less current from the supply. When bit 6 is set to '0' the TXON pin should be left open circuit. N.B. The TXO output is unaffected by this bit. 1.5.9 Ring Signal Detector This block, which functions even in Zero Power mode, can be used to detect a telephone line Ring Signal or Line Voltage Reversal and then generate a Interrupt Request signal to wake up the µC at the start of a call. Suitable interface circuits are shown in Section 1.6.2. The output of this block is the ‘Ring Detect’ line shown in Figure 1 which directly drives bit 6 of the FLAGS Register. Any ‘0’ to ‘1’ or ‘1’ to ‘0’ change on this line will also set the ‘Ring Detect Change’ bit (5) of the FLAGS Register. If this block is not used, then the RD and RT pins should be connected to VSS and the ‘Ring Detect Change’ bit (5) of the IRQ MASK Register set to ‘0’.  2003 CML Microsystems Plc 10 D/624/7 V23 / Bell 202 Modem CMX624 1.5.10 Tx/Rx UART This block connects the µC, via the ‘C-BUS’ interface, to the received data from the FSK Demodulator and to the transmit data input to the FSK Modulator. As part of this function, the block can be programmed to convert data to be transmitted from 7 or 8-bit bytes to asynchronous data characters, adding Start and Stop bits and - optionally - a parity bit to the data before passing it to the FSK Modulator. Similarly, in the receive direction it can extract data bits from asynchronous characters coming from the FSK Demodulator, stripping off the Start and Stop bits and performing an optional Parity check on the received data before passing the result over the ‘C-BUS’ to the µC. Bits 0-3 of the SETUP Register control the number of Stop and Data bits and the Parity options for both receive and transmit directions. Data to be transmitted should be loaded by the µC into the TX DATA Register when the Tx Data Ready bit (bit 0) of the FLAGS Register goes high. It will then be treated by the Tx UART block in one of two ways, depending on the setting of bit 3 of the FSK MODE Register: If the bit is ‘0’ (‘Tx Sync’ mode) then the 8 bits from the TX DATA Register will be transmitted sequentially at 75, 150 or 1200bps, LSB (D0) first. If bit 3 of the FSK MODE Register is ‘1’ (‘Tx Async’) then bits will be transmitted as asynchronous data characters at 75, 150 or 1200 bps according to the following format: One Start bit (Space). 7 or 8 Data bits from the TX DATA Register (D0-D6 or D0-D7) as determined by bit 0 of the SETUP Register. LSB (D0) transmitted first. Optional Parity bit (even or odd parity) as determined by bits 1 and 2 of the SETUP Register. One or Two Stop bits (Mark) as determined by bit 3 of the SETUP Register. In both cases data will only be transmitted if bit 1 of the FSK MODE Register is set to ‘1’. Failure to load the TX DATA Register with a new value when required will result in bit 1 (Tx Data Underflow) of the FLAGS Register being set to ‘1’ and if the ‘Tx Async’ mode of operation had been selected then a continuous Mark (‘1’) signal will then be transmitted until a new value is loaded into TX DATA, whereas in ‘Tx Sync’ mode the byte already in the TX DATA Register will be re-transmitted. Figure 6a Transmit UART Function (Async)  2003 CML Microsystems Plc 11 D/624/7 V23 / Bell 202 Modem CMX624 Received data from the FSK Demodulator goes into the receive part of the UART block, where it is handled in one of two ways depending on the setting of bit 7 of the FSK MODE Register: If the bit is ‘0’ (‘Rx Sync’ mode) then the receive part of the UART block will simply take 8 consecutive bits from the Demodulator and transfer them to the RX DATA Register (the first bit going into the D0 position). Note that this mode is intended for detection of simple data patterns such as ‘1010…’ or continuous Mark or Space signals, the CMX624’s receive data clock extraction circuits are not adequate to support a true synchronous receive data mode of operation. If bit 7 of the FSK MODE Register is ‘1’ (‘ Rx Async’) then the received data output of the FSK Demodulator is treated as 75, 150 or 1200 bps asynchronous characters each comprising: A Start bit (Space). 7 or 8 Data bits as determined by bit 0 of the SETUP Register. These bits will be placed into the RX DATA Register with the first bit received going into the D0 position. An optional Parity bit as determined by bits 1 and 2 of the SETUP Register. If Parity is enabled (bit 2 of the SETUP Register = ‘1’) then bit 7 of the FLAGS Register will be set to ‘1’ if the received parity is incorrect. At least one Stop bit (Mark). Bit 2 (Rx Data Ready) of the FLAGS Register will be set to ‘1’ every time a new received value is loaded into the RX DATA Register. If the previous contents of the RX DATA Register had not been read out over the ‘C-BUS’ before the new value is loaded from the UART then bit 3 (Rx Data Overflow) of the FLAGS Register will also be set to ‘1’. Figure 6b Receive UART Function (Async)  2003 CML Microsystems Plc 12 D/624/7 V23 / Bell 202 Modem CMX624 1.5.11 ‘C-BUS’ Interface This block provides for the transfer of data and control or status information between the CMX624’s internal registers and the µC over the ‘C-BUS’ serial bus. Each transaction, see Figure 7, consists of a single Register Address byte sent from the µC which may be followed by a single data byte sent from the µC to be written into one of the CMX624’s Write Only Registers, or a single byte of data read out from one of the CMX624’s Read Only Registers, as illustrated in Figure 7. Data sent from the µC on the Command Data line is clocked into the CMX624 on the rising edge of the Serial Clock input. Reply Data sent from the CMX624 to the µC is valid when the Serial Clock is high. The interface is compatible with the most common µC serial interfaces such as SCI, SPI and Microwire, and may also be easily implemented with general purpose µC I/O pins controlled by a simple software routine. See Figure 10 for detailed ‘C-BUS’ timing requirements. Figure 7 ‘C-BUS’ Transactions  2003 CML Microsystems Plc 13 D/624/7 V23 / Bell 202 Modem CMX624 1.5.12 ‘C-BUS’ Registers Write Only ‘C-BUS’ Registers Addr $01 $E0 $E1 Reg. RESET 7 6 N/A TXON o/p: 0 = Off 1 = On Tone or FSK o/p: 0 = Off. 1 = On. 5 N/A Relay Drive: 0 = o/c 1 = Pull low Reserved, set to 0 Command Data Byte Bits 4 3 N/A 0 = Zero Power 1 = Normal 0 = DTMF 1 = Single tone N/A Stop bits: 0 = 1 bit 1 = 2 bits Reserved, set to 0 2 N/A Parity: 0 = None 1 = Parity Reserved, set to 0 1 N/A Parity: 0 = Odd 1 = Even Reserved, set to 0 0 N/A Data bits: 0 = 8 bits 1 = 7 bits Set Detect: 0 = FSK/CP 1 = 2100Hz N/A FSK mode: SETUP 0 = V.23 1 = Bell 202 Tx Mode: TX TONES 0 = FSK. 1 = Tones. $E3 $E7 TX DATA FSK MODE IRQ MASK D7 D6 0 = Rx Sync Rx Equal: 1 = Async 0 = Off 1 = On Reserved, Set to 0 Reserved, Set to 0 D5 0 = Rx Call Progress 1 = Rx FSK Ring Detect Change D4 0 = Rx 75 / 150 bps 1 = 1200 Reserved, Set to 0 D3 0 = Tx Sync 1 = Async D2 Tx o/p level: 0 = Normal 1 = +3dB Rx Data ready D1 FSK enable: $EE Rx Data overflow 0 = Off 1 = On (Tx & Rx) Tx Data underflow D0 0 = Tx 75 / 150 bps 1 = 1200 or DTMF Tx Data ready Read Only ‘C-BUS’ Registers Addr $EA $EF Reg. RX DATA FLAGS 7 D7 Bad Rx Parity 6 D6 Ring Detect 5 D5 Ring Detect Change ** Reply Data Byte Bits 4 3 D4 Rx Energy or 2100Hz detect. D3 Rx Data overflow ** 2 D2 Rx Data ready ** 1 0 D1 D0 Tx Data Tx Data underflow ** ready ** ** See notes 2 and 3 Notes: 1. Accessing the RESET Register over the ‘C-BUS’ clears all of the bits in the SETUP, TX TONES, TX DATA, FSK MODE and IRQ MASK registers, and bits 0-3 and 5 of the FLAGS Register to ‘0’. This will set the device into Zero Power mode. Note that this is a single-byte ‘C-BUS’ transaction consisting solely of the address byte value $01. Note that putting the device in Zero Power mode by directly setting SETUP Bit 4 to ‘0’ does not clear the other register bits. Care should be taken before re-enabling the device that the other bits are set so as to prevent undesired transient operation. In particular, bit 6 of the TXTONES Register should be set to ‘0’ to prevent modulation of the transmitter output. 2. 3. 4. 5. 6. If any of bits 0, 1, 2, 3 or 5 of the FLAGS Register is ‘1’ and the corresponding bit of the IRQ MASK Register is also ‘1’ then the IRQN output of the CMX624 will be pulled low. Bit 5 (Ring Detect Change) of the FLAGS Register is set on every ‘0’ to ‘1’ or ‘1’ to ‘0’ change of bit 6 (Ring Detect). Clearing bit 4 of the SETUP Register puts the CMX624 into the Zero Power mode by turning off all blocks except for the ‘C-BUS’ interface and Ring Detector circuit. Reading the FLAGS Register clears the IRQN output and also clears bits 0, 1, 2, 3 and 5 of the FLAGS Register. FLAGS Register (bit 4) is ‘1’ whenever the received signal being looked for is detected and ‘0’ when both signals are absent. IRQ MASK Register (bit 4) is normally set to ‘0’ - but can be set to ‘1’ to enable interrupts on the IRQN output. In the latter case, IRQN will be continuously pulled to ‘0’ whilst Rx Energy or 2100Hz are present. This may be useful for device evaluation purposes.  2003 CML Microsystems Plc 14 D/624/7 V23 / Bell 202 Modem CMX624 1.6 1.6.1 Application Notes Line Interface A line interface circuit is needed to provide dc isolation between the modem and the line, to perform line impedance termination, and to set the correct transmit and receive signal levels. 4-Wire Line Interface Figure 8a shows an interface circuit for use with a 600Ω 4-wire line. The line terminations are provided by R10 and R15, while R11 and R13 should be selected to give the desired transmit and receive levels. The gain of the receive input amplifier (R12 / R11) should be set to compensate for the loss of the input transformer and the supply voltage. Assuming transformer loss of about 1dB, R11 should be 91kΩ at 5.0V, or 130kΩ at 3.0V. Note relay circuit, ac and dc loads and line protection not shown for clarity. R10 R11 R12 600Ω See text 100kΩ R13 R14 R15 See text 100kΩ 600Ω C10 C11 C12 C13 100nF 220pF 330pF 100nF Resistors ±1%, capacitors ±20%. Figure 8a 4-Wire Line Interface Circuit  2003 CML Microsystems Plc 15 D/624/7 V23 / Bell 202 Modem CMX624 In the transmit direction, the level on the 4-wire line is determined by the level at the TOP pin, the gain of the Output Buffer Amplifier, a loss of nominally 6dB due to the line termination resistor R15, and the loss in the transformer. The TOP pin signal level is proportional to VDD and is also affected by the setting of the Tx o/p level control bit (bit 2) of the FSK Mode Register. Assuming that the Tx o/p level control bit is set to ‘1’ (giving a FSK signal level of -3dB wrt 775mVrms at the TOP pin when VDD = 5.0V) and that there is 1dB loss in the transformer, then: Tx FSK 4-wire line level = -(3 +6 +1) + 20 x LOG10(2 x R14 / R13) + 20 x LOG10(VDD / 5.0) dBm For example, to generate a nominal Tx FSK line level of -9dBm, R13 should be 180kΩ when VDD = 5.0V, falling to 120kΩ at 3.3V. 2-Wire Line Interface Figure 8b shows an interface circuit suitable for connection to a 600Ω 2-wire line. The circuit also shows how a relay may be driven from the RLYDRV pin. Note that when the CMX624 is powered from less than 5.0V, buffer circuitry will be required to drive a 5V relay. Note ac and dc loads and line protection not shown for clarity. R11 R12 R13 R14 See text 100kΩ See text 100kΩ R15 R16 R17 600Ω 120kΩ 100kΩ C11 C12 C13 C14 220pF 330pF 10nF 100nF Resistors ±1%, capacitors ±20% Figure 8b 2-Wire Line Interface Circuit This circuit includes a 2-wire to 4-wire hybrid circuit, formed by R11, R15, R16, R17, C13 and the impedance of the line itself, which ensures that the modem receive input and transmit output paths are both coupled efficiently to the line, while minimising coupling from the modem’s transmit signal into the receive input. The values of R11 and R13 should be calculated in the same way as for the 4-wire interface circuit of Figure 8a.  2003 CML Microsystems Plc 16 D/624/7 V23 / Bell 202 Modem CMX624 1.6.2 Ring Detector Interface Figure 9 shows how the CMX624 may be used to detect the large amplitude Ringing signal received at the start of an incoming telephone call. The ring signal is usually applied at the subscriber's exchange as an ac voltage inserted in series with one of the telephone wires and will pass through either C20 and R20 or C21 and R21 to appear at the top end of R22 (point X in Figure 9) in a rectified and attenuated form. The signal at point X is further attenuated by the potential divider formed by R22 and R23 before being applied to the CMX624 RD input. If the amplitude of the signal appearing at RD is greater than the input threshold (Vthi) of Schmitt trigger 'A' then the N transistor connected to RT will be turned on, pulling the voltage at RT to VSS by discharging the external capacitor C22. The output of the Schmitt trigger 'B' will then go high, setting bit 6 (Ring Detect) of the FLAGS Register. The minimum amplitude ringing signal that is certain to be detected is: ( 0.7 + Vthi x [R20 + R22 + R23] / R23 ) x 0.707 Vrms where Vthi is the high-going threshold voltage of the Schmitt trigger A (see Section 1.7.1). With R20-22 all 470kΩ as Figure 9, then setting R23 to 68kΩ will guarantee detection of ringing signals of 40Vrms and above for VDD over the range 3.0 to 5.5V. R20, 21, 22 R23 R24 C20, 21 470kΩ See text C22 D1-4 470kΩ Resistors ±1%, capacitors ±20% 0.1µF 0.33µF 1N4004 Figure 9 Ring Signal Detector Interface Circuit  2003 CML Microsystems Plc 17 D/624/7 V23 / Bell 202 Modem CMX624 If the time constant of R24 and C22 is large enough then the voltage on RT will remain below the threshold of the 'B' Schmitt trigger for the duration of a ring cycle. The time for the voltage on RT to charge from VSS towards VDD can be derived from the formula VRT = VDD x [1 - exp(-t/(R24 x C22)) ] As the Schmitt trigger high-going input threshold voltage (Vthi) has a minimum value of 0.56 x VDD , then the Schmitt trigger B output will remain high for a time of at least 0.821 x R24 x C22 following a pulse at RD. The values of R24 and C22 given in Figure 9 (470kΩ and 0.33µF) give a minimum RT charge time of 100 msec, which is adequate for ring frequencies of 10Hz or above. Note that the circuit will also respond to a telephone line voltage reversal. If necessary the µC can distinguish between a Ring signal and a line voltage reversal by measuring the time that bit 6 of the FLAGS Register (Ring Detect) is high.  2003 CML Microsystems Plc 18 D/624/7 V23 / Bell 202 Modem CMX624 1.7 1.7.1 Performance Specification Electrical Performance 1.7.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Min. -0.3 -0.3 -50 -20 Max. 7.0 VDD + 0.3 +50 +50 +20 Unit V V mA mA mA Supply (VDD - VSS) Voltage on any pin to VSS Current into or out of VDD and VSS pins Current into RLYDRV pin Current into or out of any other pin D2 Package Total Allowable Power Dissipation at Tamb = 25°C ... Derating Storage Temperature Operating Temperature D5 Package Total Allowable Power Dissipation at Tamb = 25°C ... Derating Storage Temperature Operating Temperature P4 Package Total Allowable Power Dissipation at Tamb = 25°C ... Derating Storage Temperature Operating Temperature Min. -55 -40 Min. Max. 800 13 +125 +85 Max. 550 9 +125 +85 Max. 800 13 +125 +85 Unit mW mW/°C °C °C Unit mW mW/°C °C °C Unit mW mW/°C °C °C -55 -40 Min. -55 -40 1.7.1.2 Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply (VDD - VSS) Operating Temperature Xtal Frequency Notes: Min. 2.7 -40 3.575965 Max. 5.5 +85 3.583125 Unit V °C MHz 1 1. A Xtal frequency of 3.579545MHz ±0.1% is required for correct operation.  2003 CML Microsystems Plc 19 D/624/7 V23 / Bell 202 Modem CMX624 1.7.1.3 Operating Characteristics For the following conditions unless otherwise specified: VDD = 2.7V at Tamb = 25°C and VDD = 3.0V to 5.5V at Tamb = -40 to +85°C, Xtal Frequency = 3.579545MHz ± 0.1%, 0dBm corresponds to 775mVrms. DC Parameters IDD (Zero Power mode) (Running, TXON o/p Off, VDD= 5.0V) (Running, TXON o/p Off, VDD= 3.3V) (Running, TXON o/p On, VDD= 5.0V) (Running, TXON o/p On, VDD= 3.3V) Logic '1' Input Level Logic '0' Input Level Logic Input Leakage Current (Vin = 0 to VDD), (excluding XTAL/CLOCK input) Output Logic '1' Level (lOH = 360µA) Output Logic '0' Level (lOL = 360µA) IRQN O/P 'Off' State Current (Vout = VDD) Schmitt trigger input high-going threshold (Vthi) (see Figure 11) Schmitt trigger input low-going threshold (Vtlo) (see Figure 11) RLYDRV ‘ON’ resistance to VSS (VDD= 5.0V) Notes: Notes 1, 2 1 1 1 1 3 3 Min. 70% -1.0 VDD-0.4 0.56VDD 0.44VDD - 0.6V Typ. 1.0 3.4 1.8 3.5 1.9 38.0 Max. 6.0 3.2 6.2 3.4 30% +1.0 0.4 1.0 0.56VDD + 0.6V 0.44VDD TBD Unit µA mA mA mA mA VDD VDD µA V V µA V V Ω 1. At 25°C, not including any current drawn from the CMX624 pins by external circuitry other than X1, C1 and C2. 2. All logic inputs at VSS except for RT and CSN inputs which are at VDD. 3. Excluding RD, RT and XTAL/CLOCK pins. Notes 4 Min. -4.0 -2.0 1194 1297 2097 74 388 448 1194 1197 2197 149 385 485 Typ. -3.0 0 1200 1300 2100 75 390 450 1200 1200 2200 150 387 487 Max. -2.0 +2.0 1206 1303 2103 76 392 452 1206 1203 2203 151 389 489 Unit dBm dB Baud Hz Hz Baud Hz Hz Baud Hz Hz Baud Hz Hz FSK Modulator and Tx UART Level at TOP pin. Twist (Mark level WRT Space level) Tx 1200bits/sec (V.23 mode) Baud Rate (set by UART and Xtal frequency) Mark (Logical 1) Frequency Space (Logical 0) Frequency Tx 75bits/sec (V.23 mode) Baud Rate (set by UART and Xtal frequency) Mark (Logical 1) Frequency Space (Logical 0) Frequency Tx 1200bits/sec (Bell 202 mode) Baud Rate (set by UART and Xtal frequency) Mark (Logical 1) Frequency Space (Logical 0) Frequency Tx 150bits/sec (Bell 202 mode) Baud Rate (set by UART and Xtal frequency) Mark (Logical 1) Frequency Space (Logical 0) Frequency Notes: 4. At VDD = 5.0V, Tx o/p level control bit set to ‘1’; load resistance greater than 40kΩ.  2003 CML Microsystems Plc 20 D/624/7 V23 / Bell 202 Modem CMX624 DTMF Transmitter Level at TOP pin; tones in High Group Twist (level of High Group tones WRT level of Low Group tones) Tone frequency accuracy (worst case) Notes 4 Min. -1.0 -0.5 Typ. 0.0 +2.0 - Max. +1.0 +0.5 Unit dBm dB % Tx Filter and Output Buffer Change in level at TOP pin caused by changing bit 2 of FSK MODE Register Buffer output signal swing; Load greater than 500Ω. Notes: Notes Min. 2.5 2.2 Typ. 3.0 - Max. 3.5 - Unit dB Vp-p 5 5. For each of the TXON (if enabled) and TXO pins, load between pin and VDD / 2. Notes 6 7 8 Min. -43.0 -7.0 20.0 1188 1280 2068 TBD TBD TBD 1188 1180 2168 TBD TBD TBD Typ. 1200 1300 2100 75 390 450 1200 1200 2200 150 387 487 Max. -9.0 +7.0 1212 1320 2132 TBD TBD TBD 1212 1220 2232 TBD TBD TBD Unit dBm dB dB Baud Hz Hz Baud Hz Hz Baud Hz Hz Baud Hz Hz FSK Demodulator and Rx UART Valid Input Level Range Acceptable Twist (Mark level WRT Space level) Acceptable Signal to Noise Ratio Rx 1200bits/sec (V.23 mode) Acceptable Rx Data Rate Mark (Logical 1) Frequency Space (Logical 0) Frequency Rx 75bits/sec (V.23 mode) Acceptable Rx Data Rate Mark (Logical 1) Frequency Space (Logical 0) Frequency Rx 1200bits/sec (Bell 202 mode) Acceptable Rx Data Rate Mark (Logical 1) Frequency Space (Logical 0) Frequency Rx 150bits/sec (Bell 202 mode) Acceptable Rx Data Rate Mark (Logical 1) Frequency Space (Logical 0) Frequency Notes: 8 8 8 6. Measured at point A in Figures 8a and 8b, for VDD = 5.0V. The internal threshold levels are proportional to VDD. To cater for other supply voltages or different signal level ranges the voltage gain of the Rx Input Amplifier should be adjusted by selecting the appropriate external components as described in Section 1.6.1. 7. Flat noise in 300-3400 Hz band for V.23, 200-3400 Hz for Bell 202. 8. Set by Rx UART and Xtal frequency. Notes Min. 2040 2265 25 Unit Hz Hz ms ms 2100Hz Detector ‘Will Decode’ Frequency Range ‘Will Not Decode’ Frequency Range ‘Off’ to ‘On’ time ‘On’ to ‘Off’ time Notes: 9 9 9. 2100Hz detection requires a signal within the amplitude range given in the Rx Energy Detector section.  2003 CML Microsystems Plc 21 D/624/7 V23 / Bell 202 Modem CMX624 Rx Energy Detector ‘Off’ to 'On' Threshold Level (FSK) ‘Off’ to 'On' Threshold Level (Call Progress) Hysteresis (measured at VDD = 3V and 5V) 'Off' to 'On' Time (Figure 4 Teon): 1200bps Rx mode 75/150bps Rx mode Call Progress Detect mode 'On' to 'Off' Time (Figure 4 Teoff): 1200bps Rx mode 75/150bps Rx mode Call Progress Detect mode Notes: Notes 6, 10 6, 10 6, 10 6, 10 Min. -48.0 -48.0 2.0 - Typ. - Max. -43.0 -40.0 25 48 48 - Unit dBm dBm dB ms ms ms ms ms ms 6, 10 8.0 20 20 10. Measured with 1300Hz signal in 1200bps mode, 390Hz for 75 or 150 bps and Call Progress mode, signal level -33dBm for time delay measurements. XTAL/CLOCK Input 'High' Pulse Width 'Low' Pulse Width Notes: Notes 11 11 Min. 100 100 Typ. - Max. - Unit ns ns 11. Timing for an external input to the XTAL/CLOCK pin. ‘C-BUS’ Timings (See Figure 10) tCSE CSN-Enable to Clock-High time tCSH Last Clock-High to CSN-High time Clock-Low to Reply Output enable time tLOZ CSN-High to Reply Output 3-state time tHIZ CSN-High Time between transactions tCSOFF Inter-Byte Time tNXT Clock-Cycle time tCK Serial Clock-High time tCH Serial Clock-Low time tCL Command Data Set-Up time tCDS Command Data Hold time tCDH Reply Data Set-Up time tRDS Reply Data Hold time tRDH Notes Min. 100 100 0.0 1.0 200 200 100 100 75 25 50 0 Typ. - Max. 1.0 - Unit ns ns ns µs µs ns ns ns ns ns ns ns ns Note: These timings are for the latest version of the ‘C-BUS’ as embodied in the CMX624.  2003 CML Microsystems Plc 22 D/624/7 V23 / Bell 202 Modem CMX624 Figure 10 ‘C-BUS’ Timing 3.5 3 2.5 2 Vin 1.5 1 0.5 0 2.5 3 3.5 4 Vdd 4.5 5 5.5 Vthi Vtlo Figure 11 Typical Schmitt Trigger Input Voltage Thresholds vs. VDD  2003 CML Microsystems Plc 23 D/624/7 V23 / Bell 202 Modem CMX624 1.7.2 Packaging Figure 12a 24-pin SOIC (D2) Mechanical Outline: Order as part no. CMX624D2 Figure 12b 24-pin SSOP (D5) Mechanical Outline: Order as part no. CMX624D5  2003 CML Microsystems Plc 24 D/624/7 V23 / Bell 202 Modem CMX624 Figure 12c 24-pin DIL (P4) Mechanical Outline: Order as part no. CMX624P4 Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed. w ww.cmlmicro.com For FAQs see: www.cmlmicro.com/products/faqs/ For a full data sheet listing see: www.cmlmicro.com/products/datasheets/download.htm For detailed application notes: www.cmlmicro.com/products/applications/ Oval Park, Langford, Maldon, Essex, CM9 6WG - England. 4800 Bethania Station Road, Winston-Salem, NC 27105 - USA. No 2 Kallang Pudding Road, #09 to 05/06 Mactech Industrial Building, Singapore 349307 No. 218, Tian Mu Road West, Tower 1, Unit 1008, Shanghai Kerry Everbright City, Zhabei, Shanghai 200070, China. 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