CMX993Q3

CMX993/CMX993W CML Microcircuits 30MHz – 1GHz Quadrature Modulator COMMUNICATION SEMICONDUCTORS D/993/12 May 2021 Provisional Issue This document describes two separate, high performance, RF quadrature modulator ICs: The standard CMX993 and the wide bandwidth CMX993W product variant. Features Applications                    30MHz to 1GHz Operating Frequency Wide Band Noise –148dBc/Hz Noise Floor –155dBm/Hz Programmable 30dB Output Gain Range +3dBm (PEP) Output Power Low LO Drive Requirements, -15dBm Uncommitted Amplifiers for Filtering and Interfacing CMX993W – Wide Bandwidth Version (>50MHz I/Q Bandwidth) C-BUS (SPI Compatible) Serial Interface Low Voltage 3.3V Operation Small 7x7mm VQFN Package (Q3) +25dBm Equivalent Output IP3 Input Amplifiers       Filter/Interface Amplifiers APCO P25, Wireless Data ISM Transmitters Digital TV/CATV Modulators Wireless LAN, Wireless Local Loop IF or RF Modulators FSK, GMSK, 4FSK, C4FM QPSK, QAM, SSB, OFDM, Multi-carrier Systems SDR (Software Defined Radios) WiMAX Systems OFDM/COFDM Systems Satellite Communications Cellular Picocell / Nanocell Systems RF Channel Bandwidths up to 100MHz I/Q Mixer and Gain Control I Channel I/Q MOD Output Q Channel LO Input 1 Divide by 2 or Divide by 4 0° Bandgap VREF Control Interface C-BUS 90° Brief Description The CMX993 and CMX993W are integrated, low voltage quadrature (I/Q) modulator ICs suitable for use in applications operating from 30MHz to 1000MHz. The devices integrate two matched double balanced mixers driven from a buffered and quadrature split local oscillator. The LO frequency is divided by either 2 or 4. The mixers form an I/Q vector modulator with programmable gain stages offering up to 30dB of gain, controlled in 2.5dB steps. Uncommitted low frequency differential amplifiers are provided for users to configure. These may be used to implement functions such as filtering, differential- to single-ended signal conversion and level shifting. The CMX993W product variant offers wide-bandwidth operation. A digital control interface, C-BUS, (an SPI compatible interface) allows gain control as well as power management of individual internal blocks to optimise system performance. The C-BUS interface operates from its own supply domain enabling the device to be interfaced to different voltage baseband devices. The CMX993 and CMX993W devices are supplied in RF optimised VQFN packages.  2021 CML Microsystems Plc Quadrature Modulator CMX993/CMX993W CONTENTS Section 1 1.1 2 Page Brief Description .................................................................................................. 1 History............................................................................................................. 3 Block Diagrams .................................................................................................... 4 3 3.1 Signal List ............................................................................................................. 5 Signal Definitions .......................................................................................... 6 4.1 4.2 4.3 External Components .......................................................................................... 7 Power Supply Decoupling ............................................................................ 7 Quadrature Modulator ................................................................................... 8 Local Oscillator Input .................................................................................. 10 5.1 5.2 5.3 5.4 General Description ........................................................................................... 11 Quadrature Modulator ................................................................................. 11 Differential Amplifiers.................................................................................. 11 Reference Voltages ..................................................................................... 12 Data Interface ............................................................................................... 12 6.1 6.2 6.3 6.4 C-BUS Interface and Register Description ...................................................... 13 General Reset Command: C-BUS address $01 ....................................... 13 General Control Register: C-BUS address $02 8-bit write-only ............ 14 Gain Control Register: C-BUS address $05 8-bit write-only ................ 14 Frequency Control Register: C-BUS address $08 8-bit write-only ....... 15 7.1 7.2 Application Notes ............................................................................................... 16 Typical Performance ................................................................................... 16 Intermodulation and Modulator Spurious ................................................. 18 8.1 8.2 Performance Specification ................................................................................ 20 Electrical Performance ................................................................................ 20 Packaging ..................................................................................................... 26 4 5 6 7 8  2021 CML Microsystems Plc 2 D/993/12 Quadrature Modulator 1.1 History Version 12 11 10 9 8 7 6 5 4 3 2 1 CMX993/CMX993W Changes  Section 4.3 – corrected Figure 5 and typo in manufacturer’s part number.  Gain steps variation specified  LO input level specified to -20dBm for operation above 200MHz.  Editorial corrections  Extra information on third order intermodulation added.  Note added for clarification in Figure 4 / Figure 4a.  Added note 32 to AC Parameters section, identifying a drop in gain and output power below a frequency of 100MHz - typically 4dB down at 30MHz.  Differential Amplifier connections in Figure 4 and Figure 4a corrected.  Operating characteristics clarified for Tamb rather than Tcase and at 25degC only for notes 0 and 1.  Current consumption specification reduced, following test of several wafer batches.  Editorial corrections, Modulator Common Mode input range minimum now 1.3V and Input/Filter Amplifiers ‘Input Offset’ specification updated.  Updated inline with abbreviations and pin assignments document  CMX993W wide-bandwidth product variant included  Lowest operating frequency specified as 30MHz  Change to pin out and Signal List  Original document, first approved.  2021 CML Microsystems Plc 3 Date 18/5/21 7/8/20 13/2/13 13/3/10 3/2/10 20/1/10 30/11/09 30/06/09 29/05/09 28/05/09 7/11/08 14/8/08 D/993/12 Quadrature Modulator A1QP + A1QN - Input Amplifier A1QO VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 Ground VEE VDD DVSS + Filter Amplifier Divide by 2 or Divide by 4 - A2QP LON Block Diagrams LOP 2 CMX993/CMX993W A2QO MODQP MODQN MOP Mixer Gain Control MODIN MODIP MON VREF A2IO BVREF Bandgap - A1IO A1IN - A1IP VDDIO Filter Amplifier + A2IP + C-BUS Control Interface Input Amplifier CDATA CSN SCLK RESETN 100k External Reset CMX993 A1QP + A1QN - A2QP + A2QN - A1QO LON LOP Figure 1 CMX993 Block Diagram Input Amplifier VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 Ground VEE VDD DVSS Filter Amplifier Divide by 2 or Divide by 4 A2QO MODQP MODQN MOP Mixer Gain Control MODIN MODIP MON VREF A2IO + A2IP BVREF Bandgap - A2IN A1IO A1IN - A1IP VDDIO Filter Amplifier + Input Amplifier C-BUS Control Interface CDATA CSN SCLK RESETN 100k External Reset CMX993W Figure 1a CMX993W Block Diagram  2021 CML Microsystems Plc 4 D/993/12 Quadrature Modulator 3 CMX993/CMX993W Signal List CMX993 Pin No. CMX993W Pin No. Name Signal Type 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A2QN A2QO NC MODQP MODQN NC MON MOP NC MODIN MODIP NC A2IO A2IN A2IP A1IO A1IN A1IP VCC1 VCC2 I/P O/P NC I/P I/P NC O/P O/P NC I/P I/P NC O/P I/P I/P O/P I/P I/P Power Power 19 19 LON I/P 20 20 LOP I/P 21 22 23 24 25 26 27 28 29 30 31 32 33 34 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VCC3 VCC4 VREF BVREF NC NC NC NC VCC5 NC NC VCC6 NC NC Power Power O/P O/P NC NC NC NC Power NC NC Power NC NC  2021 CML Microsystems Plc Description Amplifier 2 negative input (Q channel) Amplifier 2 output (Q channel) reserved, do not connect to this pin Modulator input (Q channel) Modulator input reference (Q channel) reserved, do not connect to this pin Modulator negative output Modulator positive output reserved, do not connect to this pin Modulator input reference (I channel) Modulator input (I channel) reserved, do not connect to this pin Amplifier 2 output (I channel) Amplifier 2 negative input (I channel) Amplifier 2 positive input (I channel) Amplifier 1 output (I channel) Amplifier 1 negative input (I channel) Amplifier 1 positive input (I channel) Analogue supply Analogue supply Local Oscillator Negative Input (Note: when differentially driving LOP and LON this LON pin requires a low impedance dc path to ground otherwise it may be decoupled to ground) Local Oscillator Positive Input (Note: this pin requires a low impedance dc path to ground) Analogue supply Analogue supply Bandgap reference decoupling Buffered VREF reserved, do not connect to this pin reserved, do not connect to this pin reserved, do not connect to this pin reserved, do not connect to this pin Analogue supply reserved, do not connect to this pin reserved, do not connect to this pin Analogue supply reserved, do not connect to this pin reserved, do not connect to this pin 5 D/993/12 Quadrature Modulator CMX993/CMX993W CMX993 Pin No. CMX993W Pin No. Name Signal Type 35 36 37 38 39 40 41 42 43 44 45 46 47 48 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NC NC VDD VDDIO SCLK CDATA CSN RESETN DVSS VCC7 A1QP A1QN A1QO A2QP NC NC Power Power I/P I/P I/P I/P Power Power I/P I/P O/P I/P reserved, do not connect to this pin reserved, do not connect to this pin Digital supply Supply voltage for digital control interface C-BUS serial clock C-BUS command data input C-BUS enable General reset (Reset when pin is held LOW) Digital ground (0V) Analogue supply Amplifier 1 positive input (Q channel) Amplifier 1 negative input (Q channel) Amplifier 1 Output (Q Channel) Amplifier 2 positive input (Q channel) EXPOSED METAL PAD EXPOSED METAL PAD VEE Power This pad must be connected to analogue ground (0V) Description Table 1 Pin List I/P = Input O/P = Output T/S = 3-state NC = reserved, do not connect to this pin 3.1 Signal Definitions Signal Name Pins Usage DVDD VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7 VDD VDDIO VDDIO AVSS DVSS VEE (Metal pad) DVSS VREF VREF AVDD BVREF Power supply for analogue circuits Power supply for digital circuits Power supply voltage for digital interface (C-BUS and RESETN) Ground for all analogue circuits Ground for all digital circuits Connection for decoupling of internal bandgap reference voltage Buffered version of VREF which may be used for bias of input signals etc. BVREF Table 2 Definition of Power Supply and Reference Voltages  2021 CML Microsystems Plc 6 D/993/12 Quadrature Modulator CMX993/CMX993W 4 External Components 4.1 Power Supply Decoupling The CMX993/CMX993W has separate supply pins for the analogue and digital circuitry; a 3.3V nominal supply is recommended for all circuits but a different voltage for VDDIO may be used (see section 5.4). R9 +3.3V (Digital) VDDIO R8 VDD R7 VCC1 R6 VCC2 R5 +3.3V (Analogue) VCC3 R4 VCC4 R3 VCC5 VCC6 R1 VCC7 C9 C8 C7 C6 C5 C4 C3 C1 Analogue Ground Pad GND Digital Ground for VDDIO and VDD Figure 2 Power Supply Connections and Decoupling C1 C3 C4 C5 C6 C7 C8 C9 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF R1 R3 R4 R5 R6 R7 R8 R9 3.3 10 3.3 3.3 3.3 3.3 10 100 Resistors 5%, capacitors and inductors 20% unless otherwise stated Note: It is expected that low frequency interference on the 3.3V supply will be removed by active regulation; a large capacitor is an alternative but may require more board space and so may not be preferred. It is particularly important to ensure that there is no interference from VDDIO (which supplies the digital I/O) that might affect the sensitive analogue supplies, like VCC1, VCC2 etc. The supply decoupling shown is intended for RF noise suppression. It is necessary to have a small series impedance prior to the decoupling capacitor for the decoupling to work well; this may be cost effectively done with the resistor and capacitor values shown. The use of resistors results in small dc voltage drops (up to approx 0.1V). Choosing resistor values approximately inversely proportional to the dc current requirements of each supply ensures the dc voltage drop on each supply is reasonably matched. In any case, the dc voltage change that results is well within the design tolerance of the device. If higher impedance resistors are used then greater care will be needed to ensure the supply voltages are maintained within tolerance, including when parts of the device are enabled or disabled.  2021 CML Microsystems Plc 7 D/993/12 Quadrature Modulator 4.2 CMX993/CMX993W Quadrature Modulator Typical values for the quadrature modulator output circuits are shown in Figure 3/Table 3 and typical configuration and values for the input circuits in Figure 4/4a and Table 4. Concerning Figure 3, the transformer T1 should be located close to the CMX993/CMX993W and tracks from the MOP and MON pins to T1 should be as close to equal in length as possible, preferably with a symmetrical layout. The decoupling capacitor (C1) should be close to the centre tap of T1. Note: Details of a simpler alternative output configuration are provided in an Application Note available from www.cmlmicro.com. MOP MODQP MODQN T1 R3 MODIN MODIP MON R4 Output AVDD C1 VREF C4 Bandgap BVREF CMX993 CMX993W Figure 3 Modulator Output External Components (30MHz to 1GHz) C1 C4 10nF 1µF T1 R3, R4 Balun 4:1 (See Note 1) (See Note 2) Note 1: For example TC4-14+ from mini circuits; for applications between 200MHz and 1GHz or Coilcraft WBC4-1WL for applications between 30MHz and 300MHz. Note 2: The resistors R3 and R4 are optional. Fitting these with 110 resistors will give a good broadband match however will reduce output level available. For many applications they will be unnecessary. Table 3 Quadrature Modulator Output Components The input configuration in Figure 4/4a is a possible solution for a single ended input with 0V dc bias. The input amplifiers are used to translate the input to BVREF. In order to balance the small bias current drawn by the modulator, the filter amplifiers are used to buffer BVREF. RC filters are used on the input to the modulator to remove wideband noise generated by the differential amplifiers. The values of the resistors and capacitors should be selected based on the bandwidths of the modulation. It is important to keep the values of R6, R7, R8 and R9 the same so that small dc offsets generated by the modulator input bias currents are matched, thereby providing the best carrier rejection. The networks R6/C1, R7/C2, R8/C3 and R9/C4 should be placed close to the modulator input pins of the CMX993/CMX993W to ensure optimum noise performance. It is important to note that due to small input bias currents, offset voltages and component tolerances it is impractical to expect this type of input configuration to give ideal carrier suppression. To achieve optimal carrier suppression it is recommended to have the ability to finely adjust the dc offsets (see section 5.1.1).  2021 CML Microsystems Plc 8 D/993/12 Quadrature Modulator CMX993/CMX993W BVREF LO Input R2 + R3 R1 - Q in Q channel input amplifier R4 + R5 Q channel filter amplifier Divide by 2 or Divide by 4 - BVREF R6 C1 Balun R7 C2 R8 RF Output C3 R9 VREF C4 BVREF Bandgap I channel filter amplifier + BVREF R10 R11 - I in R12 BVREF CMX993 I channel input amplifier + R14 R13 Figure 4 CMX993 Modulator and Input/Filter Amplifier Typical Configuration LO Input R5 Q channel input amplifier - + BVREF BVREF R2 Q channel filter amplifier Divide by 2 or Divide by 4 + R3 R1 - Q in R4 R7 C2 C1 R9 R8 C4 C3 R12 I in RF Output VREF R11 BVREF Bandgap - BVREF R13 + Note: The modulation signals may be connected to the modulator via either the MODxN or MODxP inputs as long as the connection is the same for both I and Q channels. Balun R6 R14 I channel filter amplifier - R10 + BVREF I channel input amplifier CMX993W Figure 4a CMX993W Modulator and Input/Filter Amplifier Typical Configuration  2021 CML Microsystems Plc 9 D/993/12 Quadrature Modulator CMX993/CMX993W C1 C2 C3 C4 C5 R1 R2 R3 R4 R5 33nF Note 1 Note 1 33nF 1F 10k 5.1k 10k 5.1k 5.1k R6 R7 R8 R9 R10 R11 R12 R13 R14 10 10 10  10 5.1k 5.1k 10 k 5.1k 10k Resistors 5%, capacitors and inductors 20% unless otherwise stated Note1: Value should be selected depending on modulation bandwidth: 33nF typically for CMX993, 3.3nF typically for CMX993W Table 4 Quadrature Modulator and Input Circuits: Typical Components 4.3 Local Oscillator Input A 1:1 balun transformer should be used on the local oscillator input for optimum performance. In the local oscillator divide by 4 mode, a single ended input may be used by decoupling the LON pin to ground and applying the LO signal to LOP noting that a dc path to ground on LOP must still be provided. The divide by 4 mode is not recommended for operation below 200MHz LO frequency (50MHz RF output). For output frequencies below 50MHz the divide by 2 mode is recommended. Users should be aware that the presence of high levels of harmonics in the signal applied to the LO Input might degrade quadrature accuracy. T1 LOP LON LO_INPUT C1 1n CMX993/CMX993W Figure 5 LO Input Configuration using a 1:1 Balun (60MHz to 2GHz) C1 1nF T1 Balun 1:1 (e.g. MABA-007748-CT1160) from M/A-com, see Note 3) Notes: 1. The configuration of the 1:1 balun used at the LO input has to create a dc path to analogue GND for both LO inputs, LOP and LON as shown in Figure 5. 2. The capacitor C1 is optional and should be used where the 0V dc connection provided by the balun is not acceptable to the circuitry providing the LO signal. 3. The MABA-007748-CT11160 is specified between 5MHz and 1.2GHz. The part has been found to remain functional with the CMX993/CX993W up to at least 2GHz however such operation is outside the manufacturer's rating.  2021 CML Microsystems Plc 10 D/993/12 Quadrature Modulator 5 CMX993/CMX993W General Description The CMX993 and CMX993W are RF quadrature modulators with additional features such as gain control and uncommitted differential amplifiers. Detailed block diagrams for the ICs are shown in section 2. The ICs can support a wide range of modulation formats and standards including TDMA operation. The following sections describe the functionality of the ICs. 5.1 Quadrature Modulator The quadrature modulator provides translation from baseband I and Q signals to a modulated RF signal. The wideband inputs can be driven differentially or single-ended. In the case of single ended operation a reference voltage equal to the nominal dc level of the modulation must be supplied. The input and filter amplifiers allow single-ended signals to be translated to an appropriate dc level, one solution for an input signal with 0V dc bias is shown in Figure 4/4a. 5.1.1 DC Offsets and Carrier Leakage The modulator inputs (MODIN/MODIP and MODQN/MODQP) are differential and require a common dc level or common mode voltage. Differences in the bias voltages on the pins will result in an increased level of carrier present at the output. Care should be taken to minimise offsets, thereby minimising carrier leakage. Some systems implement carrier nulling before transmission. This results in a compensation of the small internal offsets in the modulator and any offsets generated in external circuits. Digital to analogue converters designed for I/Q systems, e.g. CMX981, often include registers which allow a programmable offset to be applied to the I/Q signals, making this nulling process straightforward. 5.1.2 Wideband Noise and Gain Control The wideband noise of this modulator is optimised to ensure a low noise floor at the output, compliant with common product standards. This stage also provides gain control, which allows the output level to be adjusted while maintaining the maximum possible signal-to-noise ratio. To ensure optimum performance the I/Q input signals need to be free from noise. The input bandwidth of the modulators is quite broad, so any noise on the I/Q signals will get translated to the RF output. Such noise can generally be removed by simple RC filters, as shown in Figure 4/4a. Careful attention needs to be paid to the bandwidth of these filters as, if unduly narrow, they can affect the modulation, degrading image rejection and modulation accuracy. 5.2 Differential Amplifiers 5.2.1 Input Amplifiers Two differential amplifiers are provided which may be used for signal conditioning, for example conversion of differential input signals to single ended format, or to provide dc level translation. The amplifiers are uncommitted, with the differential inputs and the output all available on pins. The stages are low power and are enabled using the ‘General Control Register’ (see section 6.2). It is not possible to independently control each amplifier, both are enabled with a common control bit.  2021 CML Microsystems Plc 11 D/993/12 Quadrature Modulator 5.2.2 CMX993/CMX993W Filter Amplifiers A further pair of amplifiers are provided which may be used to implement filtering or buffering. These uncommitted amplifiers (configured as voltage followers in the case of the CMX993) may be used to implement Sallen-Key style filters or configured as needed. The amplifiers are low power and are enabled using the ‘General Control Register’ (see section 6.2). It is not possible to independently control each amplifier, both are enabled with a common control bit. Note: Input Amplifiers and Filter Amplifiers have independent controls. 5.2.3 CMX993/CMX993W Difference The essential difference between the CMX993 and the CMX993W is the amplifier stage provided for the Filter Amplifier. In the CMX993, the Input Amplifier and Filter Amplifier are of a similar design with a gainbandwidth product of about 10MHz. To support wider modulation bandwidths the CMX993W uses a highspeed amplifier for the Filter Amplifier (Note: only the Filter Amplifier is different, the Input Amplifier in the CMX993W is the same as the Input amplifier in the CMX993.) Because of the extra gain/bandwidth in the CMX993W a ‘gain reduction’ mode is provided for the CMX993W Filter Amplifier, see section 6.2. 5.3 Reference Voltages The CMX993/CMX993W includes on-chip reference voltage generation. Any noise present on the VREF pin should be decoupled to Analogue Ground (VEE). A buffered version of the reference is provided on the BVREF pin. After further filtering to remove noise, this may be used to provide the dc reference for modulator mixer inputs. 5.4 Data Interface The CMX993/CMX993W is controlled via a three wire C-BUS. A further pin (RESETN) is provided which, when ‘low’, generates a reset signal (see section 6 for further details). This pin should be pulled to VDDIO with a suitable resistor (e.g. 100k) if not used. The data interface can run at a lower voltage than the rest of the IC by setting VDDIO to the required interface level in the range 1.6V to 3.6V. Full details of the control register structure are given in section 6.  2021 CML Microsystems Plc 12 D/993/12 Quadrature Modulator 6 CMX993/CMX993W C-BUS Interface and Register Description This block provides for the transfer of data and control information between the CMX993/CMX993W internal registers and the µC over the C-BUS serial bus. Each transaction consists of a single Register Address byte sent from the µC which may be followed by one Data byte sent from the µC, to be written into one of the CMX993/CMX993W registers, as illustrated in Figure 9. Data sent from the µC on the CDATA line is clocked into the CMX993/CMX993W on the rising edge of the SCLK input. The C-BUS interface is compatible with most common µC serial interfaces and may also be easily implemented with general purpose µC I/O pins controlled by a simple software routine. Figure 9 gives detailed C-BUS timing requirements. The following C-BUS addresses and registers are: General Reset Register (Address only, no data) General Command, 8-bit write only. Gain Control, 8-bit write only. Frequency Control Register, 8-bit write only Address $01 Address $02 Address $05 Address $08 Notes:   6.1 All registers will retain data if VDD and VDDIO are held high, even if all other power supply pins are disconnected. If clock and data lines are shared with other devices VDD and VDDIO must be maintained in their normal operating ranges otherwise ESD protection diodes may cause a problem with loading signals connected to SCLK and CDATA pins, preventing correct programming of other devices. Other supplies may be turned off and all circuits on the IC may be powered down without causing this problem. General Reset Command: C-BUS address $01 This command resets the device and clears all bits in all registers. The General Reset command places the device into powersave mode. Whenever power is applied to the DVDD pin, a built in power-on-reset circuit ensures that the device powers-up into the same state as that following a General Reset command. The RESETN pin on the device will also reset the device into the same state.  2021 CML Microsystems Plc 13 D/993/12 Quadrature Modulator 6.2 CMX993/CMX993W General Control Register: C-BUS address $02 8-bit write-only This register controls general features such as powersave. All bits of this register are cleared to 0 by a General Reset command. Bit: 7 6 5 4 3 2 1 0 I/Q Pwr 0 VREF Filter Amps Pwr Input Amps Pwr Wideband Filter Amps Pwr 0 Filter Amp Gain Reduction CMX993 only CMX993W only CMX993W only General Control Register b7-b1: Select high input gain These bits control power up/power down of the various blocks of the IC. In all cases, ‘1’ = power up, ‘0’ = power down. b7 b6 b5 Enable I/Q modulator and local oscillator sections reserved, set to ‘0’ Enable internal bias circuits and bandgap reference (VREF and BVREF). CMX993 – Enable filter amplifiers CMX993W – reserved, set to ‘0’ Enable input amplifiers CMX993 – reserved, set to ‘0’ CMX993W – Enable wide bandwidth filter amplifiers reserved, set to ‘0’ b4 b3 b2 b1 General Control Register b0: Filter Amplifier Gain Reduction CMX993W – Wide bandwidth filter amplifier gain reduction by adding 1k between output and negative input. CMX993W – Normal Operation CMX993 – reserved, set to ‘0’ b0 = 1 b0 = 0 b0 6.3 Gain Control Register: C-BUS address $05 8-bit write-only This register controls the gain of the I/Q modulator. Bit: 7 6 5 4 3 2 1 0 0 F4 F3 F2 F1 0 0 0 Gain Control Register b2-b0: Reserved for future use, set to '0'.  2021 CML Microsystems Plc 14 D/993/12 Quadrature Modulator CMX993/CMX993W Gain Control Register b6-b3: Modulator Attenuation b6 b5 b4 b3 F4 F3 F2 F1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 30dB Attenuation 27.5dB Attenuation 25dB Attenuation 22.5dB Attenuation 20dB Attenuation 17.5dB Attenuation 15dB Attenuation 12.5dB Attenuation 10dB Attenuation 7.5dB Attenuation 5dB Attenuation 2.5dB Attenuation 0dB Attenuation (Max Gain) Gain Control Register b7: Reserved for Modulator Attenuation, set to '0'. 6.4 Frequency Control Register: C-BUS address $08 Bit: 8-bit write-only 7 6 5 4 3 2 1 0 0 0 0 DIV 0 0 F2 F1 Frequency Control Register b7-5 and b3-2: Reserved for future use, set to '0'. Frequency Control Register b4: Local Oscillator Divider Control Writing ‘b4’ = 1 will enable "divide the local oscillator by 4" mode, writing ‘b4’ = 0 will enable the "divide the local oscillator by 2" mode. NOTE: Divide by 4 mode is not recommended for operation below 200MHz LO frequency (50MHz RF output). For output frequencies below 50MHz the divide by 2 mode is recommended. Frequency Control Register b1-b0 Controls the operating frequency band. b1 F2 b0 F1 0 0 Operation below 500MHz 0 1 Operation above 500MHz 1 0 reserved 1 1 reserved Note: Frequencies are the operating frequency, not the local oscillator input frequency.  2021 CML Microsystems Plc 15 D/993/12 Quadrature Modulator CMX993/CMX993W 7 Application Notes 7.1 Typical Performance Examples of typical performance which may be achieved when using the CMX993/CMX993W are shown below. Ma rk er 1 [T1 ] - 3. 46 dB m 1.0 000 09 09 GH z R ef Lv l 7 d Bm 7 R BW V BW S WT 1 k Hz 1 k Hz 20 0 m s 2 dB Of fs et 1 [T 1] 0 1 1 [T 1] -10 2 [T 1] 3 [T 1] -20 4 [T 1] -30 2VIEW 1 R F Att 30 dB Ma r k er 1 [ T 1 ] - 3. 0 0 d B m 50 0 .0 0 7 3 14 6 3 M H z R ef L vl 10 d Bm U ni t dB m -3 .4 6 1 .00 00 090 9 -33 .4 4 - 27 .96 09 218 4 -33 .2 8 14 .27 85 571 1 -48 .4 4 28 .18 13 627 2 -47 .0 8 - 35 .94 68 937 9 2 d Bm A G Hz dB k Hz dB k Hz dB k Hz dB 1SA 2SA k Hz RB W VB W SW T 1 kHz 1 kHz 250 ms RF At t Mi x er Un i t 20 dB -10 dBm dBm 10 * 1 [T 1 ] 0 1 1 [T 1 ] -3 . 0 0 d B m B 5 0 0 . 0 0 7 3 1 4 6 3 M H z LN - 33 . 1 6 d B - 7 .0 1 4 02 8 0 6 - 46 . 0 3 1 6 .0 3 2 06 4 1 3 3 [T 1 ] - 46 . 0 9 - 3 2 .2 6 4 52 9 0 6 4 [T 1 ] - 68 . 2 3 3 2 .2 6 4 52 9 0 6 2 [T 1 ] - 10 - 20 1 VI E W - 30 kHz dB kHz dB kHz 1SA dB kHz 1 EXT -40 - 40 4 -50 3 3 2 - 50 -60 - 60 -70 4 - 70 -80 - 80 -90 -93 C ent er 1 GHz 8 kH z/ - 90 S pa n 8 0 k Hz C en t e r 5 0 0 M H z Two-tone signal at 1GHz, +3dBm PEP output, modulator driven from ‘filter amp’, LO = 2GHz, -15dBm. R ef L vl 10 d Bm De l t a 3 [ T 1 ] - 5 1. 3 5 d B 3 6 .0 7 2 1 44 2 9 k H z RB W VB W SW T 1 kHz 1 kHz 250 ms RF At t Mi x er Un i t D el t a 3 [ T 1 ] 20 dB -10 dBm dBm Re f L v l 0 dBm 0 1 [T 1 ] 0.02 dBm B 4 9 9 . 9 9 1 2 8 2 5 7 M H z LN 3 [T 1 ] - 51 . 3 5 d B 1 3 6 .0 7 2 14 4 2 9 - 36 . 2 5 8 .8 1 7 63 5 2 7 - 43 . 7 4 1 8 .0 3 6 07 2 1 4 1 [T 1 ] - 10 2 [T 1 ] - 20 Span 100 kHz Two-tone signal at 500MHz, +3dBm PEP output, modulator driven from ‘Input amp’, LO = 2GHz, -15dBm. 10 0 10 kHz/ 2 dB Offset - 54 . 1 7 dB - 4 9 5. 9 9 1 98 3 9 7 kH z 1 RBW 5 0 k Hz VBW 5 0 k Hz SWT 5 ms RF Att U ni t 1 [T1] 20 dB dBm - 2 . 66 d Bm 9 9 9. 4 9 6 4 92 9 9 M H z kHz dB kHz dB kHz -10 3 [T1] -20 1 [T1] -30 2 [T1] 2 * A -5 4 . 17 d B - 4 9 5. 9 9 1 9 83 9 7 k H z -3 4 . 33 d B 5 0 1. 0 0 2 0 04 0 1 k H z 1SA -3 0 . 99 d B 1. 0 0 7 0 14 0 3 M H z 1SA 2SA 1 2VIEW - 30 -40 1 EXT - 40 2 -50 3 3 - 50 -60 - 60 -70 - 70 -80 - 80 -90 - 90 C en t e r 5 0 0 M H z 10 kHz/ -100 Span 100 kHz C e nt e r 1 G H z 0dBm single-tone at 500MHz, modulator driven from ‘Input amp’, LO = 2GHz, -15dBm.  2021 CML Microsystems Plc 25 0 k H z/ Span 2.5 MHz Wideband performance with single-tone (500kHz) at 1GHz, modulator driven from ‘input amp’, LO = 2GHz, -15dBm. 16 D/993/12 Quadrature Modulator CMX993/CMX993W Marker 1 [T1] -26.49 dBm 800.07665331 MHz Ref Lvl -10 dBm RBW VBW SWT 30 kHz 300 kHz 21 ms RF Att Mixer Unit 10 dB -10 dBm dBm Ma r k er 1 [ T 1 ] - 2 2. 9 2 d B m 45 9 .9 9 9 2 38 4 8 M H z R ef L vl 0 dBm RB W VB W SW T 1 00 H z 1 kHz 20 s RF At t 30 dB Un i t dBm 0 -10 1 [T1] -26.49 800.07665331 CH PWR -15.06 ACP Up -71.83 ACP Low -72.41 ALT1 Up -84.54 ALT1 Low -84.33 ALT2 Up -66.92 ALT2 Low -66.73 -20 1 -30 -40 1VIEW 1 [T 1 ] dB m A MHz LN dBm dB dB dB dB dB dB 1RM - 10 C H PW R - 20 - 22 . 9 2 d B m A 4 5 9 .9 9 9 23 8 4 8 M H z -8 . 1 6 d B m ACP Up ACP Low 1 [T 1 ] 1 - 70 . 8 0 - 71 . 5 7 0.00 0 .0 0 0 00 0 0 0 dB dB dB Hz - 30 1RM - 40 -50 EXT EXT - 50 -60 -70 -80 cl3 cl2 cl2 -90 C0 C0 cl3 - 60 - 70 cl1 cl1 cu1 cu1 -100 - 80 c l1 cl1 - 90 cu3 cu3 cu1 cu 1 - 1 00 -110 Center 800 MHz 750 kHz/ C en t e r 4 6 0 M H z Span 7.5 MHz IS-95 reverse channel operation at 800MHz, measured at 885kHz, 1.98kHz and 2.65MHz Ref Lvl -48.6 dBm -4 8. 6 C0 C0 cu2 cu2 Marker 1 [T1 NOI] -155.04 dBm/Hz 520.00000000 MHz RBW VBW SWT 10 kHz 10 kHz 15 ms RF Att 1 [T1] Unit Marker 1 [T1 NOI] -156.50 dBm/Hz 999.95015030 MHz 0 dB Ref Lvl -43 dBm dBm -155.04 dBm/Hz 520.00000000 MHz S p an 4 0 k H z C4FM modulation for APCO Project 25 (TIA/EIA 102.BAAA); Measurement is ‘non-spurious adjacent channel power ratio’ (TIA/EIA 102.CAAB-B), requirement = 67dB, typical performance = 70dB -4 3 -11.6 dB Offset 4 kH z / A RBW VBW SWT -6 dB Offset 10 kHz 10 kHz 15 ms 1 [T1] -5 0 RF Att Unit 0 dB dBm -156.50 dBm/Hz 999.95015030 MHz A -6 0 -6 0 -7 0 -7 0 -8 0 1V IE W 1A VG 1 SA 1 SA -8 0 -9 0 -9 0 - 10 0 - 10 0 - 11 0 1 - 11 0 - 12 0 1 - 12 0 - 13 0 - 13 0 - 14 0 - 14 0 - 14 3 - 14 8 Center 520 MHz 25 kHz/ Center 1 GHz Span 250 kHz 500MHz noise floor, carrier at 500MHz  2021 CML Microsystems Plc 25 kHz/ Span 250 kHz 1GHz noise floor, carrier at 980MHz 17 D/993/12 Quadrature Modulator CMX993/CMX993W Del t a 4 [T 1] R ef Lv l RBW -4 8.7 8 d B 5 dBm -36 .07 21 442 9 k Hz VBW SWT 1 kH z RF At t 1 kH z Mi xer 20 0 ms Un it 20 dB De lt a 2 [ T1 ] - 20 dBm Re f Lv l dBm 5 0 1 4 [ T1 ] -10 - 3.1 0 d Bm B 3 0 . 0 0 9 2 1 8 4 4 M H z LN -4 8.7 8 d B SWT 1 kHz RF At t 1 kHz Mi x er 2 00 m s 1 Uni t 1 [T1 ] 0 29 . 97 9 95 9 92 kH z - 10 -3 9.7 2 d B 2 [ T1 ] 2 [T1 ] - 2 6. 28 d Bm 50 . 00 0 24 0 48 MH z - 20 -4 0.0 9 d B 3 [ T1 ] -6 3.9 2 d B 1 [T1 ] 2 14. 108 21 643 kH z -30 dBm B 4 9 . 9 9 2 7 0 5 4 1 M H z LN - 5 0. 78 d B - 28. 056 11 222 kH z -20 20 dB -2 0 d B m 0. 00 d Bm 2 [T1 ] - 36. 072 14 429 kH z 1 [ T1 ] VBW 2 9. 9 79 9 5 99 2 k H z 5 1 [ T1 ] RBW - 5 0 .7 8 d B 5 dBm - 4 6. 42 d B 15 . 07 0 14 0 28 kH z 1SA 1SA - 30 28. 056 11 222 kH z -40 1 2 - 40 EXT EX T 1 4 -50 2 - 50 -60 - 60 3 -70 - 70 -80 - 80 -90 - 90 -95 Ce nte r 3 0 MH z 8 k Hz / - 95 Sp an 80 kH z C en t e r 50 M Hz Two-tone signal at 30MHz, +3dBm PEP output, modulator driven from ‘filter amp’, LO = 60MHz, -10dBm. 7.2 8 k Hz / S p an 80 kH z 0dBm single-tone at 50MHz, modulator driven from ‘Input amp’, LO = 100MHz, -10dBm. Intermodulation and Modulator Spurious When selecting an I/Q modulator for a particular application users should take care as intermodulation performance figures given in datasheets can sometimes be difficult to interpret. Some devices similar to the CMX993 quote ‘output IP3’ performance that is only achieved at reduced input / output levels. It has been observed that at their rated output power the performance of these devices is degraded (see Figure 6). By contrast the CMX993 output IP3 is constant when measured with different input / output levels for a given frequency. Typical ‘Equivalent Output IP3’ is in the range 23dBm to 25dBm at 400MHz; lower values can be expected at higher frequencies and below 100MHz. 0dBm PEP (rated output power) 26 25 24 23 IP3 / dBm 22 CMX993 21 Competitor I/Q Modulator 20 19 18 17 16 -15 -13 -11 -9 -7 -5 -3 -1 Output level per tone / dBm Figure 6 – Variation in Effective Equivalent IP3 with signal level Another issue that has been observed with alternative I/Q modulator devices is that the third-order products are not always the largest distortion products. This will be observed in Figure 7 where a competitor’s device exhibits larger distortion products resulting from the third harmonics of the modulation rd than the classic 3 order intermodulation products. Figure 8 shows the equivalent CMX993 performance at the same output power and frequency.  2021 CML Microsystems Plc 18 D/993/12 Quadrature Modulator CMX993/CMX993W Delta 2 [T4] Ref Lvl -49.82 dB 0 dBm 20.24048096 kHz RBW 1 kHz RF Att VBW 1 kHz Mixer SWT 250 ms 40 dB -40 dBm Unit dBm 0 16 kHz 1 [T4] 1 -6.33 dBm 400.00711423 MHz -10 2 [T4] A LD -49.82 dB 20.24048096 kHz 1 [T4] -20 -51.11 dB 16.03206413 kHz -30 -40 3 x 9 kHz 16 kHz 4AVG 4SA -50 16 kHz 1 2 -60 3 x 7 kHz -70 -80 -90 -100 Center 400 MHz Date: 10 kHz/ 17.FEB.2010 Span 100 kHz 12:55:17 Classic IMD Product Figure 7 – IMD Performance of alternative I/Q Modulator at 0dBm PEP (7kHz and 9kHz tones) Delta 2 [T2] Ref Lvl 0 dBm -65.07 dB 20.04008016 kHz RBW 1 kHz RF Att VBW 1 kHz Mixer SWT 0 250 ms Unit 40 dB -40 dBm dBm -10 * -6.43 dBm A 4 0 0 . 0 0 7 1 1 4 2 3 M H z LD 2 [T2] -65.07 dB -20 1 [T2] 1 1 [T2] 20.04008016 kHz -58.16 dB 16.03206413 kHz -30 2VIEW 2SA -40 -50 -60 1 2 -70 -80 -90 -100 Center 400 MHz 10 kHz/ Span 100 kHz Figure 8 – IMD Performance of CMX993 at 0dBm PEP (7kHz and 9kHz tones)  2021 CML Microsystems Plc 19 D/993/12 Quadrature Modulator 8 Performance Specification 8.1 Electrical Performance CMX993/CMX993W For a definition of voltage and reference signals see Table 2. 8.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Supply (AVDD - AVSS) or (DVDD - DVSS) Voltage on any pin to AVSS or DVSS Voltage between AVSS and DVSS Current into or out of DVSS, AVDD or DVDD pins Current into or out of AVSS (VEE, exposed metal pad) Current into or out of any other pin Q3 Package Total Allowable Power Dissipation at Tamb = 25°C ... Derating (see Note below) Storage Temperature Operating Temperature Min. -0.3 -0.3 -50 -75 -200 -30 Max. +4.0 VDD + 0.3 +50 +75 +200 +30 Units V V mV mA mA mA Min. -55 -40 Max. 1750 17.5 +125 +85 Units mW mW/°C °C °C Note: Junction-to-ambient thermal resistance is dependent on board layout and mounting arrangements. The derating factor stated will be better than this with good connection between the device and a ground plane or heat sink. 8.1.2 Operating Limits Notes Supply (AVDD – AVSS) and (DVDD – DVSS) IO Supply (VDDIO – DVSS) Operating Temperature (see Note above)  2021 CML Microsystems Plc 20 Min. 3.0 1.6 -40 Max. 3.6 3.6 +85 Units V V °C D/993/12 Quadrature Modulator 8.1.3 CMX993/CMX993W Operating Characteristics For the following conditions unless otherwise specified: VDD = AVDD = DVDD = 3.3V; VDDIO = 1.6V to VDD; VSS = AVSS = DVSS. LO Level = -15dBm and TAMB = -40ºC to +85ºC. DC Parameters Total Current Consumption Powersave mode Band gap VREF only Operating Current from VDDIO Notes Min. Typ. Max. Units 0 - 10 50 95 - 70 600 µA µA mA µA 70% -1.0 80% 1.45 1.6 30% +1.0 +0.4 VDDIO VDDIO µA VDDIO V 0.5 10 1.75 ms µs V 1 2 Logic '1' Input Level Logic '0' Input Level Logic Input Leakage Current (Vin = 0 to DVDD) Output Logic ‘1’ Level (lOH = 0.6 mA) Output Logic ‘0’ Level (lOL = -1.0 mA) Power up time Voltage Reference All blocks except Voltage Reference Reference Voltage (VREF, BVREF) 3 3 Notes: 0. 1. 2. 3. Powersave mode includes the case after general reset with all analogue and digital supplies applied and also the case with VDD applied but with all analogue supplies disconnected (i.e. in this latter scenario power from VDD will not exceed the specified value, whatever the state of the registers). At TAMB = 25ºC, not including any current drawn from device pins by external circuitry. For CMX993 only. Add 1mA for CMX993W device. TAMB = 25ºC only. Assumes 30pF on each C-BUS interface line and an operating serial clock frequency of 5MHz. Time from the rising edge of the last serial clock input following CSN being asserted for a write to the appropriate control register.  2021 CML Microsystems Plc 21 D/993/12 Quadrature Modulator CMX993/CMX993W AC Parameters Output Frequency Range Local oscillator input LO Frequency Range LO Input Impedance (Differential) LO Input Level 200MHz < F < 2000 MHz 80MHz < F < 200MHz 60MHz < F < 80MHz Input amplifiers (and filter amplifiers – CMX993) Gain Bandwidth Product Input Offset Voltage Input Common Mode Range Input Bias Current Input Resistance Slew Rate IMD Differential Input Voltage Input Referred Noise at 1kHz Output Load Notes Min. 30 Typ. - Max. 1000 Units MHz 4, 28 60 - 50 2000 - MHz 33 28 27,28 -20 -15 -10 - -10 -10 -5 dBm dBm dBm 15 31 17 1.0 - 10 3 1.6 0.4 160 6 -85 6 2.5 - MHz mV V µA - 15 V nV/Hz AVSS+0.1 1k ║100pF - 1.2 AVDD-0.1 V 1.1 - 65 3 1.6 1.6 38 32 -90 4 2.5 4.5 - MHz mV V µA - 5 1.2 - V nV/Hz AVDD-0.8 V 15 15, 16, 19 18 13 DC Output Range  k V/µs dB Filter amplifiers – CMX993W Gain Bandwidth Product Input Offset Voltage Input Common Mode Range Input Bias Current Input Resistance Slew Rate IMD 15 31 17 15 15, 16, 19 18 Differential Input Voltage Input Referred Noise at 1kHz Output Load 13 DC Output Range  2021 CML Microsystems Plc AVSS+0.2 22 1k ║100pF - k V/µs dB D/993/12 Quadrature Modulator AC Parameters CMX993/CMX993W Notes Min. Typ. Max. Units 14 1.3 1.0 - 1.6 1.55 0.5 50 -2 30 2.5 +3 1.7 4.0 10 - V V Vp-p MHz dB dB dB µs dBm - -155 -148 -145 dBm/Hz dBc/Hz - - dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz TBD TBD -35 30 - 32 40 40 32 -40 25 -153 -155 -156 -158 -159 - st - -72 - dB nd - -84 - dB - -67 - dB - +8 100 - -80 dBm  dBc Quadrature Modulator DC Bias Input I/Q Input Common Mode Voltage I/Q Mixer Input Voltage Modulator Minimum Input Bandwidth Voltage Gain Nominal Transmit Gain Control Range Transmit Gain Control Step Size Gain Switching Time Transmit Output Power (PEP) Noise Floor Wideband Noise During Modulation Output Noise with Attenuation Steps Attenuation = 5dB Attenuation = 10dB Attenuation = 15dB Attenuation = 20dB Attenuation = 25dB Image Suppression At 30MHz At 100MHz At 500MHz At 1GHz Carrier Suppression Intermodulation Equivalent Output IP3 IS-95 Performance 10 24, 32 34 25 5,6, 20, 32 25, 29 7, 8, 30 9, 12, 20 23 11 dB dB dB dB dBm dB dBm 26 1 Adjacent Channel (f=885kHz) 2 Adjacent Channel (f=1.98MHz) rd 3 Adjacent Channel (f=2.65MHz) 1dB Compression Point Load Impedance (Differential) Discrete Unwanted Emissions (other than harmonics of the output) in the Frequency Range 9kHz –12.75 GHz. 29 21 22 Notes: 4. 5. 6. 7. 8. 9. Local oscillator input frequency twice or four times the required operating frequency. Output power reduced dB for dB with forward path attenuation. Peak power: PEP measured with 2-tone signal (two equal amplitude tones). Measured between noise floor and mean power in a two-tone modulated wanted signal. Measured at 400MHz, 5MHz offset over specified Forward Path Output Power range and with forward path attenuation between 0dB and –5dB. NB: typical noise performance achieved at typical output power and above. Measured at 400MHz, 5MHz offset with specified Forward Path Output Power for relevant attenuation level.  2021 CML Microsystems Plc 23 D/993/12 Quadrature Modulator CMX993/CMX993W 10. Typical output power is achieved with the typical input drive level stated on I and Q channels, operation at 500MHz (sine and cosine waveforms on I and Q respectively). 11. Two tone test, limit met at all gain steps for ‘Forward Path Output Power Level (PEP)’ of: maximum output power below 600MHz, typical output power 600-900MHz, and 0dBm above 900MHz. 12. Measured with modulated output signal at relevant output power for forward path attenuations as specified. 13. Operating into a virtual earth (not ground). 14. Normally connected to BVREF pin via RC filter, the tolerance of BVREF is specified in the DC Parameter table and these same tolerance limits apply here. 15. With a load of 1k in parallel with 100pF. (Note 17 also applies). 16. Includes all IMD products up to and including the 7th order products e.g. 2nd, 3rd, 5th etc. Specification limit applies to each IMD product, not composite power of all products. 17. For small signal operation. It is recommended that for this application the input levels be restricted to +/-0.4V about a defined reference voltage of 1.6V (nominal); this will allow for some tolerance in components and for the precision of the reference voltage setting. 18. The inputs are protected with diodes. These diodes prevent the inadvertent application of voltages that may cause damage to the input transistors. 19. Two-tone test with value measured relative to power in either tone, unity gain, 0.8V p-p signal with two tones at 70kHz and 90kHz (400mV p-p each tone). 20. The output power appropriate for a particular application depends on the type of modulation and the spectral purity requirements in each particular case. For some applications it may be necessary to operate the output level below the specified typical level in order to achieve the desired results. Note also that the intermodulation performance, which influences the achievable output level, varies with frequency, see Note 11. 21. This is the impedance that should be presented to the output of the up-converter, e.g. using a balun. The precise load impedance may be optimised for a given operating frequency, or band of frequencies, to achieve improved output level and signal-to-noise ratio. 22. With a spurious-free LO input and specified output level. 23. Measured with MODIN, MODIP, MODQN, MODQP connected to BVREF with 10 resistors decoupled by 33nF capacitors. 24. Voltage gain measured from modulator input (MODIN or MODQN) to output of a 4:1 balun, using 7kHz sine/cosine waves on MODIN/MODQN. 25. Measured at 20MHz offset from the operating frequency, all modulator I/Q inputs at BVREF. 26. Performance measured based on IS-95B section 6.1.4.1.1; measurement bandwidths 1.23MHz rd st nd for wanted and 3 adjacent channel and 30kHz for 1 and 2 adjacent channels. 27. LO divide by 2 mode operation only. 28. LO divide by 4 mode is not recommended for output frequencies below 50MHz. 29. Specification applies over the range 100MHz to 1GHz. 30. A typical figure at 40MHz or 50 MHz is –146dBc/Hz at a 5MHz offset. 31. The maximum value is derived from analysis of statistical evaluation results and is not guaranteed by 100% testing. 32. Gain and Output Power will reduce below 100MHz. Values are typically 4dB lower at 30MHz. 33. For operation with a modulator output above 600MHz optimum performance will typically be achieved with the LO input level in the range -15dBm to -20dBm. 34. Typical range 28.2 dB, standard deviation 0.3.  2021 CML Microsystems Plc 24 D/993/12 Quadrature Modulator CMX993/CMX993W C-BUS Timings (See Figure 9) tCSE CSN-Enable to Clock-High Time tCSH Last Clock-High to CSN-High Time tCSOFF CSN-High Time between transactions tNXT Inter-Byte Time tCK Clock-Cycle Time tCH Serial Clock (SCLK) - High Time tCL Serial Clock (SCLK) - Low Time tCDS Command Data (CDATA) - Set-Up Time tCDH Command Data (CDATA) – Hold Time Notes Min. 100 100 1.0 200 200 100 100 75.0 25.0 Typ. - Max. - Units ns ns µs ns ns ns ns ns ns Maximum 30pF load on each C-BUS interface line. CSN tCSE tCK tCSH tNXT tCSOFF SCLK CDATA 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 = Level not important or undefined tCH 70%VDD SCLK 30%VDD tCL tCDH tCDS CDATA Note: Only 1 byte of data is used in CMX993/CMX993W C-BUS transactions. Figure 9 C-BUS Timing  2021 CML Microsystems Plc 25 D/993/12 Quadrature Modulator 8.2 CMX993/CMX993W Packaging DIM. * * MIN. TYP. MAX. 7.00 BSC A B C F G H J K L L1 P T 0.80 4.60 4.60 0.00 0.18 0.20 0.30 0 7.00 BSC 0.90 0.25 1.00 5.65 5.65 0.05 0.30 0.50 0.15 0.40 0.50 0.20 NOTE : * Exposed Metal Pad A & B are reference data and do not include mold deflash or protrusions. All dimensions in mm Angles are in degrees Index Area 1 Dot Index Area 2 Dot Chamfer Index Area 1 is located directly above Index Area 2 Depending on the method of lead termination at the edge of the package, pull back (L1) may be present. L minus L1 to be equal to, or greater than 0.3mm The underside of the package has an exposed metal pad which should ideally be soldered to the pcb to enhance the thermal conductivity and mechanical strength of the package fixing. Where advised, an electrical connection to this metal pad may also be required Note: In this device, the underside of the Q3 package must be electrically connected to the analogue ground. The circuit board should be designed so that no unwanted short circuits can occur. Figure 10 Q3 Mechanical Outline: Order as part no. CMX993Q3 or CMX993WQ3 Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.