CN7221

LANfinity™ CN7221 Home Networking Physical Layer Device with Integrated Analog Front End Circuitry This document describes the CN7221 Home Networking Physical Layer (PHY) with Integrated Analog Front End (AFE). It includes device pinouts, signal descriptions, and timing diagrams. The CN7221 allows home networks to operate over common telephone wires at 1 Mbps. The CN7221 simplifies system designs and improves their reliability by eliminating the need for a separate AFE comprised of discrete components. The CN7221 supports the emerging home phoneline networking standard proposed by the Home Phoneline Networking Alliance (HomePNA). Conexant has announced plans to release a family of multifunction home phoneline networking chipsets. The first products to be announced in this family include the RS7111A 1/10/100 PCI/CardBus Multifunction Controller, the RS7220 Home Networking PHY, the RS7112 Multifunction Controller with Integrated PHY, and the CN7221 Home Networking PHY with Integrated AFE (see Ordering Information, page 2). The HomePNA phoneline network utilizes existing telephone wiring to connect computers and devices without interrupting phone service. Industry-standard home networking products will enable a variety of home computing opportunities including • • • • shared Internet access using a single phone line printer/peripheral sharing file and application sharing networked gaming Features • • • • • • Supports the HomePNA 1.0 specification for a home phoneline network 1 Mbps data rate Integrated Analog Front End Configurable transmit power level; high- and low-power Configurable transmit data rate; low- and high-speed 32-pin TQFP package HomePNA 1.0 Specification Features • • • Meets HomePNA certification test requirements Uses existing phonelines, no new wires required Compatible with existing services – • • . Internet access, voice services, and home network coexist on the same wire Robust protocol assures performance over poor wiring infrastructure FCC Part 15- and Part 68-compliant The CN7221 can be combined with the RS7112 Multifunction PCI/CardBus Controller and Conexant’s host-controlled (HCF) V.90/K56flex modem to provide a variety of home networking plus 56 Kbps modem solutions. Data Sheet Conexant Proprietary Information Dissemination or use of this information is not permitted without the written permission of Conexant Systems, Inc. Order No. LAN-056 Rev. A, March 12, 1999 Ordering Information Product CN7221 HomePNA 1.0 Physical Layer with Integrated Analog Front End Related Products RS7112 Multifunction PCI/CardBus Ethernet and HomeLAN Controller with Integrated HomePNA 1.0 Physical Layer and 56 Kbps HCF/HSF Modem Interface RS7112-LAN Multifunction PCI/CardBus Ethernet and HomeLAN Controller with Integrated HomePNA 1.0 Physical Layer Only RS7111A Multifunction PCI/CardBus Ethernet and HomeLAN Controller with V.90 HCF Modem Interface RS7111A-LAN Multifunction PCI/CardBus Ethernet and HomeLAN Controller Only RS7220 HomePNA 1.0 Physical Layer device 64-pin TQFP R8293-11 176-pin TQFP 11617-12 176-pin TQFP 11617-14 176-pin TQFP 11623-12 176-pin TQFP 11623-14 Package 32-pin TQFP Device Number 11625-11 Information provided by Conexant Systems, Inc. is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products. Conexant reserves the right to change circuitry at any time without notice. This document is subject to change without notice. Conexant, “What’s Next in Communications Technologies,” and LANfinity are registered trademarks of Conexant Systems, Inc. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders. ©1999, Conexant Systems, Inc. All Rights Reserved Home Networking PHY with Integrated AFE LANfinity™ CN7221 Typical Application V.90 DSP (optional) V.90 CODEC DAA RJ-11 P C I RS7112 Multifunction Controller (Ethernet MAC/V.90 Modem Combination) 7-Wire Serial I/F (7WS) CN7221 Home Networkin g P HY with Inte g rated AFE Media Independent I/F (MII) Ethernet 10 Mbps or 100 Mbps PHY/ Transceiver RJ-45 LAN-056_CN7221_f1 Figure 1. Typical Application Description The typical application shown in Figure 1 displays a multifunction PCI Network Interface Card (NIC). The NIC incorporates the RS7112 Home Networking Controller, the CN7221 Home Networking PHY with Integrated AFE, and a V.90 56 Kbps host-controlled modem. The RS7112’s 7wire serial interface (7WS) is used to support the CN7221. Home Networking The home phoneline network is an Ethernet-compatible LAN running over the random-tree wiring found in nearly all homes. It does not require any hubs, routers, splitters, filters or terminations. Initial products are PC network interface cards, which will interface home computers directly to the network via an in-home telephone jack. Home phoneline networking will also work with current Internet access technologies, such as cable modems, V.90 and ADSL. LAN-056, Rev. A Conexant PROPRIETARY INFORMATION 3 LANfinity™ CN7221 Home Networking PHY with Integrated AFE Functional Description CN7221 Home Networking PHY with Integrated AFE 7-Wire Serial Interface (7WS) Ph y sical La y er Data Processin g RS7112 Bus Interface Serial Peripheral Interface ( SPI ) Interrupt Processin g Analo g F ront End Circuitr y RJ-11 Re g isters EPROM Interface EEPROM LAN-056_CN7221_f2 Figure 2. CN7221 Device Block Diagram Overview The CN7221 PHY + AFE resides between the RS7112 and the physical medium and is responsible for receiving and transmitting data on that physical medium, detecting collisions on the physical medium, and translating data to and from the RS7112. For the purpose of this discussion, the interface to the RS7112 is referred to as the back end. The discussion of the back end briefly describes the signals involved in that interface as well as some of the operation of those signals. More detailed information may be gathered from the section of this document on the 7wire serial interface itself (page 5). Back End (PHY to MAC Interface) The back end interface is wholly defined by the seven following signals: HLAN_TX_CLK, HLAN_TX_EN, HLAN_TXD, HLAN_RX_CLK, HLAN_CRS, HLAN_RXD, and HLAN_COL. The Tx signals are sampled on the falling edge of HLAN_TX_CLK and the Rx signals are changed on the falling edge of the HLAN_RX_CLK. HLAN_COL may change on either edge of either the HLAN_TX_CLK or the HLAN_RX_CLK. All signals are active high. Due to the nature of the encoding/decoding algorithm as well as the collision detection algorithm used in the CN7221, the resulting variable bit rate forces the PHY to “hold off” the MAC data stream by gating the HLAN_RX_CLK and HLAN_TX_CLK signals. Gating is done in a manner guaranteed to be glitch-free. 4 Conexant PROPRIETARY INFORMATION LAN-056, Rev. A Home Networking PHY with Integrated AFE LANfinity™ CN7221 System Signals The system level signals provide hardware level initialization, configuration and status indications from the device. They are shown in Table 1. The HLAN_OSC pin is the 60 MHz clock input pin. The HLAN_IRQ signal is an active-low interrupt signal intended for use as a level-sensitive interrupt to an external processor. All interrupt sources are maskable and capable of being stimulated through software via the ISR and IMR programmable registers. Table 1. System Signals Signal HLAN_RESET# HLAN_IRQ# HLAN_OSC Description Asynchronous system reset Active low processor interrupt 60 MHz oscillator input Seven Wire Serial (7WS) Interface Signals The 7-Wire serial interface provides the digital interface to the Ethernet MAC. The seven signals that comprise the 7WS are HLAN_TX_CLK, HLAN_TX_EN, HLAN_TXD, HLAN_RX_CLK, HLAN_CRS, HLAN_RXD, and HLAN_COL. Of these, only HLAN_TX_EN and HLAN_TXD are inputs to the PHY; the other five are outputs from the PHY. These signals behave differently depending on which operation is currently happening in the PHY. The operations of the PHY are as follows: • • • Idle (no activity in either direction) RxPKT (receiving data) TxPKT (transmitting data). The subsequent subsections analyze each 7WS-related state of the PHY in detail. Table 2. 7WS Interface Signals Signal HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL Description Transmit clock Transmit enable Transmit data Receive clock Receive carrier sense Receive data Collision (active high) Idle State HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL HLAN_RX_CLK and HLAN_TX_CLK are synchronized to the same phase. All other signals are inactive. The two clock signals toggle low for 116.7ns and high for 466.7ns, for an overall period of 583.3ns (about 1.7MHz). LAN-056, Rev. A Conexant PROPRIETARY INFORMATION 5 LANfinity™ CN7221 Home Networking PHY with Integrated AFE RxPKT  Carrier Sense Asserted HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL HLAN_RX_CLK becomes disabled (and left in the high state) as soon as HLAN_CRS is asserted. HLAN_CRS may be asserted at a multiple of 116.7ns after the rising edge of HLAN_RX_CLK (that is, 0ns, 116.7ns, 233.3ns, 350.0ns, or 466.7ns). The clock is re-enabled about 135 uS into the packet. RxPKT  HLAN_RX_CLK Active and HLAN_CRS Cleared HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL HLAN_RX_CLK and HLAN_TX_CLK are unrelated to each other during this time. When a symbol has been received and decoded, HLAN_RX_CLK toggles at a rate of 233.3ns (full period, 50% duty cycle) in order to shift out the three to six bits encoded in the symbol. The middle portion of this diagram shows the end of the preamble, followed by an SFD and the beginning of the datagram. HLAN_CRS will fall approximately 16us after the last received symbol. Once HLAN_CRS falls, HLAN_RX_CLK and HLAN_TX_CLK are toggled continuously at 233.3ns for 97 cycles, after which the PHY returns to the Idle state. TxPKT  HLAN_TX_EN Asserted HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL Once HLAN_TX_EN is asserted, the PHY stops HLAN_RX_CLK, asserts HLAN_CRS, and toggles HLAN_TX_CLK at 233.3ns. 6 Conexant PROPRIETARY INFORMATION LAN-056, Rev. A Home Networking PHY with Integrated AFE LANfinity™ CN7221 TxPKT  HLAN_RX_CLK Active HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL HLAN_TX_CLK continues to toggle at 233.3ns until the SFD is observed, as shown in the first section of the above diagram. At this point, HLAN_TX_CLK is disabled (high) until the AID header has been transmitted on the wire (or until a HLAN_COL has been detected). This takes about 120us, at which time HLAN_RX_CLK starts toggling, thereby shifting 32 bits of preamble and SFD back to the MAC. Sometime later, the HLAN_TX_CLK restarts as symbols get sent onto the wire in an analogous manner as HLAN_RX_CLK during packet reception. TxPKT  HLAN_TX_EN Cleared HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL Once HLAN_TX_EN is cleared, the last symbol gets encoded and transmitted, the looped-back data is presented back to the MAC, and about 22us later, HLAN_CRS falls. Once HLAN_CRS falls, HLAN_TX_CLK and HLAN_RX_CLK toggle with a period of 233.3ns for 97 clocks, after which the system returns to the Idle state. LAN-056, Rev. A Conexant PROPRIETARY INFORMATION 7 LANfinity™ CN7221 Home Networking PHY with Integrated AFE TxPKT  HLAN_COL Asserted HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL HLAN_COL will be asserted some time after the preamble and SFD have been clocked in. HLAN_TX_CLK and HLAN_RX_CLK are then clocked with a period of 233.3ns until HLAN_CRS drops. HLAN_TX_EN drops about 32 clocks after HLAN_COL was asserted. HLAN_CRS and HLAN_COL are dropped together after more than 500 clocks (about 120us). HLAN_TX_CLK and HLAN_RX_CLK keep toggling at 233.3ns period for roughly another 100 clock cycles, when the system returns to the idle state. RxPKT  HLAN_COL Asserted HLAN_TX_CLK HLAN_TX_EN HLAN_TXD HLAN_RX_CLK HLAN_CRS HLAN_RXD HLAN_COL HLAN_COL may be asserted up to 120us after HLAN_CRS has been asserted. Once HLAN_COL has been asserted, HLAN_TX_CLK and HLAN_RX_CLK run at a period of 233.3ns per cycle until 97 cycles after HLAN_COL and HLAN_CRS are cleared. It can take up to about 60us for HLAN_CRS to clear. 8 Conexant PROPRIETARY INFORMATION LAN-056, Rev. A Home Networking PHY with Integrated AFE LANfinity™ CN7221 Serial Peripheral Interface The SPI provides a software interface for configuration and status of the CN7221. The SPI signals are composed of: HLAN_SPI_CLK, HLAN_SPI_DOUT, HLAN_SPI_DIN, and HLAN_SPI_CS#. Commands are issued to the device by asserting the HLAN_SPI_CS# signal (active low), shifting in an eight-bit opcode; if the operation is a read or a write, the opcode is followed by an eight-bit register address. If the operation is a write, the address is followed by an eight-bit data byte. If the operation is a read, the HLAN_SPI_DOUT pin will shift out an eight bit data byte representing the contents of the register referenced by the address field. All commands must be initiated with a high-to-low transition on the HLAN_SPI_CS# pin. The device also may be commanded to set or clear its WE flag. This flag is cleared upon reset, and disables all write operations when in that state. Opcodes are as follows: TSETcsh Signal HLAN_SPI_CLK HLAN_SPI_DOUT HLAN_SPI_DIN HLAN_SPI_CS# Table 3. SPI Signals Description Serial interface clock Serial data output Serial data input Serial interface chip select (active low) Table 4. SPI Timing Mnemonic TWIDTHclkl TWIDTHclkh TSETcsl Description Positive half-cycle pulse width Negative half-cycle pulse width CSN low to rising clock edge CSN high to rising clock edge Falling clock edge to SO valid Falling clock edge to SO tri-state SI valid to rising clock edge 50 Min 400 400 50 50 50 100 Max Units ns ns ns ns ns ns ns 0000 0110 0000 0100 0000 0011 0000 0010 SET WE CLEAR WE READ WRITE TDLYsov TDLYsoz TSETsiv Timing for the various signals in SPI mode is defined in Table 4 and in Figure 3. The HLAN_SPI_DIN signal should not be changed until at least 100ns after the rising edge of HLAN_SPI_CLK. In other words, the HLAN_SPI_DIN signal has a hold time constraint of 100ns past the rising edge of HLAN_SPI_CLK. TWIDTHclkl TWIDTHclkh CLK TSETcsl TSETcsh CSN TSETsiv HLAN_SPI_DIN b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Instruction Byte HLAN_SPI_DOU T Address Byte Data Byte (don't-care when reading) TDLYsov b7 b6 b5 b4 b3 b2 b1 b0 TDLYsoz Data Byte (high-Z when writing) Figure 3. SPI Timing LAN-056, Rev. A Conexant PROPRIETARY INFORMATION 9 LANfinity™ CN7221 Home Networking PHY with Integrated AFE LANfinity RS7112 Interface The RS7112 interface consists of the SPI signals (see page 9), and the HLAN_IRQ# signal. All SPI registers in the system are readable and writable. The TxSPEED, TxPOWER, and CMDignore bits of the CONTROL register may be set or cleared in two ways: SPI CONTROL register write or remote management command (TxSPEED and TxPOWER only). These methods may overwrite one another. After reset, any change in the state of those pins will update the CONTROL register bits. Table 5. RS7112 Interface Signals Signal HLAN_IRQ# Description Active low processor interrupt Remote Commands Any node in a home phoneline network may issue remote commands. The effect of a remote command is to set the transmit speed and power of all nodes in the network. A remote command is encoded in the AID header and is identified by having an AID address of 0xFF. The remaining AID header information contains the commanded power and speed. Three identical remote commands must be received before a PHY will respond by changing its’ transmit speed and power. Once three identical remote commands have been received, however, the transmit speed and power are updated and bit 1 of the ISTAT register is set. The PHY will issue three remote commands when any one of bits 8 through 11 of the CONTROL register is set. As soon as these bits are set, the PHY will automatically update it’s own transmit speed and power and start issuing the remote command on subsequent packets until three packets have been successfully transmitted (that is, without collision). Once the three remote commands have been sent, bits 8 through 11 of the CONTROL register will be cleared and bit 0 of the ISTAT register will be set. 10 Conexant PROPRIETARY INFORMATION LAN-056, Rev. A Home Networking PHY with Integrated AFE LANfinity™ CN7221 Pinout Diagram 32 HLAN_SPI_DIN 31 HLAN_TX_CLK 30 HLAN_TXD 29 VDD 28 VSS 27 HLAN_TX_EN 26 HLAN_CRS 25 HLAN_COL 1 2 3 4 5 6 7 8 HLAN_RX_CLK HLAN_OSC HLAN_RXD HLAN_SPI_DOUT HLAN_SPI_CS# HLAN_SPI_CLK HLAN_IRQ# SCAN_MODE SCAN_ENABLE 24 23 22 21 20 19 18 17 HLAN_RESET# VSS AFE_REF_NOISE AFE_REF_PEAK AFE_REF_DATA AFE_RX_MINUS AFE_RX_PLUS VDD AFE_TX_PLUS AFE_TX_MINUS AFE_VDD_RX AFE_VSS_RX 9 10 11 12 13 14 AFE_VSS_TX AFE_RBIAS AFE_VC 15 16 Figure 4. CN7221 32-pin TQFP Pinout Diagram LAN-056, Rev. A Conexant PROPRIETARY INFORMATION 11 LANfinity™ CN7221 Home Networking PHY with Integrated AFE Pin Designations by Number Table 6. CN7221 32-pin TQFP Pin Designations by Number Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Signal HLAN_OSC HLAN_SPI_DOUT HLAN_SPI_CS# HLAN_SPI_CLK HLAN_RESET# VSS AFE_REF_NOISE AFE_REF_PEAK AFE_REF_DATA AFE_VDD_RX AFE_VSS_RX AFE_RBIAS AFE_VC AFE_VSS_TX AFE_RX_MINUS AFE_RX_PLUS Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Signal AFE_TX_MINUS AFE_TX_PLUS VDD SCAN_ENABLE SCAN_MODE HLAN_IRQ# HLAN_RXD HLAN_RX_CLK HLAN_COL HLAN_CRS HLAN_TX_EN VSS VDD HLAN_TXD HLAN_TX_CLK HLAN_SPI_DIN 12 Conexant PROPRIETARY INFORMATION LAN-056, Rev. A Home Networking PHY with Integrated AFE LANfinity™ CN7221 Pin Designations by Group Table 7. Pin Designations by Group Home LAN Pin Name HLAN_OSC HLAN_RESET# HLAN_IRQ# HLAN_TX_EN HLAN_TXD HLAN_TX_CLK HLAN_COL HLAN_CRS HLAN_RXD HLAN_RX_CLK HLAN_SPI_CS# HLAN_SPI_CLK HLAN_SPI_DOUT HLAN_SPI_DIN Type I I O I I O O O O O I/O I/O O I ↑100Koh m ↓ 25Kohm ↓ 25Kohm ↓ 25Kohm Schmitt Resistive Drive CMOS CMOS 6mA CMOS CMOS 6mA 6mA 6mA 6mA 6mA 6mA 6mA 6mA CMOS Description 60 MHz oscillator input Active high asynchronous system reset Active low processor interrupt 7WS transmit enable 7WS transmit data 7WS transmit clock 7WS collision (active high) 7WS receive carrier sense 7WS receive data 7WS receive clock Serial interface chip select Active low Serial interface clock Serial data output Serial data input 4 2 32 Pin Number(s) 1 5 22 27 30 31 25 26 23 24 3 AFE Interface (Reference) Pin Name Type Schmitt Resistive Drive Description Pin Number(s) AFE_REF_NOISE AFE_REF_PEAK AFE_REF_DATA AFE_RBIAS AFE_RX_MINUS AFE_RX_PLUS AFE_TX_MINUS Noise reference filtered with an external 0.0075 uF Cap for data CT comparator. Peak reference filtered with an external 0.0034 uF Cap for peak CT comparator. Data reference filtered with an external 0.0134 uF Cap for data CT comparator. External 1% 2.75kOhm resistor to set reference current. Negative input of the 7.5MHz receive signal Positive input of the 7.5MHz receive signal Negative output of the 7.5MHz TX signal connected to the 50ohm resistor and 1000pF AC coupling Caps. RX power supply (3-3.6V or 3.15-3.45) RX ground TX ground Middle point of the power supply filtered with an external 10uF Cap. Positive output of the 7.5MHz TX signal connected to the 50ohm resistor and 1000pF AC coupling Caps. 7 8 9 12 15 16 17 AFE_VDD_RX AFE_VSS_RX AFE_VSS_TX AFE_VC AFE_TX_PLUS 10 11 14 13 18 LAN-056, Rev. A Conexant PROPRIETARY INFORMATION 13 LANfinity™ CN7221 Home Networking PHY with Integrated AFE Test Signals Pin Name Type Schmitt Resistive Drive Description Pin Number(s) SCAN_MODE SCAN_ENABLE I I & & ↓ ↓   Selects different scan modes Scan enable (1 = enable scan) 21 20 Power Pins Pin Name VDD VSS Type P 5 pins G 7 pins Ground 6, 28 Characteristic Description +3.3V Power Pin Number(s) 19, 29 14 Conexant PROPRIETARY INFORMATION LAN-056, Rev. A Home Networking PHY with Integrated AFE LANfinity™ CN7221 Electrical Characteristics Table 8.Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Voltage Applied to Outputs in High Z state DC Input Clamp Current DC Input Clamp Current Static Discharge Voltage (25 oC) Latch-up Current Symbol VDD VIN T Tstg Vhz Ilk Iok ESD Itrig Min Typ Max Units V V oC oC V mA mA V mA Table 9. DC Electrical Characteristics o o TA = 0 C to +70 C, VDD = +3.3V ± 5%, VSS = 0V. Parameter Input Voltage Low Input Voltage High Output Voltage Low @ IOL = 2, 4, 8, 12 mA Output Voltage High @ IOH = 2, 4, 8, 12 mA Symbol VIL VIH VOL VOH Min Typ Max Units V V V V Table 10. AC Electrical Characteristics TA = 0oC to +70oC, VDD = +3.3V ± 5%, VSS = 0V. Parameter Frequency (PCI_CLK) Frequency (8023_MII_TX_CLK) 100 Mbps Frequency (8023_MII_RX_CLK) 100 Mbps Frequency (8023_MII_TX_CLK) 10 Mbps Frequency (8023_MII_RX_CLK) 10 Mbps Frequency (8023_MII_MDC) Symbol fpck fxtal TBD TBD TBD TBD Min Typ Max Units MHz MHz MHz MHz MHz MHz Note: Setup, Hold and Delays are with respect to the rising edge of the respective clock unless specified. PCI Bus signals conform to the PCI Bus Timing Specification. LAN-056, Rev. A Conexant PROPRIETARY INFORMATION 15 LANfinity™ CN7221 Table 11. Mode Typical Current (mA) Home Networking PHY with Integrated AFE Current and Power Characteristics Typical Power (W) Maximum Power (W) Notes Maximum Current (mA) Active Idle Power down 16 Conexant PROPRIETARY INFORMATION LAN-056, Rev. A Home Networking PHY with Integrated AFE LANfinity™ CN7221 Package Dimensions D D1 D2 PIN 1 REF D D1 D2 D1 e b DETAIL A Dim. A Millimeters Max. Min. 1.6 MAX 0.15 0.05 1.4 REF 9.25 8.75 7.0 REF 5.6 REF 0.75 0.5 1.0 REF 0.80 BSC 0.30 0.40 0.19 0.13 0.10 MAX Inches* Max. Min. 0.0630 MAX 0.0020 0.3445 0.0059 0.3642 0.0551 REF 0.2756 REF 0.2205 REF 0.0197 0.0295 0.0394 REF 0.0315 BSC 0.0118 0.0051 0.0157 0.0075 D1 A1 A2 D D1 D2 L L1 e b c Coplanarity A A2 0.004 MAX Ref: 32-PIN TQFP (GP00-D262) c A1 L1 DETAIL A PD-TQFP-32 (040395) L * Metric values (millimeters) should be used for PCB layout. English values (inches) are converted from metric values and may include round-off errors. Figure 5. 32-pin TQFP Package Dimensions LAN-056, Rev. A Conexant PROPRIETARY INFORMATION 17 Further Information literature@conexant.com 1-800-854-8099 (North America) 33-14-906-3980 (International) Web Site www.conexant.com Hong Kong Phone: (852) 2827 0181 Fax: (852) 2827 6488 India Phone: (91 11) 692 4780 Fax: (91 11) 692 4712 Korea Phone: (82 2) 565 2880 Fax: (82 2) 565 1440 Phone: (82 53) 745 2880 Fax: (82 53) 745 1440 World Headquarters Conexant Systems, Inc. 4311 Jamboree Road P. O. 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