CY74FCT2374ATQCTG4

CY74FCT2374T 8-BIT REGISTER WITH 3-STATE OUTPUTS SCCS040A – SEPTEMBER 1994 – REVISED OCTOBER 2001 D D D D D D D D D D D D Function and Pinout Compatible With FCT and F Logic 25-Ω Output Series Resistors to Reduce Transmission-Line Reflection Noise Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times Fully Compatible With TTL Input and Output Logic Levels ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 3-State Outputs 12-mA Output Sink Current 15-mA Output Source Current Edge-Triggered D-Type Inputs 250-MHz Typical Switching Rate SN74FCT2374T . . . Q OR SO PACKAGE (TOP VIEW) OE O0 D0 D1 O1 O2 D2 D3 O3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC O7 D7 D6 O6 O5 D5 D4 O4 CP description The CY74FCT2374T is a high-speed, low-power, octal D-type flip-flop featuring separate D-type inputs for each flip-flop. On-chip termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2374T can replace the CY74FCT374T to reduce noise in an existing design. The device has 3-state outputs for bus-oriented applications. A buffered clock (CP) and output-enable (OE) inputs are common to all flip-flops. The flip-flops in the CY74FCT2374T store the state of their individual data (D) inputs that meet the setup-time and hold-time requirements on the low-to-high CP transition. When OE is low, the contents of the flip-flops are available at the outputs. When OE is high, the outputs are in the high-impedance state. The state of OE does not affect the state of the flip-flops. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CY74FCT2374T 8-BIT REGISTER WITH 3-STATE OUTPUTS SCCS040A – SEPTEMBER 1994 – REVISED OCTOBER 2001 ORDERING INFORMATION TA PACKAGE† QSOP – Q SOIC – SO SO –40°C to 85°C to 85 QSOP – Q SOIC – SO SO SOIC – SO SO Tape and reel Tube Tape and reel Tape and reel Tube Tape and reel Tube Tape and reel SPEED (ns) 5.2 5.2 5.2 6.5 6.5 6.5 10 10 ORDERABLE PART NUMBER CY74FCT2374CTQCT CY74FCT2374CTSOC CY74FCT2374CTSOCT CY74FCT2374ATQCT CY74FCT2374ATSOC CY74FCT2374ATSOCT CY74FCT2374TSOC CY74FCT2374TSOCT TOP-SIDE MARKING FCT2374C FCT2374C FCT2374A FCT2374A FCT2374 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS D H L X CP ↑ ↑ X OE L L H OUTPUT O H L Z H = High logic level, L = Low logic level, X = Don’t care, Z = High-impedance state, ↑ = Low-to-high clock transition logic diagram (positive logic) OE 1 CP 11 CP 2 D0 3 D Q O0 To Seven Other Channels 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY74FCT2374T 8-BIT REGISTER WITH 3-STATE OUTPUTS SCCS040A – SEPTEMBER 1994 – REVISED OCTOBER 2001 absolute maximum rating over operating free-air temperature range (unless otherwise noted)† Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA Package thermal impedance, θJA (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 2) MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature –40 4.75 2 0.8 – 15 12 85 NOM 5 MAX 5.25 UNIT V V V mA mA °C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CY74FCT2374T 8-BIT REGISTER WITH 3-STATE OUTPUTS SCCS040A – SEPTEMBER 1994 – REVISED OCTOBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL ROUT Vhys II IIH IIL IOZH IOZL IOS‡ Ioff ICC ∆ICC ICCD¶ VCC = 4.75 V, VCC = 4.75 V, VCC = 4.75 V, VCC = 4.75 V, All inputs VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 0 V, VIN = VCC VIN = 2.7 V VIN = 0.5 V VOUT = 2.7 V VOUT = 0.5 V VOUT = 0 V VOUT = 4.5 V 0.1 0.5 0.06 0.7 1.2 1.6 3.9 5 9 –60 –120 TEST CONDITIONS IIN = –18 mA IOH = –15 mA IOL = 12 mA IOL = 12 mA MIN 2.4 20 TYP† –0.7 3.3 0.3 25 0.2 5 ±1 ±1 10 –10 –225 ±1 0.2 2 0.12 1.4 3.4 3.2|| 12.2|| 10 12 pF mA 0.55 40 MAX –1.2 UNIT V V V Ω V µA µA µA µA µA mA µA mA mA mA/ MHz VCC = 5.25 V, VIN ≤ 0.2 V, VIN ≥ VCC – 0.2 V §, f1 = 0, Outputs open VCC = 5.25 V, VIN = 3.4 V VCC = 5.25 V, Outputs open, One input switching at 50% duty cycle, OE = GND, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V One bit switching at f1 = 5 MHz at 50% duty cycle Eight bits switching at f1 = 2.5 MHz at 50% duty cycle VIN ≤ 0.2 V or VIN ≥ VCC – 0.2V VIN = 3.4 V or GND VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V VIN = 3.4 V or GND IC# VCC = 5.25 V, Outputs open, , f0 = 10 MHz, OE = GND Ci Co pF † Typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. § Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND ¶ This parameter is derived for use in total power-supply calculations. # IC = ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1) Where: IC = Total supply current ICC = Power-supply current with CMOS input levels ∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V) DH = Duty cycle for TTL inputs high NT = Number of TTL inputs at DH ICCD = Dynamic current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero f1 = Input signal frequency N1 = Number of inputs changing at f1 All currents are in milliamperes and all frequencies are in megahertz. || Values for these conditions are examples of the ICC formula. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY74FCT2374T 8-BIT REGISTER WITH 3-STATE OUTPUTS SCCS040A – SEPTEMBER 1994 – REVISED OCTOBER 2001 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) CY74FCT2374T MIN tw tsu th Pulse duration, CP Setup time, data before CP↑ Hold time, data after CP↑ 7 2 1.5 MAX CY74FCT2374AT MIN 5 2 1.5 MAX CY74FCT2374CT MIN 4 1.5 1 MAX UNIT ns ns ns switching characteristics over operating free-air temperature range (see Figure 1) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) CP TO (OUTPUT) O O O CY74FCT2374T MIN 2 2 1.5 1.5 1.5 1.5 MAX 10 10 12.5 12.5 8 8 CY74FCT2374AT MIN 2 2 1.5 1.5 1.5 1.5 MAX 6.5 6.5 6.5 6.5 5.5 5.5 CY74FCT2374CT MIN 2 2 1.5 1.5 1.5 1.5 MAX 5.2 5.2 6.2 6.2 5 5 UNIT ns ns ns OE OE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CY74FCT2374T 8-BIT REGISTER WITH 3-STATE OUTPUTS SCCS040A – SEPTEMBER 1994 – REVISED OCTOBER 2001 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test CL = 50 pF (see Note A) Test Point 500 Ω From Output Under Test CL = 50 pF (see Note A) 500 Ω S1 Open GND 500 Ω TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input tw 3V tsu Data Input 0V 1.5 V 1.5 V 0V th 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 3V 1.5 V 1.5 V 0V tPZL VOH 1.5 V 1.5 V VOL tPLH VOH 1.5 V 1.5 V VOL Output Waveform 2 (see Note B) Output Waveform 1 (see Note B) tPZH 1.5 V 1.5 V tPLZ ≈3.5 V VOL + 0.3 V tPHZ VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOL Input 1.5 V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION Input tPLH In-Phase Output tPHL Out-of-Phase Output 1.5 V 1.5 V 0V tPHL Output Control VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 PACKAGING INFORMATION Orderable Device 74FCT2374ATSOCTE4 74FCT2374ATSOCTG4 74FCT2374CTSOCTE4 74FCT2374CTSOCTG4 74FCT2574ATQCTE4 74FCT2574ATSOCTE4 74FCT2574ATSOCTG4 74FCT2574CTSOCTE4 74FCT2574CTSOCTG4 CY74FCT2374ATQCT CY74FCT2374ATQCTE4 CY74FCT2374ATQCTG4 CY74FCT2374ATSOC CY74FCT2374ATSOCE4 CY74FCT2374ATSOCG4 CY74FCT2374ATSOCT CY74FCT2374CTQCT CY74FCT2374CTQCTE4 CY74FCT2374CTQCTG4 CY74FCT2374CTSOC CY74FCT2374CTSOCE4 CY74FCT2374CTSOCG4 CY74FCT2374CTSOCT CY74FCT2374TSOC CY74FCT2374TSOCE4 Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type SOIC SOIC SOIC SOIC SSOP/ QSOP SOIC SOIC SOIC SOIC SSOP/ QSOP SSOP/ QSOP SSOP/ QSOP SOIC SOIC SOIC SOIC SSOP/ QSOP SSOP/ QSOP SSOP/ QSOP SOIC SOIC SOIC SOIC SOIC SOIC Package Drawing DW DW DW DW DBQ DW DW DW DW DBQ DBQ DBQ DW DW DW DW DBQ DBQ DBQ DW DW DW DW DW DW Pins Package Eco Plan (2) Qty 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 25 25 25 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-2-260C-1 YEAR Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 25 25 25 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 25 25 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 Orderable Device CY74FCT2374TSOCG4 CY74FCT2374TSOCT CY74FCT2374TSOCTE4 CY74FCT2374TSOCTG4 CY74FCT2574ATQCT CY74FCT2574ATQCTG4 CY74FCT2574ATSOC CY74FCT2574ATSOCE4 CY74FCT2574ATSOCG4 CY74FCT2574ATSOCT CY74FCT2574CTQCT CY74FCT2574CTQCTE4 CY74FCT2574CTQCTG4 CY74FCT2574CTSOC CY74FCT2574CTSOCE4 CY74FCT2574CTSOCG4 CY74FCT2574CTSOCT CY74FCT2574TSOC CY74FCT2574TSOCE4 CY74FCT2574TSOCG4 CY74FCT2574TSOCT CY74FCT2574TSOCTE4 CY74FCT2574TSOCTG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type SOIC SOIC SOIC SOIC SSOP/ QSOP SSOP/ QSOP SOIC SOIC SOIC SOIC SSOP/ QSOP SSOP/ QSOP SSOP/ QSOP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC Package Drawing DW DW DW DW DBQ DBQ DW DW DW DW DBQ DBQ DBQ DW DW DW DW DW DW DW DW DW DW Pins Package Eco Plan (2) Qty 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 25 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 25 25 25 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 25 25 25 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 25 25 25 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Device Package Pins Site Reel Diameter (mm) 330 330 330 330 330 330 330 330 330 330 Reel Width (mm) 16 24 16 24 24 16 24 16 24 24 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8 12 8 12 12 8 12 8 12 12 W Pin1 (mm) Quadrant 16 24 16 24 24 16 24 16 24 24 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1 CY74FCT2374ATQCT CY74FCT2374ATSOCT CY74FCT2374CTQCT CY74FCT2374CTSOCT CY74FCT2374TSOCT CY74FCT2574ATQCT CY74FCT2574ATSOCT CY74FCT2574CTQCT CY74FCT2574CTSOCT CY74FCT2574TSOCT DBQ DW DBQ DW DW DBQ DW DBQ DW DW 20 20 20 20 20 20 20 20 20 20 MLA MLA MLA MLA MLA MLA MLA MLA MLA MLA 6.5 10.8 6.5 10.8 10.8 6.5 10.8 6.5 10.8 10.8 9.0 13.0 9.0 13.0 13.0 9.0 13.0 9.0 13.0 13.0 2.1 2.7 2.1 2.7 2.7 2.1 2.7 2.1 2.7 2.7 TAPE AND REEL BOX INFORMATION Device CY74FCT2374ATQCT CY74FCT2374ATSOCT CY74FCT2374CTQCT CY74FCT2374CTSOCT CY74FCT2374TSOCT CY74FCT2574ATQCT CY74FCT2574ATSOCT CY74FCT2574CTQCT CY74FCT2574CTSOCT CY74FCT2574TSOCT Package DBQ DW DBQ DW DW DBQ DW DBQ DW DW Pins 20 20 20 20 20 20 20 20 20 20 Site MLA MLA MLA MLA MLA MLA MLA MLA MLA MLA Length (mm) 0.0 333.2 0.0 333.2 333.2 0.0 333.2 0.0 333.2 333.2 Width (mm) 0.0 333.2 0.0 333.2 333.2 0.0 333.2 0.0 333.2 333.2 Height (mm) 0.0 31.75 0.0 31.75 31.75 0.0 31.75 0.0 31.75 31.75 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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