MSTM-S3-T2F1

MSTM-S3-T2F1 Stratum 3 Timing Module 21 1 Comprehensive Drive 1 Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com Application The Connor-Winfield MSTM-S3-T2F1 Simplified Control Timing Module acts as a complete system clock module for Stratum 3 timing applications in accordance with GR1244, Issue 2 and GR-253, Issue 3. Connor Winfield’s Stratum 3 timing modules helps reduce the cost of your design by minimizing your development time and maximizing your control of the system clock with our simplified design. Features • 5V Miniature Timing Module • Redundant 19.44 MHz References • 40 sec., Filtered, Hold Over History • Operational Status Flags Bulletin Page Revision Date Issued By TM030 1 of 16 Advance A00 03 October 01 MBatts © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice General Description The Connor-Winfield Stratum 3 Miniature Simplified Control Timing Module acts as a complete system clock module for general Stratum 3 timing applications. The MSTM is designed for external control functions. Full external control input allows for selections and monitoring of any of four possible operating states: 1) Holdover, 2) External Reference #1, 3) External Reference #2, and 4) Free Run. The Table 5 (pg. 4) illustrates the control signal inputs and corresponding operational states: In the absence of External Control Inputs (A,B), the MSTM enters the Free Run mode and signals an External Alarm. The MSTM will enter other operating modes upon application of a proper control signal. Mode 1 operation (A=1, B=0) results in an output signal that is phase locked to the External Reference Input #1. Mode 2 operation (A=0, B=1) results in an output signal that is phase locked to External Reference Input #2. Holdover mode operation (A=1, B=1) results in an output signal at or near the frequency as determined by the latest (last) locked-signal input values and the holdover performance of the MSTM. The primary feature of this model is the Reference Frequency Detector (RFD). This is an independent circuit that monitors both reference inputs simultaneously to determine that a signal is present and its frequency is within a valid range. A logical one on the outputs VALID_R1 and VALID_R2 indicates that the signals applied to EX_REF1 and EX_REF2 respectively have been detected and have a frequency that is within at least +/- 4.6 ppm of nominal. A range of +/-4.6 ppm is guaranteed for the life of the module. The actual range is somewhat more than twice that to account for normal drift and aging that will occur. When, for example, the reference applied to EX_REF1 disappears, VALID_R1 will go to a logical zero within 500 microseconds. When the signal returns at a frequency within +/ - 4.6 ppm of nominal the VALID_R1 output will return to a logical one after a 4-second delay. The delay is a validation period that requires the output of the frequency detector to remain stable for 4 seconds before confirming the status of the reference applied. This eliminates the incessant toggling of the frequency detector that occurs when the reference frequency is at the threshold frequency of the detector The function of the RFD is not related to the operational alarms, LOL and TVL, which monitor the operation of the PLL relative to the selected active reference. In fact the operational alarms function only at the extreme edge of the PLL operating range. This means that it is quite possible for the active reference to drift out of range of the Reference Frequency Detector and still remain well within the capture range of the PLL and not activate the operational alarms. If the other reference was still marked valid by the RFD it might make sense to switch to the better reference before the selected reference drifts completely out of range. Alarm signals are generated at the Alarm Output during Holdover and Free Run operation. Alarm Signals are also generated by loss-of-lock, loss of Reference, and by a Tune-Limit indication from the PLL. A Tune-Limit alarm signal indicates that the OCXO tuning voltage is approaching within 10% the limits of its lock capability and that the External Reference Input may be erroneous. A high level indicates an alarm condition. Real-time indication of the operational mode is available from outputs S0 and S1, which are determined from internal mode registers. Control loop filters effectively attenuate any reference jitter and smooth out phase transients. Functional Block Diagram Figure 1 Control Select Alarm Select CNTL A CNTL B 0 1 S0 S1 Lock and Detection A0 PLL TVL A1 EX REF 1 EX REF 2 Internal Free Run DAC Filter Tuning Voltage Monitor Source Selector DAC Stratum 3 OCXO SYNC_OUT 3:1 MUX Phase Comparator ÷N Filter/ FIFO TCXO CLK_OUT Holdover Circuit ÷N EX REF 2 R2-CHK VALID_R2 EX REF 1 R1-CHK VALID_R1 Advance Data Sheet #: TM030 Page 2 of 16 Rev: A00 Date: 10 / 03 / 01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Absolute Maximum Rating Table 1 Symbol VCC VI Ts Parameter Power Supply Voltage Input Voltage Storage Temperature Minimum -0.5 -0.5 -55 Nominal Maximum 7.0 VCC + 0.5 100 Units Volts Volts deg. C Notes 1.0 1.0 1.0 Recommended Operating Conditions Table 2 Symbol Vcc VIH VIL tIN CIN VOH VOL tTRANS tPULSE TOP Parameter Power supply voltage High level input voltage - TTL Low level input voltage - TTL Input signal transition - TTL Input capacitance High level output voltage, IOH = -4.0mA, VCC = min. Low level output voltage, IOL = 12.0 mA, VCC = min. Clock out transition time 8kHz input reference pulse width( positive or negative) Operating temperature 30 0 70 4.0 2.4 Minimum 4.75 2.0 0 Nominal 5.00 Maximum 5.25 VCC 0.8 250 15 5.25 0.4 Units Volts Volts Volts ns pF Volts Volts ns ns °C 2.0 Notes Specifications Table 3 Parameter Synchronized Output Frequency (SYNC_OUT) Non-synchronized Output Frequency (CLK_OUT) Input Reference Frequency Supply Current Jitter, Wander and Phase Transient Tolerances Wander Generation Wander Transfer Jitter Generation Jitter Transfer Phase Transients Free Run Accuracy Hold Over Stability Inital Offset Temperature Drift Maximum Hold Over History Pull-in/ Hold-in Range Lock Time PLL_TVL Alarm Limit Specifications 19.44 MHz 19.44 MHz Dual 19.44 MHz references 250 mA typical, 400 mA during warm-up (Maximum) GR-1244-CORE 4.2-4.4, GR-253-CORE 5.4.4.3.6 GR-1244-CORE 5.3, GR-253-CORE 5.4.4.3.2 GR-1244-CORE 5.4 GR-1244-CORE 5.5, GR-253-CORE 5.6.2.3 GR-1244-CORE 5.5, GR-253-CORE 5.6.2.1 GR-1244-CORE 5.6, GR-253-CORE 5.4.4.3.3 4.6 ppm over TOP ±0.37 ppm for initial 24 hrs ±0.05 ppm ±0.28 ppm ±0.04 ppm 40 seconds ±4.6 ppm minimum 17 ppm) Normal Tune Limit LOR LOL (>17 ppm) Operational Mode Alarm Outputs A0 0 0 1 0 1 0 1 0 1 0 A1 0 0 0 1 1 0 0 1 1 0 Condition State Output S0 0 1 1 1 1 0 0 0 0 1 S1 0 0 0 0 0 1 1 1 1 1 0 1 1 1 Hold Over NOTES: 1.0: Stresses beyond those listed under Absolute Maximum Rating may cause damage to the device. Operation beyond Recommended Conditions is not implied. 2.0: Logic is 3.3V CMOS 3.0: GR-1244-CORE 3.2.1 4.0: 5.0: Hold Over stability is the cumulative fractional frequency offset as described by GR-1244-CORE, 5.2 Pull-in Range is the maximum frequency deviation from nominal clock rate on the reference inputs to the timing module that can be overcome to pull into synchronization with the reference Advance Data Sheet #: TM030 Page 4 of 16 Rev: A00 Date: 10 / 03 / 01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Qualification Outputs Table 6 Condition Ref 1 is within ±4.6 ppm Ref 1 > ±4.6 ppm Ref 1 (No Signal) Ref 2 is within ±4.6 ppm Ref 2 > ±4.6 ppm Ref 2 (No Signal) Valid_R1 1 0 0 X X X Valid_R2 X X X 1 0 0 Valid Reference Thresholds Table 7 Minimum VALID_R1 VALID_R2 ±4.6 ppm ±4.6 ppm Nominal ±9.2 ppm ±9.2 ppm Maximum ±13.8 ppm ±13.8 ppm Frequency Detector Range Over Lifetime Table 8 Detector Frequency Offset 0 ppm +4.6 ppm -4.6 ppm VALID_R1/R2 Range ±9.2 ppm +13.8 ppm -4.6 ppm +4.6 ppm -13.8 ppm Advance Data Sheet #: TM030 © Copyright 2001 The Connor-Winfield Corp. Page 5 of 16 Rev: A00 Date: 10 / 03 / 01 All Rights Reserved Specifications subject to change without notice Typical Application Figure 2 BITS System Signal Input Select Timing Card #1 A Y S Line Card #1 B C CW’s SCG 2500/4500 CW’s STM/MSTM module Clock out MUX RCV Timing Card #2 A B C Line Card #N MUX S Y CW’s SCG 2500/4500 CW’s STM/MSTM module Clock out RCV System Select Typical System Test Set-up Figure 3 G P S or LO R AN T i m in g S o u r c e T h is d e v ic e s u p p lie s s y s t e m t im e in fo rm a tio n . I t c a n b e t h o u g h t o f a s s u p p ly in g " a b s o lu t e tim e " r e f e r e n c e in fo rm a tio n S a m p l e M T IE D a t a f o r S T M - S 3 / M S T M - S 3 1 .0 E - 6 10 MHz M T IE (s P o s s i b le C h o ic e s I n c lu d e S ta n fo rd R e s e a r c h M o d e l: F S 7 0 0 T r u e tim e M o d e l X X X T yp i c al r e s p o n s e - 3 0 0 0 s e c o n d te s t - J it t e r a p p lie d ( 2 U I @ re f d a t e A P R k dh 22 1998 1 0 H z) 1 0 0 .0 E - 9 1 0 .0 E - 9 M T IE 1 2 4 4 - 5 .2 M a s k ( A ) 1 2 4 4 - 5 .2 M a s k ( B ) 1 2 4 4 - 5 .6 M a s k G R 2 5 3 - 5 .4 . 4 .3 . 2 1 .0 E - 9 1 0 0 .0 E - 3 1 .0 E +0 1 0.0E +0 1 0 0 .0 E + 0 C o p y ri g ht 1.0 E +3 1 0 .0 E + 3 O b s e r v a t i o n T im e ( s ) 1 9 9 8 C o n n o r - W in f ie ld a l l r ig h ts r e s e r v e d T a r g e t S y s te m U n d e r T e s t E x te r n a l R e fe re n ce In p u t A r b i tr a r y W a v e fo rm G e n e ra to r D S 1 ra te R Z ( 1 . 5 4 4 M H z ) , E 1 ra te R Z o r 8 k H z c lo c k R Z w it h n o is e m o d u la t io n C l o c k o r B IT S l o g i c l e v e l c lo c k in p u t (T T L , C M O S , e tc .) S ta n d a r d s C o m p lia n c e D o c u m e n ts M T IE , T D E V , W a n d e r T r a n s fe r , a n d W a n d e r G e n e r a t io n P l o t s OC-12 Line Card OC-48 Line Card OC-3 Line Card DS-1 Line Card Timing Card Timing Card Line Card S a m p le 1 .0 E - 6 Noise Modulation Input W a n d e r G e n e r a tio n 10 H z ) (T D E V ) f o r S T M / M S T M - S 3 T yp i c a l r e s p o n s e - 3 0 0 0 s e c o n d te s t - J it t e r a p pl ie d ( 2 U I @ r e f da t e A P R 2 2 1 9 9 8 k dh 10 MHz 1 0 0 .0 E - 9 . . . . . .. 1 0 .0 E - 9 T D E V ( se c TDEV 1 .0 E - 9 G R 1 2 4 4 - F ig 5 . 1 G R 1 2 4 4 - F ig 5 - 3 E x te r n a l R e fe re n ce In p u t A r b i tr a r y W a v e fo rm G e n e ra to r [N o i s e S o u rc e ] 1 0 0 .0 E - 1 2 1 0 .0 E - 3 1 0 0 .0 E - 3 1 .0 E + 0 1 0 .0 E +0 1 0 0 .0 E + 0 1 .0 E + 3 In te g r a t io n T im e (s e c ) C o p y r i gh t 1 9 9 8 C o n n o r -W in f ie ld a ll l r ig h ts r e s e r v e d 10 MHz D S 1 r a t e [ 1 . 5 4 4 M H z ] B IT S B ip o la r D S - 1 , O C - 3 , O C - 1 2 e le c tr ic a l o r o p t ic a l s ig n a ls 10 MHz T e k t ro n ix S J300E E x te r n a l R e fe re n c e In p u t T im e - s t a m p e d e n s e m b le b a s e d o n a b s o lu t e tim e re fe re n c e ( 1 0 M H z in p u t ) P h a s e E r ro r d a t a o u tp u t HP 53310A M o d u la t io n A n a ly z e r / T im e I n t e r v a l A n a ly z e r W a n d e r A n a ly z e r d a ta ( I E E E - 4 8 8 ) E x te r n a l R e fe re n ce In p u t T E K T R O N IX S J 3 0 0 E I E E E - 4 8 8 C o n tr o lle r P la t fo r m f o r s o f tw a r e H P 5 3 3 0 5 A P h a s e A n a ly z e r H P E 1748A Sync M e a s u re m e n t T e k t ro n ix W a n d e r A n a ly z e r Advance Data Sheet #: TM030 Page 6 of 16 Rev: A00 Date: 10 / 03 / 01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice MSTM-S3-T2F1 Typical Current Draw Figure 4 0.45 0.4 0.35 CURRENT (A) 0.3 0.25 0.2 0.15 0.1 0.05 0 0 10 20 30 40 50 60 TIME (Sec) Typical Calibrated Wander Transfer TDEV Figure 5 10000 1000 TDEV (ns) 100 TDEV (ns) 10 GR1244, Fig 5.3 1 0.1 0.01 1 10 100 1000 10000 Integration Time (Sec.) Advance Data Sheet #: TM030 © Copyright 2001 The Connor-Winfield Corp. Page 7 of 16 Rev: A00 Date: 10 / 03 / 01 All Rights Reserved Specifications subject to change without notice Typical Wander Generation MTIE Figure 6 1000 G R 1 2 4 4 , F ig 5 .2 (A ) G R 1 2 4 4 , F ig 5 .2 (B ) G R 2 5 3 -5 .4 .4 .3 .2 , F ig 5 .1 7 M T IE (n s ) MTIE (ns) 100 10 0.1 1 10 100 1000 10000 100000 1000000 O b s e r v a tio n T im e (s e c .) Typical Wander Generation TDEV Figure 7 100 T D E V (n s) G R 1 24 4, F ig 5 .1 10 TDEV (ns) 1 0 .1 10000 1000 0.1 100 10 1 In te g ra tio n T im e (s e c .) Advance Data Sheet #: TM030 Page 8 of 16 Rev: A00 Date: 10 / 03 / 01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice 1µ s Phase Transient TIE Figure 8 1200 1000 800 TIE (ns) 600 400 200 0 -200 0 1 2 3 4 5 Time (sec) 6 7 8 9 10 1µ s Phase Transient MTIE Figure 9 10000 1000 MTIE (ns) G R -2 5 3 , F i g . 5 -1 9 100 M T I E (n s) 10 1 0 .0 1 0 .1 1 10 100 1000 O b s e rv a tio n T im e (s e c ) Advance Data Sheet #: TM030 © Copyright 2001 The Connor-Winfield Corp. Page 9 of 16 Rev: A00 Date: 10 / 03 / 01 All Rights Reserved Specifications subject to change without notice Entry Into Hold Over Figure 10 10000 1000 MTIE (ns) 100 10 G R -1 2 4 4 O b je c t ive , F ig . 5 -8 G R -1 2 4 4 R e q u ire m e n t , F ig . 5 -8 Ty p ic a l M TIE 1 0.001 0.01 0.1 1 10 100 O b se r v a ti o n T i m e (se c o n d s) Return from Hold Over Figure 11 10000 1000 MTIE (ns) 100 10 G R -1 2 4 4 R e q u ire m e n t , F ig . 5 -7 M TIE (n s ) Ty p ic a l M TIE 1 0.001 0.01 0 .1 O b se rv a ti o n T i m e (se c . ) 1 10 100 Advance Data Sheet #: TM030 Page 10 of 16 Rev: A00 Date: 10 / 03 / 01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice MSTM-S3-T2F1 Mode Indicator Delay Figure 12 Change in Operational Mode Operational Mode Indicator ∆tm 2 msec